TWI697085B - 半導體元件及其形成方法 - Google Patents

半導體元件及其形成方法 Download PDF

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TWI697085B
TWI697085B TW107125093A TW107125093A TWI697085B TW I697085 B TWI697085 B TW I697085B TW 107125093 A TW107125093 A TW 107125093A TW 107125093 A TW107125093 A TW 107125093A TW I697085 B TWI697085 B TW I697085B
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Taiwan
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dielectric layer
via hole
layer
integrated circuit
conductive
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TW107125093A
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TW201924007A (zh
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曾士豪
郭宏瑞
何明哲
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台灣積體電路製造股份有限公司
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Abstract

在實施例中，元件包含：積體電路晶粒；鄰近積體電路晶粒的穿孔；包封積體電路晶粒及穿孔的模製化合物；以及重佈線結構，其包含：延伸穿過第一介電層的第一導通孔，第一導通孔電性連接至積體電路晶粒，第一介電層在積體電路晶粒、穿孔以及模製化合物上方；以及在第一介電層及第一導通孔上方的第一導電線，第一導通孔延伸至第一導電線中。

Description

半導體元件及其形成方法
本發明的實施例是有關於半導體元件及其形成方法。
半導體產業歸因於進行中的多種電子組件(例如，電晶體、二極體、電阻器、電容器等)的積體密度(integration density)的改良而經歷快速發展。主要地，積體密度的改良源自於最小特徵尺寸的迭代減小，其允許更多組件整合至給定區域中。隨著對於縮小的電子元件的需求增長，已出現對於更小且更具創造性之半導體晶粒的封裝技術之需求。此等封裝系統之實例為疊層封裝(Package-on-Package；PoP)技術。在PoP元件中，頂部半導體封裝體堆疊於底部半導體封裝體之頂部上，以提供高積體密度以及高組件密度。PoP技術通常能夠在印刷電路板(printed circuit board；PCB)上使半導體元件的生產具有增強之功能性以及小的佔據面積。
本發明實施例的一種半導體元件，包括積體電路晶粒、穿 孔、模製化合物以及重佈線結構。穿孔鄰近所述積體電路晶粒。模製化合物包封所述積體電路晶粒及所述穿孔。重佈線結構包括第一導通孔以及第一導電線。第一導通孔延伸穿過第一介電層，所述第一導通孔電性連接至所述積體電路晶粒，所述第一介電層在所述積體電路晶粒、所述穿孔以及所述模製化合物上方。第一導電線在所述第一介電層及所述第一導通孔上方，所述第一導通孔延伸至所述第一導電線中。
本發明實施例的一種形成半導體元件的方法包括：使用模製化合物包封積體電路晶粒，所述積體電路晶粒具有晶粒連接件；在所述積體電路晶粒之所述晶粒連接件上形成第一導通孔；在所述積體電路晶粒、所述模製化合物以及所述第一導通孔上方沈積第一介電層，所述第一介電層沿所述第一導通孔之側壁及頂部表面延伸，所述第一導通孔之所述頂部表面在所述第一介電層的主表面上方；移除所述第一介電層在所述第一導通孔之所述側壁及所述頂部表面上的部分，由此暴露所述第一導通孔之一部分；以及在所述第一介電層及所述第一導通孔之所述暴露部分上形成第一導電線。
本發明實施例的一種形成半導體元件的方法包括：將積體電路晶粒置放在第一介電層上，所述積體電路晶粒具有晶粒連接件；使用模製化合物包封所述積體電路晶粒；在所述積體電路晶粒之所述晶粒連接件上形成第一導通孔，所述第一導通孔具有設置為離所述第一介電層第一距離之最頂部表面；在所述積體電路晶粒、所述模製化合物以及所述第一導通孔上沈積第二介電層，所述第二介電層具有設置為離所述第一介電層第二距離之主表面， 所述第一距離大於所述第二距離；移除所述第二介電層之部分以暴露所述第一導通孔之側面及所述最頂部表面；以及在所述第一導通孔上形成第一導電線，所述第一導電線與所述第一導通孔之所述側面及所述最頂部表面接觸。
100:載體基底
102:釋放層
104、108、136、148、164、170:介電層
106:金屬化圖案
110:背側重佈線結構
112、306:穿孔
114:積體電路晶粒
116:黏著劑
118:半導體基底
120:互連結構
122:焊墊
124:鈍化膜
126:晶粒連接件
128:介電材料
130:包封體
132:前側重佈線結構
134、146、162、168:導通孔
138、150:晶種層
140:罩幕層
142、154、158、178:開口
144、160、166:導電線
152、156:罩幕層
172:導電墊
174、314:導電連接件
176:膠帶
200:第一封裝體
300:第二封裝體
302:基底
303、304、402:接合墊
308、308A、308B:堆疊式晶粒
310:電線接合
312:模製材料
400:封裝基底
500:封裝結構
600:第一封裝區域
602:第二封裝區域
650:區域
D1、D2、D3、D4:距離
結合附圖閱讀以下詳細描述，會最佳地理解本發明之態樣。應注意，根據業界中之標準慣例，各種特徵未按比例繪製。事實上，出於論述清楚起見，可任意地增加或減小各種特徵之尺寸。
圖1至圖16繪示根據一些實施例用於形成元件封裝體之製程期間的中間步驟之橫截面視圖。
圖17至圖18繪示根據一些實施例用於形成封裝結構之製程期間的中間步驟之橫截面視圖。
以下揭露內容提供用於實施本發明之不同特徵的多個不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露內容。當然，此等組件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上之形成可包含第一特徵以及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成以使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露內容可在各種實例中重複參考數字及/或字母。此重複是出於簡單性及清晰性之目的，且本身並不指示所論述之各種實施例及/或組態之間的關係。
另外，諸如「在...下方(beneath)」、「在...下面(below)」、「下部的(lower)」、「在...上方(above)」、「上部的(upper)」及類似者的空間相對術語可在本文中出於簡單描述而使用以描述如圖式中所說明的一個元件或特徵與另一元件或特徵之關係。除圖式中所描繪之定向以外，空間相對術語意欲涵蓋元件在使用或操作中之不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用之空間相對描述詞可同樣相應地進行解釋。
本文中所論述之實施例可在特定情況下論述，亦即具有精細間距前側重佈線結構之封裝結構(例如，疊層封裝(PoP)結構)。前側重佈線結構之通孔經形成具有錨定(anchor)連接，所述錨定連接具有上覆金屬化圖案。在錨定連接中，通孔部分延伸至上覆金屬化圖案中，且上覆金屬化圖案在通孔上方不具凹陷。形成具有錨定連接之通孔可避免形成盲孔，所述盲孔例如不貫穿各別介電層以完全暴露之通孔。另外，錨定連接可具有較好機械強度。
本揭露內容之教示適用於包含重佈線結構之任何封裝結構。其他實施例預期其他應用，諸如一般熟習此項技術者在閱讀本揭露內容後就將顯而易見之不同封裝類型或不同組態。應注意，本文中所論述之實施例可不必說明可存在於結構中之每一組件或特徵。舉例而言，諸如當對組件中之一者的論述可充分傳達實施例之態樣時，可自圖式省略多個組件。另外，可將本文中所論述之方法實施例論述為以特定次序執行；然而，其他方法實施例可以任何邏輯次序執行。
圖1至圖16繪示根據一些實施例用於形成第一封裝體200之製程期間的中間步驟之橫截面視圖。繪示第一封裝區域600 及第二封裝區域602，且第一封裝體200形成於每一封裝區域中。第一封裝體200亦可稱為積體扇出型(integrated fan-out；InFO)封裝體。
在圖1中，提供載體基底100，且釋放層102形成於載體基底100上。載體基底100可為玻璃載體基底、陶瓷載體基底或其類似者。載體基底100可為晶圓，使得多個封裝體可在載體基底100上同時形成。釋放層102可由聚合物基材料形成，可將其連同載體基底100一起自將在後續步驟中形成之上覆結構移除。在一些實施例中，釋放層102為在加熱時損失其黏著特性之環氧樹脂基熱釋放材料，諸如光-熱轉換(light-to-heat-conversion；LTHC)釋放塗層。在其他實施例中，釋放層102可為在暴露於紫外線(ultra-violet；UV)光時損失其黏著特性之UV黏膠。釋放層102可配製為液體及經固化，可為疊層至載體基底100上之層壓膜，或可為其類似者。釋放層102之頂部表面可經水平化，且可具有高度共面性。
在圖2中，形成介電層104以及金屬化圖案106(有時稱為重佈線層或重佈線)。介電層104形成於釋放層102上。介電層104之底部表面可與釋放層102之頂部表面接觸。在一些實施例中，介電層104由聚合物形成，諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺、苯環丁烷(benzocyclobutene；BCB)或類似者。在其他實施例中，介電層104由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼矽酸鹽玻璃(borosilicate glass；BSG)、硼摻磷矽酸鹽玻璃(boron-doped phosphosilicate glass； BPSG)或其類似者；或其類似者。介電層104可藉由任何可接受的沈積製程形成，諸如旋塗、化學氣相沈積(chemical vapor deposition，CVD)、疊層、類似者或其組合。
金屬化圖案106形成於介電層104上。作為形成金屬化圖案106之實例，晶種層(未繪示)形成於介電層104上方。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料形成之多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方之銅層。可使用例如PVD或其類似者形成晶種層。隨後在晶種層上形成圖案化光阻劑。光阻劑可藉由旋塗或其類似者形成且可暴露於光以用於圖案化。光阻劑之圖案對應於金屬化圖案106。圖案化穿過光阻劑形成開口以暴露晶種層。導電材料形成於光阻劑之開口中且形成於晶種層之暴露部分上。導電材料可藉由電鍍(plating)形成，諸如有電電鍍(electroplating)或無電式電鍍(electroless plating)，或其類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或其類似者。隨後，移除上方未形成導電材料之光阻劑及部分之晶種層。可藉由可接受的灰化或剝離製程移除光阻劑，諸如使用氧電漿或其類似者。一旦移除光阻劑，諸如使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)移除晶種層之暴露部分。晶種層之剩餘部分以及導電材料形成金屬化圖案106。
在圖3中，介電層108形成於金屬化圖案106及介電層104上。在一些實施例中，介電層108由聚合物形成，聚合物可為可使用微影罩幕圖案化之感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層108由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或其 類似者。介電層108可藉由旋塗、疊層、CVD、其類似者或其組合形成。隨後圖案化介電層108以形成開口來暴露金屬化圖案106之部分。圖案化可藉由可接受的製程，諸如藉由當介電層108為感光性材料時將介電層108暴露於光或藉由使用例如非等向性蝕刻進行蝕刻。
介電層104及介電層108以及金屬化圖案106可稱為背側重佈線結構110。在所繪示之實施例中，背側重佈線結構110包含兩個介電層104及介電層108以及一個金屬化圖案106。在其他實施例中，背側重佈線結構110可包含任何數目的介電層、金屬化圖案以及導通孔。一或多個額外金屬化圖案及介電層可藉由重複用於形成金屬化圖案106及介電層108之製程而形成於背側重佈線結構110中。導通孔(未繪示)可在形成金屬化圖案期間藉由在介電層之下的開口中形成金屬化圖案之晶種層及導電材料而形成。導通孔可因此互連且電性耦接各種金屬化圖案。
在圖4中，形成穿孔112。作為形成穿孔112之實例，晶種層形成於背側重佈線結構110上方，例如，如所說明之介電層108及金屬化圖案106的暴露部分上方。在一些實施例中，晶種層為金屬層，金屬層可為單層或包括由不同材料形成之多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方之銅層。可使用例如PVD或其類似者形成晶種層。在晶種層上形成圖案化光阻劑。光阻劑可藉由旋塗或其類似者形成且可暴露於光以用於圖案化。光阻劑之圖案對應於穿孔。圖案化穿過光阻劑形成開口以暴露晶種層。導電材料形成於光阻劑之開口中且形成於晶種層之暴露部分上。導電材料可藉由電鍍形成，諸如有電電鍍或無電 式電鍍，或其類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁，或其類似者。移除上方未形成導電材料之光阻劑及部分之晶種層。可藉由可接受的灰化或剝離製程移除光阻劑，諸如使用氧電漿或其類似者。一旦移除光阻劑，諸如使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)移除晶種層之暴露部分。晶種層之剩餘部分以及導電材料形成穿孔112。
在圖5中，積體電路晶粒114藉由黏著劑116黏附至介電層108。儘管兩個積體電路晶粒114說明為黏附於第一封裝區域600及第二封裝區域602中之每一者中，但應瞭解，較多或較少積體電路晶粒114可黏附於每一封裝區域中。舉例而言，僅一個積體電路晶粒114可黏附於每一區域中。積體電路晶粒114可為邏輯晶粒(例如，中央處理單元、微控制器等)、記憶體晶粒(例如，動態隨機存取記憶體(dynamic random access memory；DRAM)晶粒、靜態隨機存取記憶體(static random access memory；SRAM)晶粒等)、功率管理晶粒(例如，功率管理積體電路(power management integrated circuit；PMIC)晶粒)、射頻(radio frequency；RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system；MEMS)晶粒、信號處理晶粒(例如，數位信號處理(digital signal processing；DSP)晶粒)、前端晶粒(例如，類比前端(analog front-end；AFE)晶粒)、類似者或其組合。又，在一些實施例中，積體電路晶粒114可為不同大小(例如，不同高度及/或表面積)，且在其他實施例中，積體電路晶粒114可為相同大小(例如，相同高度及/或表面積)。
在黏附至介電層108之前，可根據適用製造製程來處理 積體電路晶粒114，以在積體電路晶粒114中形成積體電路。舉例而言，積體電路晶粒114各自包含半導體基底118，諸如摻雜或未摻雜矽或絕緣層上半導體(semiconductor-on-insulator；SOI)基底的主動層。半導體基底可包含其他半導體材料，諸如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含矽鍺(SiGe)、磷化鎵砷(GaAsP)、砷化銦鋁(AlInAs)、砷化鎵鋁(AlGaAs)、砷化銦鎵(GaInAs)、磷化銦鎵(GaInP)及/或磷砷化銦鎵(GaInAsP)；或其組合。亦可使用其他基底，諸如多層基底或梯度基底。諸如電晶體、二極體、電容器、電阻器等元件可形成於半導體基底118中及/或形成於半導體基底118上，且可藉由例如由半導體基底118上的一或多個介電層中的金屬化圖案形成的互連結構120互連，以形成積體電路。
積體電路晶粒114進一步包括焊墊122(諸如鋁焊墊)，對焊墊122進行外部連接。焊墊122在可稱為積體電路晶粒114之各別主動側的物件上。鈍化膜124在積體電路晶粒114上且在焊墊122之部分上。開口穿過鈍化膜124至焊墊122。諸如導電柱(例如，包括諸如銅之金屬)之晶粒連接件126在穿過鈍化膜124的開口中，且機械及電性耦接至各別焊墊122。晶粒連接件126可藉由例如電鍍或類似者形成。晶粒連接件126電性耦接積體電路晶粒114之各別積體電路。
介電材料128在積體電路晶粒114之主動側上，諸如在鈍化膜124及晶粒連接件126上。介電材料128側向地包封晶粒連接件126，且介電材料128與各別積體電路晶粒114側向地有共同邊界。介電材料128可為聚合物，諸如PBO、聚醯亞胺、BCB 或類似者；氮化物，諸如氮化矽或類似者；氧化物，諸如氧化矽、PSG、BSG、BPSG或其類似者；其類似者或其組合，且可例如藉由旋轉塗佈、疊層、CVD或其類似者形成。
黏著劑116在積體電路晶粒114之背側上且將積體電路晶粒114黏附至背側重佈線結構110，諸如介電層108。黏著劑116可為任何合適之黏著劑、環氧樹脂、晶粒貼合膜(die attach film；DAF)或其類似者。黏著劑116可塗覆於積體電路晶粒114之背側，諸如塗覆於各別半導體晶圓之背側，或可塗覆於載體基底100的表面上方。可藉由諸如鋸割或切割而使積體電路晶粒114單體化，且使用例如抓放工具(pick-and-place tool)藉由黏著劑116將積體電路晶粒114黏附至介電層108。
在圖6中，包封體130形成於各種組件上。包封體130可為模製化合物、環氧樹脂或其類似者，且可藉由壓縮模製(compression molding)、轉移模製(transfer molding)或其類似者來應用。包封體130可在載體基底100上方形成，以使得內埋或覆蓋穿孔112及/或積體電路晶粒114之晶粒連接件126。隨後固化包封體130。
在圖7中，對包封體130執行平坦化製程以暴露穿孔112及晶粒連接件126。平坦化製程亦可研磨介電材料128。穿孔112之頂部表面、晶粒連接件126、介電材料128以及包封體130在平坦化製程之後共面。平坦化製程可為例如化學機械研磨(chemical-mechanical polish；CMP)、研磨(grinding)製程或其類似者。在一些實施例中，例如，若穿孔112及晶粒連接件126已暴露，則可省略平坦化。
在圖8至圖13中，形成前側重佈線結構132。如將說明，前側重佈線結構132包含介電層136、介電層148、介電層164、介電層170，且亦包含金屬化圖案。金屬化圖案亦可稱為重佈線層或重佈線，且包含導通孔134、導通孔146、導通孔162、導通孔168以及導電線144、導電線160、導電線166。因為前側重佈線結構132為精細間距重佈線結構，所以導電線144、導電線160、導電線166可具有在約1微米或更小的相鄰線之間的間距，且導電線144、導電線160、導電線166可具有約1微米或更小之平均寬度。
在圖8中，形成電性連接至例如穿孔112及/或晶粒連接件126之導通孔134。介電層136隨後沈積於導通孔134上及周圍，且沈積於包封體130、穿孔112以及晶粒連接件126上。圖9A至圖9D為繪示用於形成導通孔134及介電層136之製程期間之區域650的更多細節之橫截面視圖。
在圖9A中，晶種層138形成於包封體130、穿孔112、晶粒連接件126以及介電材料128上。在一些實施例中，晶種層138為金屬層，其可為單層或包括由不同材料形成之多個子層的複合層。在一些實施例中，晶種層138包括鈦層及在鈦層上方之銅層。可使用例如PVD或其類似者形成晶種層138。罩幕層140在晶種層138上形成及圖案化。罩幕層140可為光阻劑，諸如單層光阻劑、三層光阻劑或其類似者。罩幕層140可藉由旋塗或其類似者形成且可暴露於光以用於圖案化。罩幕層140之圖案對應於穿孔。圖案化穿過罩幕層140形成開口142以暴露晶種層138。
在圖9B中，導電材料形成於罩幕層140之開口142中 且形成於晶種層138的暴露部分上。導電材料可藉由電鍍形成，諸如有電電鍍或無電式電鍍，或其類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁，或其類似者。移除上方未形成導電材料之罩幕層140及部分之晶種層138。在罩幕層140為光阻劑之實施例中，可藉由可接受的灰化或剝離製程移除罩幕層140，諸如使用氧電漿或其類似者。一旦移除罩幕層140，諸如使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)移除晶種層138之暴露部分。晶種層138之剩餘部分以及導電材料形成導通孔134。
在圖9C中，介電層136隨後沈積於包封體130、穿孔112、晶粒連接件126以及導通孔134上。在一些實施例中，介電層136由聚合物形成，聚合物可為可使用微影罩幕圖案化之感光性材料，諸如PBO、聚醯亞胺、BCB，或類似者。在其他實施例中，介電層136由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或其類似者。介電層136可藉由旋塗、疊層、CVD、其類似者或其組合形成。詳言之，介電層136共形地沈積於導通孔134上方以使得導通孔134之最頂部表面在介電層136之主表面上方延伸距離D1。距離D1可為約0.1微米至約0.5微米。換言之，介電層136「處於沈積下(under-deposited)」以使得鄰近導通孔134之間的介電層136之部分凹入導通孔134之頂部表面下方。
在圖9D中，執行移除製程以移除介電層136之部分，由此暴露導通孔134。移除製程使導通孔134及介電層136變薄。在移除製程之後，導通孔134之頂部表面在介電層136的主表面上方延伸距離D2，其中距離D2小於距離D1。距離D2可為約0.1 微米至約0.3微米。在進行沈積介電層136之後執行移除製程可避免形成盲孔(例如，減少導通孔134在移除製程之後仍被覆蓋之機會)。
在一些實施例中，移除製程為CMP，其中選擇CMP之參數以致使介電層136凹陷。凹陷可藉由選擇CMP之參數引入，所述參數諸如墊(pad)、研磨漿(slurry)或朝下壓力。可使用諸如聚胺甲酸酯(polyurethane；PU)研磨墊之軟墊，致使研磨更共形。可使用對介電層136之材料而言具有高度選擇性之研磨漿，諸如二氧化矽研磨漿，允許介電層136以比導通孔134更高之速率移除。舉例而言，可使用包括更溫和化學試劑或研磨劑之研磨漿。可使用較少朝下壓力，允許CMP對介電層136之材料而言更具選擇性，所述材料可為快速移除之有機材料。舉例而言，可使用約2磅/平方英吋至約5磅/平方英吋之朝下壓力。藉由增大介電層136相較於導通孔134之移除速率，可有意地引入凹陷，從而使介電層136在導通孔134之頂部下方凹入距離D2。
在一些實施例中，移除製程為CMP，隨後為回蝕製程。選擇CMP之參數以避免介電層136之凹陷。凹陷可藉由選擇上文所描述之CMP之參數來避免，以使得導通孔134及介電層136之移除速率類似。在執行CMP之後，導通孔134及介電層136之頂部表面實質上齊平。隨後執行回蝕製程以使介電層136變薄。回蝕製程以比導通孔134更高之速率移除介電層136。舉例而言，回蝕製程可與使用對介電層136之有機材料而言具有選擇性之蝕刻劑的乾式蝕刻製程一起執行，所述蝕刻劑諸如氧(O2)或氬(Ar)。
在整體平坦化製程中移除介電層136在導通孔134上方 之部分可比移除介電層136之剩餘部分更快。舉例而言，在相同CMP程序中，尤其當介電層136經歷特徵加載時，突起部分處之介電層136之移除速率可比沿主表面之介電層136之移除速率快高達十倍。因而，可執行較少平坦化以暴露穿過介電層136之導通孔134且使介電層136平坦化。
在圖10中，導電線144形成於介電層136上，電性連接至導通孔134。接著，形成電性連接至導電線144之導通孔146。介電層148隨後沈積於導電線144及導通孔146上及周圍。圖11A至圖11G為繪示用於形成導電線144、導通孔146以及介電層148之製程期間的區域650之更多細節之橫截面視圖。
在圖11A中，晶種層150形成於導通孔134及介電層136上方。詳言之，晶種層150沿介電層136之頂部表面、導通孔134之暴露側壁以及導通孔134之頂部表面延伸。在一些實施例中，晶種層150為金屬層，其可為單層或包括由不同材料形成之多個子層的複合層。在一些實施例中，晶種層150包括鈦層及在鈦層上方之銅層。可使用例如PVD或其類似者形成晶種層150。
在圖11B中，罩幕層152在晶種層150上形成及圖案化。罩幕層152可為光阻劑，諸如單層光阻劑、三層光阻劑或其類似者。罩幕層152可藉由旋塗或其類似者形成且可暴露於光以用於圖案化。罩幕層152之圖案對應於導電線144。圖案化穿過罩幕層152形成開口154以暴露晶種層150。因為底層介電層136之主表面為平面，所以罩幕層152可形成為實質上均一厚度。因而，罩幕層152可更一致地鋪展，其可減少殘餘罩幕層152覆蓋晶種層150在開口154中之部分的機會。
在圖11C中，導電材料形成於罩幕層152之開口154中且形成於晶種層150的暴露部分上。導電材料可藉由電鍍形成，諸如有電電鍍或無電式電鍍，或其類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁，或其類似者。隨後，移除罩幕層152。在罩幕層152為光阻劑之實施例中，可藉由可接受的灰化或剝離製程移除罩幕層152，諸如使用氧電漿或其類似者。導電材料及導電材料下方之晶種層之部分形成導電線144。因為導通孔134延伸至介電層136上方，電線144之部分具有升高之拓樸(topology)。導通孔134上方之導電線144之部分可具有凸面形狀，以使得導通孔134上方的導電線144之頂部表面在非導通孔134上方的導電線144之頂部表面上方升高距離D3。距離D3可為約0微米至約0.2微米。換言之，導電線144在導通孔134上方不具凹陷。在一些實施例，諸如距離D2較小之實施例中，導通孔134上方之導電線144的部分可不為凸面形狀，且可相反為實質上扁平的。在形成之後，導通孔134及晶種層150部分地延伸至導電線144之各別導電線中，由此在導通孔134與導電線144之間形成錨定連接件。
在圖11D中，罩幕層156在導電線144及晶種層150上形成及圖案化。罩幕層156可為光阻劑，諸如單層光阻劑、三層光阻劑或其類似者。罩幕層156可藉由旋塗或其類似者形成且可暴露於光以用於圖案化。罩幕層156之圖案對應於導通孔146。圖案化穿過罩幕層156形成開口158以暴露導電線144之部分。因為底層介電層136之主表面為平面，所以罩幕層156可形成為實質上均一厚度。因而，罩幕層156可更一致地鋪展，其可減少殘餘罩幕層156覆蓋導電線144在開口158中之部分的機會。
在圖11E中，導電材料形成於罩幕層156之開口158中且形成於導電線144的暴露部分上。導電材料可藉由電鍍形成，諸如有電電鍍或無電式電鍍，或其類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁，或其類似者。
接著，移除上方未形成導電線144之罩幕層156及部分之晶種層150。在罩幕層156為光阻劑之實施例中，可藉由可接受的灰化或剝離製程移除罩幕層156，諸如使用氧電漿或其類似者。一旦移除罩幕層156，諸如使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)移除晶種層150之暴露部分。開口158中之導電材料形成導通孔146。
在圖11F中，介電層148沈積於介電層136、導電線144以及導通孔146上。在一些實施例中，介電層148由聚合物形成，聚合物可為可使用微影罩幕圖案化之感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層148由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或其類似者。介電層148可藉由旋塗、疊層、CVD、其類似者，或其組合形成。詳言之，介電層148共形地沈積於導電線144及導通孔146上方，以使得導通孔146之最頂部表面在介電層148之主表面上方延伸距離D4。距離D4可為約0.1微米至約0.5微米，且可與距離D1相同。換言之，介電層148處於沈積下以使得相鄰導通孔146之間的介電層148之部分凹入導通孔146之頂部表面下方。
在圖11G中，執行移除製程以移除介電層148之部分，由此暴露導通孔146。移除製程使導通孔146及介電層148變薄。 移除製程可類似與上文圖9D中所繪示之移除製程。
在圖12中，導電線160形成於介電層148上，電性連接至導通孔146。接著，形成電性連接至導電線160之導通孔162。介電層164隨後沈積於導電線160及導通孔162上及周圍。導電線160、導通孔162以及介電層164可以與導電線144、導通孔146以及介電層148類似之方式形成。
在圖13中，導電線166形成於介電層164上，電性連接至導通孔162。接著，形成電性連接至導電線166之導通孔168。介電層170隨後沈積於導電線166及導通孔168上及周圍。導電線166、導通孔168以及介電層170可以與導電線144、導通孔146以及介電層148類似之方式形成。
前側重佈線結構132作為實例示出。更多或更少介電層、金屬化圖案以及導通孔可形成於前側重佈線結構132中。若將形成更少介電層、金屬化圖案或導通孔，則可省略上文所論述之步驟及製程。若將形成較多介電層、金屬化圖案以及導通孔，則可重複上文所論述之步驟及製程。所屬領域中具有通常知識者將易於理解將省略或重複哪些步驟及製程。
在圖14中，導電墊172形成於前側重佈線結構132之外部側上。導電墊172可稱為凸塊下金屬(under bump metallurgy；UBM)。在所繪示之實施例中，形成電性及實體地耦接至導通孔168之導電墊172。導電墊172以與導電線144、導電線160、導電線166類似之方式形成，以使得導通孔168延伸至導電墊172中。作為形成導電墊172之實例，晶種層(未繪示)形成於介電層170及導通孔168上方，且形成於導通孔168之側壁上。在一些實施例 中，晶種層為金屬層，金屬層可為單層或包括由不同材料形成之多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方之銅層。可使用例如PVD或其類似者形成晶種層。隨後在晶種層上形成及圖案化光阻劑(未繪示)。光阻劑可藉由旋塗或其類似者形成且可暴露於光以用於圖案化。光阻劑之圖案對應於導電墊172。圖案化穿過光阻劑形成開口以暴露晶種層。導電材料形成於光阻劑之開口中且形成於晶種層之暴露部分上。導電材料可藉由電鍍形成，諸如有電電鍍或無電式電鍍，或其類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁，或其類似者。隨後，移除上方未形成導電材料之光阻劑及部分之晶種層。可藉由可接受的灰化或剝離製程移除光阻劑，諸如使用氧電漿或其類似者。一旦移除光阻劑，諸如使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)移除晶種層之暴露部分。晶種層之剩餘部分以及導電材料形成導電墊172。
在圖15中，導電連接件174形成於導電墊172上。導電連接件174可為球柵陣列封裝(BGA)連接件、焊料球、金屬柱、受控塌陷晶粒連接(controlled collapse chip connection；C4)凸塊、微型凸塊、無電式鍍鎳鈀浸金(electroless nickel-electroless palladium-immersion gold technique；ENEPIG)技術形成的凸塊，或其類似者。導電連接件174可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、其類似者或其組合。在一些實施例中，形成導電連接件174是藉由諸如蒸鍍、有電電鍍、列印、焊料轉移(solder transfer)、植球(ball placement)或其類似者之此等常用方法先形成焊料層。一旦焊料層已形成於結構上，則可執行回焊以便 將材料塑形成所要的凸塊形狀。在另一實施例中，導電連接件174為藉由濺鍍、列印、有電電鍍、無電式電鍍、CVD或其類似者所形成的金屬柱(諸如銅柱)。金屬柱可為無焊料且具有實質上豎直之側壁。在一些實施例中，金屬頂蓋層(未繪示)形成於金屬柱之頂部上。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、其類似者、或其組合，且可由電鍍製程形成。
在圖16中，執行載體基底剝離以將載體基底100自背側重佈線結構110(例如，介電層104)拆離(剝離)。第一封裝體200由此形成於第一封裝區域600及第二封裝區域602中之每一者中。根據一些實施例，剝離包含使諸如雷射光或UV光的光投影於釋放層102上，以使得釋放層102在光熱下分解且可移除載體基底100。接著翻轉結構且將其置放於膠帶176上。另外，穿過介電層104形成開口178以暴露金屬化圖案106之部分。舉例而言，可使用雷射鑽孔、蝕刻或其類似者形成開口178。
圖17至圖18繪示根據一些實施例用於形成封裝結構500之製程期間的中間步驟之橫截面視圖。封裝結構500可稱為疊層封裝(PoP)結構。
在圖17中，第二封裝體300附接至第一封裝體200。第二封裝體300包含基底302及耦接至基底302之一或多個堆疊式晶粒308(堆疊式晶粒308A及堆疊式晶粒308B)。儘管繪示單個堆疊晶粒308(晶粒308A及晶粒308B)，但在其他實施例中，多個堆疊式晶粒308(各自具有一或多個堆疊式晶粒)可設置成並排地耦接至基底302之同一表面。基底302可由半導體材料製成，諸如矽、鍺、金剛石或其類似者。在一些實施例中，亦可使用化合 物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、矽鍺碳化物、磷化砷化鎵、磷化鎵銦、此等之組合及其類似者。另外，基底302可為絕緣體上矽(silicon-on-insulator；SOI)基底。通常，SOI基底包含諸如磊晶矽、鍺、矽鍺、SOI、絕緣體上矽鍺(silicon germanium on insulator；SGOI)或其組合之半導體材料層。在一個替代實施例中，基底302是基於諸如玻璃纖維補強樹脂核心(fiberglass reinforced resin core)之絕緣核心。一種實例核心材料為諸如FR4之玻璃纖維樹脂。核心材料之替代物包含雙馬來醯亞胺三嗪(bismaleimide-triazine；BT)樹脂、或替代地包括其他印刷電路板(PCB)材料或膜。組成膜(build up film)，諸如味之素組成膜(Ajinomoto build-up film；ABF)或其他疊層可用於基底302。
基底302可包含主動元件及被動元件(未繪示)。如所屬領域中具有通常知識者將理解到，諸如電晶體、電容器、電阻器、此等之組合及其類似者之廣泛多種元件可用於產生第二封裝體300的結構及功能要求的設計。這些元件可使用任何適合之方法形成。
基底302亦可包含金屬化層(未繪示)及穿孔306。金屬化層可形成於主動元件及被動元件上方，且經設計以連接各種元件以形成功能電路。金屬化層可由介電材料(例如，低k介電材料)與導電材料(例如銅)之交替層形成，其中通孔互連導電材料層且可經由任何適合的製程(諸如沈積、鑲嵌、雙鑲嵌或其類似者)形成。在一些實施例中，基底302實質上不含主動元件及被動元件。
基底302可在基底302之第一側上具有接合墊303以耦 接至堆疊式晶粒308，且在基底302的第二側上具有接合墊304，以耦接至導電連接件314，所述第二側與基底302之第一側相對。在一些實施例中，藉由在基底302之第一側及第二側上形成凹陷(未繪示)至介電層(未繪示)中來形成接合墊303及接合墊304。可形成凹陷以允許接合墊303及接合墊304嵌入於介電層中。在其他實施例中，省略凹陷，這是因為接合墊303及接合墊304可形成於介電層上。在一些實施例中，接合墊303及接合墊304包含由銅、鈦、鎳、金、鈀、其類似者或其組合製成之薄晶種層(未繪示)。接合墊303及接合墊304之導電材料可沈積於薄晶種層上方。可藉由電化學電鍍製程、無電式電鍍製程、CVD、ALD、PVD、其類似者或其組合形成導電材料。在一實施例中，接合墊303及接合墊304之導電材料為銅、鎢、鋁、銀、金、其類似者或其組合。
在一實施例中，接合墊303及接合墊304為包含三個導電材料層(諸如鈦層、銅層以及鎳層)之UBM。然而，一般所屬本領域中具有通常知識者將認識到，存在適合形成接合墊303及接合墊304之許多適合之材料及層的配置，諸如鉻/鉻銅合金/銅/金之配置、鈦/鈦鎢/銅之配置，或銅/鎳/金的配置。可用於接合墊303及接合墊304之任何適合的材料或材料層全部意欲包含於本申請案之範疇內。在一些實施例中，穿孔306延伸穿過基底302且將至少一個接合墊303耦接至至少一個接合墊304。
在所說明之實施例中，堆疊式晶粒308藉由電線接合310耦接至基底302，但可使用其他連接件，諸如導電凸塊。在一實施例中，堆疊式晶粒308為堆疊式記憶體晶粒。舉例而言，堆疊 式晶粒308可為諸如低功率(low-power；LP)雙資料速率(double data rate；DDR)記憶體模組之記憶體晶粒，諸如LPDDR1、LPDDR2、LPDDR3、LPDDR4或其類似記憶體模組。
堆疊式晶粒308及電線接合310可藉由模製材料312包封。可例如使用壓縮模製將模製材料312模製於堆疊式晶粒308及電線接合310上。在一些實施例中，模製材料312為模製化合物、聚合物、環氧樹脂、氧化矽填充物材料、其類似者或其組合。可執行固化步驟以固化模製材料312，其中固化可為熱固化、UV固化、其類似者或其組合。
在一些實施例中，堆疊式晶粒308及電線接合310埋入於模製材料312中，且在固化模製材料312之後，執行諸如研磨的平坦化步驟以移除模製材料312之過量部分且為第二封裝體300提供實質上平面之表面。
在形成第二封裝體300之後，第二封裝體300藉助於導電連接件314、接合墊304以及金屬化圖案106機械地及電性接合至第一封裝體200。在一些實施例中，堆疊式晶粒308可經由電線接合310、接合墊303以及接合墊304、穿孔306、導電連接件314以及穿孔112耦接至積體電路晶粒114。
導電連接件314可類似於上文所描述之導電連接件174，且在此不再贅述，而導電連接件314與導電連接件174不必相同。導電連接件314可設置於開口178中之基底302與堆疊式晶粒308相對的側上。在一些實施例中，阻焊劑亦可形成於與堆疊式晶粒308相對的基底302之一側上。導電連接件314可設置於阻焊劑中之開口中以電性及機械地耦接至基底302中之導電特 徵(例如，接合墊304)。阻焊劑可用於保護基底302之區域不受外部損害。
在一些實施例中，在接合導電連接件314之前，導電連接件314塗佈有助焊劑(flux)(未繪示)，諸如免清助焊劑。導電連接件314可浸漬於助焊劑中，或助焊劑可噴射至導電連接件314上。在另一實施例中，助焊劑可塗覆於金屬化圖案106之表面。
在一些實施例中，在第二封裝體300附接至第一封裝體200之後，在導電連接件314與剩餘的環氧樹脂助焊劑之環氧樹脂部分中之至少一些回焊之前，導電連接件314可具有視情況選用之環氧樹脂助焊劑(未繪示)形成於其上。
底填充料(未繪示)可形成於第一封裝體200與第二封裝體300之間且包圍導電連接件314。底填充料可減小應力且保護由導電連接件314之回焊產生的接點。底填充料可在附接第一封裝體200之後藉由毛細流動製程形成或可在附接第一封裝體200之前藉由適合的沈積方法形成。在形成環氧樹脂助焊劑之實施例中，環氧樹脂助焊劑可充當底填充料。
第二封裝體300與第一封裝體200之間的接合可為焊料接合。在一實施例中，藉由回焊製程將第二封裝體300接合至第一封裝體200。在此回焊製程期間，導電連接件314與接合墊304以及金屬化圖案106接觸，以將第二封裝體300實體且電性耦接至第一封裝體200。在接合製程之後，金屬間化合物(intermetallic compound；IMC，未繪示)可形成於金屬化圖案106與導電連接件314之界面處，且亦形成於導電連接件314與接合墊304(未繪示)之間的界面處。
藉由沿例如第一封裝區域600與第二封裝區域602之間的切割道區域鋸割執行單體化製程。鋸割使第一封裝區域600自第二封裝區域602單體化。所得單體化之第一封裝體200及第二封裝體300來自第一封裝區域600或第二封裝區域602中之一者。在一些實施例中，在將第二封裝體300附接至第一封裝體200之後執行單體化製程。在其他實施例(未繪示)中，在第二封裝體300附接至第一封裝體200之前，諸如在剝離載體基底100且形成開口178之後，執行單體化製程。
在圖18中，第一封裝體200使用導電連接件174安裝至封裝基底400。封裝基底400可由半導體材料製成，諸如矽、鍺、金剛石或其類似者。替代地，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、矽鍺碳化物、磷化砷化鎵、磷化鎵銦、此等之組合及其類似者。另外，封裝基底400可為SOI基底。大體而言，SOI基底包含半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合。在一個替代實施例中，封裝基底400是基於諸如玻璃纖維補強樹脂核心之絕緣核心。一種實例核心材料為諸如FR4之玻璃纖維樹脂。核心材料之替代物包含雙馬來醯亞胺三嗪BT樹脂，或替代地，其他PCB材料或膜。諸如ABF或其他疊層之組成膜可用於封裝基底400。
封裝基底400可包含主動元件及被動元件(未繪示)。如所屬領域中具有通常知識者將理解到，諸如電晶體、電容器、電阻器、此等之組合及其類似者之廣泛多種元件可用於產生用於封裝結構500的結構以及功能要求之設計。這些元件可使用任何適合之方法形成。
封裝基底400亦可包含金屬化層及通孔(未繪示)，以及在金屬化層及通孔上方之接合墊402。金屬化層可形成於主動元件及被動元件上方，且設計為連接各種元件以形成功能電路。金屬化層可由介電材料(例如，低k介電材料)與導電材料(例如，銅)之交替層形成，其中通孔互連導電材料層且可經由任何適合的製程(諸如沈積、鑲嵌、雙鑲嵌或其類似者)形成。在一些實施例中，封裝基底400實質上不含主動元件及被動元件。
在一些實施例中，回焊導電連接件174以將第一封裝體200附接至接合墊402。導電連接件174將封裝基底400(包含封裝基底400中之金屬化層)電性及/或實體耦接至第一封裝體200。在一些實施例中，可在安裝在封裝基底400上之前將被動元件(例如，表面安裝元件(surface mount devices；SMD))附接至第一封裝體200(例如，接合至接合墊402)。在此等實施例中，被動元件可接合至第一封裝體200的與導電連接件174相同的表面。
在第一封裝體200附接至封裝基底400之後，在導電連接件174與剩餘的環氧樹脂助焊劑的環氧樹脂部分中之至少一些回焊之前，導電連接件174可具有環氧樹脂助焊劑(未繪示)形成於其上。此剩餘環氧樹脂部分可充當底填充料以減小應力且保護產生於導電連接件174之回焊的接點。在一些實施例中，底填充料(未繪示)可形成於第一封裝體200與封裝基底400之間，且包圍導電連接件174。底填充料可在附接第一封裝體200之後藉由毛細流動製程形成或可在附接第一封裝體200之前藉由適合的沈積方法形成。
實施例可實現優勢。在導通孔與金屬化圖案之間形成錨 定連接件可改良導通孔與金屬化圖案之間的界面之機械強度，可改良元件可靠性。另外，導通孔上方及周圍之沈積下的介電層可允許導通孔更易於穿過介電層而顯露、減少形成盲孔之機會，例如，不貫穿各別介電層以完全暴露之通孔。
在一實施例中，一種半導體元件包含：積體電路晶粒；鄰近積體電路晶粒之穿孔；包封積體電路晶粒及穿孔之模製化合物；以及重佈線結構，其包含：延伸穿過第一介電層之第一導通孔，第一導通孔電性連接至積體電路晶粒，第一介電層在積體電路晶粒、穿孔以及模製化合物上方；以及在第一介電層及第一導通孔上方之第一導電線，第一導通孔延伸至第一導電線中。
在一些實施例中，第一導通孔之最頂部表面在第一介電層之最頂部表面上方延伸。在一些實施例中，第一導電線包含：沿第一介電層之最頂部表面、第一導通孔之側面以及第一導通孔之最頂部表面延伸的晶種層；以及設置於晶種層上之導電材料。在一些實施例中，第一導電線具有第一部分及第二部分，第一部分設置於第一導通孔上方，第一部分之最頂部表面設置得比第二部分之最頂部表面設置得離第一介電層更遠。在一些實施例中，重佈線結構更包含：延伸穿過第二介電層之第二導通孔，第二導通孔電性連接至第一導電線，第二介電層在第一介電層及第一導電線上方。在一些實施例中，半導體元件更包含：在第二介電層及第二導通孔上方之導電墊，第二導通孔延伸至導電墊中；以及導電墊上之導電連接件。在一些實施例中，半導體元件更包含：連接至導電連接件之第一基底；以及連接至穿孔之第二基底。在一些實施例中，在第一導通孔上方之第一導電線的部分具有凸面形狀。
在一實施例中，一種形成半導體元件的方法包含：使用模製化合物包封積體電路晶粒，積體電路晶粒具有晶粒連接件；在積體電路晶粒之晶粒連接件上形成第一導通孔；在積體電路晶粒、模製化合物以及第一導通孔上方沈積第一介電層，第一介電層沿第一導通孔之側壁及頂部表面延伸，第一導通孔的頂部表面在第一介電層之主表面上方；移除第一介電層在第一導通孔之側壁及頂部表面上的部分，由此暴露第一導通孔之一部分；以及在第一介電層及第一導通孔之暴露部分上形成第一導電線。
在一些實施例中，移除第一介電層之部分包含：在第一介電層上執行平坦化製程，第一導通孔之側壁及頂部表面在平坦化製程之後暴露。在一些實施例中，以2磅/平方英吋至5磅/平方英吋之朝下壓力執行平坦化製程直至第一導通孔之暴露部分在第一介電層之主表面上方延伸0.1米至0.5米之距離。在一些實施例中，移除第一介電層之部分包含：在第一介電層及第一導通孔上執行平坦化製程，第一介電層及第一導通孔之頂部表面齊平；以及在第一介電層上執行蝕刻製程，第一導通孔之側壁及頂部表面在蝕刻製程之後暴露。在一些實施例中，第一介電層為有機介電材料，且蝕刻製程為以氧或氬執行之乾式蝕刻製程。在一些實施例中，在第一導通孔上方之第一導電線的部分具有凸面形狀。在一些實施例中，在第一導通孔上方之第一導電線的部分具有扁平形狀。
在一實施例中，一種形成半導體元件的方法包含：將積體電路晶粒置放在第一介電層上，積體電路晶粒具有晶粒連接件；使用模製化合物包封積體電路晶粒；在積體電路晶粒之晶粒連接件上形成第一導通孔，第一導通孔具有設置為離第一介電層第一 距離的最頂部表面；在積體電路晶粒、模製化合物以及第一導通孔上沈積第二介電層，第二介電層具有設置為離第一介電層第二距離之主表面，第一距離大於第二距離；移除第二介電層之部分以暴露第一導通孔之側面及最頂部表面；以及在第一導通孔上形成第一導電線，第一導電線與第一導通孔之側面及最頂部表面接觸。
在一些實施例中，形成第一導通孔包含：在積體電路晶粒及模製化合物上沈積第一晶種層；在第一晶種層上形成第一罩幕層；圖案化第一罩幕層中之第一開口；在第一開口中電鍍第一導電材料；以及移除第一罩幕層以及第一晶種層的暴露部分，第一導電材料以及第一晶種層之剩餘部分形成第一導通孔。在一些實施例中，形成第一導電線包含：在第二介電層上以及在第一導通孔之側面及最頂部表面上沈積第二晶種層；在第二晶種層上形成第二罩幕層；圖案化第一導通孔上方之第二罩幕層中的第二開口；以及從第二開口中之第二晶種層電鍍第二導電材料，第二導電材料以及在第二導電材料之下的第二晶種層之部分形成第一導電線。在一些實施例中，方法更包含：在第二導電材料及第二晶種層上形成第三罩幕層；圖案化第二導電材料上方之第三罩幕層中之第三開口；從第三開口中的第二導電材料電鍍第三導電材料；移除第三罩幕層以及第二晶種層之暴露部分，第三導電材料以及第二晶種層的剩餘部分形成第二導通孔；以及在第二介電層、第一導電線以及第二導通孔上沈積第三介電層。在一些實施例中，在第一導通孔上方之第一導電材料的部分具有凸面形狀。
前文概述若干實施例之特徵，使得所屬領域中具通常知識者可更好地理解本揭露內容的態樣。所屬領域中具通常知識者 應理解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入之實施例的相同目的且/或達成相同優點的其他處理程序及結構的基礎。所述領域具通常知識者亦應認識到，此類等效構造並不脫離本揭露內容之精神及範疇，且其可在不脫離本揭露內容的精神及範疇之情況下在本文中進行作出改變、替代及更改。
100‧‧‧載體基底
102‧‧‧釋放層
104、108、136、148‧‧‧介電層
106‧‧‧金屬化圖案
110‧‧‧背側重佈線結構
112‧‧‧穿孔
114‧‧‧積體電路晶粒
116‧‧‧黏著劑
130‧‧‧包封體
132‧‧‧前側重佈線結構
134、146‧‧‧導通孔
144‧‧‧導電線
600‧‧‧第一封裝區域
602‧‧‧第二封裝區域
650‧‧‧區域

Claims (12)

  1. 一種半導體元件，包括：積體電路晶粒；穿孔，鄰近所述積體電路晶粒；模製化合物，包封所述積體電路晶粒及所述穿孔；以及重佈線結構，包括：第一導通孔，延伸穿過第一介電層，所述第一導通孔電性連接至所述積體電路晶粒，所述第一介電層在所述積體電路晶粒、所述穿孔以及所述模製化合物上方，且所述第一導通孔之最頂部表面在所述第一介電層之最頂部表面上方延伸；以及第一導電線，在所述第一介電層及所述第一導通孔上方，所述第一導通孔延伸至所述第一導電線中，其中所述第一導電線包括：晶種層，沿所述第一介電層之所述最頂部表面、所述第一導通孔之側面以及所述第一導通孔之所述最頂部表面延伸；以及導電材料，設置於所述晶種層上。
  2. 如申請專利範圍第1項所述的半導體元件，其中所述第一導電線具有第一部分及第二部分，所述第一部分設置於所述第一導通孔上方，所述第一部分之最頂部表面比所述第二部分之最頂部表面設置得離所述第一介電層更遠。
  3. 如申請專利範圍第1項所述的半導體元件，其中所述重佈線結構更包括：第二導通孔，延伸穿過第二介電層，所述第二導通孔電性連 接至所述第一導電線，所述第二介電層在所述第一介電層及所述第一導電線上方。
  4. 如申請專利範圍第3項所述的半導體元件，更包括：導電墊，在所述第二介電層及所述第二導通孔上方，所述第二導通孔延伸至所述導電墊中；以及導電連接件，在所述導電墊上。
  5. 如申請專利範圍第4項所述的半導體元件，其中所述第一導通孔上方之所述第一導電線的部分具有凸面形狀。
  6. 一種形成半導體元件的方法，包括：使用模製化合物包封積體電路晶粒，所述積體電路晶粒具有晶粒連接件；在所述積體電路晶粒之所述晶粒連接件上形成第一導通孔；在所述積體電路晶粒、所述模製化合物以及所述第一導通孔上方沈積第一介電層，所述第一介電層沿所述第一導通孔之側壁及頂部表面延伸，所述第一導通孔之所述頂部表面在所述第一介電層的主表面上方；移除所述第一介電層在所述第一導通孔之所述側壁及所述頂部表面上的部分，由此暴露所述第一導通孔之一部分；以及在所述第一介電層及所述第一導通孔之所述暴露部分上形成第一導電線。
  7. 如申請專利範圍第6項所述的方法，其中所述移除所述第一介電層之所述部分包括：在所述第一介電層上執行平坦化製程，所述第一導通孔之所述側壁及所述頂部表面在所述平坦化製程之後暴露。
  8. 如申請專利範圍第7項所述的方法，其中以2磅/平方英吋至5磅/平方英吋之朝下壓力執行所述平坦化製程直至所述第一導通孔之所述暴露部分在所述第一介電層之所述主表面上方延伸0.1微米至0.5微米的距離。
  9. 如申請專利範圍第6項所述的方法，其中所述移除所述第一介電層之所述部分包括：在所述第一介電層及所述第一導通孔上執行平坦化製程，所述第一介電層及所述第一導通孔之頂部表面齊平；以及在所述第一介電層上執行蝕刻製程，所述第一導通孔之所述側壁及所述頂部表面在所述蝕刻製程之後暴露。
  10. 一種形成半導體元件的方法，包括：將積體電路晶粒置放在第一介電層上，所述積體電路晶粒具有晶粒連接件；使用模製化合物包封所述積體電路晶粒；在所述積體電路晶粒之所述晶粒連接件上形成第一導通孔，所述第一導通孔具有設置為離所述第一介電層第一距離之最頂部表面；在所述積體電路晶粒、所述模製化合物以及所述第一導通孔上沈積第二介電層，所述第二介電層具有設置為離所述第一介電層第二距離之主表面，所述第一距離大於所述第二距離；移除所述第二介電層之部分以暴露所述第一導通孔之側面及所述最頂部表面；以及在所述第一導通孔上形成第一導電線，所述第一導電線與所述第一導通孔之所述側面及所述最頂部表面接觸。
  11. 如專利申請範圍第10項所述的方法，其中所述形成所述第一導通孔包括：在所述積體電路晶粒及所述模製化合物上沈積第一晶種層；在所述第一晶種層上形成第一罩幕層；圖案化所述第一罩幕層中之第一開口；在所述第一開口中電鍍第一導電材料；以及移除所述第一罩幕層以及所述第一晶種層之暴露部分，所述第一導電材料以及所述第一晶種層之剩餘部分形成所述第一導通孔。
  12. 如專利申請範圍第11項所述的方法，其中所述形成所述第一導電線包括：在所述第二介電層以及所述第一導通孔之所述側面及所述最頂部表面上沈積第二晶種層；在所述第二晶種層上形成第二罩幕層；圖案化所述第一導通孔上方之所述第二罩幕層中之第二開口；以及從所述第二開口中之所述第二晶種層電鍍第二導電材料，所述第二導電材料以及在所述第二導電材料之下的所述第二晶種層之部分形成所述第一導電線。
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