CN111312726B - Array substrate, manufacturing method thereof and display device - Google Patents
Array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN111312726B CN111312726B CN202010118718.6A CN202010118718A CN111312726B CN 111312726 B CN111312726 B CN 111312726B CN 202010118718 A CN202010118718 A CN 202010118718A CN 111312726 B CN111312726 B CN 111312726B
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- 239000000758 substrate Substances 0.000 title claims abstract description 77
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 21
- 230000008569 process Effects 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 316
- 239000011810 insulating material Substances 0.000 claims description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 10
- 238000004380 ashing Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 18
- 239000002245 particle Substances 0.000 description 6
- 238000001514 detection method Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract
The invention discloses an array substrate, a manufacturing method thereof and a display device, comprising the following steps: a substrate, a touch transistor and a display transistor on the substrate; wherein, touch transistor includes: a first active layer, a first gate insulating layer, and a first gate electrode stacked; a display transistor, comprising: a second active layer, a second gate insulating layer, and a second gate electrode stacked; the thickness of the first gate insulating layer is greater than the thickness of the second gate insulating layer. The thick gate insulating layer is deposited, the thick first gate insulating layer is formed by carrying out primary etching on the gate insulating layer in the area where the touch transistor is located through a half exposure process, and the thinned second gate insulating layer is formed by carrying out secondary etching on the gate insulating layer in the area where the display transistor is located, so that bright spots and dark spots caused by the defect of the gate insulating layer are effectively improved, the characteristics of the touch transistor and the display transistor are ensured, and the product quality is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof and a display device.
Background
Active matrix electroluminescent display products (AMOLED) are currently moving towards high definition, large size and high refresh frequency. This places a higher demand on the transistor (TFT) performance of the AMOLED driving circuit. The TFT structures currently used in AMOLED driving circuits mainly include an etch stop layer structure (ESL), a Top Gate structure (Top Gate), and a back channel etch structure (BCE). The Gate electrode and the source electrode of the Top Gate structure are not overlapped, so that parasitic capacitance can be effectively reduced, the refresh frequency is better, the size is smaller, and the requirement of AMOLED development can be met, so that the Top Gate structure is an important direction of research and development.
However, the Gate insulating layer (GI) of the Top Gate structure formed by the deposition process has uneven film thickness distribution, which causes a weak area of the GI film to be easily stripped (Peeling) during the subsequent high-temperature annealing process of the GI film; in addition, due to thinner GI film layerGI is easily detached during subsequent washing, resulting in GI loss. In this way, the Gate and the active layer separated by the GI film layer in the TFT may cause defects such as short-circuit (Gate-IGZO short) between the Gate and the active layer due to GI loss.
Disclosure of Invention
In view of the above, the embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device, which are used for reducing bright spots and dark spot defects caused by GI deficiency and improving product quality.
Therefore, the array substrate provided by the embodiment of the invention comprises: a substrate, a touch transistor and a display transistor which are positioned on the substrate;
wherein, touch transistor includes: a first active layer, a first gate insulating layer, and a first gate electrode stacked;
the display transistor includes: a second active layer, a second gate insulating layer, and a second gate electrode stacked;
the thickness of the first gate insulating layer is greater than the thickness of the second gate insulating layer.
In a possible implementation manner, in the above array substrate provided by the embodiment of the present invention, the method further includes: and the third gate insulating layer and the gate line are stacked, and the thickness of the third gate insulating layer is zero.
In a possible implementation manner, in the above array substrate provided by the embodiment of the present invention, the touch transistor further includes: and a first source electrode and a first drain electrode electrically connected with the first active layer.
In a possible implementation manner, in the above array substrate provided by the embodiment of the present invention, the display transistor further includes: and a second source electrode and a second drain electrode electrically connected to the second active layer.
In a possible implementation manner, in the above array substrate provided by the embodiment of the present invention, the method further includes: a light shielding layer located between the substrate base plate and the second active layer;
the orthographic projection of the light shielding layer on the substrate is overlapped with the orthographic projection of the second active layer, and the second source electrode or the second drain electrode is electrically connected with the light shielding layer.
Based on the same inventive concept, the embodiment of the invention also provides a manufacturing method of the array substrate, which comprises the following steps:
providing a substrate base plate;
forming a touch transistor and a display transistor on the substrate;
wherein, touch transistor includes: a first active layer, a first gate insulating layer, and a first gate electrode stacked;
the display transistor includes: a second active layer, a second gate insulating layer, and a second gate electrode stacked;
the thickness of the first gate insulating layer is greater than the thickness of the second gate insulating layer.
In a possible implementation manner, in the above manufacturing method provided by the embodiment of the present invention, the method further includes: forming a third gate insulating layer and a gate line which are stacked, wherein the thickness of the third gate insulating layer is zero;
forming the first active layer, the second active layer, the first gate insulating layer, the second gate insulating layer, the third gate insulating layer, the gate line, the first gate electrode and the second gate electrode on the substrate, specifically including:
sequentially depositing an oxide material layer, an insulating material layer and a photoresist layer on the substrate;
exposing the photoresist layer by adopting a half-exposure mask plate, removing the photoresist layer positioned between a grid line area, a touch transistor area and a display transistor area and positioned in the grid line area, wherein the photoresist layer positioned outside the areas of the second grid electrodes in the touch transistor area and the display transistor area has a first thickness, and the photoresist layer positioned in the areas of the second grid electrodes has a second thickness smaller than the first thickness;
etching the insulating material layer, and reserving the insulating material layer positioned in the touch transistor area and the display transistor area;
ashing the photoresist layer to remove the photoresist layer with the second thickness in the display transistor area;
thinning the insulating material layer of the region where the second grid is located;
etching the oxide material layer to form the first active layer and the second active layer;
stripping the photoresist layer;
forming the gate line, the first gate electrode and the second gate electrode on the insulating material layer;
etching the insulating material layer, reserving the insulating material layer overlapped with the first grid electrode to form a first grid insulating layer, and forming a second grid insulating layer by the insulating material layer subjected to thinning treatment in the area where the second grid electrode is positioned;
and conducting the first active layer and the second active layer.
In a possible implementation manner, in the above manufacturing method provided by the embodiment of the present invention, after conducting the conducting treatment on the first active layer and the second active layer, the method further includes:
forming an interlayer dielectric layer on the layer where the first grid electrode and the second grid electrode are located in sequence, wherein the first source electrode and the first drain electrode of the touch transistor, the second source electrode and the second drain electrode of the display transistor and the data line with the extending direction crossing the grid line are formed;
the first source electrode and the first drain electrode are electrically connected with the first active layer through a first via hole of the interlayer dielectric layer;
the second source electrode and the second drain electrode are electrically connected with the second active layer through a second via hole of the interlayer dielectric layer.
In a possible implementation manner, in the above manufacturing method provided by the embodiment of the present invention, before forming the touch transistor and the display transistor on the substrate, the method further includes:
and forming a shading layer in the area where the display transistor is located, wherein the orthographic projection of the shading layer on the substrate and the orthographic projection of the second active layer are overlapped.
Based on the same inventive concept, an embodiment of the present invention further provides a display apparatus, including: the array substrate.
The invention has the following beneficial effects:
the array substrate, the manufacturing method thereof and the display device provided by the embodiment of the invention comprise the following steps: a substrate, a touch transistor and a display transistor on the substrate; wherein, touch transistor includes: a first active layer, a first gate insulating layer, and a first gate electrode stacked; a display transistor, comprising: a second active layer, a second gate insulating layer, and a second gate electrode stacked; the thickness of the first gate insulating layer is greater than the thickness of the second gate insulating layer. The thick gate insulating layer is deposited, the thick first gate insulating layer is formed by carrying out primary etching on the gate insulating layer in the area where the touch transistor is located through a half exposure process, and the thinned second gate insulating layer is formed by carrying out secondary etching on the gate insulating layer in the area where the display transistor is located, so that bright spots and dark spots caused by the defect of the gate insulating layer are effectively improved, the characteristics of the touch transistor and the display transistor are ensured, and the product quality is improved.
Drawings
Fig. 1 to fig. 4 are schematic structural diagrams of an array substrate according to an embodiment of the present invention;
fig. 5 to fig. 10 are schematic structural diagrams of an array substrate in a manufacturing process according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. The thickness and shape of the various layers in the drawings are not to scale, and are intended to illustrate the invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present invention fall within the protection scope of the present invention.
Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms first, second and the like in the description and in the claims, are not used for any order, quantity or importance, but are used for distinguishing between different elements. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. "inner", "outer", "upper", "lower", etc. are used merely to denote relative positional relationships, which may also change accordingly when the absolute position of the object to be described changes.
An array substrate provided in an embodiment of the present invention, as shown in fig. 1, includes: a substrate 100, a touch transistor 101 and a display transistor 102 (may include a switching transistor and a driving transistor in particular) on the substrate 100;
the touch transistor 101 includes: a first active layer 1011, a first gate insulating layer 1012, and a first gate electrode 1013 which are stacked;
display transistor 102, comprising: a second active layer 1021, a second gate insulating layer 1022, and a second gate 1023 which are stacked;
the thickness of the first gate insulating layer 1012 is greater than the thickness of the second gate insulating layer 1022.
In the array substrate provided by the embodiment of the invention, a thicker gate insulating layer is deposited, then a first thicker gate insulating layer 1012 is formed by carrying out primary etching on the gate insulating layer in the area where the touch transistor 101 is located through a half exposure process, and a second thinned gate insulating layer 1022 is formed by carrying out secondary etching on the gate insulating layer in the area where the display transistor 102 is located, so that bright spots and dark spot defects caused by the defect of the gate insulating layer are effectively improved, the characteristics of the touch transistor 101 and the display transistor 102 are ensured, and the product quality is improved.
In the related art, at the crossing position of the gate line 103 and the data line 104, there is a third gate insulating layer between the gate line 103 and the buffer layer 105. The buffer layer 105 at the edge of the third insulating layer is damaged during the process of etching to form the third gate insulating layer, so that when the data line 104 climbs the gate line 103, a larger film step exists, and the edge of the film overlapping the gate line 103 and the data line 104 has a blackening phenomenon. When there is a black foreign matter such as particles (particles), the difference in gray scale of AOI is small, and this failure cannot be detected.
In order to solve the above technical problem, in the array substrate provided by the embodiment of the present invention, as shown in fig. 2, the method further includes: the third gate insulating layer and the gate line 103 are stacked, and the thickness of the third gate insulating layer is zero.
That is, the pad layer structure of the third gate insulating layer is removed at the crossing of the gate line 103 and the data line 104, so that the step difference between the gate line 103 and the data line 104 is reduced, the blackening phenomenon of the edge of the film layer where the gate line 103 and the data line 104 overlap is improved, and further, when black foreign matters such as particles (particles) exist, the gray scale contrast difference of optical defect detection can be enhanced, and the defect detection rate is improved.
Optionally, in the above array substrate provided by the embodiment of the present invention, the touch transistor 101 may further include: a first source electrode and a first drain electrode electrically connected to the first active layer 1011. Specifically, the first active layer 1011 includes a channel region (i.e., a sparse diagonal line region in the first active layer 1011), and a source contact region and a drain contact region (i.e., a dense diagonal line region in the first active layer 1011) which are disposed on both sides of the channel region and are subjected to a conductive process, wherein the first source is electrically connected to the source contact region, and the first drain is electrically connected to the drain contact region.
Optionally, in the above array substrate provided by the embodiment of the present invention, the display transistor 102 may further include: a second source electrode 1024 and a second drain electrode 1025 electrically connected to the second active layer 1021, as shown in fig. 3. The second active layer 1021 includes a channel region (i.e., a sparse diagonal line region in the second active layer 1021), and a source contact region and a drain contact region (i.e., a dense diagonal line region in the second active layer 1021) that are disposed at two sides of the channel region and are subjected to conductive treatment, wherein the second source 1024 is electrically connected to the source contact region, and the second drain 1025 is electrically connected to the drain contact region.
Optionally, in order to ensure stability of the display transistor 102, in the array substrate provided in the embodiment of the present invention, as shown in fig. 1, fig. 3 and fig. 4, the array substrate further includes: a light shielding layer 106 between the substrate 100 and the second active layer 1021; wherein, the orthographic projection of the light shielding layer 106 on the substrate 100 and the orthographic projection of the second active layer 1021 overlap each other to shield the channel region of the second active layer 1021 from the influence of external light; the second source 1024 or the second drain 1025 is electrically connected to the light shielding layer 106, and further electrically connected to the pixel anode through the light shielding layer 106, so as to realize pixel light emission.
In the related art, the active layer is thinIn the process of etching the active layer, etching liquid is easy to infiltrate into the boundary between the photoresist and the active layer, so that the active layer is etched excessively to form a defect, and further the buffer layer 105 at the defect position of the active layer is etched, so that the source electrode and the drain electrode of the transistor are conducted with the light shielding layer 106, and bright spots of conduction of the source electrode and the drain electrode are formed.
In the array substrate provided by the embodiment of the invention, the gate insulating layer (specifically, the first gate insulating layer 1012 and the second gate insulating layer 1022) and the active layer (specifically, the first active layer 1011 and the second active layer 1021) can be manufactured by using a Half-exposure Mask (Half-tone Mask), so that the first gate insulating layer 1012 can effectively protect the first active layer 1011, and the second gate insulating layer 1022 can effectively protect the second active layer 1021, thereby reducing the bright point defect caused by the active layer deficiency.
Generally, in the above array substrate provided by the embodiment of the present invention, as shown in fig. 2 and fig. 3, in order to avoid short circuit between the gate metal layer and the source drain metal layer, the method may generally further include: an interlayer dielectric layer 107 of silicon oxide, silicon nitride or silicon oxynitride.
Based on the same inventive concept, the embodiment of the invention provides a manufacturing method of an array substrate, which specifically comprises the following steps:
providing a substrate base plate 100;
forming a touch transistor 101 and a display transistor 102 on a substrate 100;
the touch transistor 101 includes: a first active layer 1011, a first gate insulating layer 1012, and a first gate electrode 1013 which are stacked;
display transistor 102, comprising: a second active layer 1021, a second gate insulating layer 1022, and a second gate 1023 which are stacked;
the thickness of the first gate insulating layer 1012 is greater than the thickness of the second gate insulating layer 1022.
Optionally, in the above manufacturing method provided by the embodiment of the present invention, the following steps may be further performed: forming a third gate insulating layer and a gate line 103 which are stacked, wherein the thickness of the third gate insulating layer is zero;
forming the first active layer 1011, the second active layer 1021, the first gate insulating layer 1012, the second gate insulating layer 1022, the third gate insulating layer, the gate line 103, the first gate 1013, and the second gate 1023 on the substrate 100 may be specifically performed by:
sequentially depositing a thickness ofOxide material layer 108 (e.g. indium gallium zinc oxide IGZO) of thickness +.>As shown in fig. 5, and a photoresist layer 110;
exposing the photoresist layer 110 by using a half-exposure mask plate, removing the photoresist layer 110 positioned between the gate line 103 region, the touch transistor 101 region and the display transistor 102 region and positioned in the gate line 103 region, wherein the photoresist layer 110 positioned outside the second gate 1023 region in the touch transistor 101 region and the display transistor 102 region has a first thickness H1, and the photoresist layer 110 positioned in the second gate 1023 region has a second thickness H2 smaller than the first thickness H1, as shown in FIG. 6;
etching the insulating material layer 109 to retain the insulating material layer 109 in the region of the touch transistor 101 and the region of the display transistor 102, as shown in fig. 7;
ashing the photoresist layer 110 to remove the photoresist layer 110 having the second thickness H2 in the region of the display transistor 102, as shown in fig. 8;
the insulating material layer 109 in the region where the second gate 1023 is located is thinned, as shown in fig. 9;
etching the oxide material layer 108 to form a first active layer 1011 and a second active layer 1021, as shown in fig. 10;
stripping photoresist layer 110, as shown in FIG. 10;
forming a gate line 103, a first gate electrode 1013, and a second gate electrode 1023 of copper or aluminum material on the insulating material layer 109;
etching the insulating material layer 109, leaving the insulating material layer 109 overlapping the first gate 1013 to form a first gate insulating layer 1012, and thinning the insulating material layer 109 in the region where the second gate 1023 is located to form a second gate insulating layer 1022;
the first active layer 1011 and the second active layer 1021 are subjected to a conductive treatment, as shown in fig. 1.
As can be seen from the above description, after the oxide material layer 108 for fabricating the active layer and the insulating material layer 109 for fabricating the gate insulating layer are sequentially deposited, the two are etched by using the half-exposure mask in common, forming three regions of different roles. Specifically, the first active layer 1011 in the area where the touch transistor 101 is located is normal, and the first gate insulating layer 1012 is thicker; the second active layer 1021 in the area where the display transistor 102 is located is normal, the insulating material layer 109 is etched for the second time to form a thinner second gate insulating layer 1022, so that bright spots and dark spot defects caused by the defect of the gate insulating layer are effectively improved, and the characteristics of the touch transistor 101 and the display transistor 102 are ensured. In addition, the first gate insulating layer 1012 can effectively protect the first active layer 1011, and the second gate insulating layer 1022 can effectively protect the second active layer 1021, thereby reducing bright point defects caused by active layer defects. In addition, at the crossing position of the gate line 103 and the data line 104, the oxide material layer 108 and the insulating material layer 109 are removed, so that the step difference between the gate line 103 and the data line 104 is reduced, the blackening phenomenon of the film edge where the gate line 103 and the data line 104 overlap is improved, and further, when black foreign matters such as particles (particles) exist, the gray scale contrast difference of optical defect detection can be enhanced, and the defect detection rate is improved. Furthermore, the half-exposure mask plate can avoid the need of respectively manufacturing the gate insulating layer and the active layer through two mask processes, namely, no additional mask process is needed, the operability and the compatibility are strong, and the process is simple.
Optionally, in the above manufacturing method provided by the embodiment of the present invention, after the performing step performs the conductive treatment on the first active layer 1011 and the second active layer 1021, the following steps may be further performed:
an interlayer dielectric layer 107 made of silicon oxide, silicon nitride or silicon oxynitride, a first source electrode and a first drain electrode of the touch transistor 101, a second source electrode 1024 and a second drain electrode 1025 of the display transistor 102, and a data line 104 extending in a direction intersecting the gate line 103 are sequentially formed on the layers of the first gate electrode 1013 and the second gate electrode 1023;
wherein the first source and the first drain are electrically connected to the first active layer 1011 through a first via of the interlayer dielectric layer 107;
the second source electrode 1024 and the second drain electrode 1025 are electrically connected to the second active layer 1021 through a second via hole of the interlayer dielectric layer 107.
Optionally, in the above manufacturing method provided by the embodiment of the present invention, before the performing step of forming the touch transistor 101 and the display transistor 102 on the substrate 100, the following steps may be further performed:
a light shielding layer 106 is formed in a region where the display transistor 102 is located, and a front projection of the light shielding layer 106 on the substrate 100 and a front projection of the second active layer 1021 overlap each other.
In addition, after the light shielding layer 106 is formed, and before the touch transistor 101 and the display transistor 102 are formed, the buffer layer 105 may be formed; after forming the touch transistor 101 and the display transistor 102, a thickness ofIs a passivation layer of (a); and an OLED white light device electrically connected with the display transistor 102 is fabricated on the passivation layer; in order to realize color display, a color film substrate comprising an RGB color resistance layer and a flat layer can be manufactured; and finally, the color film substrate and the array substrate are paired to form a display panel. Of course, the OLED device on the passivation layer may also be an RGB single-color device, and color display may be achieved by packaging the array substrate.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which includes the array substrate provided by the embodiment of the invention, and the display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a smart watch, a body-building wristband, a personal digital assistant, and the like. Other essential components of the display device will be understood by those skilled in the art, and are not described herein in detail, nor should they be considered as limiting the invention. In addition, since the principle of the display device for solving the problems is similar to that of the array substrate, the implementation of the display device can refer to the embodiment of the array substrate, and the repetition is not repeated.
The array substrate, the manufacturing method and the display device disclosed by the invention comprise the following steps: a substrate, a touch transistor and a display transistor on the substrate; wherein, touch transistor includes: a first active layer, a first gate insulating layer, and a first gate electrode stacked; a display transistor, comprising: a second active layer, a second gate insulating layer, and a second gate electrode stacked; the thickness of the first gate insulating layer is greater than the thickness of the second gate insulating layer. The thick gate insulating layer is deposited, the thick first gate insulating layer is formed by carrying out primary etching on the gate insulating layer in the area where the touch transistor is located through a half exposure process, and the thinned second gate insulating layer is formed by carrying out secondary etching on the gate insulating layer in the area where the display transistor is located, so that bright spots and dark spots caused by the defect of the gate insulating layer are effectively improved, the characteristics of the touch transistor and the display transistor are ensured, and the product quality is improved.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (8)
1. An array substrate, characterized by comprising: a substrate, a touch transistor and a display transistor which are positioned on the substrate;
wherein, touch transistor includes: a first active layer, a first gate insulating layer, and a first gate electrode stacked;
the display transistor includes: a second active layer, a second gate insulating layer, and a second gate electrode stacked; the display transistor further includes: a second source electrode and a second drain electrode electrically connected to the second active layer;
the array substrate further comprises: a light shielding layer located between the substrate base plate and the second active layer;
the orthographic projection of the shading layer on the substrate base plate and the orthographic projection of the second active layer are overlapped, and the second source electrode or the second drain electrode is electrically connected with the shading layer;
the thickness of the first gate insulating layer is larger than that of the second gate insulating layer, the first gate insulating layer is formed by carrying out primary etching on a gate insulating material layer in an area where the touch transistor is located, the second gate insulating layer is formed by carrying out secondary etching on a gate insulating material layer in an area where the display transistor is located, and the first gate insulating layer is used for protecting the first active layer and the second gate insulating layer is used for protecting the second active layer in the process of etching an oxide material layer to form the first active layer and the second active layer.
2. The array substrate of claim 1, further comprising: and the third gate insulating layer and the gate line are stacked, and the thickness of the third gate insulating layer is zero.
3. The array substrate of claim 1 or 2, wherein the touch transistor further comprises: and a first source electrode and a first drain electrode electrically connected with the first active layer.
4. The manufacturing method of the array substrate is characterized by comprising the following steps of:
providing a substrate base plate;
forming a touch transistor and a display transistor on the substrate;
wherein, touch transistor includes: a first active layer, a first gate insulating layer, and a first gate electrode stacked;
the display transistor includes: a second active layer, a second gate insulating layer, and a second gate electrode stacked; the display transistor further includes: a second source electrode and a second drain electrode electrically connected to the second active layer;
the array substrate further comprises: a light shielding layer located between the substrate base plate and the second active layer;
the orthographic projection of the shading layer on the substrate base plate and the orthographic projection of the second active layer are overlapped, and the second source electrode or the second drain electrode is electrically connected with the shading layer;
the thickness of the first gate insulating layer is larger than that of the second gate insulating layer, the first gate insulating layer is formed by carrying out primary etching on a gate insulating material layer in an area where the touch transistor is located, the second gate insulating layer is formed by carrying out secondary etching on a gate insulating material layer in an area where the display transistor is located, and the first gate insulating layer is used for protecting the first active layer and the second gate insulating layer is used for protecting the second active layer in the process of etching an oxide material layer to form the first active layer and the second active layer.
5. The method of manufacturing of claim 4, further comprising: forming a third gate insulating layer and a gate line which are stacked, wherein the thickness of the third gate insulating layer is zero;
forming the first active layer, the second active layer, the first gate insulating layer, the second gate insulating layer, the third gate insulating layer, the gate line, the first gate electrode and the second gate electrode on the substrate, specifically including:
sequentially depositing an oxide material layer, an insulating material layer and a photoresist layer on the substrate;
exposing the photoresist layer by adopting a half-exposure mask plate, removing the photoresist layer positioned between a grid line area, a touch transistor area and a display transistor area and positioned in the grid line area, wherein the photoresist layer positioned outside the areas of the second grid electrodes in the touch transistor area and the display transistor area has a first thickness, and the photoresist layer positioned in the areas of the second grid electrodes has a second thickness smaller than the first thickness;
etching the insulating material layer, and reserving the insulating material layer positioned in the touch transistor area and the display transistor area;
ashing the photoresist layer to remove the photoresist layer with the second thickness in the display transistor area;
thinning the insulating material layer of the region where the second grid is located;
etching the oxide material layer to form the first active layer and the second active layer;
stripping the photoresist layer;
forming the gate line, the first gate electrode and the second gate electrode on the insulating material layer;
etching the insulating material layer, reserving the insulating material layer overlapped with the first grid electrode to form a first grid insulating layer, and forming a second grid insulating layer by the insulating material layer subjected to thinning treatment in the area where the second grid electrode is positioned;
and conducting the first active layer and the second active layer.
6. The method of manufacturing of claim 5, further comprising, after conducting the first active layer and the second active layer:
forming an interlayer dielectric layer on the layer where the first grid electrode and the second grid electrode are located in sequence, wherein the first source electrode and the first drain electrode of the touch transistor, the second source electrode and the second drain electrode of the display transistor and the data line with the extending direction crossing the grid line are formed;
the first source electrode and the first drain electrode are electrically connected with the first active layer through a first via hole of the interlayer dielectric layer;
the second source electrode and the second drain electrode are electrically connected with the second active layer through a second via hole of the interlayer dielectric layer.
7. The method of any of claims 4-6, further comprising, prior to forming the touch transistor and the display transistor on the substrate:
and forming a shading layer in the area where the display transistor is located, wherein the orthographic projection of the shading layer on the substrate and the orthographic projection of the second active layer are overlapped.
8. A display device, comprising: the array substrate of any one of claims 1-3.
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| CN113594182A (en) * | 2021-07-27 | 2021-11-02 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
| CN115377166A (en) * | 2022-08-31 | 2022-11-22 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
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| CN104282259A (en) * | 2013-07-12 | 2015-01-14 | 三星显示有限公司 | Organic light emitting diode display |
| CN104659285A (en) * | 2015-01-20 | 2015-05-27 | 深圳市华星光电技术有限公司 | TFT backboard manufacturing method and structure suitable for AMOLED |
| CN110660814A (en) * | 2019-09-29 | 2020-01-07 | 合肥京东方卓印科技有限公司 | Array substrate, display panel and manufacturing method of array substrate |
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| CN104282259A (en) * | 2013-07-12 | 2015-01-14 | 三星显示有限公司 | Organic light emitting diode display |
| CN104659285A (en) * | 2015-01-20 | 2015-05-27 | 深圳市华星光电技术有限公司 | TFT backboard manufacturing method and structure suitable for AMOLED |
| CN110660814A (en) * | 2019-09-29 | 2020-01-07 | 合肥京东方卓印科技有限公司 | Array substrate, display panel and manufacturing method of array substrate |
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