TWI683437B - 高壓半導體裝置 - Google Patents

高壓半導體裝置 Download PDF

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TWI683437B
TWI683437B TW105144151A TW105144151A TWI683437B TW I683437 B TWI683437 B TW I683437B TW 105144151 A TW105144151 A TW 105144151A TW 105144151 A TW105144151 A TW 105144151A TW I683437 B TWI683437 B TW I683437B
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voltage semiconductor
conductivity type
semiconductor device
isolation
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TW201824544A (zh
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楊紹明
簡廷耀
吳玠志
李自捷
賴秋仲
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新唐科技股份有限公司
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Priority to CN201710207296.8A priority patent/CN108269842B/zh
Priority to US15/859,050 priority patent/US20180190763A1/en
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Abstract

本發明實施例提供高壓半導體裝置，其包含具有第一導電型態的基底及設置於基底上的閘極。高壓半導體裝置也包含分別位於閘極的相對兩側的源極區及汲極區。高壓半導體裝置也包含設置於閘極和汲極區之間且具有第一導電型態的線性摻雜區，其中線性摻雜區具有不均勻的摻雜深度。高壓半導體裝置更包含設置於源極區下方且具有第一導電型態的第一掩埋層。

Description

高壓半導體裝置
本發明係有關於半導體裝置，且特別係有關於高壓半導體裝置。
高壓半導體裝置技術適用於高電壓與高功率的積體電路領域。傳統高壓半導體裝置，例如垂直式擴散金氧半導體(vertically diffused metal oxide semiconductor,VDMOS)電晶體及水平擴散金氧半導體(laterally diffused metal oxide semiconductor,LDMOS)電晶體，主要用於18V以上的元件應用領域。高壓裝置技術的優點在於符合成本效益，且易相容於其它製程，已廣泛應用於顯示器驅動IC元件、電源供應器、電力管理、通訊、車用電子或工業控制等領域中。
在高壓半導體裝置的發展過程中，同時具有高崩潰電壓和低導通電阻(on-resistance,Ron)的高壓半導體裝置是難以達成的目標。因此，有必要尋求一種新的高壓半導體裝置結構以滿足上述需求。
本發明的一些實施例係關於高壓半導體裝置，其包含基底具有第一導電型態，閘極設置於基底上，源極區及汲極區分別位於閘極的相對兩側；線性摻雜區設置於閘極和汲極 區之間，且具有第一導電型態，其中線性摻雜區具有不均勻的摻雜深度；以及第一掩埋層設置於源極區下方，且具有第一導電型態。
本發明的一些實施例係關於高壓半導體裝置，其包含閘極沿第一方向延伸，源極區及汲極區分別位於閘極的相對兩側，且沿第一方向延伸，隔離區設置於閘極與汲極區間，隔離區具有複數個隔開的隔離塊，以及線性摻雜區設置於閘極和汲極區之間，且位於該些隔離塊間，其中在沿著垂直於第一方向的第二方向，線性摻雜區具有不均勻的摻雜深度。
100‧‧‧高壓半導體裝置
102‧‧‧基底
104‧‧‧第一井區
106‧‧‧第二井區
108‧‧‧第一摻雜區
110‧‧‧第二摻雜區
112‧‧‧閘極
114‧‧‧第三摻雜區
116‧‧‧線性摻雜區
118‧‧‧隔離區
118A、1108B‧‧‧隔離塊
120‧‧‧第一掩埋層
122‧‧‧第二掩埋層
L1、L2‧‧‧長度
為讓本發明之特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：第1圖係根據本發明的一些實施例之高壓半導體裝置的上視圖。
第2圖係根據一些實施例，沿第1圖所示的高壓半導體裝置之A-A’切線的剖面示意圖。
第3圖係根據一些實施例，沿第1圖所示的高壓半導體裝置之B-B’切線的剖面示意圖。
第4圖係根據另一些實施例，沿第1圖所示的高壓半導體裝置之B-B’切線的剖面示意圖。
以下針對本發明之高壓半導體裝置及其製造方法作詳細說明。應了解的是，以下之敘述提供許多不同的實施例或例子，用以實施本發明之不同樣態。以下所述特定的元件及 排列方式僅為簡單描述本發明。當然，這些僅用以舉例而非用以限定本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，例如，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸之情形。或者，亦可能間隔有一或更多其它材料層之情形，在此情形中，第一材料層與第二材料層之間可能不直接接觸。
必需了解的是，特別描述之圖示之元件可以此發明中所屬技術領域中具有通常知識者所熟知之各種形式存在。此外，當某層在其它層或基板「上」時，有可能是指「直接」在其它層或基板上，或指某層在其它層或基板之間夾設其它層。
此外，實施例中可能使用相對性的用語，例如「較低」、「下方」或「底部」及「較高」、「上方」或「頂部」，以描述圖示的一個元件對於另一元件的相對關係。能理解的是，如果將圖示的裝置翻轉使其上下顛倒，則所敘述在「較低」側的元件將會成為在「較高」側的元件。
在此，「約」、「大約」之用語通常表示在一給定值或範圍的20%之內，較佳是10%之內，且更佳是5%之內。在此給定的數量為大約的數量，意即在沒有特定說明的情況下，仍可隱含「約」、「大約」之含義。
本發明係揭露高壓半導體裝置之實施例，且上述實施例可被包含於例如微處理器、記憶元件及/或其他元件之 積體電路(integrated circuit,IC)中。上述積體電路也可包含不同的被動和主動微電子元件，例如薄膜電阻器(thin-film resistor)、其他類型電容器例如，金屬-絕緣體-金屬電容(metal-insulator-metal capacitor,MIMCAP)、電感、二極體、金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor field-effect transistors,MOSFETs)、互補式MOS電晶體、雙載子接面電晶體(bipolar junction transistors,BJTs)、橫向擴散型MOS電晶體、高功率MOS電晶體或其他類型的電晶體。在本發明所屬技術領域中具有通常知識者可以了解也可將高壓半導體裝置使用於包含其他類型的半導體元件於積體電路之中。
參見第1圖，第1圖係根據本發明的一些實施例之高壓半導體裝置100的上視圖。如第1圖所示，高壓半導體裝置100包含各別沿第一方向，例如為Y方向延伸的第一摻雜區108、第二摻雜區110、閘極112及第三摻雜區114。其中，第一摻雜區108及第二摻雜區110可作為高壓半導體裝置100的源極區，第三摻雜區114可作為高壓半導體裝置100的汲極區。此外，第一摻雜區108、第二摻雜區110及第三摻雜區114可為重摻雜區或輕摻雜區。
如第1圖所示，在一些實施例，高壓半導體裝置100更包含隔離區118及線性摻雜區116。隔離區118設置於閘極112和汲極區114之間，隔離區118在第一方向上被分隔成複數個區塊，例如互相隔開的隔離塊118A及隔離塊118B。線性摻雜區116則位於隔離塊118A和隔離塊118B之間，在線性摻雜區116圖案中，點的密度代表摻雜的深度及/或濃度。其中，點的密度越 高，代表摻雜的深度越深，或摻雜濃度越濃，點的密度越低，代表摻雜的深度越淺，或摻雜濃度越低。在一些實施例，在沿著第二方向，例如為X方向，線性摻雜區116的深度及/或濃度並非均勻。如第1圖所示，在沿著由閘極112朝向第三摻雜區114(即汲極區)的方向，線性摻雜區116的摻雜深度及/或濃度遞減。
參閱第2圖，第2圖係根據一些實施例，沿第1圖所示的高壓半導體裝置100之A-A’切線的剖面示意圖。如第2圖所示，高壓半導體裝置100包含基底102。基底102可為半導體基板，例如矽基板。此外，上述半導體基板亦可為元素半導體，包括鍺(germanium)；化合物半導體，包括碳化矽(silicon carbide)、砷化鎵(gallium arsenide)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide)；合金半導體，包括矽鍺合金(SiGe)、磷砷鎵合金(GaAsP)、砷鋁銦合金(AlInAs)、砷鋁鎵合金(AlGaAs)、砷銦鎵合金(GaInAs)、磷銦鎵合金(GaInP)及/或磷砷銦鎵合金(GaInAsP)或上述材料之組合。此外，基底102也可以是絕緣層上覆半導體(semiconductor on insulator,SOI)基底。在一些實施例，基底102具有第一導電型態，例如為P型。
如第2圖所示，高壓半導體裝置100包含第一井區104及第二井區106，其中第一井區104具有第一導電型態，第二井區106具有不同於第一導電型態的第二導電型態，例如為N型。其中第一井區104的摻雜濃度可例如為1014cm3-1018cm3，第二井區106的摻雜濃度可例如為1014cm3-1018cm3。
在一些實施例，第二井區106可被摻雜第二導電型態的磊晶層所取代，此磊晶層可包含矽、鍺、矽與鍺、V族化合物或上述之組合。此磊晶層可藉由磊晶成長(epitaxial growth)製程形成，例如金屬有機物化學氣相沉積法(metal-organic chemical vapor deposition,MOCVD)、金屬有機物化學氣相磊晶法(metal-organic vapor phase epitaxy,MOVPE)、電漿增強型化學氣相沉積法(plasma-enhanced chemical vapor deposition,PECVD)、遙控電漿化學氣相沉積法(remote plasma chemical vapor deposition,RP-CVD)、分子束磊晶法(molecular beam epitaxy,MBE)、氫化物氣相磊晶法(hydride vapor phase Epitaxy,HVPE)、液相磊晶法(liquid phase epitaxy,LPE)、氯化物氣相磊晶法(chloride vapor phase epitaxy,Cl-VPE)或類似的方法形成。
如第2圖所示。閘極112設置在基底102上，閘極112包含閘極介電層和閘極電極(未繪示)。閘極介電層的材料可包含氧化矽、氮化矽、氮氧化矽、高介電常數(high-k)介電材料、或其它任何適合之介電材料、或上述之組合。此高介電常數(high-k)介電材料之材料可為金屬氧化物、金屬氮化物、金屬矽化物、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽化物、金屬的氮氧化物、金屬鋁酸鹽、鋯矽酸鹽、鋯鋁酸鹽。例如，此高介電常數(high-k)介電材料可為LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfO2、HfO3、HfZrO、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、HfTaTiO、HfAlON、(Ba,Sr)TiO3(BST)、Al2O3、其它 適當材料之其它高介電常數介電材料、或上述組合。此介電材料層可藉由化學氣相沉積法(CVD)或旋轉塗佈法形成。閘極電極的材料包含非晶矽、多晶矽、一或多種金屬、金屬氮化物、導電金屬氧化物、或上述之組合。上述金屬可包含但不限於鉬(molybdenum)、鎢(tungsten)、鈦(titanium)、鉭(tantalum)、鉑(platinum)或鉿(hafnium)。上述金屬氮化物可包括但不限於氮化鉬(molybdenum nitride)、氮化鎢(tungsten nitride)、氮化鈦(titanium nitride)以及氮化鉭(tantalum nitride)。上述導電金屬氧化物可包含但不限於釕金屬氧化物(ruthenium oxide)以及銦錫金屬氧化物(indium tin oxide)。此導電材料層之材料可藉由化學氣相沉積法、濺鍍法、電阻加熱蒸鍍法、電子束蒸鍍法、或其它任何適合的沈積方式形成。
由第一摻雜區108和第二摻雜區110所組成的源極區設置在第一井區104內，第一摻雜區108和第二摻雜區110分別具有第一導電型態和第二導電型態。由第三摻雜區114組成的汲極區114設置在第二井區106內，且具有第二導電型態。
在一些實施例，高壓半導體裝置包含線性摻雜區116，設置在第二井區106內，且位於閘極112和第三摻雜區114之間。在一些實施例，線性摻雜區116具有第一導電型態。如第2圖所示，線性摻雜區116的摻雜深度並非均勻，在沿著由閘極112朝向第三摻雜區114的方向，線性摻雜區116的摻雜深度遞減。雖然未顯示於第2圖，在另一些實施例，線性摻雜區116的摻雜濃度並非均勻，在沿著由閘極112朝向第三摻雜區114的方向，線性摻雜區116的摻雜濃度遞減。在一些實施例，線性 摻雜區116的摻雜濃度可藉於約1015cm3-1018cm3的範圍間。
在一些實施例，如第2圖所示，高壓半導體裝置100包含第一掩埋層120，設置於第一井區104內，且位於第一摻雜區108和第二摻雜區110(即源極區)的下方。第一掩埋層120具有第一導電型態，且第一掩埋層120的摻雜濃度可為均勻，亦可為不均勻。在一些實施例，在沿著源極區朝向閘極112的方向，第一掩埋層120的摻雜濃度遞減。第一掩埋層120的摻雜濃度可藉於約1016cm3-1019cm3的範圍間。此外，在一些實施例，第一掩埋層120在基底102上的投影與閘極112在基底102上的投影不重疊。並且，第一掩埋區120被源極區完全覆蓋。
此外，高壓半導體裝置100包含第二掩埋層122，設置在基底102內，且具有第二導電型態。如第2圖所示，第二掩埋層122設置在第一掩埋層120下方。在一些實施例，第一掩埋層120投影在基底102上的長度小於第二掩埋層122的長度。此外，第二掩埋層122由第一井區104的下方延伸至第二井區106和閘極112的下方。在一些實施例，閘極112在基底102上的一部分投影未與第二掩埋層122重疊，且線性摻雜區116在基底102上的投影不與第二掩埋層122重疊。此外，雖然未繪示於第2圖，在另一些實施例，第二掩埋層122可全面性地形成在基底102上。在此實施例，閘極112在基底102上的投影與第二掩埋層122完全重疊，且線性摻雜區116在基底102上的投影與第二掩埋層122完全重疊。另外，在一些實施例，第一掩埋層120在基底102上的投影與閘極112在基底102上的投影不重疊。在一些實施例，第二掩埋層122的摻雜濃度可藉於約1016cm3-1019cm3的範圍間。
參閱第3圖，第3圖係根據一些實施例，沿第1圖所示的高壓半導體裝置100之B-B’切線的剖面示意圖。如第3圖所示，高壓半導體裝置100包含隔離區118。在一些實施例，隔離區118為淺溝槽(shallow trench)隔離結構，且由介電材料組成，例如氧化矽、氮化矽、氮氧化矽或其他介電材料。隔離區118可利用微影製程及蝕刻製程在第二井區106內形成溝槽(未繪示)，接著在此溝槽填入上述介電材料。微影製程包含光阻塗佈(例如旋轉塗佈)、軟烤、光罩對位、曝光、曝後烤、將光阻顯影、沖洗、乾燥(例如硬烤)、其他合適的製程或前述之組合。另外，微影製程可由其他適當的方法，例如無遮罩微影、電子束寫入(electron-beam writing)及離子束寫入(ion-beam writing)進行或取代。蝕刻製程包含乾蝕刻、濕蝕刻或其他蝕刻方法。
在一些實施例，如第3圖所示，在第一方向上，線性摻雜區116並未延伸至隔離區118的下方。亦即，線性摻雜區116僅形成在如第1圖所示的兩個隔離塊118A和118B之間。且如第3圖所示，在一些實施例，第二掩埋層122並未延伸至隔離區118的下方。
參閱第4圖，第4圖係根據另一些實施例，沿第1圖所示的高壓半導體裝置100之B-B’切線的剖面示意圖。第4圖與第3圖所示的實施例的不同處在於：線性摻雜區116僅不僅形成在如第1圖所示的兩個隔離塊118A和118B之間，更形成在隔離塊118A和118B的下方。亦即，在第一方向上，線性摻雜區116延伸至隔離區118的下方。
回到第1圖，如第1圖所示，隔離塊118A和隔離塊118B在第一方向上具有長度L1，而兩個隔離塊118A和隔離塊118B之間的距離為長度L2。在一些實施例，L2與L1的比值介於1-10，較佳為介於4-6。在如第3圖所示的實施例，當線性摻雜區116僅形成在兩個隔離塊118A和118B之間時，線性摻雜區116在第一方向的長度與長度L1的比值介於1-10，較佳為介於4-6。
在一些實施例，在之後的製程可形成源極和汲極電極連接至各自的源極區、汲極區。電極可由適合的導電材料形成，例如銅、鎢、鎳、鈦或類似材料。在一些實施例，金屬矽化物形成在導電材料和源極區、汲極區的界面以增加界面的導電性。在一些實施例，利用鑲嵌及/或雙鑲嵌製程以形成多層內連線結構。在其他實施例，利用鎢形成鎢插塞。
在一些實施例，之後的製程也可形成各種接觸窗/孔洞/線及多層內連線元件(例如金屬層和層間介電層)於基底102上，來連接各種元件或結構。例如，多層內連線包含垂直內連線，例如傳統的孔洞或接觸窗，以及水平內連線，例如金屬線。
本發明實施例提供的線型摻雜區設置在閘極和汲極區之間，相對於均勻摻雜的方式，線型摻雜區可以讓高壓半導體表面的峰值電場比較小，但是表面電場更加均勻，以提高高壓半導體的崩潰電壓，同時提升高壓半導體的可靠度。此外，藉由設置第一掩埋層在源極區和第二掩埋區之間，可降低第一井區的電阻，使得導通電阻下降。與傳統的高壓半導體裝置相比，本發明實施例提供的高壓半導體裝置更能防止克爾克效應(kirk effect)，來同時達到高崩潰電壓和低導通電阻的效能。此外，藉由調整隔離塊的長度與隔離塊之間的距離的比值(亦可稱為WSi/WSiO2)，可減少飄移區的長度，亦有助於提高高壓半導體裝置的崩潰電壓。
雖然本發明的實施例及其優點已揭露如上，但應該瞭解的是，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。此外，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明實施例揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大抵相同功能或獲得大抵相同結果皆可根據本發明實施例使用。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
100‧‧‧高壓半導體裝置
102‧‧‧基底
104‧‧‧第一井區
106‧‧‧第二井區
108‧‧‧第一摻雜區
110‧‧‧第二摻雜區
112‧‧‧閘極
114‧‧‧第三摻雜區
116‧‧‧線性摻雜區
120‧‧‧第一掩埋層
122‧‧‧第二掩埋層

Claims (6)

  1. 一種高壓半導體裝置，包括：一基底，具有一第一導電型態；一井區，設置於該基底上，具有不同於該第一導電型態的一第二導電型態；一閘極，設置於該基底上並沿一第一方向延伸；一源極區及一汲極區，分別位於該閘極的相對兩側；一隔離區，設置於該閘極與該汲極區間，其中沿著該第一方向，該隔離區具有複數個隔開的隔離塊，且該些隔開的隔離塊中相鄰的兩個隔離塊在該第一方向的距離與每該隔離塊在該第一方向的長度的比值介於4-6；一線性摻雜區，設置於該井區內且位於該閘極和該汲極區之間，且具有該第一導電型態，其中在沿著該閘極朝向該汲極區的方向，該線性摻雜區的一摻雜深度遞減；一第一掩埋層，設置於該源極區下方，且具有該第一導電型態；以及一第二掩埋層，設置於該基底內且位於該第一掩埋層下方，其中該第二掩埋層具有一與第一導電型態相反的第二導電型態，其中該第二掩埋層未延伸至該線性摻雜區下方。
  2. 如申請專利範圍第1項所述之高壓半導體裝置，其中在沿著該閘極朝向該汲極區的方向，該線性摻雜區具有一遞減的摻雜濃度。
  3. 如申請專利範圍第1項所述之高壓半導體裝置，其中該第 二掩埋層由該源極區下方延伸至該閘極下方。
  4. 一種高壓半導體裝置，包括：一井區，具有一第一導電型態；一閘極，沿一第一方向延伸；一源極區及一汲極區，分別位於該閘極的相對兩側，且沿該第一方向延伸；一隔離區，設置於該閘極與該汲極區間，其中沿著該第一方向，該隔離區具有複數個隔開的隔離塊；以及一線性摻雜區，設置於該井區內且位於該閘極和該汲極區之間，且位於該些隔離塊間，其中由該閘極朝向該汲極區的方向，該線性摻雜區的一摻雜深度遞減，且具有與該第一導電型態不同的一第二導電型態。
  5. 如申請專利範圍第4項所述之高壓半導體裝置，其中該線性摻雜區不與該隔離區重疊。
  6. 如申請專利範圍第4項所述之高壓半導體裝置，其中該些隔離塊在沿著該第一方向具有一第一長度，該線性摻雜區在該第一方向具有一第二長度，且該第二長度與該第一長度的比值介於1-10。
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