TWI683415B - 晶片封裝體的製造方法 - Google Patents
晶片封裝體的製造方法 Download PDFInfo
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- TWI683415B TWI683415B TW107134515A TW107134515A TWI683415B TW I683415 B TWI683415 B TW I683415B TW 107134515 A TW107134515 A TW 107134515A TW 107134515 A TW107134515 A TW 107134515A TW I683415 B TWI683415 B TW I683415B
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- microns
- wafer
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
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- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
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Abstract
一種晶片封裝體的製造方法包含以下操作。提供晶圓,此晶圓具有一上表面及與其相對之一下表面,且包含多個導電墊位於上表面。切割晶圓之上表面以形成多個凹槽。形成圖案化光阻層於上表面上及凹槽內。形成多個導電凸塊分別位於對應的導電墊上。由下表面朝上表面薄化晶圓,使凹槽內之圖案化光阻層由下表面暴露出來。形成絕緣層於下表面下方。沿著各凹槽切割圖案化光阻層和絕緣層,以形成多個晶片封裝體。
Description
本發明係關於一種晶片封裝體的製造方法。
傳統的晶片封裝製程係對切割自晶圓的半導體晶粒逐一進行封裝,相當耗時費工。或者,將切割自晶圓的半導體晶粒逐一排列於載板上進行封裝後重新切割成晶片封裝體,這種晶片封裝體的製造方法也相當耗時費工,且容易產生對位偏移的問題。
有鑑於此,本發明之一目的在於提出一種可解決上述問題之晶片封裝體的製造方法。
本發明之一態樣是提供一種晶片封裝體的製造方法包含以下步驟:首先,提供晶圓,此晶圓具有一上表面及與其相對之一下表面,且包含多個導電墊位於上表面上。切割晶圓之上表面以形成多個凹槽。形成圖案化光阻層於上表面上及凹槽內。形成多個導電凸塊分別位於對應的這些導電墊上。由下表面朝上表面薄化晶圓,使凹槽內之圖案化光
阻層由下表面暴露出來。形成一絕緣層於下表面下方。沿著各凹槽切割圖案化光阻層和絕緣層,以形成多個晶片封裝體。
根據本發明一實施方式,在形成導電凸塊的步驟之後更包含:形成一表面處理層於導電凸塊上。
根據本發明一實施方式,在形成導電凸塊的步驟之後且在薄化晶圓的步驟之前,更包含:形成一黏著層覆蓋圖案化光阻層和導電凸塊;以及形成一載板於黏著層上。
根據本發明一實施方式,在形成絕緣層的步驟之後且在沿著各凹槽切割圖案化光阻層和絕緣層的步驟之前,更包含:移除載板及黏著層。
根據本發明一實施方式,在薄化晶圓的步驟之後,晶圓的厚度為100至150微米。
根據本發明一實施方式,在形成絕緣層的步驟之後,晶圓、導電凸塊和絕緣層具有一總厚度為120至210微米。
根據本發明一實施方式,沿著各凹槽切割圖案化光阻層和絕緣層的一切割寬度為15至22微米。
根據本發明一實施方式,各導電凸塊具有一高度為20至45微米。
根據本發明一實施方式,各凹槽具有一寬度為50至60微米,且具有一深度為150至200微米。
根據本發明一實施方式,在提供晶圓的步驟之後,此晶圓具有一厚度為525至725微米。
100‧‧‧方法
20‧‧‧晶圓
20T1‧‧‧厚度
20T2‧‧‧厚度
210‧‧‧上表面
220‧‧‧下表面
230‧‧‧導電墊
240‧‧‧凹槽
240C‧‧‧中心
240D‧‧‧深度
240W‧‧‧寬度
250‧‧‧光阻層
250a‧‧‧第一部分
250b‧‧‧第二部分
250P‧‧‧圖案化光阻層
250R‧‧‧凹部
260‧‧‧導電凸塊
260H‧‧‧高度
270‧‧‧絕緣層
310‧‧‧表面處理層
320‧‧‧黏著層
330‧‧‧載板
340‧‧‧雷射標記
CW‧‧‧切割寬度
Tf‧‧‧總厚度
S110、S120、S130、S140‧‧‧步驟
S150、S160、S170‧‧‧步驟
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:
第1圖繪示本發明之一實施方式之晶片封裝體製造方法的流程圖。
第2至12圖繪示本發明一實施方式之晶片封裝體製造方法中各製程階段的剖面示意圖。
為了使本揭示內容的敘述更加詳盡與完備,下文針對了本發明的實施態樣與具體實施例提出了說明性的描述;但這並非實施或運用本發明具體實施例的唯一形式。以下所揭露的各實施例,在有益的情形下可相互組合或取代,也可在一實施例中附加其他的實施例,而無須進一步的記載或說明。
在以下描述中,將詳細敘述許多特定細節以使讀者能夠充分理解以下的實施例。然而,可在無此等特定細節之情況下實踐本發明之實施例。在其他情況下,為簡化圖式,熟知的結構與裝置僅示意性地繪示於圖中。
本發明之一態樣是提供一種晶片封裝體的製造方法,藉由此製造方法可以減少製程時數和成本,也不會產生對位偏移的問題。第1圖繪示本發明之一實施方式之晶片封裝體的製造方法的流程圖。第2至11圖繪示本發明一實施
方式之晶片封裝體製造方法中各製程階段的剖面示意圖。如第1圖所示,方法100包含步驟S110、步驟S120、步驟S130、步驟S140、步驟S150、步驟S160及步驟S170。
在步驟S110中,提供晶圓20,如第2圖所示。具體的說,晶圓20具有一上表面210及與其相對之一下表面220,且晶圓20包含多個導電墊230位於上表面210。在一實施例中,晶圓20可包含矽(silicon)、鍺(Germanium)或III-V族元素,但不以此為限。在多個實施例中,導電墊230包含銅(copper)、鎳(nickel)、錫(tin)或其他合適的導電材料。在一些實施例中,晶圓20具有一厚度20T1為525至725微米,例如可為550微米、575微米、600微米、625微米、650微米、675微米或700微米。
在步驟S120中,切割晶圓20之上表面210以形成多個凹槽240,如第3圖所示。在多個實施例中,可使用刀輪切割、雷射切割或水刀切割來實現此步驟S120。在一實施例中,各凹槽240具有一寬度240W為50至60微米,且具有一深度240D為120至200微米。舉例來說,寬度240W可以為51微米、52微米、53微米、54微米、55微米、56微米、57微米、58微米或59微米,且深度240D可以為125微米、130微米、135微米、140微米、145微米、150微米、155微米、160微米、165微米、170微米、175微米、180微米、185微米、190微米或195微米,但不限於此。
在步驟S130中,形成一圖案化光阻層於上表面上及凹槽內。第4圖至第5圖為本發明一實施方式用以實現
步驟S130的剖面示意圖。如第4圖所示,形成一光阻層250填充凹槽240並全面覆蓋晶圓20的上表面210。在一實施例中,光阻層250在晶圓20的上表面210上具有一特定厚度。在多個實施例中,光阻層250可以為正型光阻層或負型光阻層。在一實施例中,可以藉由噴塗(spray)、印刷(printing)、塗佈(coating)或電著光阻(Electro-deposited photoresist)的方式形成光阻層250。
接著,如第5圖所示,在一實施方式中,可以進行曝光顯影製程使得光阻層250形成一圖案化光阻層250P。圖案化光阻層250P包含第一部分250a和第二部分250b,其中第一部分250a填充在凹槽240中,且第二部分250b位於上表面210之任兩相鄰的導電墊230之間。詳細的說,曝光光阻層250的方式例如可以是以具有特定圖案的光罩(圖未示)搭配適當波長之紫外光(圖未示),對光阻層250進行曝光。值得注意的是,當光阻層250係採用正型光阻層時,曝光的部分光阻層會轉化為已曝光光阻,且已曝光光阻將在往後的顯影步驟中被洗去,留下未被曝光的另一部分光阻層。換言之,第5圖所示即圖案化光阻層250P會形成多個凹部250R,且導電墊230會藉由這些凹部250R而暴露出來。也就是說,光罩的特定圖案中遮蔽紫外光的部分,即為後續未被曝光所留下來的另一部分光阻層。在此值得特別注意的是,於曝光顯影光阻層250的步驟中,凹部250R之中的光阻層250被曝光並顯影洗去,使晶圓20上表面210的導電墊230暴露出來。相反地,當光阻層250採用的是負型光
阻層時,凹部250R之中的光阻層250則需以光罩遮蔽不可曝光,方能在後續顯影中被洗去。
在步驟S140中,形成多個導電凸塊260分別位於對應的這些導電墊230上,如第6圖所示。在一實施例中,導電凸塊260具有一高度260H為20至45微米,例如可為22微米、24微米、26微米、28微米、30微米、32微米、34微米、36微米、38微米、40微米、42微米或44微米。在多個實施例中,導電凸塊260的頂表面可以略高、齊平或略低於圖案化光阻層250P的頂表面。在一些實施例中,導電凸塊260包含金(gold)、錫(tin)、銅(copper)、鎳(nickel)或其他合適的金屬材料。在一些實施例中,可以藉由電鍍(plating)、濺鍍(sputtering)、蒸鍍(evaporation)或其他適當之製程方法形成導電凸塊260。應注意,圖案化光阻層250P的第二部分250b可以直接當作在形成導電凸塊260的光罩,進而可以減少一道微影蝕刻金屬材料層的製程。此外,圖案化光阻層250P的第二部分250b也可以作為後續形成晶片封裝體的封裝層,用以保護晶圓20的上表面210。
接著,請參閱第7圖,在多個實方式中,可以在形成導電凸塊260的步驟S140之後,形成一表面處理層310於導電凸塊260上。在一些實施例中,表面處理層310可為單層結構或是由不同材料之子層所組成的多層結構,其中單層結構例如可為鎳層或錫層等,多層結構例如可為鎳金層等,但不限於此。表面處理層310的形成方法包括但不限於物理方式,例如電鍍鎳金和噴錫,或者化學方式,例如化鎳
浸金(Electroless Nickel Immersion Gold,ENIG)。表面處理層310可以防止導電凸塊260接觸空氣而被氧化。
請參閱第8圖,可在步驟S140之後,先形成一黏著層320覆蓋圖案化光阻層250P和導電凸塊260,接著形成一載板330於黏著層320上。黏著層320能減少後續薄化製程中產生的應力,因此降低了晶圓破裂的風險。在一實施例中,黏著層320包含紫外光解膠(UV release adhesive)或熱釋放膠(thermal release adhesive)。在一實施例中,形成黏著層320的方式例如可以是旋轉塗佈(spin coating),但不以此方式為限。載板330可以對晶圓20提供較佳的保護效果,因此,載板330可以是硬質絕緣基板,比如是玻璃基板、陶瓷基板、藍寶石基板或石英基板,但不限於此。
在其他實施方式中,可在形成表面處理層310於導電凸塊260上的步驟之後,形成黏著層320覆蓋圖案化光阻層250P和表面處理層310,接著形成一載板330於黏著層320上。
在步驟S150中,由下表面220朝上表面210薄化晶圓20,使凹槽240內之圖案化光阻層250P由下表面220暴露出來,如第9圖所示。薄化晶圓20的方式例如可以使用化學機械研磨(chemical-mechanical polishing)、乾蝕刻等適當的製程方法進行,以讓最後形成的晶片封裝體具有較小的尺寸。在一些實施例中,在薄化晶圓20的步驟S150之後,晶圓20的厚度20T2為100至150微米,例如110微米、
115微米、120微米、125微米、130微米、135微米、140微米或145微米。在完成此步驟S150之後,晶圓20被分開成多個晶片,且這些晶片藉由凹槽240中的圖案化光阻層250P使得晶片之間的相對位置維持不變。如此,可以解決先前技術中對位偏移的問題。
在步驟S160中,形成一絕緣層270於下表面220下方,如第10圖所示。絕緣層270可以作為晶片封裝體的封裝層,用以保護晶圓20的下表面220。在多個實施例中,絕緣層270所使用的材料可以是聚亞醯胺(polyimide)、環氧樹脂(Epoxy)或其它合適之絕緣材料。在一些實施例中,可以藉由印刷(printing)、塗佈(coating)或封膠(molding)的方式來形成絕緣層270。於本實施例中,在形成絕緣層270的步驟S160之後,晶圓20、絕緣層270和導電凸塊260具有一總厚度Tf為120至210微米,例如可為125微米、130微米、135微米、140微米、145微米、150微米、155微米、160微米、165微米、170微米、175微米、180微米、185微米、190微米、195微米、200微米或205微米。
然後,請參閱第11圖,在形成絕緣層270的步驟S160之後,移除載板330及黏著層320。詳細的說,可以藉由紫外光照射或加熱黏著層320,使得載板330可以隨著黏著層320的黏性下降得以一併脫落。
如第11圖所示,在某些實施例中,可以在形成絕緣層270的步驟S160之後,在每個對應之晶片的絕緣層
270上設置雷射標記(Laser Mark)340編碼。
在步驟S170中,沿著各凹槽240切割圖案化光阻層250P和絕緣層270,以形成多個晶片封裝體,如第12圖所示。在一實施例中,例如可沿著各凹槽240的中心240C切割圖案化光阻層250P和絕緣層270,以形成多個晶片封裝體。在多個實施例中,可使用刀輪切割、雷射切割或水刀切割來實現此步驟S170。於本實施例中,沿著各凹槽240切割圖案化光阻層250P和絕緣層270的切割寬度CW為15至22微米,例如可為15.5微米、16.0微米、16.5微米、17.0微米、17.5微米、18.0微米、18.5微米、19.0微米、19.5微米、20.0微米、20.5微米、21.0微米或21.5微米。須說明的是,由於切割寬度CW小於凹槽240的寬度240W,因此在執行步驟S170之後所得到的每個晶片封裝體,其鄰近凹槽240中心240C的側壁仍具有部分的圖案化光阻層250P保護晶圓20。換言之,每個晶片封裝體的各個表面皆有圖案化光阻層250P和絕緣層270的保護,並僅暴露出表面處理層310作為外部電性連接之用。
在多個實例中,晶片封裝體可用以封裝光感測元件或發光元件。然其應用不限於此,舉例來說,其可應用於各種包含離散元件、主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components),例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical
System,MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package,WSP)製程對影像感測元件、發光二極體(light-emitting diodes,LEDs)、二極體(Diode)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
綜上所述,本發明之晶片封裝體的製造方法不但可以減少製程時數和成本,也不會產生對位偏移的問題。
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧方法
S110、S120、S130、S140‧‧‧步驟
S150、S160、S170‧‧‧步驟
Claims (9)
- 一種晶片封裝體的製造方法,包含:提供一晶圓,該晶圓具有一上表面及與其相對之一下表面,該晶圓包含多個導電墊位於該上表面;切割該晶圓之該上表面以形成多個凹槽;形成一圖案化光阻層於該上表面上及該些凹槽內;形成多個導電凸塊分別位於對應的該些導電墊上;形成一表面處理層於該些導電凸塊上;由該下表面朝該上表面薄化該晶圓,使該些凹槽內之該圖案化光阻層由該下表面暴露出來;形成一絕緣層於該下表面下方;以及沿著各該凹槽切割該圖案化光阻層和該絕緣層,以形成多個晶片封裝體。
- 如請求項1所述之晶片封裝體的製造方法,在形成該些導電凸塊的步驟之後且在薄化該晶圓的步驟之前,更包含:形成一黏著層覆蓋該圖案化光阻層和該些導電凸塊;以及形成一載板於該黏著層上。
- 如請求項2所述之晶片封裝體的製造方法,在形成該絕緣層的步驟之後且在沿著各該凹槽切割該圖案化光阻層和該絕緣層的步驟之前,更包含: 移除該載板及該黏著層。
- 如請求項1所述之晶片封裝體的製造方法,其中在薄化該晶圓的步驟之後,該晶圓的厚度為100至150微米。
- 如請求項1所述之晶片封裝體的製造方法,其中在形成該絕緣層的步驟之後,該晶圓、該些導電凸塊和該絕緣層具有一總厚度為120至210微米。
- 如請求項1所述之晶片封裝體的製造方法,其中沿著各該凹槽切割該圖案化光阻層和該絕緣層的一切割寬度為15至22微米。
- 如請求項1所述之晶片封裝體的製造方法,其中各該導電凸塊具有一高度為20至45微米。
- 如請求項1所述之晶片封裝體的製造方法,其中各該凹槽具有一寬度為50至60微米,且具有一深度為150至200微米。
- 如請求項1所述之晶片封裝體的製造方法,在提供該晶圓的步驟之後,該晶圓具有一厚度為525至725微米。
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