CN207966971U - General-purpose built-up circuit layer for semiconductor package - Google Patents
General-purpose built-up circuit layer for semiconductor package Download PDFInfo
- Publication number
- CN207966971U CN207966971U CN201820517801.9U CN201820517801U CN207966971U CN 207966971 U CN207966971 U CN 207966971U CN 201820517801 U CN201820517801 U CN 201820517801U CN 207966971 U CN207966971 U CN 207966971U
- Authority
- CN
- China
- Prior art keywords
- general
- circuit layer
- purpose built
- area
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000009413 insulation Methods 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 abstract description 3
- 238000005538 encapsulation Methods 0.000 description 9
- 230000005540 biological transmission Effects 0.000 description 3
- 230000004064 dysfunction Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000011664 signaling Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model discloses a kind of general-purpose built-up circuit layers for semiconductor package, it is disposed upon on chip, and chip is disposed upon on substrate, and the general-purpose built-up circuit floor includes extending signal region, at least a relay contact area, access area, power supply area and electric insulation layer, wherein extend signal region, relay contact area, access area and power supply area are to be constructed from a material that be electrically conducting and conductive, and positioned at the upper surface of electric insulation layer.In addition, it includes multiple signal line and multiple connection pads to extend signal region, and relay contact area includes multiple relay contacts.Especially, it is arranged in parallel between each signal line, and connects an at least connection pad, and connection pad, relay contact, access area, power supply area and the pin selecting type are electrically connected by lead to the connection mound of the substrate.
Description
Technical field
The utility model is related to a kind of general-purpose built-up circuit layer for semiconductor package, especially with connection pad,
Relay contact, access area, power supply area and pin and be electrically connected by corresponding lead according to the electric function of chip.
Background technology
In the encapsulation procedure of the general prior art, need partly to lead to realize using bonding wire or routing (wire bonding)
Electrical connection between the integrated circuit (IC) and lead frame of body, and routing typically uses gold thread, aluminum steel or copper wire, will integrate
The pin of circuit is connected to the pin of lead frame, finally carries out encapsulating solidification and completes to encapsulate.
The pin of integrated circuit must be configured with the design of internal circuit, used and reached optimum performance, and when difference
When routing between pin and corresponding pin occurs to interlock, it is easy to short circuit occur, alternatively, if between pin and pin
Routing is apart from too long, then when follow-up pressing mold is handled, bonding wire is highly susceptible to excessive mould stream punching press and deviates, and influences electrically,
Even short circuit and fail.
Therefore, it is sought after a kind of general-purpose built-up circuit layer for semiconductor package of innovation, can not only simplify and beat
The design of line shortens routing distance, moreover it is possible to avoid interlocking, use and solve above-mentioned problem of the prior art.
Utility model content
In view of the deficiencies of the prior art, the purpose of this utility model is to provide a kind of general-purpose for semiconductor package
Built-up circuit layer.
In order to achieve the above object, the utility model uses technical solution as described below：
The utility model discloses a kind of general-purpose built-up circuit layer for semiconductor package comprising：One extends news
Number area, including multiple signal line and multiple connection pads, such signal line are arranged in parallel, and each such signal line connects to
A few connection pad, and the corresponding connection pad that the different signal line is connected is arranged to be spaced from each other without contacting；At least one
Relay contact area, each relay contact area include multiple relay contacts；One access area；One power supply area；An and electric insulation
Layer has electric insulating quality, and the extension signal region, at least a relay contact area, the access area and the power supply area are led by one for this
Electric material constitute and it is conductive, and positioned at the electric insulation layer a upper surface；Wherein the general-purpose built-up circuit layer is peace
It sets in a upper surface of a chip, and the chip is further placed in a upper surface of a substrate, which has a line map
Case and multiple pins, the connection pad, the relay contact, the access area, the power supply area and the pin of the general-purpose built-up circuit layer, can
Selecting type is electrically connected by lead to the connection mound of the substrate.
Preferably, this at least a relay contact area is disposed on a left border region of the general-purpose built-up circuit floor, one
Top edge region and a right border region.
Preferably, the access area and the power supply area are arranged to adjacent and do not contact.
Preferably, such signal line connected this at least a connection pad is arranged to wavy arrangement.
Preferably, at least connection pad that such signal line is connected is arranged to parallel shape arrangement.
Preferably, the access area and the power supply area are strip.
In an embodiment of the utility model, which is a flash memory.
Preferably, the substrate or the flash memory are equipped with a controller, which has multiple connection gaskets, general-purpose switching
The connection pad of circuit layer, the relay contact, the access area, the power supply area and the contact, selecting type electrically connect by lead
It is connected to the connection mound of the substrate, the connection gasket of the flash memory or the controller.
The utility model discloses another general-purpose built-up circuit layer for being used for semiconductor package comprising：One extends
Signal region, including multiple signal line and multiple connection pads, such signal line are arranged in parallel, and each such signal linear system connection
An at least connection pad, and the corresponding connection pad that the different signal line is connected is arranged to be spaced from each other without contacting；At least
One relay contact area, each relay contact area include multiple relay contacts；One access area；One power supply area；And one it is electrical absolutely
Edge layer has electric insulating quality, and the extension signal region, at least a relay contact area, the access area and the power supply area are by one for this
Conductive material constitute and it is conductive, and positioned at the electric insulation layer a upper surface；Wherein the general-purpose built-up circuit layer is
It is placed in a upper surface of one first chip, and first chip is further placed in a upper table of one of lead frame supporting seat
Face, the connection pad, the relay contact, the access area, the power supply area and the pin selecting type of the general-purpose built-up circuit layer by
Lead and be electrically connected to one of lead frame pin.
Preferably, this at least a relay contact area is disposed on a left border region of the general-purpose built-up circuit floor, one
Top edge region and a right border region.
Preferably, the access area and the power supply area are arranged to adjacent and do not contact.
Preferably, such signal line connected this at least a connection pad is arranged to wavy arrangement.
Preferably, at least connection pad that such signal line is connected is arranged to parallel shape arrangement.
Preferably, the access area and the power supply area are strip.
Preferably, one second chip is set between first chip and the supporting seat, and this of the general-purpose built-up circuit layer connects
Pad, the relay contact, the access area, the power supply area selecting type are electrically connected one of lead frame pin and second by lead
The connection gasket of chip.
Therefore, compared with the prior art, the advantages of the utility model, includes：The general-purpose built-up circuit layer of the utility model can carry
Signal signaling transfer point between substrate, chip can significantly simplify so being not required between substrate, chip directly carry out routing
The configuration of lead improves routing yield, and shortens the distance of lead, improves the transmission quality of electrical signal, while being also avoided that
Lead interlocks, and effectively prevent that signal short circuit occurs and leads to dysfunction or even fails.
In addition, the general-purpose built-up circuit layer of the utility model has higher design flexibility, exploitation switching can be greatly decreased
The design cost of plate is especially not limited to specific chip design, so the utility model can be used on various chips
Or arrange in pairs or groups with it, thus promote application elasticity and expand application field.
Description of the drawings
Fig. 1 is the signal of the general-purpose built-up circuit layer for semiconductor package in one exemplary embodiments of the utility model
Figure.
Fig. 2 is that the general-purpose built-up circuit layer in another exemplary embodiments of the utility model for semiconductor package shows
It is intended to.
Fig. 3 is the semiconductor package completed using the general-purpose built-up circuit layer of one exemplary embodiments of the utility model
Top view.
Fig. 4 is the A-A sectional views of semiconductor package in Fig. 3.
Fig. 5 is another semiconductor packages completed using the general-purpose built-up circuit layer of one exemplary embodiments of the utility model
The top view of structure.
Fig. 6 is the sectional view of semiconductor package in Fig. 4.
Fig. 7 is the another semiconductor packages completed using the general-purpose built-up circuit layer of one exemplary embodiments of the utility model
The top view of structure.
Fig. 8 is the sectional view of semiconductor package in Fig. 7.
Fig. 9 is the another semiconductor packages completed using the general-purpose built-up circuit layer of one exemplary embodiments of the utility model
The sectional view of structure.
Reference sign：10- general-purpose built-up circuit layers, 11- extend signal region, 11A- signal line, 11B- connection pads, 12-
Relay contact area, 12A- relay contacts, the access areas 13-, 14- power supply areas, 15- electric insulation layers, 20- chips, 30- substrates, 32-
Pin, 33 connections are abundant, 34- lead frames, 35- supporting seats, 36- pins, and 40,41- leads, 60- controllers, 62- connection gaskets, 70-
Flash memory.
Specific implementation mode
In view of deficiency in the prior art, inventor is able to propose that this practicality is new through studying for a long period of time and largely putting into practice
The technical solution of type.Below in conjunction with attached drawing and more specifically embodiment is to the technical solution of the utility model, its implementation process
And the works such as principle are further clear, complete explanation.
Icon and component symbol is coordinated to do more detailed description to the embodiment of the utility model below, so that being familiar with this
Item those skilled in the art can implement according to this after studying this specification carefully.
Referring to Fig. 1, schematic diagram of the utility model embodiment for the general-purpose built-up circuit layer of semiconductor package.
As shown in Fig. 1, the general-purpose built-up circuit layer 10 of the utility model embodiment includes extending signal region 11, at least a relay contact
Area 12, access area 13, power supply area 14 and electric insulation layer 15, wherein extending signal region 11, relay contact area 12, access area 13
And power supply area 14 is to be constructed from a material that be electrically conducting and conductive, and positioned at the upper surface of electric insulation layer 15.Further, above-mentioned
Extension signal region 11 include multiple signal line 11A and multiple connection pad 11B, wherein such signal line 11A is arranged in parallel, and
Each signal line 11A connection at least connection pad 11B, and the corresponding connection pad 11B that different signal line 11A is connected is configuration
At be spaced from each other without contact.In addition, relay contact area 12 includes multiple relay contact 12A, and electric insulation layer 15 is tool
Electric insulating quality.In particular, it is to be constructed from a material that be electrically conducting to extend signal region 11, relay contact area 12, access area 13 and power supply area 14
And it is conductive, and positioned at the upper surface of electric insulation layer 15.
More specifically, the general-purpose built-up circuit layer 10 in Fig. 1 is that exemplary expression shares 16 signal line 11A,
And it is divided into 4 groups, that is, each group includes 4 signal line 11A, wherein each signal line 11A connect multiple connection pad 11B certainly, because
And it will be apparent that the corresponding connection pad 11B of adjacent two signal line 11A is not in the same horizontal position, but there is difference of height, institute
With on the whole, all signal line 11A are such as to be repeated as many times with the arrangement mode from top to bottom right from a left side, use to be formed
Dipping and heaving it is wavy.This wavy connection pad 11B can solve the problems, such as that chip 20 occurs staggeredly in routing.
In addition, each relay contact 12A in relay contact area 12 can be adopted to turn wire jumper, it is avoided that the distance mistake of lead 40
Yield that is long and influencing routing, or generate the risk of cross-line.Furthermore since access area 13 and power supply area 14 are designed to strip
Shape, so will not all interlock when with 20 routing of chip.Generally speaking, the utility model can be provided shortest beats using upper
Thread path.
As shown in Fig. 2, the adjacent two signal line 11A and connection pad 11B of the general-purpose built-up circuit layer 10 of the utility model are visual
Be electrically connected need, be designed as being arranged parallel to each other, so it is without being limited thereto, general-purpose built-up circuit layer be adjacent two signal line 11A and
Connection pad 11B can be the design of the assembled arrangement of rule or random geometry.
As shown in Figures 3 and 4, for completed using the general-purpose built-up circuit layer of one exemplary embodiments of the utility model half
The top view and sectional view of conductor package structure, in this semiconductor package, the general-purpose built-up circuit layer of the utility model
10 are disposed upon the upper surface of chip 20, and chip 20 is further to be placed in the upper surface of substrate 30, and then transferred by general-purpose
Circuit layer 10 provides the electrical signal signaling transfer point between chip 20 and substrate 30 so that this of general-purpose built-up circuit layer 30 connects
Pad 11B, relay contact 12A, the access area 12 in relay contact area 12,13 selecting type of power supply area are electric by lead 40
Gas is connected to the connection mound 33 of the substrate 30.As shown in figure 3, the connection mound 33 of substrate 30 is electrically connected the power supply area 14, it is profit
With lead 40 via the connection pad 11B of the adjacent specific range on same signal line 11A, relaying is electrically connected the connection of the substrate 30
Mound 33 and the power supply area 14 improve the transmission quality of electrical signal to prevent deformation that is long using single lead 40 and generating,
It is also avoided that lead 40 interlocks simultaneously, effectively prevent that signal short circuit occurs and leads to dysfunction or even fails.
As shown in Figures 5 and 6, respectively according to view and section view on another semiconductor package of the utility model
Figure, and also referring to Fig. 1.In this embodiment, there is semiconductor package lead frame 34, wherein lead frame 34 to be held including one
Put seat 35 and a pin 36.The general-purpose built-up circuit layer 10 of the utility model can be placed in the upper surface of the first chip 20, and first
Chip 20 be further be placed on the second chip 21, and the second chip 21 be positioned over lead frame 34 supporting seat 35 and simultaneously can be according to
According to the first chip 20 and the electric function of the second chip 21, lead 40 is electrically connected general-purpose built-up circuit layer by selecting type respectively
10 connection pad 11B, relay contact 12A, access area 13, power supply area 14 and the second connection gasket 22 of chip 21 and drawing for lead frame 34
Foot 36.
Therefore the utility model is used for the general-purpose built-up circuit layer of semiconductor package, is suitable for classes of semiconductors and encapsulates
Structure, such as the attached leaded chip bearing (PLCC) of encapsulation group (DIP), plastics, quadrangle flat panel enclosure group (QFP), low shape in two-wire
Quadrangle flat panel enclosure group (LQFP), thin small outline border encapsulation group (TSOP), slim quadrangle flat panel enclosure group (TQFP), band bearing
Encapsulation group (TCP), ball trellis array (BGA), Chip Size Package group (CSP), the non-lead encapsulation group of quadrangle tablet
(QFN), the non-lead encapsulation group (SON) of small-sized outline border, lead frame BGA (LF-BGA), module array encapsulation group type BGA
(MAP-BGA) and the usual well known semiconductor package of memory card (Memory Card) etc..
With further reference to the top view and sectional view of Fig. 7 and Fig. 8, respectively the utility model embodiment general-purpose is utilized to transfer
The schematic diagram for the another semiconductor package that circuit layer is completed, and also referring to Fig. 1.In this semiconductor package,
It is general-purpose built-up circuit layer 10, substrate 30, controller 60 and the flash memory 70 for including the utility model, wherein general-purpose built-up circuit
Layer 10 be as between substrate 30, controller 60, flash memory 70 signal transfer medium, meanwhile, utilize corresponding lead 41
And it connects.
Furthermore, flash memory 70 is disposed upon the upper surface of substrate 30, and general-purpose built-up circuit layer 10 and controller
60 are disposed upon the upper surface of flash memory 70.Furthermore include multiple connection gaskets 62, wherein general-purpose positioned at controller 60 on flash memory 70
Built-up circuit layer 10 and controller 60 are separated without being in contact.Furthermore the semiconductor package such as Fig. 9 is please referred to, is dodged
Depositing 70 can optionally be placed on substrate 30 with controller 60, non-flash memory 70 as shown in Figure 8 and the side that controller 60 is storehouse
Formula is placed on substrate 30.Specifically, the controller 60 of Fig. 8 and Fig. 9 by corresponding lead 41 company in the way of routing
It is connected to general-purpose built-up circuit layer 10 and substrate 30, for example certain connection gaskets 62 of controller 60 may be connected to general-purpose built-up circuit layer
10 corresponding multiple relay contact 12A, and other connection gaskets 62 may be connected to corresponding multiple connection mounds 33 of substrate 30,
So that controller 60 can transfer via the signal of general-purpose built-up circuit layer 10 and be electrically connected to substrate 30.
Generally speaking, each connection pad 11B of general-purpose built-up circuit layer 10, each relay contact 12A, access area 13, power supply
14 selecting type of area is by being by corresponding lead and the connection mound 33 of electric connecting substrate 30, the connection gasket of controller 60
62 or flash memory 70, in other words, the primary efficacy of general-purpose built-up circuit layer 10 is to provide substrate 30, flash memory 70 and controller
Electrical connection between 60 so that flash memory 70 is not required to direct routing to substrate 30, controller 60, thus can shorten routing distance,
And simplify routing configuration, while generation routing being avoided staggeredly to influence electric property.Furthermore above-mentioned semiconductor package is very
It is suitably applied the encapsulation field of memory card, but is not limited by this.
In conclusion being mainly characterized by for the utility model provides signal signaling transfer point using general-purpose built-up circuit layer,
General-purpose built-up circuit layer is electrically connected to substrate by lead, can so be not required between substrate, chip directly carry out routing
The configuration of lead is significantly simplified, routing yield is improved, and shorten the distance of lead, improves the transmission quality of electrical signal, simultaneously
It is also avoided that lead interlocks, effectively prevent that signal short circuit occurs and leads to dysfunction or even fails.
Another feature of the utility model is to provide between substrate, flash memory, controller using general-purpose built-up circuit layer
Electrical interconnecting function, wherein general-purpose built-up circuit layer, controller are on flash memory, and flash memory is electrically connected to the line map of substrate
Case.Since the wiring layout of whole structure simplifies very much, it is well suited for being applied to memory card or needs high integration and more frivolous short
The encapsulation process of miscellaneous goods.
Generally speaking, the design cost of exploitation pinboard can be greatly decreased in the general-purpose built-up circuit layer of the utility model, especially
It is that the design flexibility of general-purpose built-up circuit layer is higher, it is not limited to specific chip design, so the utility model can
It is used on various chips or arranges in pairs or groups with it, thus promote application elasticity, expand application field.
It should be appreciated that the above preferred embodiment is merely to illustrate the content of the utility model, in addition to this, the utility model
Also other embodiment, as long as those skilled in the art because of the technical inspiration involved by the utility model, and use and equally replace
It changes or technical solution that equivalent deformation mode is formed is all fallen in the scope of protection of the utility model.
Claims (15)
1. a kind of general-purpose built-up circuit layer for semiconductor package, it is characterised in that including：
One extends signal region, including multiple signal line and multiple connection pads, such signal line are arranged in parallel, and each such news
Number linear system connects an at least connection pad, and the corresponding connection pad that is connected of the different signal line be arranged to be spaced from each other without
Contact；
An at least relay contact area, each relay contact area include multiple relay contacts；
One access area；
One power supply area；And
One electric insulation layer, have electric insulating quality, and the extension signal region, an at least relay contact area, the access area and should
Power supply area is made of and conductive a conductive material, and positioned at a upper surface of the electric insulation layer,
Wherein the general-purpose built-up circuit layer is disposed upon a upper surface of a chip, and the chip is further placed in a substrate
One upper surface, the substrate have a line pattern and a multiple pins, the connection pad of the general-purpose built-up circuit layer, the relay contact,
The access area, the power supply area and the pin, selecting type are electrically connected by lead to the connection mound of the substrate.
2. the general-purpose built-up circuit layer according to claim 1 for semiconductor package, it is characterised in that：This is at least
One relay contact area is disposed on a left border region, a top edge region and a right edge for the general-purpose built-up circuit floor
Edge region.
3. the general-purpose built-up circuit layer according to claim 1 for semiconductor package, it is characterised in that：The ground connection
Area and the power supply area are arranged to adjacent and do not contact.
4. the general-purpose built-up circuit layer according to claim 1 for semiconductor package, it is characterised in that：Such news
Number line connected this at least a connection pad is arranged to wavy arrangement.
5. the general-purpose built-up circuit layer according to claim 1 for semiconductor package, it is characterised in that：Such news
At least connection pad that number line is connected is arranged to parallel shape arrangement.
6. the general-purpose built-up circuit layer according to claim 1 for semiconductor package, it is characterised in that：The ground connection
Area and the power supply area are strip.
7. the general-purpose built-up circuit layer according to claim 1 for semiconductor package, it is characterised in that：The chip
System is a flash memory.
8. the general-purpose built-up circuit layer according to claim 7 for semiconductor package, it is characterised in that：The substrate
Or the flash memory is equipped with a controller, which has multiple connection gaskets, the connection pad, the relaying of the general-purpose built-up circuit layer
Contact, the access area, the power supply area and the contact, selecting type be electrically connected by lead the connection to the substrate it is abundant,
The connection gasket of the flash memory or the controller.
9. a kind of general-purpose built-up circuit layer for semiconductor package, it is characterised in that including：
One extends signal region, including multiple signal line and multiple connection pads, such signal line are arranged in parallel, and each such news
Number linear system connects an at least connection pad, and the corresponding connection pad that is connected of the different signal line be arranged to be spaced from each other without
Contact；
An at least relay contact area, each relay contact area include multiple relay contacts；
One access area；
One power supply area；And
One electric insulation layer, have electric insulating quality, and the extension signal region, an at least relay contact area, the access area and should
Power supply area is made of and conductive a conductive material, and positioned at a upper surface of the electric insulation layer,
Wherein the general-purpose built-up circuit layer is disposed upon a upper surface of one first chip, and first chip is further placed in
One upper surface of one of one lead frame supporting seat, the connection pad of the general-purpose built-up circuit layer, the access area, are somebody's turn to do at the relay contact
Power supply area and the pin selecting type are electrically connected by lead to one of lead frame pin.
10. the general-purpose built-up circuit layer according to claim 9 for semiconductor package, it is characterised in that：This is extremely
A few relay contact area is disposed on a left border region, a top edge region and a right side for the general-purpose built-up circuit floor
Fringe region.
11. the general-purpose built-up circuit layer according to claim 9 for semiconductor package, it is characterised in that：This connects
Area and the power supply area are arranged to adjacent and do not contact.
12. the general-purpose built-up circuit layer according to claim 9 for semiconductor package, it is characterised in that：It is such
Signal line connected this at least a connection pad is arranged to wavy arrangement.
13. the general-purpose built-up circuit layer according to claim 9 for semiconductor package, it is characterised in that：It is such
At least connection pad that signal line is connected is arranged to parallel shape arrangement.
14. the general-purpose built-up circuit layer according to claim 9 for semiconductor package, it is characterised in that：This connects
Area and the power supply area are strip.
15. the general-purpose built-up circuit layer according to claim 9 for semiconductor package, it is characterised in that：This
One second chip, the connection pad of the general-purpose built-up circuit layer, the relay contact, the ground connection are set between one chip and the supporting seat
Area, the power supply area selecting type are electrically connected the connection gasket of one of lead frame pin and the second chip by lead.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820517801.9U CN207966971U (en) | 2018-04-12 | 2018-04-12 | General-purpose built-up circuit layer for semiconductor package |
| TW107205109U TWM565880U (en) | 2018-04-12 | 2018-04-19 | Universal adapting circuit layer for semiconductor package structure |
| TW107113313A TWI677956B (en) | 2018-04-12 | 2018-04-19 | A universal transfer layer for semiconductor packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820517801.9U CN207966971U (en) | 2018-04-12 | 2018-04-12 | General-purpose built-up circuit layer for semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207966971U true CN207966971U (en) | 2018-10-12 |
Family
ID=63727774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820517801.9U Withdrawn - After Issue CN207966971U (en) | 2018-04-12 | 2018-04-12 | General-purpose built-up circuit layer for semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207966971U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108336056A (en) * | 2018-04-12 | 2018-07-27 | 苏州震坤科技有限公司 | General-purpose built-up circuit layer for semiconductor package |
-
2018
- 2018-04-12 CN CN201820517801.9U patent/CN207966971U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108336056A (en) * | 2018-04-12 | 2018-07-27 | 苏州震坤科技有限公司 | General-purpose built-up circuit layer for semiconductor package |
| CN108336056B (en) * | 2018-04-12 | 2024-06-04 | 苏州震坤科技有限公司 | Universal switching circuit layer for semiconductor packaging structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102201388B (en) | QFN semiconductor package and fabrication method thereof | |
| US6534879B2 (en) | Semiconductor chip and semiconductor device having the chip | |
| US7274092B2 (en) | Semiconductor component and method of assembling the same | |
| CN101154607A (en) | Unmolded package for a semiconductor device | |
| CN102768959B (en) | Integrated circuit package system and its manufacture method with coiling circuit lead array | |
| US7671474B2 (en) | Integrated circuit package device with improved bond pad connections, a lead-frame and an electronic device | |
| CN103050467B (en) | Encapsulating structure and manufacture method thereof | |
| CN105826209A (en) | Package structure and method to fabricate same | |
| US20080308951A1 (en) | Semiconductor package and fabrication method thereof | |
| CN207966971U (en) | General-purpose built-up circuit layer for semiconductor package | |
| CN101131978A (en) | Integrated circuit packaging construction and multi-layer conducting wire holder used for it | |
| TWI677956B (en) | A universal transfer layer for semiconductor packaging structure | |
| US20080150098A1 (en) | Multi-chip package | |
| US20070267756A1 (en) | Integrated circuit package and multi-layer lead frame utilized | |
| US20150084171A1 (en) | No-lead semiconductor package and method of manufacturing the same | |
| CN115995440A (en) | Semiconductor packaging structure and manufacturing method thereof | |
| US7154169B2 (en) | Substrate for IC package | |
| CN108336056A (en) | General-purpose built-up circuit layer for semiconductor package | |
| US7242083B2 (en) | Substrate for IC package | |
| CN103107145A (en) | Semiconductor package, prefabricated lead frame and manufacturing method thereof | |
| JP3211532U (en) | Lead frame preform and lead frame package | |
| US5866941A (en) | Ultra thin, leadless and molded surface mount integrated circuit package | |
| US20030080418A1 (en) | Semiconductor device having power supply pads arranged between signal pads and substrate edge | |
| JPH0256942A (en) | Semiconductor device | |
| CN206480617U (en) | Without Pin-Grid Array lead frame preform and lead frame encapsulation structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20181012 Effective date of abandoning: 20240604 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20181012 Effective date of abandoning: 20240604 |
|
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |