TWI667653B - 記憶胞 - Google Patents

記憶胞 Download PDF

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Publication number
TWI667653B
TWI667653B TW107135207A TW107135207A TWI667653B TW I667653 B TWI667653 B TW I667653B TW 107135207 A TW107135207 A TW 107135207A TW 107135207 A TW107135207 A TW 107135207A TW I667653 B TWI667653 B TW I667653B
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TW
Taiwan
Prior art keywords
transistor
voltage
memory cell
coupled
terminal
Prior art date
Application number
TW107135207A
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English (en)
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TW201916035A (zh
Inventor
印秉宏
王佳祥
Original Assignee
香港商印芯科技股份有限公司
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Priority to US16/274,263 priority Critical patent/US10580483B1/en
Publication of TW201916035A publication Critical patent/TW201916035A/zh
Application granted granted Critical
Publication of TWI667653B publication Critical patent/TWI667653B/zh

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    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
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    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21K—NON-ELECTRIC LIGHT SOURCES USING LUMINESCENCE; LIGHT SOURCES USING ELECTROCHEMILUMINESCENCE; LIGHT SOURCES USING CHARGES OF COMBUSTIBLE MATERIAL; LIGHT SOURCES USING SEMICONDUCTOR DEVICES AS LIGHT-GENERATING ELEMENTS; LIGHT SOURCES NOT OTHERWISE PROVIDED FOR
    • F21K9/00—Light sources using semiconductor devices as light-generating elements, e.g. using light-emitting diodes [LED] or lasers
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Abstract

一種記憶胞，其包括第一電晶體、反相器以及第二電晶體。第一電晶體的第一端用以做為記憶胞的資料輸入端。第一電晶體的控制端接收寫入控制信號。第一電晶體的第二端耦接記憶節點。反相器的輸入端耦接記憶節點。反相器的輸出端用以做為記憶胞的資料輸出端。第二電晶體的第一端耦接第一電壓。第二電晶體的控制端耦接反相器的輸出端。第二電晶體的第二端耦接記憶節點。第二電晶體的基體耦接第二電壓，其中第二電壓的電壓值不等於第一電壓的電壓值，以降低第二電晶體的漏電流。

Description

記憶胞
本發明是有關於一種記憶胞，且特別是有關於一種可改善漏電流狀況的記憶胞。
在深次微米技術中，電晶體的漏電流(leakage)已成為一個非常關鍵且不可忽視的問題。特別是，在以電晶體所設計的記憶胞中，漏電流會造成其所儲存的資料發生錯誤。因此，如何改善記憶胞的漏電流，乃是本領域技術人員所面臨的重大課題之一。
有鑑於此，本發明提供一種可改善漏電流狀況的記憶胞。
本發明的記憶胞包括第一電晶體、反相器以及第二電晶體。第一電晶體的第一端用以做為記憶胞的資料輸入端。第一電晶體的控制端接收寫入控制信號。第一電晶體的第二端耦接記憶節點。反相器的輸入端耦接記憶節點。反相器的輸出端用以做為記憶胞的資料輸出端。第二電晶體的第一端耦接第一電壓。第二電晶體的控制端耦接反相器的輸出端。第二電晶體的第二端耦接記憶節點。第二電晶體的基體耦接第二電壓，其中第二電壓的電壓值不等於第一電壓的電壓值，以降低第二電晶體的漏電流。
在本發明的一實施例中，上述的第二電晶體為P型金氧半場效電晶體，第一電壓與第二電壓為正電壓，且第二電壓的電壓值高於第一電壓的電壓值。
在本發明的一實施例中，上述的第一電晶體為N型金氧半場效電晶體，且第一電晶體的基體耦接負電壓。
在本發明的一實施例中，上述的第一電晶體為P型金氧半場效電晶體，且第一電晶體的基體耦接第二電壓。
在本發明的一實施例中，上述的第二電晶體為N型金氧半場效電晶體，第一電壓為接地電壓，且第二電壓為負電壓。
在本發明的一實施例中，上述的第一電晶體為P型金氧半場效電晶體，且第一電晶體的基體耦接第三電壓，其中第三電壓為正電壓，且第三電壓的電壓值高於記憶胞的資料輸入端的電壓值。
基於上述，在本發明實施例所提出的記憶胞中，藉由增加記憶胞的電晶體的基體效應，以降低電晶體與記憶節點之間的漏電流，可有效防止記憶節點所儲存的資料發生錯誤。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
為了使本發明的內容可以被更容易明瞭，以下特舉實施例做為本發明確實能夠據以實施的範例。另外，凡可能之處，在圖式及實施方式中使用相同標號的元件/構件，是代表相同或類似部件。
圖1是依照本發明一實施例所繪示的記憶胞的電路架構示意圖。請參照圖1，記憶胞100包括第一電晶體MN1、第二電晶體MP2以及反相器120。第一電晶體MN1的第一端用以做為記憶胞100的資料輸入端E_IN，第一電晶體MN1的控制端接收寫入控制信號CS，且第一電晶體MN1的第二端耦接記憶節點SN。其中可透過寫入控制信號CS導通第一電晶體MN1，以將資料輸入端E_IN的資料寫入記憶節點SN，並在資料輸入端E_IN的資料寫入記憶節點SN之後，關斷第一電晶體MN1，以將資料儲存在記憶節點SN。
反相器120的輸入端耦接記憶節點SN。反相器120的輸出端用以做為記憶胞100的資料輸出端E_OUT。第二電晶體MP2的第一端耦接第一電壓VP1。第二電晶體MP2的控制端耦接反相器120的輸出端。第二電晶體MP2的第二端耦接記憶節點SN。第二電晶體MP2的基體耦接第二電壓VP2。特別是，為了降低第二電晶體MP2的漏電流，第二電壓VP2的電壓值不等於第一電壓VP1的電壓值。
詳細來說，在圖1所示的實施例中，第二電晶體MP2為P型金氧半場效電晶體，第一電壓VP1與第二電壓VP2皆為正電壓，且第二電壓VP2的電壓值高於第一電壓VP1的電壓值。如此一來，可增加第二電晶體MP2的基體效應，以降低自第二電晶體MP2流入記憶節點SN的漏電流，從而防止記憶節點SN所儲存的資料發生錯誤。
舉例來說，當記憶節點SN所儲存的資料為邏輯低位準的資料時，反相器120的輸出端為邏輯高位準，因此第二電晶體MP2為截止狀態，故而記憶節點SN所儲存的資料可保持在邏輯低位準。然而，若第二電晶體MP2於截止狀態下的漏電流過大，將會導致記憶節點SN的電壓逐漸上升，並最終透過反相器120而導通第二電晶體MP2，致使記憶節點SN所儲存的資料成為邏輯高位準資料。因此，藉由增加第二電晶體MP2的基體效應，以降低第二電晶體MP2流至記憶節點SN的漏電流，可有效防止記憶節點SN所儲存的資料發生錯誤。
另外，在圖1所示的實施例中，第一電晶體MN1為N型金氧半場效電晶體，且第一電晶體MN1的基體耦接負電壓VN以增加第一電晶體MN1的基體效應，但本發明不限於此。可以理解的是，藉由增加第一電晶體MN1的基體效應，以降低第一電晶體MN1與記憶節點SN之間的漏電流，也可有效防止記憶節點SN所儲存的資料發生錯誤。
在本發明的一實施例中，反相器120可採用互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor， CMOS)反相器來實現，但本發明不限於此。由於CMOS反相器包括一個P型金氧半場效電晶體與一個N型金氧半場效電晶體，如此一來，圖1所示的記憶胞100則可視為四電晶體式記憶胞(4T memory cell)。
圖2是依照本發明另一實施例所繪示的記憶胞的電路架構示意圖。請參照圖2，記憶胞200包括第一電晶體MP1、第二電晶體MP2以及反相器120。圖2的記憶胞200類似於圖1的記憶胞100，兩者的差異僅在於：圖1的第一電晶體MN1為N型金氧半場效電晶體，且第一電晶體MN1的基體耦接負電壓VN以降低第一電晶體MN1與記憶節點SN之間的漏電流；而圖2的第一電晶體MP1為P型金氧半場效電晶體，且第一電晶體MP1的基體耦接第二電壓VP2以降低第一電晶體MP1與記憶節點SN之間的漏電流。藉由降低第一電晶體MP1與記憶節點SN之間的漏電流，可有效防止記憶節點SN所儲存的資料發生錯誤。另外，關於圖2的記憶胞200的其他實施細節及運作，可參考上述圖1的相關說明，在此不再贅述。
圖3是依照本發明又一實施例所繪示的記憶胞的電路架構示意圖。請參照圖3，記憶胞300包括第一電晶體MN1、第二電晶體MN2以及反相器120。第一電晶體MN1的第一端用以做為記憶胞300的資料輸入端E_IN，第一電晶體MN1的控制端接收寫入控制信號CS，且第一電晶體MN1的第二端耦接記憶節點SN。其中可透過寫入控制信號CS導通第一電晶體MN1，以將資料輸入端E_IN的資料寫入記憶節點SN，並在資料輸入端E_IN的資料寫入記憶節點SN之後，關斷第一電晶體MN1，以將資料儲存在記憶節點SN。
反相器120的輸入端耦接記憶節點SN。反相器120的輸出端用以做為記憶胞300的資料輸出端E_OUT。第二電晶體MN2的第一端耦接第一電壓VG。第二電晶體MN2的控制端耦接反相器120的輸出端。第二電晶體MN2的第二端耦接記憶節點SN。第二電晶體MN2的基體耦接第二電壓VN2。特別是，為了降低第二電晶體MN2的漏電流，第二電壓VN2的電壓值不等於第一電壓VG的電壓值。
詳細來說，在圖3所示的實施例中，第二電晶體MN2為N型金氧半場效電晶體，第一電壓VG為接地電壓，且第二電壓VN2為負電壓。亦即第二電壓VN2的電壓值低於第一電壓VG的電壓值。如此一來，可增加第二電晶體MN2的基體效應，以降低自記憶節點SN流入第二電晶體MN2的漏電流，從而防止記憶節點SN所儲存的資料發生錯誤。
舉例來說，當記憶節點SN所儲存的資料為邏輯高位準的資料時，反相器120的輸出端為邏輯低位準，因此第二電晶體MN2為截止狀態，故而記憶節點SN所儲存的資料可保持在邏輯高位準。然而，若第二電晶體MN2於截止狀態下的漏電流過大，將會導致記憶節點SN的電壓逐漸降低，並最終透過反相器120而導通第二電晶體MN2，致使記憶節點SN所儲存的資料成為邏輯低位準資料。因此，藉由增加第二電晶體MN2的基體效應，以降低記憶節點SN流至第二電晶體MN2的漏電流，可有效防止記憶節點SN所儲存的資料發生錯誤。
另外，在圖3所示的實施例中，第一電晶體MN1為N型金氧半場效電晶體，且第一電晶體MN1的基體耦接第二電壓VN2(為負電壓)以增加第一電晶體MN1的基體效應，但本發明不限於此。可以理解的是，藉由增加第一電晶體MN1的基體效應，以降低第一電晶體MN1與記憶節點SN之間的漏電流，也可有效防止記憶節點SN所儲存的資料發生錯誤。
圖4是依照本發明又一實施例所繪示的記憶胞的電路架構示意圖。請參照圖4，記憶胞400包括第一電晶體MP1、第二電晶體MN2以及反相器120。圖4的記憶胞400類似於圖3的記憶胞300，兩者的差異僅在於：圖3的第一電晶體MN1為N型金氧半場效電晶體，且第一電晶體MN1的基體耦接第二電壓VN2(為負電壓)以增加第一電晶體MN1的基體效應；而圖4的第一電晶體MP1為P型金氧半場效電晶體，且第一電晶體MP1的基體耦接第三電壓VP3(為正電壓)。特別是，第三電壓VP3的電壓值高於記憶胞400的資料輸入端E_IN的電壓值，如此可增加第一電晶體MP1的基體效應，以降低第一電晶體MP1與記憶節點SN之間的漏電流，故可有效防止記憶節點SN所儲存的資料發生錯誤。至於圖4的記憶胞400的其他實施細節及運作，可參考上述圖3的相關說明，在此不再贅述。
綜上所述，在本發明實施例所提出的記憶胞中，藉由增加記憶胞的電晶體的基體效應，以降低電晶體與記憶節點之間的漏電流，可有效防止記憶節點所儲存的資料發生錯誤。除此之外，本發明實施例所提出的記憶胞實質上可視為一種四電晶體式記憶胞。由於四電晶體式記憶胞的電路架構簡單且電路面積小，故可有效降低生產製造的風險及硬體成本。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、200、300、400‧‧‧記憶胞
120‧‧‧反相器
CS‧‧‧寫入控制信號
E_IN‧‧‧資料輸入端
E_OUT‧‧‧資料輸出端
MN1、MP1‧‧‧第一電晶體
MP2、MN2‧‧‧第二電晶體
SN‧‧‧記憶節點
VN‧‧‧負電壓
VG、VP1‧‧‧第一電壓
VN2、VP2‧‧‧第二電壓
VP3‧‧‧第三電壓
下面的所附圖式是本發明的說明書的一部分，繪示了本發明的示例實施例，所附圖式與說明書的描述一起說明本發明的原理。 圖1是依照本發明一實施例所繪示的記憶胞的電路架構示意圖。 圖2是依照本發明另一實施例所繪示的記憶胞的電路架構示意圖。 圖3是依照本發明又一實施例所繪示的記憶胞的電路架構示意圖。 圖4是依照本發明又一實施例所繪示的記憶胞的電路架構示意圖。

Claims (8)

  1. 一種記憶胞，包括： 一第一電晶體，該第一電晶體的第一端用以做為該記憶胞的資料輸入端，該第一電晶體的控制端接收一寫入控制信號，且該第一電晶體的第二端耦接一記憶節點； 一反相器，該反相器的輸入端耦接該記憶節點，且該反相器的輸出端用以做為該記憶胞的資料輸出端；以及 一第二電晶體，該第二電晶體的第一端耦接一第一電壓，該第二電晶體的控制端耦接該反相器的該輸出端，該第二電晶體的第二端耦接該記憶節點，且該第二電晶體的基體耦接一第二電壓， 其中該第二電壓的電壓值不等於該第一電壓的電壓值，以降低該第二電晶體的漏電流。
  2. 如申請專利範圍第1項所述的記憶胞，其中該第二電晶體為P型金氧半場效電晶體，該第一電壓與該第二電壓為正電壓，且該第二電壓的電壓值高於該第一電壓的電壓值。
  3. 如申請專利範圍第2項所述的記憶胞，其中該第一電晶體為N型金氧半場效電晶體，且該第一電晶體的基體耦接負電壓。
  4. 如申請專利範圍第2項所述的記憶胞，其中該第一電晶體為P型金氧半場效電晶體，且該第一電晶體的基體耦接該第二電壓。
  5. 如申請專利範圍第1項所述的記憶胞，其中該第二電晶體為N型金氧半場效電晶體，該第一電壓為接地電壓，且該第二電壓為負電壓。
  6. 如申請專利範圍第5項所述的記憶胞，其中該第一電晶體為N型金氧半場效電晶體，且該第一電晶體的基體耦接該第二電壓。
  7. 如申請專利範圍第5項所述的記憶胞，其中該第一電晶體為P型金氧半場效電晶體，且該第一電晶體的基體耦接一第三電壓，其中該第三電壓為正電壓，且該第三電壓的電壓值高於該記憶胞的該資料輸入端的電壓值。
  8. 如申請專利範圍第1項所述的記憶胞，其中該反相器為一互補式金屬氧化物半導體反相器。
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