TWI662660B - 發光二極體封裝結構及其製造方法 - Google Patents
發光二極體封裝結構及其製造方法 Download PDFInfo
- Publication number
- TWI662660B TWI662660B TW107130865A TW107130865A TWI662660B TW I662660 B TWI662660 B TW I662660B TW 107130865 A TW107130865 A TW 107130865A TW 107130865 A TW107130865 A TW 107130865A TW I662660 B TWI662660 B TW I662660B
- Authority
- TW
- Taiwan
- Prior art keywords
- emitting diode
- circuit
- self
- build
- layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 229910000679 solder Inorganic materials 0.000 claims abstract description 86
- 239000000463 material Substances 0.000 claims abstract description 67
- 238000001338 self-assembly Methods 0.000 claims abstract description 52
- 238000004806 packaging method and process Methods 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims description 182
- 239000002335 surface treatment layer Substances 0.000 claims description 50
- 239000000758 substrate Substances 0.000 claims description 49
- 239000012790 adhesive layer Substances 0.000 claims description 24
- 239000008393 encapsulating agent Substances 0.000 claims description 13
- 239000000696 magnetic material Substances 0.000 claims description 10
- 210000004508 polar body Anatomy 0.000 claims 1
- 238000004381 surface treatment Methods 0.000 claims 1
- 239000000956 alloy Substances 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 229910006913 SnSb Inorganic materials 0.000 description 3
- 239000003086 colorant Substances 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000001179 sorption measurement Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16141—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged on opposite sides of a substrate, e.g. mirror arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
- H01L2224/24011—Deposited, e.g. MCM-D type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
- H01L2224/2402—Laminated, e.g. MCM-L type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/24146—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/24147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/245—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/32237—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/81411—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/839—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector with the layer connector not providing any mechanical bonding
- H01L2224/83901—Pressing the layer connector against the bonding areas by means of another connector
- H01L2224/83902—Pressing the layer connector against the bonding areas by means of another connector by means of another layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01026—Iron [Fe]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/099—Coating over pads, e.g. solder resist partly over pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10106—Light emitting diode [LED]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0186—Mask formed or laid on PCB, the mask having recesses or openings specially designed for mounting components or body parts thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/104—Using magnetic force, e.g. to align particles or for a temporary connection during processing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/168—Wrong mounting prevention
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Metallurgy (AREA)
- Led Device Packages (AREA)
Abstract
一種發光二極體封裝結構,包括載板、至少一自組裝材料層、第一防焊層以及至少一發光二極體。載板包括第一增層線路。自組裝材料層配置於第一增層線路上。第一防焊層配置於第一增層線路上。第一防焊層具有至少一開口,以暴露出部份自組裝材料層。發光二極體配置於第一增層線路上。發光二極體具有自組裝圖案。發光二極體透過自組裝圖案與自組裝材料層之間的作用力而自組裝於第一防焊層的開口內。另提供一種上述發光二極體封裝結構的製造方法。
Description
本發明是有關於一種封裝結構及其製造方法,且特別是有關於一種可自組裝的發光二極體封裝結構及其製造方法。
目前,次毫米發光二極體(mini LED)或微型發光二極體(Micro LED,μLED)之背板結構多使用非防銲層定義(Non-Solder Mask Define, NSMD)結構。而為了提升畫面的精細度及解析能力,需要以高密度之矩陣排列來進行組裝,且需進行巨量轉移之作業。雖然組裝的過程可利用機台之對準系統進行對位、取件置件、熱壓接合等製程來進行LED晶粒與背板的結合,但由於晶粒尺寸微小且轉移量非常大,因此,若互相結合的過程僅仰賴機台對準系統的精準度,則易產生對位不佳,進而導致良率的損失。
本發明提供一種發光二極體封裝結構,可改善發光二極體於轉移時對位不佳的問題,並提升轉移的良率。
本發明提供一種發光二極體封裝結構的製造方法,可製造上述的發光二極體封裝結構。
本發明的發光二極體封裝結構包括載板、至少一自組裝材料層、第一防焊層以及至少一發光二極體。載板包括第一增層線路。自組裝材料層配置於第一增層線路上。第一防焊層配置於第一增層線路上。第一防焊層具有至少一開口,以暴露出部份自組裝材料層。發光二極體配置於第一增層線路上。發光二極體具有自組裝圖案。發光二極體透過自組裝圖案與自組裝材料層之間的作用力而自組裝於第一防焊層的開口內。
在本發明的一實施例中,上述的至少一開口包括至少一第一開口、至少一第二開口以及至少一第三開口。其中,第一開口的尺寸大於第二開口的尺寸,且第二開口的尺寸大於第三開口的尺寸。
在本發明的一實施例中,上述的至少一發光二極體包括至少一第一發光二極體、至少一第二發光二極體以及至少一第三發光二極體。第一發光二極體具有第一自組裝圖案、第二發光二極體具有第二自組裝圖案以及第三發光二極體具有第三自組裝圖案。其中,第一開口、第二開口以及第三開口的尺寸分別對應於第一自組裝圖案、第二自組裝圖案以及第三自組裝圖案的尺寸設置。
在本發明的一實施例中,上述的第一開口、第二開口以及第三開口的形狀分別對應於第一自組裝圖案、第二自組裝圖案以及第三自組裝圖案的形狀設置。
在本發明的一實施例中,上述的自組裝圖案包括磁性材料,且自組裝材料層包括磁性材料。
在本發明的一實施例中,上述的發光二極體封裝結構更包括至少一第一表面處理層、黏著層以及透光層。第一表面處理層配置於第一防焊層的開口內。黏著層配置於第一防焊層上,且包覆發光二極體。透光層配置於黏著層上。透光層與第一防焊層分別位於黏著層的相對兩側。其中,上述的載板更包括至少一晶片以及封裝膠體。晶片具有主動表面。封裝膠體包覆晶片。發光二極體與晶片分別位於第一增層線路的相對兩側。
在本發明的一實施例中,上述的載板更包括第二增層線路、至少一第二表面處理層以及至少一導電通孔。第二增層線路配置於晶片上。第二表面處理層配置於第二增層線路與晶片的主動表面之間。導電通孔電性連接第一增層線路與第二增層線路。
在本發明的一實施例中,上述的載板更包括基板、多個凸塊以及第二防焊層。基板配置於第一增層線路與第二增層線路之間。凸塊配置於晶片的主動表面上,以電性連接第二增層線路與晶片。第二防焊層配置於第二增層線路與封裝膠體之間,並暴露出部份第二增層線路。第二表面處理層配置於第二防焊層暴露出的部份第二增層線路與凸塊之間。導電通孔貫穿基板。主動表面朝向發光二極體。
在本發明的一實施例中,上述的導電通孔貫穿封裝膠體,且主動表面背向發光二極體。上述的載板更包括基板。基板配置於第二增層線路上。發光二極體與基板分別位於晶片的相對兩側。
在本發明的一實施例中,上述的載板更包括至少一第二表面處理層。第二表面處理層配置於第一增層線路與晶片的主動表面之間。主動表面朝向發光二極體。
本發明的發光二極體封裝結構的製造方法包括以下步驟。形成載板,且載板包括第一增層線路。形成至少一自組裝材料層於第一增層線路上。形成第一防焊層於第一增層線路上。其中,第一防焊層具有至少一開口,以暴露出部份自組裝材料層。配置至少一發光二極體於第一增層線路上。其中,發光二極體具有自組裝圖案。發光二極體透過自組裝圖案與自組裝材料層之間的作用力而自組裝於第一防焊層的開口內。
在本發明的一實施例中,上述的發光二極體封裝結構的製造方法更包括以下步驟。在形成第一防焊層於第一增層線路上之後,形成至少一第一表面處理層於第一防焊層的開口內。在配置發光二極體於第一增層線路上之後,形成黏著層於第一防焊層上,以包覆發光二極體。配置透光層於黏著層上。透光層與第一防焊層分別位於黏著層的相對兩側。上述形成載板的步驟包括以下步驟。提供一基板。形成一第一增層線路於基板上。
在本發明的一實施例中,上述形成載板的步驟更包括以下步驟。形成第二增層線路於基板上。形成至少一導電通孔,以電性連接第一增層線路與第二增層線路。形成至少一第二表面處理層於第二增層線路上。配置至少一晶片於第二增層線路上,以使第二表面處理層位於第二增層線路與晶片之間。形成封裝膠體以包覆晶片。其中,發光二極體與晶片分別位於第一增層線路的相對兩側。
在本發明的一實施例中,上述的晶片具有多個凸塊,且凸塊位於晶片的主動表面上,以電性連接第二增層線路與晶片。而形成載板的步驟更包括:形成第二防焊層於第二增層線路與封裝膠體之間,以暴露出部份第二增層線路。其中,基板位於第一增層線路與第二增層線路之間。導電通孔貫穿基板,且主動表面朝向發光二極體。
在本發明的一實施例中,上述的發光二極體與基板分別位於晶片的相對兩側。導電通孔貫穿封裝膠體。晶片的主動表面背向發光二極體。
在本發明的一實施例中,上述在形成第一防焊層於第一增層線路上之後,更包括以下步驟。分離基板。形成至少一第二表面處理層於第一增層線路上,以使第二表面處理層與第一表面處理層分別位於第一增層線路的相對兩側。配置至少一晶片於第二表面處理層上。形成封裝膠體,以包覆晶片。其中,發光二極體與晶片分別位於第一增層線路的相對兩側。晶片的主動表面朝向發光二極體。
基於上述,在本發明的發光二極體封裝結構中,發光二極體封裝結構包括載板、自組裝材料層、第一防焊層以及具有自組裝圖案的發光二極體。其中,發光二極體透過自組裝圖案與自組裝材料層之間的作用力而自組裝於第一防焊層的開口內,進而將發光二極體配置於載板上。藉此設計,使得本發明的發光二極體封裝結構,具有可改善發光二極體於轉移時對位不佳的問題,並提升轉移的良率的效果。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1A至圖1E繪示為本發明一實施例的一種發光二極體封裝結構的製造方法的剖面示意圖。
請參照圖1A,形成載板100,且載板100至少包括第一增層線路110。詳細來說,在本實施例中,先提供基板120,並例如是以雷射方式,對基板120進行鑽孔,以形成貫穿基板120的開孔。接著,在開孔內填入導電材料以形成導電通孔140,在基板120的上表面121形成第一增層線路110,並在基板120的下表面122形成第二增層線路130。其中,第一增層線路110包括第一導電層111、第一介電層112、第二導電層113以及貫穿第一介電層112的第一導電孔114。第二增層線路130包括第三導電層131、第二介電層132、第四導電層133以及貫穿第二介電層132的第二導電孔134。其中,第一導電孔114電性連接第一導電層111與第二導電層113,且第二導電孔134電性連接第三導電層131與第四導電層133。於是,基板120位於第一增層線路110與第二增層線路130之間。導電通孔140貫穿基板120,且電性連接第一增層線路110與第二增層線路130。此處,基板120可例如是玻璃基板、陶瓷基板、矽基板或高分子玻璃纖維複合基板。第一導電層111、第二導電層113、第一導電孔114、第三導電層131、第四導電層133以及第二導電孔134的材料可例如是銅、銀、金或其他高導電度材料。第一介電層112以及第二介電層132的材料可例如是感光型介電材料、聚醯亞胺、ABF(Ajinomoto Build-up Film)或樹脂或高分子玻纖複合材料。
此外,在一些實施例中,第一增層線路110的第二導電層113還包括第一接墊1131、第二接墊1132以及第三接墊1133。其中,第一接墊1131的尺寸大於第二接墊1132的尺寸,且第二接墊1132的尺寸大於第三接墊1133的尺寸。
接著,請參照圖1B,形成至少一自組裝材料層200(圖1B示意地繪示為6個)於第一增層線路110上。詳細來說,在本實施例中,例如是以濺鍍(sputter)、電漿輔助化學氣相沉積(PECVD)或壓貼合等方式搭配微影、蝕刻等製程,形成對應於第一接墊1131的尺寸大小的第一自組裝材料層210、形成對應於第二接墊1132的尺寸大小的第二自組裝材料層220、形成對應於第三接墊1133的尺寸大小的第三自組裝材料層230。因此,第一自組裝材料層210的尺寸大於第二自組裝材料層220的尺寸,且第二自組裝材料層220的尺寸大於第三自組裝材料層230的尺寸。
然後,請參照圖1C與圖2A,先形成第一防焊層300於第一增層線路110上,並形成第二防焊層300a於第二增層線路130上。接著,形成至少一第一表面處理層320(圖1C示意地繪示為6個)於第一防焊層300的開口310內,並形成至少一第二表面處理層320a(圖1C示意地繪示為6個)於第二防焊層300a的開口310a內。其中,圖2A與圖2B繪示為圖1C中區域A的俯視圖,並省略繪示第一防焊層300以及第一增層線路110。
詳細來說,在本實施例中,先形成第一防焊層300以覆蓋第一增層線路110的第一介電層112以及第二導電層113,並形成第二防焊層300a以覆蓋第二增層線路130的第二介電層132以及第四導電層133。其中,第一防焊層300具有至少一開口310(圖1C示意地繪示為6個),以暴露出部份自組裝材料層220以及第二導電層113。第二防焊層300a具有至少一開口310a(圖1C示意地繪示為6個),以暴露出部份第四導電層133。此處,第一防焊層300與第二防焊層300a的材料可例如是感光高分子材料,但不以此為限。
接著,在形成第一防焊層300於第一增層線路110上之後,形成第一表面處理層320於第一防焊層300的開口310內,以覆蓋由第一防焊層300暴露出的第二導電層113。在形成第二防焊層300a於第二增層線路130上之後,形成第二表面處理層320a於第二防焊層300a的開口310a內,以覆蓋由第二防焊層300a暴露出的第四導電層133。此處,第一表面處理層320與第二表面處理層320a的材質可例如是SAC、SnBe、SnSb或其他適合的合金材質。
需要說明的是,請再同時參照圖1C與圖2A,在一些實施例中,第一防焊層300的開口310還包括第一開口311、第二開口312以及第三開口313。其中,第一開口311的尺寸大於第二開口312的尺寸,且第二開口312的尺寸大於第三開口313的尺寸,但不以此為限。也就是說,在其他實施例中,第一開口、第二開口以及第三開口的尺寸也可以相同。因此,在一些實施例中,可利用第一防焊層300的製程來定義出尺寸大小不同或相同的第一開口311、第二開口312以及第三開口313。
此外,在本實施例中,第一開口311、第二開口312以及第三開口313的形狀可例如是矩形,但不以此為限。在其他實施例中,第一開口311a、第二開口312a以及第三開口313a的形狀也可以是橢圓形(如圖2B所示)或其他適合封裝連接之形狀。另外,雖然本實施例的第一開口311、第二開口312以及第三開口313的形狀皆為相似的矩形,但其他實施例中,第一開口、第二開口以及第三開口的形狀也可以彼此不同(未繪示)。
然後,請參照圖1D,配置至少一發光二極體400(圖1C示意地繪示為6個)於第一增層線路110上。其中,發光二極體400具有自組裝圖案400a。詳細來說,在本實施例中,發光二極體400可為mini LED或μLED。其中,mini LED的尺寸大於125μm,μLED的尺寸小於125μm。在本實施例中,發光二極體400可包括第一發光二極體410、第二發光二極體420以及第三發光二極體430。其中,第一發光二極體410、第二發光二極體420以及第三發光二極體430的顏色可分別對應於三原色。因此,第一發光二極體410可為紅色、第二發光二極體420可為綠色且第三發光二極體430可為藍色,但不以此為限。也就是說,在其他實施例中,第一發光二極體410可為紅色以外的其他三原色、第二發光二極體420可為綠色以外的其他三原色且第三發光二極體430可為藍色以外的其他三原色。
在本實施例中,自組裝圖案400a可包括第一自組裝圖案410a、第二自組裝圖案420a以及第三自組裝圖案430a。也就是說,第一發光二極體410具有第一自組裝圖案410a、第二發光二極體420具有第二自組裝圖案420a、第三發光二極體430具有第三自組裝圖案430a。在本實施例中,例如是利用濺鍍、微影、蝕刻等製程形成第一自組裝圖案410a、第二自組裝圖案420a以及第三自組裝圖案430a。其中,第一開口311的尺寸與形狀對應於第一自組裝圖案410a的尺寸與形狀設置,第二開口312的尺寸與形狀對應於第二自組裝圖案420a的尺寸與形狀設置,且第三開口313的尺寸與形狀對應於第三自組裝圖案430a的尺寸與形狀設置。
值得說明的是,由於自組裝圖案410與自組裝材料層200之間具有互相吸引的作用力,可使自組裝圖案410與自組裝材料層200進行較精準的對位並自組裝。因此,在本實施例中,第一發光二極體410可透過第一自組裝圖案410a與第一自組裝材料層210之間的作用力而自組裝於第一防焊層300的第一開口311內,其中第一自組裝圖案410a的尺寸與形狀可對應於第一開口311的尺寸與形狀。第二發光二極體420可透過第二自組裝圖案420a與第二自組裝材料層220之間的作用力而自組裝於第一防焊層300的第二開口312內,其中第二自組裝圖案420a的尺寸與形狀可對應於第二開口312的尺寸與形狀。第三發光二極體430可透過第三自組裝圖案430a與第三自組裝材料層230之間的作用力而自組裝於第一防焊層300的第三開口313內,其中第三自組裝圖案430a的尺寸與形狀可對應於第三開口313的尺寸與形狀。藉此設計,使得本實施例的發光二極體封裝結構10,可利用自組裝的方式改善發光二極體於轉移時對位不佳的問題,並可提升轉移的良率。此處,自組裝圖案400a包括磁性材料,自組裝材料層200包括磁性材料,且自組裝圖案400a與自組裝材料層200之間具有磁性吸引力,但不以此為限。其中,磁性材料可例如是鐵、鈷、鎳等雙元或多元合金之可產生磁性之材料。
此外,請參照圖2C,圖2C繪示為圖1D的發光二極體的另一剖面圖。其中,發光二極體400具有發光二極體晶粒401以及自組裝圖案400a。自組裝圖案400a包括封裝基座400a1、吸附層400a2、導電接點層400a3以及第三表面處理層400a4。其中,發光二極體晶粒401固定在封裝基座400a1上,吸附層400a2內埋於封裝基座400a1內或於封裝基座400a1上,但不以此為限,導電接點層400a3設置於封裝基座400a1遠離發光二極體晶粒401的一側,第三表面處理層400a4設置於導電接點層400a3的表面。此處,第三表面處理層400a4的材質可例如是SAC、SnBe、SnSb或其他適合的合金材質。
而後,請參照圖1E,在配置發光二極體400於第一增層線路110上之後,形成黏著層500於第一防焊層300上,以包覆發光二極體400。接著,配置透光層510於黏著層500上,使透光層510與第一防焊層300分別位於黏著層500的相對兩側。此處,黏著層500的材料可例如是透明高分子材料、聚醯亞胺、苯並環丁烯(Benzocyclobutene,BCB)、感光型介電材料(Photoimageable Dielectric,PID)或其他可供光線穿過且具有黏著力之材料。透光層510的材質可例如是玻璃、石英或透明PET或可供光線穿過並達到保護封裝發光二極體晶粒的硬質材料或者如高透光度之樹脂材料、聚醯亞胺(PI)等軟性的材料,但不以此為限。
然後,配置至少一晶片150(圖1E示意地繪示為2個)於第二增層線路130上,以使第二表面處理層320a位於第二增層線路130與晶片150之間,並使晶片150的主動表面151朝向發光二極體400。其中,晶片150具有多個凸塊152,且凸塊152位於晶片150的主動表面151上,以電性連接第二增層線路130與晶片150。接著,形成封裝膠體160以包覆晶片150以及凸塊152。其中,第二表面處理層320a配置於第二防焊層300a暴露出的部份第二增層線路130與凸塊152之間,第二防焊層300a位於第二增層線路130與封裝膠體160之間,且發光二極體400與晶片150分別位於第一增層線路110的相對兩側。此處,凸塊152的材質可例如是SAC、SnBe、SnSb或其他適合的合金材質。封裝膠體160的材料可例如是樹脂或高分子玻璃填充物複合材料。至此,已製造完成發光二極體封裝結構10。
需要說明的是,雖然在本實施例的發光二極體封裝結構的製造方法中,是先配置發光二極體400於第一增層線路110上,再配置晶片150於第二增層線路130上,但本發明並不對此順序加以限制。也就是說,在其他實施例中,也可以是先配置晶片150於第二增層線路130上,再配置發光二極體400於第一增層線路110上。
需要說明的是,雖然本實施例的發光二極體封裝結構10的載板100包括第一增層線路110、基板120、導電通孔140、第二增層線路130、第二防焊層300a、第二表面處理層320a、凸塊152、晶片150以及封裝膠體160,但本發明並不對載板的構件及其配置方式加以限制。也就是說,在其他實施例中,載板也可以不包括導電通孔或基板,或其構件以不同的配置方式呈現。
基於上述,本實施例的發光二極體封裝結構10包括載板100、至少一自組裝材料層200、第一防焊層300以及至少一發光二極體400。載板100包括第一增層線路110。自組裝材料層200配置於第一增層線路110上。第一防焊層300配置於第一增層線路110上。第一防焊層300具有至少一開口310,以暴露出部份自組裝材料層200。發光二極體400配置於第一增層線路110上。發光二極體400具有自組裝圖案400a。發光二極體400透過自組裝圖案400a與自組裝材料層200之間的作用力而自組裝於第一防焊層300的開口310內。
在此必須說明的是,下述實施例沿用前述實施例的元件標號與部份內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部份的說明可參考前述實施例,下述實施例不再重複贅述。
圖3A至圖3E繪示為本發明另一實施例的一種發光二極體封裝結構的製造方法的剖面示意圖。請同時參考圖1A至圖1E與圖3A至圖3E,本實施例的發光二極體封裝結構的製造方法與圖1A至圖1E的發光二極體封裝結構的製造方法相似,惟二者主要差異之處在於:在本實施例的發光二極體封裝結構10a的製造方法中,不需要對基板120進行鑽孔。此外,本實施例的發光二極體封裝結構10a的載板100a的結構與發光二極體封裝結構10的載板100的結構不同。
詳細來說,請參照圖3A,在本實施例的發光二極體封裝結構的製造方法中,先在基板120的上表面121形成第二增層線路130,並在第二增層線路130上形成第二表面處理層320a。接著,請參照圖3B,配置晶片150於第二增層線路130上,以使第二表面處理層320a位於第二增層線路130與晶片150之間。接著,形成封裝膠體160以包覆晶片150、第二表面處理層320a以及第二增層線路130。接著,請參照圖3C,對封裝膠體160進行鑽孔,並填入導電材料後形成貫穿封裝膠體160的導電通孔140a。在封裝膠體160上形成第一增層線路110,以使晶片150位於第一增層線路110與第二增層線路130之間。至此,已製造完成發光二極體封裝結構10a的載板100a。其中,本實施例的發光二極體封裝結構10a的載板100a包括第一增層線路110、導電通孔140a、第二增層線路130、封裝膠體160、晶片150、第二表面處理層320a以及基板120。
然後,請參照圖3D,形成自組裝材料層200於第一增層線路110上,形成第一防焊層300於第一增層線路110上,並形成第一表面處理層320於第一防焊層300的開口310內。
而後,請參照圖3E,配置發光二極體400於第一增層線路110上。發光二極體400可透過自組裝圖案400a與自組裝材料層200之間的作用力而自組裝於第一防焊層300的開口310內,其中自組裝圖案400a的尺寸與形狀可對應於開口310的尺寸與形狀。其中,晶片150的主動表面151背向發光二極體400,且發光二極體400與基板120分別位於晶片150的相對兩側。接著,形成黏著層500於第一防焊層300上,以包覆發光二極體400。接著,配置透光層510於黏著層500上,使透光層510與第一防焊層300分別位於黏著層500的相對兩側。至此,已製造完成發光二極體封裝結構10a。
需要說明的是,在其他實施例中,也可再對上述的發光二極體封裝結構10a進行一拆板程序,以分離基板120,並得到無基板的發光二極體封裝結構10b,如圖3F所示。
圖4A至圖4D繪示為本發明另一實施例的一種發光二極體封裝結構的製造方法的剖面示意圖。請同時參考圖1A至圖1E與圖3A至圖3E,本實施例的發光二極體封裝結構的製造方法與圖1A至圖1E的發光二極體封裝結構的製造方法相似,惟二者主要差異之處在於:在本實施例的發光二極體封裝結構的製造方法中,不需要對基板120進行鑽孔。此外,本實施例的發光二極體封裝結構10c的載板100b的結構與發光二極體封裝結構10的載板100的結構不同。
詳細來說,請參照圖4A,在本實施例的發光二極體封裝結構的製造方法中,先在基板120的上表面121形成第一增層線路110a。其中,第一增層線路110a包括第一導電層111a、第一介電層112a、第二導電層113a、貫穿第一介電層112a的第一導電孔114a、第五導電層115、第三介電層116以及貫穿第三介電層116的第三導電孔117。
接著,請參照圖4B,形成自組裝材料層200於第一增層線路110a上,形成第一防焊層300於第一增層線路110a上,並形成第一表面處理層320於第一防焊層300的開口310內。
接著,請參照圖4C,進行一拆板程序,以分離基板120。然後,形成第二表面處理層320a於第一增層線路110a上,以使第二表面處理層320a與第一表面處理層320分別位於第一增層線路110a的相對兩側。
而後,請參照圖4D,配置發光二極體400於第一增層線路110a上。發光二極體400可透過自組裝圖案400a與自組裝材料層200之間的作用力而自組裝於第一防焊層300的開口310內,其中自組裝圖案400a的尺寸與形狀可對應於開口310的尺寸與形狀。接著,形成黏著層500於第一防焊層300上,以包覆發光二極體400。配置透光層510於黏著層500上,使透光層510與第一防焊層300分別位於黏著層500的相對兩側。配置晶片150於第一增層線路110a上,以使發光二極體400與晶片150分別位於第一增層線路110a的相對兩側。接著,形成封裝膠體160以包覆晶片150、第二表面處理層320a以及第一增層線路110a。至此,已製造完成發光二極體封裝結構10c。其中,本實施例的發光二極體封裝結構10c的載板100b包括第一增層線路110a、第二表面處理層320a、晶片150以及封裝膠體160。
綜上所述,在本發明的發光二極體封裝結構中,發光二極體封裝結構包括載板、自組裝材料層、第一防焊層以及具有自組裝圖案的發光二極體。其中,發光二極體透過自組裝圖案與自組裝材料層之間的作用力而自組裝於第一防焊層的開口內,進而將發光二極體配置於載板上。藉此設計,使得本發明的發光二極體封裝結構,具有可改善發光二極體於轉移時對位不佳的問題,並提升轉移的良率的效果。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、10a、10b、10c‧‧‧發光二極體封裝結構
100、100a、100b‧‧‧載板
110、110a‧‧‧第一增層線路
111、111a‧‧‧第一導電層
112、112a‧‧‧第一介電層
113、113a‧‧‧第二導電層
1131‧‧‧第一接墊
1132‧‧‧第二接墊
1133‧‧‧第三接墊
114、114a‧‧‧第一導電孔
115‧‧‧第五導電層
116‧‧‧第三介電層
117‧‧‧第三導電孔
120‧‧‧基板
121‧‧‧上表面
122‧‧‧下表面
130‧‧‧第二增層線路
131‧‧‧第三導電層
132‧‧‧第二介電層
133‧‧‧第四導電層
134‧‧‧第二導電孔
140、140a‧‧‧導電通孔
150‧‧‧晶片
151‧‧‧主動表面
152‧‧‧凸塊
160‧‧‧封裝膠體
200、200a、200b‧‧‧自組裝材料層
210‧‧‧第一自組裝材料層
220‧‧‧第二自組裝材料層
230‧‧‧第三自組裝材料層
300‧‧‧第一防焊層
300a‧‧‧第二防焊層
310、310a‧‧‧開口
311、311a‧‧‧第一開口
312、312a‧‧‧第二開口
313、313a‧‧‧第三開口
320‧‧‧第一表面處理層
320a‧‧‧第二表面處理層
400‧‧‧發光二極體
401‧‧‧發光二極體晶粒
400a‧‧‧自組裝圖案
400a1‧‧‧封裝基座
400a2‧‧‧吸附層
400a3‧‧‧導電接點層
400a4‧‧‧第三表面處理層
410‧‧‧第一發光二極體
410a‧‧‧第一自組裝圖案
420‧‧‧第二發光二極體
420a‧‧‧第二自組裝圖案
430‧‧‧第三發光二極體
430a‧‧‧第三自組裝圖案
500‧‧‧黏著層
510‧‧‧透光層
A‧‧‧區域
圖1A至圖1E繪示為本發明一實施例的一種發光二極體封裝結構的製造方法的剖面示意圖。 圖2A與圖2B繪示為圖1C中區域A的俯視圖。 圖2C繪示為圖1D的發光二極體的另一剖面圖。 圖3A至圖3E繪示為本發明另一實施例的一種發光二極體封裝結構的製造方法的剖面示意圖。 圖3F繪示為圖3E的發光二極體封裝結構於基板分離後的剖面示意圖。 圖4A至圖4D繪示為本發明另一實施例的一種發光二極體封裝結構的製造方法的剖面示意圖。
Claims (18)
- 一種發光二極體封裝結構,包括:一載板,包括一第一增層線路;至少一自組裝材料層,配置於該第一增層線路上;一第一防焊層,配置於該第一增層線路上,具有至少一開口,以暴露出部份該自組裝材料層;以及至少一發光二極體,配置於該第一增層線路上,具有一自組裝圖案,其中該發光二極體透過該自組裝圖案與該自組裝材料層之間的作用力而自組裝於該第一防焊層的該開口內,該自組裝圖案包括磁性材料,且該自組裝材料層包括磁性材料。
- 如申請專利範圍第1項所述的發光二極體封裝結構,其中該至少一開口包括至少一第一開口、至少一第二開口以及至少一第三開口,其中該第一開口的尺寸大於該第二開口的尺寸,且該第二開口的尺寸大於該第三開口的尺寸。
- 如申請專利範圍第2項所述的發光二極體封裝結構,其中該至少一發光二極體包括至少一第一發光二極體、至少一第二發光二極體以及至少一第三發光二極體,該第一發光二極體具有一第一自組裝圖案、該第二發光二極體具有一第二自組裝圖案以及該第三發光二極體具有一第三自組裝圖案,其中該第一開口、該第二開口以及該第三開口的尺寸分別對應於該第一自組裝圖案、該第二自組裝圖案以及該第三自組裝圖案的尺寸設置。
- 如申請專利範圍第3項所述的發光二極體封裝結構,其中該第一開口、該第二開口以及該第三開口的形狀分別對應於該第一自組裝圖案、該第二自組裝圖案以及該第三自組裝圖案的形狀設置。
- 如申請專利範圍第1項所述的發光二極體封裝結構,更包括:至少一第一表面處理層,配置於該第一防焊層的該開口內;一黏著層,配置於該第一防焊層上,且包覆該發光二極體;以及一透光層,配置於該黏著層上,且該透光層與該第一防焊層分別位於該黏著層的相對兩側,其中該載板更包括:至少一晶片,具有一主動表面;以及一封裝膠體,包覆該晶片,其中該發光二極體與該晶片分別位於該第一增層線路的相對兩側。
- 如申請專利範圍第5項所述的發光二極體封裝結構,其中該載板更包括:一第二增層線路,配置於該晶片上;至少一第二表面處理層,配置於該第二增層線路與該晶片的該主動表面之間;以及至少一導電通孔,電性連接該第一增層線路與該第二增層線路。
- 如申請專利範圍第6項所述的發光二極體封裝結構,其中該載板更包括:一基板,配置於該第一增層線路與該第二增層線路之間;多個凸塊,配置於該晶片的該主動表面上,以電性連接該第二增層線路與該晶片;以及一第二防焊層,配置於該第二增層線路與該封裝膠體之間,並暴露出部份該第二增層線路,其中該第二表面處理層配置於該第二防焊層暴露出的部份該第二增層線路與該些凸塊之間,該導電通孔貫穿該基板,且該主動表面朝向該發光二極體。
- 如申請專利範圍第6項所述的發光二極體封裝結構,其中該導電通孔貫穿該封裝膠體,該主動表面背向該發光二極體,且該載板更包括:一基板,配置於該第二增層線路上,且該發光二極體與該基板分別位於該晶片的相對兩側。
- 如申請專利範圍第5項所述的發光二極體封裝結構,其中該載板更包括:至少一第二表面處理層,配置於該第一增層線路與該晶片的該主動表面之間,其中該主動表面朝向該發光二極體。
- 一種發光二極體封裝結構的製造方法,包括:形成一載板,且該載板包括一第一增層線路;形成至少一自組裝材料層於該第一增層線路上;形成一第一防焊層於該第一增層線路上,其中該第一防焊層具有至少一開口,以暴露出部份該自組裝材料層;以及配置至少一發光二極體於該第一增層線路上,其中該發光二極體具有一自組裝圖案,該發光二極體透過該自組裝圖案與該自組裝材料層之間的作用力而自組裝於該第一防焊層的該開口內,該自組裝圖案包括磁性材料,且該自組裝材料層包括磁性材料。
- 如申請專利範圍第10項所述的發光二極體封裝結構的製造方法,其中該至少一開口包括至少一第一開口、至少一第二開口以及至少一第三開口,該第一開口的尺寸大於該第二開口的尺寸,且該第二開口的尺寸大於該第三開口的尺寸。
- 如申請專利範圍第11項所述的發光二極體封裝結構的製造方法,其中該至少一發光二極體包括至少一第一發光二極體、至少一第二發光二極體以及至少一第三發光二極體,該第一發光二極體具有一第一自組裝圖案、該第二發光二極體具有一第二自組裝圖案以及該第三發光二極體具有一第三自組裝圖案,其中該第一開口、該第二開口以及該第三開口的尺寸分別對應於該第一自組裝圖案、該第二自組裝圖案以及該第三自組裝圖案的尺寸設置。
- 如申請專利範圍第12項所述的發光二極體封裝結構的製造方法,其中該第一開口、該第二開口以及該第三開口的形狀分別對應於該第一自組裝圖案、該第二自組裝圖案以及該第三自組裝圖案的形狀設置。
- 如申請專利範圍第10項所述的發光二極體封裝結構的製造方法,更包括:在形成該第一防焊層於該第一增層線路上之後,形成至少一第一表面處理層於該第一防焊層的該開口內;在配置該發光二極體於該第一增層線路上之後,形成一黏著層於該第一防焊層上,以包覆該發光二極體,以及配置一透光層於該黏著層上,且該透光層與該第一防焊層分別位於該黏著層的相對兩側,其中形成該載板的步驟包括:提供一基板;以及形成該第一增層線路於該基板上。
- 如申請專利範圍第14項所述的發光二極體封裝結構的製造方法,其中形成該載板的步驟更包括:形成一第二增層線路於該基板上;形成至少一導電通孔,以電性連接該第一增層線路與該第二增層線路;形成至少一第二表面處理層於該第二增層線路上;配置至少一晶片於該第二增層線路上,以使該第二表面處理層位於該第二增層線路與該晶片之間;以及形成一封裝膠體以包覆該晶片,其中該發光二極體與該晶片分別位於該第一增層線路的相對兩側。
- 如申請專利範圍第15項所述的發光二極體封裝結構的製造方法,其中該晶片具有多個凸塊,且該些凸塊位於該晶片的一主動表面上,以電性連接該第二增層線路與該晶片,而形成該載板的步驟更包括:形成一第二防焊層於該第二增層線路與該封裝膠體之間,以暴露出部份該第二增層線路,其中該基板位於該第一增層線路與該第二增層線路之間,該導電通孔貫穿該基板,且該主動表面朝向該發光二極體。
- 如申請專利範圍第15項所述的發光二極體封裝結構的製造方法,其中該發光二極體與該基板分別位於該晶片的相對兩側,該導電通孔貫穿該封裝膠體,且該晶片的一主動表面背向該發光二極體。
- 如申請專利範圍第14項所述的發光二極體封裝結構的製造方法,在形成該第一防焊層於該第一增層線路上之後,更包括:分離該基板;形成至少一第二表面處理層於該第一增層線路上,以使該第二表面處理層與該第一表面處理層分別位於該第一增層線路的相對兩側;配置至少一晶片於該第二表面處理層上;以及形成一封裝膠體,以包覆該晶片,其中該發光二極體與該晶片分別位於該第一增層線路的相對兩側,且該晶片的一主動表面朝向該發光二極體。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW107130865A TWI662660B (zh) | 2018-09-03 | 2018-09-03 | 發光二極體封裝結構及其製造方法 |
US16/161,080 US10700049B2 (en) | 2018-09-03 | 2018-10-16 | Light-emitting diode package structure and manufacturing method thereof |
US16/869,595 US10886264B2 (en) | 2018-09-03 | 2020-05-08 | Manufacturing method of light-emitting diode package structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW107130865A TWI662660B (zh) | 2018-09-03 | 2018-09-03 | 發光二極體封裝結構及其製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI662660B true TWI662660B (zh) | 2019-06-11 |
TW202011535A TW202011535A (zh) | 2020-03-16 |
Family
ID=67764543
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107130865A TWI662660B (zh) | 2018-09-03 | 2018-09-03 | 發光二極體封裝結構及其製造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US10700049B2 (zh) |
TW (1) | TWI662660B (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113281928A (zh) * | 2020-02-20 | 2021-08-20 | 上海天马微电子有限公司 | 显示面板及其制作方法、显示装置 |
US11335670B2 (en) | 2020-04-21 | 2022-05-17 | Unimicron Technology Corp. | Light emitting diode package structure and manufacturing method thereof |
US11764344B2 (en) | 2021-02-04 | 2023-09-19 | Unimicron Technology Corp. | Package structure and manufacturing method thereof |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110858584A (zh) * | 2018-08-23 | 2020-03-03 | 弘凯光电(深圳)有限公司 | 发光模块及发光串列装置 |
CN115700916A (zh) * | 2019-01-15 | 2023-02-07 | 泉州三安半导体科技有限公司 | 发光二极管封装器件及发光装置 |
US20210272945A1 (en) * | 2019-06-13 | 2021-09-02 | Lite-On Opto Technology (Changzhou) Co., Ltd. | Multiple pixel package structure with buried chip and electronic device using the same |
CN110379760B (zh) * | 2019-07-05 | 2021-04-02 | 深超光电(深圳)有限公司 | 发光元件的转移方法、显示面板及其制备方法、基板 |
CN110416122B (zh) * | 2019-07-05 | 2021-06-29 | 深超光电(深圳)有限公司 | 发光元件的转移方法、显示面板及其制备方法、基板 |
CN112736072B (zh) * | 2019-10-28 | 2024-02-09 | 光宝光电(常州)有限公司 | 发光模组及其制造方法 |
CN212648273U (zh) * | 2020-07-29 | 2021-03-02 | 隆达电子股份有限公司 | 发光二极管装置 |
TWI786546B (zh) * | 2021-02-22 | 2022-12-11 | 欣興電子股份有限公司 | 發光二極體封裝結構及其製作方法與顯示裝置的製作方法 |
TWI831116B (zh) * | 2022-01-17 | 2024-02-01 | 欣興電子股份有限公司 | 封裝結構及其製造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170194302A1 (en) * | 2015-12-30 | 2017-07-06 | Globalfoundries Singapore Pte. Ltd. | Integrated led and led driver units and methods for fabricating the same |
US20170278783A1 (en) * | 2015-11-14 | 2017-09-28 | Intel Corporation | Magnetic alignment for flip chip microelectronic devices |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005122706A2 (en) | 2004-05-31 | 2005-12-29 | Joon-Mo Kang | Method of aligning semiconductor device and semiconductor structure thereof |
US9076882B2 (en) | 2013-06-03 | 2015-07-07 | Intel Corporation | Methods for high precision microelectronic die integration |
-
2018
- 2018-09-03 TW TW107130865A patent/TWI662660B/zh active
- 2018-10-16 US US16/161,080 patent/US10700049B2/en active Active
-
2020
- 2020-05-08 US US16/869,595 patent/US10886264B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170278783A1 (en) * | 2015-11-14 | 2017-09-28 | Intel Corporation | Magnetic alignment for flip chip microelectronic devices |
US20170194302A1 (en) * | 2015-12-30 | 2017-07-06 | Globalfoundries Singapore Pte. Ltd. | Integrated led and led driver units and methods for fabricating the same |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113281928A (zh) * | 2020-02-20 | 2021-08-20 | 上海天马微电子有限公司 | 显示面板及其制作方法、显示装置 |
US11335670B2 (en) | 2020-04-21 | 2022-05-17 | Unimicron Technology Corp. | Light emitting diode package structure and manufacturing method thereof |
US11764344B2 (en) | 2021-02-04 | 2023-09-19 | Unimicron Technology Corp. | Package structure and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
TW202011535A (zh) | 2020-03-16 |
US10700049B2 (en) | 2020-06-30 |
US10886264B2 (en) | 2021-01-05 |
US20200266181A1 (en) | 2020-08-20 |
US20200075564A1 (en) | 2020-03-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI662660B (zh) | 發光二極體封裝結構及其製造方法 | |
JP4803844B2 (ja) | 半導体パッケージ | |
TWI703685B (zh) | 發光二極體封裝及其製作方法 | |
JP2007273782A (ja) | 半導体装置の製造方法 | |
TW201637102A (zh) | 半導體封裝及其製造方法 | |
TW202032679A (zh) | 封裝結構及其形成方法 | |
KR20210157787A (ko) | 반도체 패키지 및 이의 제조 방법 | |
KR20200017240A (ko) | 반도체 패키지 및 이의 제조 방법 | |
CN110911541B (zh) | 发光二极管封装结构及其制造方法 | |
TWI758167B (zh) | 封裝結構及其製作方法 | |
TW202215629A (zh) | 封裝結構及其製作方法 | |
TWI692802B (zh) | 線路載板結構及其製作方法與晶片封裝結構 | |
KR101605610B1 (ko) | 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스 | |
KR20170120752A (ko) | 반도체 소자 및 그 제조 방법 | |
TWI648830B (zh) | 封裝結構及其製作方法 | |
CN111211116B (zh) | 发光二极管封装及其制作方法 | |
TW202209938A (zh) | 電路板結構及其製作方法 | |
TWI806275B (zh) | 發光二極體封裝及其製作方法 | |
TWI835452B (zh) | 發光裝置及其製造方法 | |
TWI720847B (zh) | 晶片封裝結構及其製作方法 | |
TWI831749B (zh) | 封裝件基板及其製造方法 | |
TWI759095B (zh) | 封裝結構及其製作方法 | |
TWI807377B (zh) | 覆晶式微發光二極體晶粒的製法及其製品 | |
WO2022052072A1 (zh) | 一种扇出型封装结构及其制备方法 | |
TWI544846B (zh) | 封裝載板及其製作方法 |