TWI661671B - 動態放大器及晶片 - Google Patents
動態放大器及晶片 Download PDFInfo
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- H03F2203/45031—Indexing scheme relating to differential amplifiers the differential amplifier amplifying transistors are compositions of multiple transistors
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Abstract
本發明提供了一種動態放大器及晶片。其中該動態放大器包括:一電晶體輸入對,接收一對差分輸入Vip與Vin,並且提供第一端、第二端以及第三端。一負載電路,耦合至共模端,並且提供一對差分輸出Vop和Von。在放大階段,一用於放大的驅動器耦合至該第一端,以及該負載電路耦合至該第二端與第三端。一旁路電路在該放大階段中的旁路期間內耦合至該第二端與該第三端。
Description
本發明涉及電子器件領域,特別係涉及一種動態放大器及晶片。
在類比電子產品中,放大器一般用來增加信號功率。為了最小化功率消耗,引入了可動態地操作的動態放大器。在不需要放大時,動態放大器不會消耗靜態功率。但是,動態放大器的關鍵限制包括:當低電壓操作時窄的信號擺幅。因此,需要一種具有寬的信號擺幅的動態放大器。
因此,本發明之主要目的即在於提供一種動態放大器及晶片。
根據本發明至少一個實施例的一種動態放大器,包括:一電晶體輸入對,接收一對差分輸入Vip與Vin,並且提供第一端、第二端以及第三端;一負載電路,耦合至共模端,並且提供一對差分輸出Vop和Von;一用於放大的驅動器;以及一旁路電路,可***作以降低該負載電路的電流;其中:該驅動器在放大階段耦合至該第一端;該負載電路在放大階段耦合至該第二端及該第三端;以及該旁路電路在該放大階段中的旁 路期間內耦合至該第二端與該第三端。
根據本發明至少一個實施例一種晶片,包括:一前級電路,一後級電路;以及一動態放大器,其中該動態放大器為上述的動態放大器;其中,該前級電路用於將該差分輸入Vip與Vin傳送至該動態放大器,該後級電路用於從該動態放大器接收該差分輸出Vop與Von。
本發明實施例的動態放大器,旁路電路在放大階段中對負載電路進行旁路處理,因此能夠提高動態放大器的增益。
100‧‧‧動態放大器
102‧‧‧電晶體輸入對
C1、C2‧‧‧負載電容
Vin、Vip‧‧‧差分輸入
GND‧‧‧地
Vop、Von‧‧‧差分輸出
104‧‧‧電流源
I1‧‧‧電流
n1、n2、n3‧‧‧(連接)端
△Vcm‧‧‧共模電壓差
106、108‧‧‧旁路電流源
I2‧‧‧旁路電流
CS_R、CS_A、CSb、CLK‧‧‧控制信號
T_R‧‧‧重置階段
T_A‧‧‧放大階段
Tb‧‧‧旁路期間
T_S‧‧‧取樣階段
T‧‧‧時間
V‧‧‧電壓
VDD‧‧‧電源
700‧‧‧晶片
704‧‧‧前級電路
706‧‧‧後級電路
R_I2、R_Tb‧‧‧寄存器
通過閱讀接下來的詳細描述以及參考所附的圖式所做的示例,可以更全面地理解本發明。其中:第1圖為根據本發明實施例的動態放大器100的結構示意圖;第2圖示出了控制信號CS_R,CS_A以及CSb的波形以及差分輸出Vop與Von的變化;第3圖為根據本發明另一實施例的動態放大器300的結構示意圖;第4圖示出了控制信號CS_R,CS_A以及CSb的波形以及關於動態放大器300的差分輸出Vop與Von的變化;第5圖為根據本發明另一實施例的動態放大器500的結構示意圖;第6圖示出了控制信號CS_R/CLK,CS_A以及CSb的波形以及關於動態放大器500的差分輸出Vop與Von的變化;以及 第7圖為根據本發明實施例的包含動態放大器72的晶片700的結構示意圖。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有習知技術者應可理解,電子裝置製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式,而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語,故應解釋成「包含但不限定於」。以外,「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此,若文中描述一第一裝置耦接到一第二裝置,則代表該第一裝置可直接電氣連接於該第二裝置,或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
以下描述顯示了執行本發明的典型實施例。該描述僅係出於說明本發明的一般原理的目的,並且不意味著限制。本發明的範圍最好通過參考所附的申請專利範圍來確定。
第1圖為根據本發明實施例的動態放大器100的結構示意圖。其中該動態放大器100包括:電晶體輸入對102(簡稱輸入對102),以及一對負載電容C1和C2。一對差分輸入Vin與Vip通過電晶體輸入對102耦合至動態放大器100。連接在共模端(此示例中的GND)處的負載電容C1和C2用來將放大的信號呈現在一對差分輸出Vop與Von上。
動態放大器100操作於三個階段中,包括:重置 階段、放大階段和取樣階段。在重置階段中,差分輸出Vop與Von均重置為預定電平(在此示例中短路至地GND)。動態放大器100使用電流源104來為放大階段提供電流2I1。電流源104經由輸入對102(該輸入對102受差分輸入Vin和Vip控制)耦合至負載電容C1和C2。輸入對102包括:三個(連接)端n1,n2和n3。如所示,形成輸入對102的兩個電晶體的源極在連接端n1處彼此連接,形成輸入對102的兩個電晶體的汲極分別被視為連接端n2和n3,形成輸入對102的兩個電晶體的閘極分別用來接收差分輸入Vin和Vip。在放大階段,連接端n1耦合至電流源104,同時連接端n2耦合至負載電容C1以及連接端n3耦合至負載電容C2。如此,差分輸出Vop和Von的電壓電平變化。當差分輸出Vop和Von的共模電壓差達到預定的共模電壓差(以下表示為△Vcm)時,放大階段結束。在放大階段之後提供取樣階段來對差分輸出Vop和Von進行取樣。
如所示,特別地提供了一對旁路電流源106和108。旁路電流源106和108可操作地提供旁路電流I2。在放大階段中的旁路期間內,連接端n2和n3分別耦合至旁路電流源106和108,並且流過負載電容C1/C2的電流為(I1-I2)。為了通過減少電流來得到預定的共模電壓差△Vcm,延長放大階段以及在差分輸出Vop與Von之間形成更大的差。如此,由於旁路設計可以提供更大的增益。動態放大器100甚至在低電壓操作中也具有寬的信號擺幅。
在第1圖中,受控制信號CS_R控制的開關在重置 階段閉合,受控制信號CS_A控制的開關在放大階段閉合,以及受控制信號CSb控制的開關在放大階段內的旁路期間閉合。取樣階段設置在控制信號CS_A的使能狀態之後。第2圖示出了控制信號CS_R,CS_A以及CSb的波形以及差分輸出Vop與Von的變化。通過在重置階段T_R使能控制信號CS_R,負載電容C1和C2放電並且差分輸出Vop和Von均重置為地電平。在放大階段T_A,提供充電電流來對負載電容C1和C2進行充電,並且差分輸出Vop和Von的電壓電平升高。在旁路期間Tb之前,每個負載電容(C1或C2)的充電電流均為I1。在旁路期間Tb內,每個負載電容(C1或C2)的充電電流降低至(I1-I2)。當差分輸出Vop和Von的共模電壓達到預定的共模電壓差△Vcm時,放大階段T_A結束。取樣階段T_S設置在放大階段T_A之後。此處沒有示出用於對差分輸出Vop和Von進行取樣的取樣電路,但是任何的信號取樣設計均可以用來實現該取樣電路。動態放大器100的增益G為gm.△Vcm/(I1-I2.Tb/T_A),其中gm為輸入對102中每個電晶體的跨導。相比於沒有旁路設計的提供增益gm.△Vcm/I1的傳統動態放大器,動態放大器100通過簡單的旁路設計提供了更高的增益。
在一些典型實施例中,電流源106和108為可變電流源,均提供可變旁路電流I2。在一些典型實施例中,如果設計者接受負載電容C1和C2的慢的充電速度,那麼旁路期間Tb覆蓋整個放大階段T_A。當旁路期間Tb覆蓋整個放大階段T_A時,動態放大器100具有增益gm.△Vcm/(I1-I2),該增益大 於傳統動態放大器提供的有限的增益gm.△Vcm/I1。
在第3圖為根據本發明另一實施例的動態放大器300的結構。相比於第1圖的動態放大器100,第3圖中連接負載電容C1和C2的共模端為電源端VDD。第4圖示出了控制信號CS_R,CS_A和CSb的波形以及動態放大器300的差分輸出Vop和Von的變化。通過使控制信號CS_R在重置階段T_R使能,差分輸出Vop和Von均連接至電源電平(也標記為VDD)。在放大階段T_A,流過負載電容C1和C2的電流對負載電容C1和C2充電,並且差分輸出Vop和Von的電壓電平被拉下來。在放大階段T_A,旁路期間Tb之前流過每個負載電容(C1或C2)的電流為I1。在旁路期間Tb內,流過每個負載電容(C1或C2)的電流均降低至(I1-I2)。當差分輸出Vop和Von的共模電壓達到預定的共模電壓差△Vcm時,放大階段結束。取樣階段T_S設置在放大階段T_A之後。通過旁路設計(參考旁路電流I2)來有效地改善動態放大器300的增益G。
第5圖為根據本發明另一實施例的動態放大器500的結構。取代放電,連接在共模端GND的負載電容C1和C2在重置階段被預充電並且在放大階段放電。第6圖示出了控制信號CS_R,CS_A和CSb的波形以及動態放大器500的差分輸出Vop與Von的變化。通過在重置階段T_R使控制信號CS_R使能,負載電容C1和C2預充電並且差分輸出Vop與Von均連接至電源電平VDD。在放大階段T_A,提供放電電流以使負載電容C1和C2放電並且差分輸出Vop與Von的電壓電平 下降。在旁路期間Tb之前,每個負載電容(C1或C2)的放電電流均為I1。在旁路期間Tb,每個負載電容(C1或C2)的充電電流均降低至(I1-I2)。當差分輸出Vop與Von的共模電壓達到預定的共模電壓差△Vcm時,放大階段T_A結束。取樣階段T_S設置在放大階段T_A之後。通過旁路設計(參考旁路電流I2)來有效地改善動態放大器500的增益G。
任何在放大階段對一對負載電容使用旁路設計的動態放大器均考慮在本發明的範圍內。
本發明的動態放大器使用開關元件以及連接共模連接端至VDD或GND以移除不需要的靜態電流。
負載電路中形成的負載電容對C1和C2可以由其他電路來取代。任何耦合至共模端且能夠提供一對差分輸出Vop和Von的電路均可以用來替換該對負載電容C1和C2以形成負載電路。
形成驅動器的用於放大的電流源(如104)可以由其他能夠對信號放大提供驅動能力的電路來替換。
形成旁路電路的一對旁路電流源106和108可以由其他電路替代。任何能有效地降低負載電路的電流的電路均可以用來替換該對旁路電流源106和108,以形成旁路電路。
第7圖為根據本發明實施例的包含動態放大器702的晶片700的結構示意圖。動態放大器702使用本公開的旁路設計。晶片700進一步包括:前級電路704和後級電路706。前級電路704傳送差分輸入Vip和Vin至動態放大器702。後級電路706從動態放大器702接收差分輸出Vop和Von。
晶片700進一步包括:寄存器R_I2,用於設置由動態放大器702的旁路電流源提供的可變的旁路電流I2。晶片700進一步包括:寄存器R_Tb,用於設置動態放大器702中安排的旁路期間Tb。
以上所述僅為本發明的較佳實施例而已,並不用以限制本發明,凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等,均應包含在本發明的保護範圍之內。
Claims (11)
- 一種動態放大器,包括:一輸入對,接收一對差分輸入Vip與Vin,並且提供第一端、第二端以及第三端;一負載電路,耦合至共模端,並且提供一對差分輸出Vop和Von;一用於放大的驅動器;以及一旁路電路,可***作以降低該負載電路的電流;其中:該驅動器在放大階段耦合至該第一端;該負載電路在該放大階段耦合至該第二端及該第三端;以及該旁路電路在該放大階段中的旁路期間內耦合至該第二端與該第三端;其中,當該對差分輸出Vop與Von的共模電壓達到預定的共模電壓差△Vcm時,該放大階段結束。
- 如申請專利範圍第1項所述的動態放大器,其中,該負載電路包括:一對負載電容;該對負載電容提供該對差分輸出Vop和Von,並且該對負載電容在該共模端處彼此連接;在該放大階段,該對負載電容分別耦合至該第二端與第三端。
- 如申請專利範圍第1項所述的動態放大器,其中,該旁路電路包括:一對旁路電流源,可***作以降低該對負載電容的電流;其中,在該放大階段中的該旁路期間內,該對旁路電流源分別耦合至該第二端與該第三端。
- 如申請專利範圍第1項所述的動態放大器,其中,該驅動器為一用於放大的電流源,並且該電流源在該放大階段耦合至該第一端。
- 如申請專利範圍第1項所述的動態放大器,其中,該電晶體輸入對中的電晶體的源極連接至該第一端;該電晶體輸入對中的電晶體的汲極分別被視為該第二端與該第三端;以及該電晶體輸入對中的電晶體的閘極接收該對差分輸入Vip與Vin。
- 如申請專利範圍第2項所述的動態放大器,其中,該對負載電容在重置階段放電,在該放大階段中充電,其中該重置階段在該放大階段之前。
- 如申請專利範圍第6項所述的動態放大器,其中,該共模端為地;該對差分輸出Vop與Von在該重置階段均被下拉至地,以及在該放大階段升高。
- 如申請專利範圍第6項所述的動態放大器,其中,該共模端為電源端;該對差分輸出Vop與Von在該重置階段連接至該電源端,以及在該放大階段中下降。
- 如申請專利範圍第2項所述的動態放大器,其中,該對負載電容在重置階段預充電,在該放大階段中放電,其中該重置階段在該放大階段之前;該共模端為地;該對差分輸出Vop與Von在該重置階段均連接至電源端;該對差分輸出Vop與Von在該放大階段下降。
- 一種晶片,包括:一前級電路,一後級電路;以及一動態放大器,其中該動態放大器為申請專利範圍第1~9項中任一項所述的動態放大器;其中,該前級電路用於將該對差分輸入Vip與Vin傳送至該動態放大器,該後級電路用於從該動態放大器接收該對差分輸出Vop與Von。
- 如申請專利範圍第10項所述的晶片,其中,進一步包括:一第一寄存器,用於設置該旁路電路在該負載電路上引起的電流下降量;以及一第二寄存器,用於設置該旁路期間。
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