TWI646640B - 封裝結構及封裝製程方法 - Google Patents

封裝結構及封裝製程方法 Download PDF

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TWI646640B
TWI646640B TW106128344A TW106128344A TWI646640B TW I646640 B TWI646640 B TW I646640B TW 106128344 A TW106128344 A TW 106128344A TW 106128344 A TW106128344 A TW 106128344A TW I646640 B TWI646640 B TW I646640B
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Taiwan
Prior art keywords
metal carrier
layer
wafer
support structure
conductive
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TW106128344A
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English (en)
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TW201839924A (zh
Inventor
陳明志
許獻文
藍源富
徐宏欣
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力成科技股份有限公司
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Publication of TW201839924A publication Critical patent/TW201839924A/zh
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Abstract

封裝結構包含金屬載體、晶片、封模層及重配置線路層。金屬載體包含底部及支撐結構，金屬載體具有由底部及支撐結構共同形成凹陷部，且金屬載體為一體成形。晶片設置於金屬載體之凹陷部，且晶片具有複數個導電凸塊。封模層包覆晶片。封模層顯露出每一導電凸塊的一部分及支撐結構的一部分。重配置線路層設置於封模層上，且電性連接於複數個導電凸塊。

Description

封裝結構及封裝製程方法
本發明係有關於一種封裝製程方法，尤其是一種將晶片設置於一體成形之金屬載體的凹陷部的封裝製程方法。
在晶片的封裝製程中，常會利用到扇出結構。當晶片的輸入/輸出界面較多且輸入/輸出界面彼此間的間距較小時，扇出結構可透過將晶片的輸入/輸出界面經由扇出電路電性連接至另一組具有較大間距的導電界面來擴張晶片之輸入/輸出界面之間的間距。利用扇出結構擴張輸入/輸出界面之間的間距能夠提高良率並簡化封裝製程。前述的輸入/輸出界面可例如為球形柵格陣列(ball-grid-array，BGA)的焊接球。然而，前述的扇出結構雖然能夠擴張輸入/輸出界面之間的間距，卻在抗電磁干擾、散熱效果及結構強度上不盡理想。
本發明之一實施例提供一種封裝結構，封裝結構包含金屬載體、晶片、封模層及重配置線路層。
金屬載體包含底部及支撐結構，底部及支撐結構形成金屬載體之凹陷部，且金屬載體為一體成形。晶片設置於金屬載體之凹陷部，晶片具有複數個導電凸塊。封模層包覆晶片，其中封模層顯露出複數個導電凸塊之每一導電凸塊的一部分及支撐結構的一部分。重配置線路層設置於封模層上，且電性連接於複數個導電凸塊。
本發明之另一實施例提供一種封裝製程方法，方法包含形成金屬載體，金屬載體具有底部及支撐結構，底部及支撐結構形成金屬載體之凹陷部，且金屬載體為一體成形，將晶片設置於金屬載體之凹陷部，形成封模層以包覆晶片，研磨封模層以顯露出晶片之複數個導電凸塊之每一導電凸塊的一部分及支撐結構之一部分，及於封模層上形成重配置線路層。重配置線路層電性連接於複數個導電凸塊。
第1圖為本發明一實施例之封裝結構100的示意圖。封裝結構100可包含金屬載體110、晶片120、複數個導電凸塊130、封模層140、重配置線路層150及複數個第一焊接球160。金屬載體110為一體成形，並可包含底部1101及第一支撐結構1102，且金屬載體110的底部1101及第一支撐結構1102可形成金屬載體110的凹陷部，其中第一支撐結構1102圍繞著凹陷部。金屬載體110同其底部1101及第一支撐結構1102可透過將單一導電基底蝕刻來形成。透過以單一導電基體來成型，能夠使金屬載體110更強固而耐用。此外，底部1101可隔離電磁干擾以保護電路。金屬載體110可具有低熱容量。金屬載體110的結構還可作為散熱槽以助晶片120散熱。因此封裝結構100在抗電磁干擾、散熱效果及結構強度方面都能夠有所提升。
晶片120可具有複數個功能界面120c。導電凸塊130可對應地形成於功能界面120c。晶片120可設置在金屬載體110的凹陷部以熱耦合至底部1101。在晶片120及底部1101之間可設置保護層f1。保護層f1可為黏性層或薄膜，例如晶圓黏結薄膜(die attach film，DAF)，以黏合晶片120及金屬載體110。封模層140可透過在凹陷部中填入封模材料來形成，並可包覆晶片120。封模層140可被研磨至顯露出導電凸塊130及第一支撐結構1102的對應表面。如此一來，便能得到外露的導電凸塊130及第一支撐結構1102的外露表面1102e。
在本發明的部分實施例中，第一支撐結構1102可電性連接至接地端或電性連接至電壓源。重配置線路層150可形成於封模層140、外露的導電凸塊130及第一支撐結構1102的外露表面1102e的上方，並可根據電路繞線的需求，包含一層或多層線路層。重配置線路層150可包含複數個第一界面1501、線路150c及複數個第二界面1502。第一界面1501可對應地耦接於外露的導電凸塊130以及第一支撐結構1102的外露表面1102e。第二界面1502可經由線路150c電性連接至重配置線路層150的第一界面1501。第一焊接球160可對應地設置於重配置線路層150的第二界面1502。
如第1圖所示，可透過形成防焊層170來覆蓋重配置線路層150上除第二界面1502以外的部分。防焊層170可以在焊接過程中，保護重配置線路層150中除了第二界面1502以外的其他部分。
第2圖為本發明另一實施例之封裝結構200的示意圖。相較於第1圖中的封裝結構100，封裝結構200還可包含第二支撐結構210，第二支撐結構210可包含複數個支柱210p，且支柱210p可如第19圖所示，環繞著第一支撐結構1102排列。在蝕刻金屬載體110以形成底部1101及第一支撐結構1102時，也可同時一起形成第二支撐結構210。當凹陷部填入封模材料以形成封模層240之後，於蝕刻過程中所產生的空間，例如第一支撐結構1102與第二支撐結構210之間的空隙，以及複數個支柱210p之間的空隙，都將由封模層240填充。封模層240固化後可被研磨至顯露出第一外露面(外露於封模層240)，以形成複數個第一附屬界面2101。
部分在第一支撐結構1102與第二支撐結構210之間以及在複數個支柱210p之間的底部1101可透過蝕刻封裝結構200的背面(亦即封裝結構200中相對於晶片120較靠近底部1101的這一面)來移除，以形成第二外露面(同樣外露於封模層240)並藉此形成複數個第二附屬界面2102，同時也使複數個支柱210p彼此之間及複數個支柱210p與第一支撐結構1102保持電性隔離。封裝結構200的整個背面，包含外露的封模層240及複數個第二附屬界面2102，可由介電層2301覆蓋。防焊層2302可形成於介電層2301上方，並可覆蓋以保護除了在第二附屬界面2102上方以外的介電層2301。在第二附屬界面2102上方的介電層2301可接著被移除，以使在第二附屬界面2102上的第二焊接球220能夠電性連接至下一個接續的半導體封裝，如第18圖所示。
在第2圖中，重配置線路層250與第1圖的重配置線路層150相似，並可形成於封模層240上方。重配置線路層250的第一界面2501可設置於導電凸塊130、第一支撐結構1102的外露表面1102e及第一附屬界面2101的上方。如第2圖所述，部分的介電層2301及部分的防焊層2302可被移除或不設置，藉以顯露出金屬載體110的底部1101，達到較好的散熱效果。由於底部1101可作為電磁干擾的屏蔽以及散熱槽，因此將底部1101外露即可進一步提升散熱效果。在部份其他的實施例中，底部1101也可由介電層2301及/或防焊層2302所覆蓋。
在部分實施例中，第1圖的重配置線路層150及第2圖的重配置線路層250可包含複數個介電層及複數個導電層。重配置線路層150及250的介電層與導電層可根據需求形成客製化的線路。重配置線路層150及250可包含根據需求所設計的線路，並可用來將晶片120上具有較小間距的功能界面120c重新配置連接。重配置線路層150及250可提供扇出線路以將功能界面120c之間的狹小間距擴張至焊接球之間的較大間距。在部分實施例中，重配置線路層150及250的介電層可包含可與對應波長光顯影成型的至少一感光層。在部分實施例中，重配置線路層150及250還可包含至少一金種濺鍍層。
如第1及2圖所示，第一支撐結構1102及第二支撐結構210可作為加強結構的支撐柱。第一支撐結構1102可被蝕刻至所需的大小，以提升散熱能力。第二支撐結構210可被形成為一組電性隔離的支柱。
第3圖為本發明一實施例之製造第1圖之封裝結構100之製程方法300的流程圖。第4至10圖為封裝結構100對應於第3圖之各個步驟的示意圖。封裝製程方法300可包含步驟310至360。
步驟310： 將單一導電基底蝕刻以形成一體成型且具有凹陷部110r的金屬載體110；
步驟320： 將晶片120設置於金屬載體110之凹陷部110r；
步驟330： 利用封模材料填充凹陷部110r以形成包覆晶片120的封模層140；
步驟340： 研磨封模層140以顯露出導電凸塊130的對應表面；
步驟350： 於封模層140上形成重配置線路層150，使得重配置線路層150的第一界面1501能夠對應地耦接至外露的導電凸塊130；
步驟360： 將第一焊接球160設置於重配置線路層150的第二界面1502，且第一焊接球160可經由重配置線路層150的線路150c電性連接至功能界面120c。
第4圖可對應於步驟310。第5圖可對應於步驟320。第6圖可對應於步驟330至340。第7至9圖可對應於步驟350。第10圖可對應於步驟360。
在步驟310中，凹陷部110r的底部1101可實質上與第一支撐結構1102形成直角。由於蝕刻的過程，底部1101可能並非完全平整。然而，底部1101的不平整通常可以忽略，而晶片120的大小可小到足以讓晶片120能夠穩定地設置於凹陷部110r中。如第5圖所示，保護層f1可形成於晶片120及凹陷部110r之間，以在步驟320中將晶片120黏合至底部1101。
導電凸塊130可為透過柱狀凸塊製程(pillar bump process)所形成或設置的銅柱，並可對應地電性連接至晶片120的功能界面120c。在部分實施例中，導電凸塊130可能在晶片120設置於金屬載體110之前就已經先行形成。除了銅以外，其他適合的導電材料也可用來形成導電凸塊130。
在步驟360中，防焊層170可在焊接過程中，保護重配置線路層150中除了界面1502以外的部分。如第7至9圖所示，介電層150p1、150p2及150pt和導電層150m1、150m2及150mt可透過光罩顯影圖案的方式一層一層製作來形成重配置線路層150。
導電層150m1、150m2及150mt可透過移除不需要的部分來形成所需的圖案。第一光阻層、第二光阻層及第三光阻層可分別用來形成導電層150m1、150m2及150mt的圖案。線路150c可利用至少導電層150m1、150m2及150mt來形成。在第7至10圖中，重配置線路層150可包含三層介電層及三層導電層。然而，第7至10圖是為方便說明所提供的實施例。在本發明的其他實施例中，重配置線路層150也可能根據需求而包含其他數量的介電層及導電層。舉例來說，根據本發明的一實施例，重配置線路層150也可僅包含一層介電層及一層導電層即可形成重配置線路層150的第一界面1501及第二界面1502。在其他實施例中，重配置線路層150可包含至少一介電層及至少一導電層。另可將適合的材料設置於界面1502以作為與第一焊接球160相接的球下冶金層(under bump metallurgy，UBM)。
由於上述的製程能夠製作複數個彼此相連、形成陣列的封裝結構100，因此在封裝結構100製作完畢後，還可透過切割程序(亦即分離程序)來將複數個封裝結構100彼此分離。切割程序可包含機械鋸切、雷射切割或其他切割方法。
第11圖為本發明一實施例之製造第2圖之封裝結構200之製程方法1200的流程圖。第12至17圖為封裝結構200對應於第11圖之各個步驟的示意圖。封裝製程方法1200可包含步驟1210至1288。
步驟1210： 將單一導電基底蝕刻以形成具有底部1101、第一支撐結構1102及第二支撐結構210的金屬載體110，底部1101及第一支撐結構1102可共同形成凹陷部110r，而第一支撐結構1102及第二支撐結構210之間可形成間隙110i；
步驟1220： 將晶片120設置於金屬載體110之凹陷部110r；
步驟1230： 利用封模材料填充凹陷部110r及間隙110i以形成包覆晶片120的封模層240；
步驟1240： 研磨封模層240以顯露出導電凸塊130，並顯露出第一支撐結構1102及第二支撐結構210以取得第一支撐結構1102的外露表面1102e及第二支撐結構210的第一附屬界面2101；
步驟1250： 於封模層240、第一支撐結構的1102的外露表面1102e及第二支撐結構210的第一附屬界面2101上形成重配置線路層250，使得重配置線路層250能夠對應地將其第一界面2501耦接至外露的導電凸塊130、第一支撐結構的1102的外露表面1102e及第一附屬界面2101；
步驟1260： 將第一焊接球160設置於重配置線路層250的第二界面2502，使得第一焊接球160能夠經由重配置線路層250的線路250c與晶片120的功能界面120c有電性連接；
步驟1270： 蝕刻金屬載體110的底部1101以使第一支撐結構1102及第二支撐結構210分離；
步驟1280： 形成介電層2301以使第一支撐結構1102與第二支撐結構210在顯露出第二附屬界面2102的情況下保持隔離；
步驟1285： 形成防焊層2302以覆蓋介電層2301，且防焊層2301具有圖案以顯露出第二附屬界面2102；
步驟1288： 於第二附屬界面2102上設置第二焊接球220。
第12圖可對應於步驟1210。第13圖可對應於步驟1220。第14圖可對應於步驟1230至1240。第15至17圖可對應於步驟1250至1288。在步驟1240中，研磨程序可以移除封模層240中不需要的部分。
在步驟1210中，根據本發明的其他實施例，除了第一支撐結構1102及第二支撐結構210外，還可形成更多數量的支撐結構。複數個支撐結構可用以形成支柱陣列以利層疊封裝時提供所需的電性連接。支柱間的間隔可以根據半導體封裝的需求增大或縮小。在步驟1220至1240中，會形成可容置晶片120並形成封模層240的凹陷部110r。在步驟1250至1260中，可形成重配置線路層250(如第2圖所示)。此外，第一焊接球160可設置於重配置線路層250上方。在步驟1270中，透過蝕刻金屬載體110的底部1102即可使第一支撐結構1102及第二支撐結構210相分離。再者，第二支撐結構210可透過蝕刻來形成複數個支柱。第二支撐結構210所形成的支柱可例如以下所述及第19圖之俯視圖所示的支柱210p。
重配置線路層250與前述的重配置線路層150相似，重配置線路層250可包含介電層250p1、250p2及250pt，以及導電層250m1及 250mt，亦即如第2、15及16圖所示。重配置線路層250的介電層可利用鑽孔方式形成通路。重配置線路層250的導電層可形成具有特定圖案並能夠透過介電層的通路連接至其他的導電層以形成線路250c。第2、15及16圖中，重配置線路層250中的介電層的數量及導電層的數量僅為方便說明的實施例。重配置線路層250可根據需求形成任意數量的介電層及導電層。第一導電層250m1及/或頂部導電層250mt可與濺鍍的傳導性接種層(conductive seed)一起電鍍以提升焊接球的焊接準確度。透過執行表面拋光程序還可清潔界面2502及第二附屬界面2102並使其平整，以便固定焊接球160及220。如第2圖所示，底部1101的至少一部份可外露，以達到較佳的散熱效果。如同先前所述，在複數個共同形成且彼此具有物理連接的封裝結構200製作完成後，還可執行切割程序以將這些封裝結構200彼此分離。
第17圖為本發明一實施例之封裝結構1700的示意圖。封裝結構1700與第2圖之封裝結構200相似。然而，如第17圖所示，此實施例的散熱槽(亦即金屬載體110)的背側還覆蓋了介電層及防焊層。在第17圖中，底部1101可被介電層2301及防焊層2302覆蓋，並僅顯露出第二附屬界面2102。在本發明的部分實施例中，第2圖的封裝結構200可透過對第17圖的封裝結構1700執行其他程序來製作。在第17圖中，若移除部分的介電層2301及對應部分的防焊層2302即可顯露出散熱槽的背側表面1101e，提升散熱效果。根據本發明之實施例所提供的封裝結構100(第1圖)、200(第2圖)及1700(第17圖)，(具導電性的)支撐結構1102及210能夠提升散熱槽(亦即金屬載體110)的支撐強度，並可作為導電通路以提升設計的彈性，還可提供良好的散熱及抗電磁干擾(electromagnetic interference，EMI)效果。使用者可以根據產品的規格選擇適當類型的封裝結構。
第18圖為本發明一實施例之包含封裝結構200的層疊封裝(package-on-package，PoP)結構的示意圖。外部晶片1910可設置於第二焊接球220以使外接晶片1910的複數個界面1915與第二焊接球220相耦接。外接晶片1910可透過第二焊接球220、第二支撐結構210所形成的一組支柱、線路250c及導電凸塊130與晶片120電性通聯。
第19圖為本發明一實施例之一批次之封裝結構的俯視圖。如同先前所述，在第19圖中，第二支撐結構210可具有一組排列成方形的支柱210p。第一支撐結構1102可圍繞晶片120以提供電磁屏蔽。在第19圖中，複數個封裝結構可形成如陣列。例如在第19圖所示的四個封裝結構。在封裝結構製作完成後，可沿著切割線2011至2012執行切割程序來將各個封裝結構分離。
綜上所述，透過本發明之實施例所提供的封裝製程方法及封裝結構，就能夠藉由蝕刻單一導電基底使金屬載體一體成形且具有凹陷部以作為容置晶片的散熱槽，同時實作出能夠提升抗電磁干擾、散熱效果及結構強度的扇出結構。且在此架構下，還可允許層疊封裝結構。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100、200、1700 封裝結構 110 金屬載體 120 晶片 130 導電凸塊 140、240 封模層 150、250 重配置線路層 160 第一焊接球 1101 底部 1102 第一支撐結構 1102e 外露表面 120c 功能界面 1501、2501 第一界面 1502、2502 第二界面 150c、250c 線路 170、2302 防焊層 f1 保護層 1101e 背側表面 210 第二支撐結構 2101 第一附屬界面 2102 第二附屬界面 220 第二焊接球 2301、150p1、150p2、150pt、250p1、 介電層 250p2、250pt 300、1200 方法 310至360、1210至1288 步驟 110r 凹陷部 150m1、150m2、150mt、250m1、 導電層 250mt 1910 外接晶片 1915 界面 2011、2012 切割線
第1圖為本發明一實施例之封裝結構的示意圖。 第2圖為本發明另一實施例之封裝結構的示意圖。 第3圖為本發明一實施例之製造第1圖之封裝結構之製程方法的流程圖。 第4至10圖為對應於第3圖之各個步驟的封裝結構示意圖。 第11圖為本發明一實施例之製造第2圖之封裝結構之製程方法的流程圖。 第12至17圖為對應於第11圖之各個步驟的封裝結構示意圖。 第18圖為本發明一實施例之包含封裝結構之層疊封裝結構的示意圖。 第19圖為本發明一實施例之一批次之封裝結構的俯視圖。

Claims (7)

  1. 一種封裝結構，包含：一金屬載體，包含一底部、一第一支撐結構及一第二支撐結構，該底部及該第一支撐結構形成該金屬載體之一凹陷部，該金屬載體係為一體成形，該第二支撐結構設置於該第一支撐結構周圍，且包含複數個支柱，該金屬載體之該底部之至少一部份及該第二支撐結構之至少一部份係被一介電層覆蓋，且金屬載體之該底部之至少另一部分係暴露於該封裝結構外；一晶片，設置於該金屬載體之該凹陷部，該晶片具有複數個導電凸塊；一封模層，包覆該晶片即該第二支撐結構，其中該封模層顯露出該些導電凸塊之每一導電凸塊的一部分及該第一支撐結構的一部分；及一重配置線路層，設置於該封模層上，且直接電性連接於該些導電凸塊、該第一支撐結構及該第二支撐結構。
  2. 如請求項1所述之封裝結構，另包含：一保護層，設置於該晶片及該金屬載體之間。
  3. 一種封裝製程方法，用以製造一封裝結構，包含：形成一金屬載體，該金屬載體具有一底部及複數個支撐結構，該底部及該些支撐結構中的一第一支撐結構形成該金屬載體之一凹陷部，且該金屬載體係為一體成形；將一晶片設置於該金屬載體之該凹陷部；形成一封模層以包覆該晶片；研磨該封模層以顯露出該晶片之複數個導電凸塊之每一導電凸塊的一部分及該些支撐結構之一部分；及於該封模層上形成一重配置線路層，其中該重配置線路層直接電性連接於該些導電凸塊及該第一支撐結構；其中該金屬載體之該底部的至少一部分係暴露於該封裝結構外。
  4. 如請求項3所述之方法，另包含：在該晶片及該金屬載體的該底部之間設置一保護層。
  5. 如請求項3所述之方法，其中形成該金屬載體係將一單一導電基底蝕刻以形成該底部及該些支撐結構。
  6. 如請求項5所述之方法，另包含：在形成該封模層後，蝕刻該金屬載體以使該些支撐結構中的一第二支撐結構區隔於該底部及該第一支撐結構；其中該第二支撐結構包含複數個支柱。
  7. 如請求項5所述之方法，另包含：形成一介電層以覆蓋該底部之至少一部份及該第二支撐結構之至少一部份。
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CN108807308A (zh) 2018-11-13
TW201839924A (zh) 2018-11-01

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