TWI641138B

TWI641138B - Semiconductor power device unit and manufacturing method thereof

Info

Publication number: TWI641138B
Application number: TW105133619A
Authority: TW
Inventors: 陳明欽; 楊亞諭; 杜尚儒
Original assignee: 晶元光電股份有限公司
Priority date: 2016-10-19
Filing date: 2016-10-19
Publication date: 2018-11-11
Also published as: TW201817009A

Abstract

一種半導體功率元件單元，包含一基板；一通道層，位於前述基板上；一障壁層，位於前述通道層上；一二維電子氣層，位於鄰近前述通道層與前述障壁層間之一介面；一汲極電極、一閘極電極、以及一源極電極，分別位於前述障壁層上，且前述閘極電極位於前述汲極電極及前述源極電極之間；一第一區域，包含一第一鎂佈植特徵，位於前述障壁層內相對應於前述閘極電極的下方；以及一第二區域，包含一第二鎂佈植特徵，位於前述障壁層內相對應於前述汲極電極與前述閘極電極之間及/或前述源極電極與前述閘極電極之間；其中，前述第一區域與前述第二區域相連接；其中，前述第一鎂佈植特徵大於前述第二鎂佈植特徵。A semiconductor power component unit includes a substrate; a channel layer on the substrate; a barrier layer on the channel layer; and a two-dimensional electron gas layer adjacent to an interface between the channel layer and the barrier layer; a drain electrode, a gate electrode, and a source electrode are respectively located on the barrier layer, and the gate electrode is located between the gate electrode and the source electrode; and a first region includes a first magnesium An implant feature located in the barrier layer corresponding to the gate electrode; and a second region including a second magnesium implant feature located in the barrier layer corresponding to the gate electrode and the gate Between the electrodes and/or between the source electrode and the gate electrode; wherein the first region is connected to the second region; wherein the first magnesium implant feature is greater than the second magnesium implant feature.

Description

半導體功率元件單元及其製造方法Semiconductor power component unit and method of manufacturing same

本揭露是關於一種半導體元件單元及其製造方法，更具體而言，係關於一種半導體功率元件單元及其製造方法。The present disclosure relates to a semiconductor device unit and a method of fabricating the same, and more particularly to a semiconductor power device unit and a method of fabricating the same.

近幾年來，由於高頻及高功率產品的需求與日俱增，三五族半導體材料氮化鎵(GaN)的能隙約為3.4eV，熱傳導性＞1.5 W/cm，其寬能隙及高熱傳導性(易於散熱)適合操作在高溫以及耐化學腐蝕的環境。此外，氮化鎵材料的崩潰電場為(3 x 10⁶ V/cm) ，載子傳輸速度可以達到3× 10⁷ cm/s，使得氮化鎵材料適合作為微波高功率電子元件，可施加高電壓於其上而不致崩壞。因此，以氮化鎵材料為主的半導體功率元件，如氮化鋁鎵-氮化鎵(AlGaN/GaN)半導體功率元件等…因具高速電子遷移率、可達到非常快速的切換速度、可於高頻、高功率及高溫工作環境下操作的元件特性，廣泛地被應用在電源供應器(power supply)、DC/DC轉換器(DC/DC converter)、DC/AC逆變器(AC/DC inverter)以及工業運用，其領域包含電子產品、不斷電系統、汽車、馬達、風力發電等。In recent years, due to the increasing demand for high-frequency and high-power products, the gallium nitride (GaN) of the three-five semiconductor materials has an energy gap of about 3.4 eV, thermal conductivity of >1.5 W/cm, and wide energy gap and high thermal conductivity. (Easy to dissipate heat) Suitable for operation in high temperature and chemical resistant environments. In addition, the breakdown electric field of the gallium nitride material is (3 x 10 ⁶ V/cm), and the carrier transmission speed can reach 3 × 10 ⁷ cm/s, making the gallium nitride material suitable as a microwave high-power electronic component, which can be applied high. The voltage is on it without collapse. Therefore, semiconductor power devices based on gallium nitride materials, such as aluminum gallium nitride-gallium nitride (AlGaN/GaN) semiconductor power devices, etc., can achieve very fast switching speeds due to high-speed electron mobility. Component characteristics for operation in high frequency, high power and high temperature operating environments are widely used in power supply, DC/DC converter, DC/AC inverter (AC/DC) Inverter) and industrial applications, including electronic products, uninterruptible power systems, automobiles, motors, wind power generation, etc.

本揭露係關於一種半導體功率元件單元，包含一基板；一通道層，位於前述基板上；一障壁層，位於前述通道層上；一二維電子氣層，位於鄰近前述通道層與前述障壁層間之一介面；一汲極電極、一閘極電極、以及一源極電極，分別位於前述障壁層上，且前述閘極電極位於前述汲極電極及前述源極電極之間；一第一區域，包含一第一鎂佈植特徵，位於前述障壁層內相對應於前述閘極電極的下方；以及一第二區域，包含一第二鎂佈植特徵，位於前述障壁層內相對應於前述汲極電極與前述閘極電極之間及/或前述源極電極與前述閘極電極之間；其中，前述第一區域與前述第二區域相連接；其中，前述第一鎂佈植特徵大於前述第二鎂佈植特徵。The present disclosure relates to a semiconductor power device unit including a substrate; a channel layer on the substrate; a barrier layer on the channel layer; and a two-dimensional electron gas layer adjacent to the channel layer and the barrier layer An interface, a gate electrode, a gate electrode, and a source electrode are respectively disposed on the barrier layer, and the gate electrode is located between the gate electrode and the source electrode; a first region includes a first magnesium implant feature located in the barrier layer corresponding to the gate electrode; and a second region comprising a second magnesium implant feature located in the barrier layer corresponding to the gate electrode Between the foregoing gate electrode and/or the source electrode and the gate electrode; wherein the first region is connected to the second region; wherein the first magnesium implant feature is greater than the second magnesium Planting characteristics.

一種半導體功率元件單元的製造方法，包含提供一基板；形成一磊晶疊層於前述基板上，前述磊晶疊層包含一通道層、一障壁層，以及一二維電子氣層，位於鄰近前述通道層與前述障壁層間之一介面；形成一暫時性遮罩層於前述障壁層上；透過前述暫時性遮罩層對前述障壁層進行一次鎂佈植，並藉由前述一次鎂佈植步驟以使得前述障壁層具有一第一區域以及一第二區域；以及形成一源極電極、一閘極電極、以及一汲極電極於前述障壁層上；其中，前述閘極電極位於前述源極電極及前述汲極電極之間；其中，前述第一區域與前述第二區域相連接；其中，前述第一區域具有一第一鎂佈植特徵，前述第二區域具有一第二鎂佈植特徵；其中，前述第一鎂佈植特徵大於前述第二鎂佈植特徵。A method of fabricating a semiconductor power device unit, comprising: providing a substrate; forming an epitaxial layer on the substrate, the epitaxial layer stack comprising a channel layer, a barrier layer, and a two-dimensional electron gas layer adjacent to the foregoing Interfacing a channel layer with the barrier layer; forming a temporary mask layer on the barrier layer; performing a magnesium implantation on the barrier layer through the temporary mask layer, and using the first magnesium implantation step The barrier layer has a first region and a second region; and a source electrode, a gate electrode, and a drain electrode are formed on the barrier layer; wherein the gate electrode is located at the source electrode and The first region is connected to the second region; wherein the first region has a first magnesium implant feature, and the second region has a second magnesium implant feature; The first magnesium implant feature is greater than the second magnesium implant feature.

為讓本揭露之上述和其他目的、特徵和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims.

以下實施例將伴隨著圖式說明本揭露之概念，在圖式或說明中，相似或相同之部分係使用相同之標號，並且在圖式中，元件之形狀或厚度可擴大或縮小。需特別注意的是，圖中未繪示或描述之元件，可以是熟習此技藝之人士所知之形式。The present invention will be described with reference to the drawings, in which the same or the same reference numerals are used in the drawings or the description, and in the drawings, the shape or thickness of the elements may be enlarged or reduced. It is to be noted that elements not shown or described in the figures may be in a form known to those skilled in the art.

請參閱第1圖，第1圖為本揭露第一實施例之一半導體功率元件S的上視圖。半導體功率元件S例如為三端點的元件。於本實施例中，半導體功率元件S包含一源極墊S70、一汲極墊S80、一閘極墊S90和至少一個半導體功率元件單元E1。半導體功率元件單元E1例如是場效電晶體(FET)，具體來說可以是高電子遷移率電晶體(HEMT)。半導體功率元件單元E1可包括與源極墊S70電性連接之一源極電極70、與汲極墊S80電性連接之一汲極電極80、與閘極墊S90電性連接之一閘極電極90，以及一半導體疊層(未標示)，半導體疊層的材料、位置與外觀設計可依實際的需求而做調整。此外，半導體元件S所包含的半導體功率元件單元E1亦可被本揭露其他實施例中的半導體功率元件單元所取代。Please refer to FIG. 1. FIG. 1 is a top view of a semiconductor power device S according to a first embodiment of the present disclosure. The semiconductor power element S is, for example, a three-terminal element. In the embodiment, the semiconductor power device S includes a source pad S70, a drain pad S80, a gate pad S90, and at least one semiconductor power device unit E1. The semiconductor power device unit E1 is, for example, a field effect transistor (FET), and specifically may be a high electron mobility transistor (HEMT). The semiconductor power device unit E1 may include one source electrode 70 electrically connected to the source pad S70, one drain electrode 80 electrically connected to the drain pad S80, and one gate electrode electrically connected to the gate pad S90. 90, and a semiconductor stack (not labeled), the material, location and design of the semiconductor stack can be adjusted according to actual needs. In addition, the semiconductor power device unit E1 included in the semiconductor device S can also be replaced by the semiconductor power device unit in other embodiments.

請參閱第2A圖至第2B圖所示本揭露第一實施例之半導體功率元件單元E1的結構。為了清楚說明半導體功率元件單元E1的細部結構，第2A圖繪示了半導體功率元件單元E1之局部放大上視示意圖，而第2B圖繪示了第2A圖沿剖線FF’之剖面示意圖。半導體功率元件單元E1例如為一種常關型高電子遷移率電晶體，包括一基板10、一成核層20、一緩衝結構30、一通道層40、一障壁層50、一保護層60、一源極電極70、一汲極電極80、以及一閘極電極90。其中，成核層20與緩衝結構30依序位於基板10的上方；通道層40具有一第一能隙，且位於緩衝結構30上方；障壁層50位於通道層40上方，具有一第二能隙，且第二能隙大於第一能隙。障壁層50包含一具有第一鎂佈植特徵的第一區域501，其位置相對應於閘極電極90的下方；以及一具有第二鎂佈植特徵的第二區域502，包含有5021及5022的兩個子區域，其位置分別為相對應於源極電極70與閘極電極90之間的下方以及汲極電極80與閘極電極90之間的下方，在一實施例中第二區域也可以只包含有5021一個子區域或是只包含有5022一個子區域，於本領域具有通常知識者可以了解，可依元件需求進行適當調整當，本揭露並不以此實施例為限；保護層60則位於源極電極70與閘極電極90之間以及汲極電極80與閘極電極90之間。此外，第一區域501分別與第二區域502的子區域5021及5022相連接，而於第一區域501中的第一鎂佈植特徵大於於第二區域中的第二鎂佈植特徵。於本實施例中，鎂佈植特徵例如是障壁層50中的最高鎂佈植濃度或最大鎂佈植深度等物理性特徵；在一實施例中鎂佈植特徵同時具有最高鎂佈植濃度及最大鎂佈植深度兩個物理性特徵。詳細內容將於後續進行描述。Please refer to the structure of the semiconductor power device unit E1 of the first embodiment of the present disclosure shown in FIGS. 2A to 2B. In order to clearly illustrate the detailed structure of the semiconductor power device unit E1, FIG. 2A is a partially enlarged top view of the semiconductor power device unit E1, and FIG. 2B is a cross-sectional view of the second A drawing taken along the line FF'. The semiconductor power device unit E1 is, for example, a normally-off high electron mobility transistor, and includes a substrate 10, a nucleation layer 20, a buffer structure 30, a channel layer 40, a barrier layer 50, a protective layer 60, and a A source electrode 70, a drain electrode 80, and a gate electrode 90. The nucleation layer 20 and the buffer structure 30 are sequentially located above the substrate 10; the channel layer 40 has a first energy gap and is located above the buffer structure 30; the barrier layer 50 is located above the channel layer 40 and has a second energy gap. And the second energy gap is greater than the first energy gap. The barrier layer 50 includes a first region 501 having a first magnesium implant feature corresponding to the underside of the gate electrode 90; and a second region 502 having a second magnesium implant feature, including 5021 and 5022 The two sub-regions are respectively located below the source electrode 70 and the gate electrode 90 and below the gate electrode 80 and the gate electrode 90. In an embodiment, the second region is also It may contain only 5021 one sub-region or only 5022 one sub-region, which can be understood by those skilled in the art and can be appropriately adjusted according to component requirements. The disclosure is not limited to this embodiment; 60 is located between the source electrode 70 and the gate electrode 90 and between the drain electrode 80 and the gate electrode 90. In addition, the first region 501 is coupled to the sub-regions 5021 and 5022 of the second region 502, respectively, and the first magnesium implant feature in the first region 501 is greater than the second magnesium implant feature in the second region. In the present embodiment, the magnesium implant feature is, for example, a physical feature such as the highest magnesium implant concentration or the maximum magnesium implant depth in the barrier layer 50; in one embodiment, the magnesium implant feature has the highest magnesium implant concentration and The maximum magnesium implant depth has two physical characteristics. The details will be described later.

以下接著以第3A至第3F圖表示本實施例半導體功率元件單元E1製造方法的中間製程步驟圖。首先，如第3A圖所示，本實施例之半導體功率元件單元E1之製造方法包含一磊晶疊層形成步驟，首先提供基板10。基板10的材料可以是半導體材料或是氧化物材料，上述的半導體材料例如可以包含矽(Si) 、氮化鎵(GaN)、碳化矽(SiC)、砷化鎵(GaAs)等，而上述的氧化物材料例如可以包含藍寶石(sapphire)。另外，當以導電性來區分時，基板10本身可為導電基板或者是絕緣基板，上述的導電基板包含矽(Si)基板、氮化鎵(GaN)基板、砷化鎵(GaAs)等基板，而上述的絕緣基板則包含藍寶石(sapphire)、絕緣矽基板(Silicon on insulator, SOI)等基板。此外，基板10可選擇性的摻雜物質於其中，以改變其導電性，以形成導電基板或不導電基板，以矽(Si)基板而言，其摻雜物可為硼(B)或砷(As)或磷(P)。於本實施例中，基板10為導電之矽基板，厚度約為1000~1200um。Next, an intermediate process step diagram of the method of manufacturing the semiconductor power device unit E1 of the present embodiment will be described with reference to FIGS. 3A to 3F. First, as shown in FIG. 3A, the method of manufacturing the semiconductor power device unit E1 of the present embodiment includes an epitaxial layer forming step of first providing the substrate 10. The material of the substrate 10 may be a semiconductor material or an oxide material, and the semiconductor material may include, for example, germanium (Si), gallium nitride (GaN), tantalum carbide (SiC), gallium arsenide (GaAs), or the like. The oxide material may, for example, comprise sapphire. In addition, when distinguished by conductivity, the substrate 10 itself may be a conductive substrate or an insulating substrate, and the conductive substrate includes a substrate of a bismuth (Si) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs). The above insulating substrate includes a substrate such as sapphire or silicon on insulator (SOI). In addition, the substrate 10 may selectively dope a substance therein to change its conductivity to form a conductive substrate or a non-conductive substrate. For a germanium (Si) substrate, the dopant may be boron (B) or arsenic. (As) or phosphorus (P). In this embodiment, the substrate 10 is a conductive germanium substrate having a thickness of about 1000 to 1200 um.

接著，將前述的成核層20以磊晶方式成長於基板10的(111)面上，其中成核層20係沿{0001}方向成長，厚度約可為數十奈米或數百奈米，可用以減少基板10和上方半導體層之間的晶格差異。磊晶成長的方式例如為物理氣相沉積法 (physical vapor deposition, PVD)、原子層沉積法(atomic layer deposition, ALD)、金屬有機物化學氣相沉積法(metal-organic chemical vapor deposition, MOCVD)、或分子束磊晶法(molecular-beam epitaxy, MBE)。藉由成核層20可讓後續形成於其上的緩衝結構30、通道層40等半導體層的磊晶品質較佳。成核層20的材料例如是三五族半導體材料，包括氮化鋁(AlN)、氮化鎵(GaN)、氮化鋁鎵(AlGaN)等、或其混和組成的疊層，而成核層20的結構例如可以是非晶、多晶、單晶或是晶質漸變的混和層。於本實施例中，成核層20為氮化鋁層，厚度約為50~20nm，是藉由物理氣相沉積法形成，更具體而言是以濺鍍法(Sputtering)形成。Next, the nucleation layer 20 is epitaxially grown on the (111) plane of the substrate 10, wherein the nucleation layer 20 is grown in the {0001} direction and has a thickness of about several tens of nanometers or hundreds of nanometers. It can be used to reduce the lattice difference between the substrate 10 and the upper semiconductor layer. The methods of epitaxial growth are, for example, physical vapor deposition (PVD), atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), Or molecular beam epitaxy (MBE). The nucleation layer 20 allows the epitaxial quality of the semiconductor layer such as the buffer structure 30 and the channel layer 40 to be subsequently formed thereon to be better. The material of the nucleation layer 20 is, for example, a tri-five semiconductor material, including aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), or the like, or a mixture thereof, and a nucleation layer. The structure of 20 may be, for example, an amorphous, polycrystalline, single crystal or a crystalline gradient mixed layer. In the present embodiment, the nucleation layer 20 is an aluminum nitride layer having a thickness of about 50 to 20 nm, which is formed by physical vapor deposition, more specifically by sputtering.

形成成核層20之後，再以與前述相似的磊晶方式將緩衝結構30成長於成核層20的上方，緩衝結構30係用以讓後續形成於其上的通道層40與障壁層50之磊晶品質較佳，其厚度約為1um~10um。緩衝結構30可以是單層或是多層，當緩衝結構30為多層時，可包括超晶格疊層(super lattice multilayer)或兩層以上材料各不相同之交互疊層。單層或多層緩衝結構30之材料可包括三五族半導體材料，例如氮化鋁(AlN)、氮化鎵(GaN)、或氮化鋁鎵(AlGaN)等材料，並且可摻雜其他元素，例如碳(C)或是鐵(Fe)於其中，摻雜濃度可為依成長方向漸變或固定。此外，當緩衝結構30為超晶格疊層時，其可由兩層具不同材料交互堆疊之多層磊晶層所構成，其材料可為三五族半導體材料，例如是由氮化鋁層(AlN)與氮化鋁鎵層(AlGaN)交疊所構成或是由氮化鎵層(GaN)與氮化銦鎵層(InGaN) 交疊所構成，氮化鋁層與氮化鋁鎵層兩層相加的一組疊層總厚度約為2nm~30nm，而整體疊層總厚度約為1um~9um。疊層中氮化鋁層與氮化鋁鎵層的材料亦可以氮化鎵層與氮化銦鎵層置換之。After the nucleation layer 20 is formed, the buffer structure 30 is grown above the nucleation layer 20 in a similar epitaxial manner as described above, and the buffer structure 30 is used to allow the channel layer 40 and the barrier layer 50 subsequently formed thereon. The epitaxial quality is better, and its thickness is about 1um~10um. The buffer structure 30 may be a single layer or a plurality of layers. When the buffer structure 30 is a plurality of layers, it may include a super lattice multilayer or an alternating stack of two or more layers of materials. The material of the single-layer or multi-layer buffer structure 30 may include a group of three or five semiconductor materials, such as aluminum nitride (AlN), gallium nitride (GaN), or aluminum gallium nitride (AlGaN), and may be doped with other elements. For example, carbon (C) or iron (Fe) may be used, and the doping concentration may be gradual or fixed depending on the growth direction. In addition, when the buffer structure 30 is a superlattice laminate, it may be composed of two layers of epitaxial layers stacked with different materials, and the material thereof may be a group of three or five semiconductor materials, for example, an aluminum nitride layer (AlN). ) formed by overlapping with an aluminum gallium nitride layer (AlGaN) or composed of a gallium nitride layer (GaN) and an indium gallium nitride layer (InGaN), and an aluminum nitride layer and an aluminum gallium nitride layer. The total thickness of the added stack is about 2 nm to 30 nm, and the total thickness of the overall laminate is about 1 um to 9 um. The material of the aluminum nitride layer and the aluminum gallium nitride layer in the stack may also be replaced by a gallium nitride layer and an indium gallium nitride layer.

於緩衝結構30形成之後，再以與前述相似的磊晶方式形成通道層40及障壁層50於緩衝結構30之上，通道層40的厚度範圍例如在50~300nm，形成於緩衝結構30之上，並具有一第一能隙。障壁層50的厚度範圍例如在20~50nm，形成在通道層40之上，並具有一第二能隙，而第二能隙較第一能隙高，且障壁層50之晶格常數比通道層40小。在本實施例中，通道層40的材料包含例如氮化銦鎵(In_x Ga_(1-x) N)，0≦x＜1，障壁層50包含氮化鋁銦鎵(Al_y In_z Ga_(1-y-z) N)，0＜y＜1，0≦z＜1。通道層40自身以及障壁層50自身形成自發性極化(spontaneous polarization)，而障壁層50與通道層40彼此之間又因通道層40與下方磊晶疊層中各層之間不同晶格常數相互作用的總和對上層障壁層50產生壓電極化(piezoelectric polarization)，進而在通道層40及障壁層50間的異質接面產生二維電子氣層(以虛線表示於圖中)。於本實施例中，通道層40及障壁層50的材料例如可為無摻雜其他元素的本質性半導體，但亦可以視元件特性摻雜其他元素。例如可摻雜元素矽(Si)於其中，以摻雜的元素濃度調整二維電子氣層的濃度，完成後的製程中間結構如第3A圖所示。After the buffer structure 30 is formed, the channel layer 40 and the barrier layer 50 are formed on the buffer structure 30 in an epitaxial manner similar to the foregoing. The channel layer 40 has a thickness ranging, for example, from 50 to 300 nm, and is formed on the buffer structure 30. And has a first energy gap. The barrier layer 50 has a thickness in the range of, for example, 20 to 50 nm, formed on the channel layer 40, and has a second energy gap, and the second energy gap is higher than the first energy gap, and the lattice constant ratio of the barrier layer 50 is larger than that of the channel layer 50. Layer 40 is small. In the present embodiment, the material of the channel layer 40 comprises, for example, indium gallium nitride (In _x Ga _(1-x) N), 0 ≦ x < 1, and the barrier layer 50 comprises aluminum indium gallium nitride (Al _y In _z Ga _(1-yz) N), 0 < y < 1, 0 ≦ z < 1. The channel layer 40 itself and the barrier layer 50 themselves form a spontaneous polarization, and the barrier layer 50 and the channel layer 40 are mutually different from each other due to different lattice constants between the channel layer 40 and the layers in the lower epitaxial layer. The sum of the effects produces piezoelectric polarization on the upper barrier layer 50, and a two-dimensional electron gas layer is formed on the heterojunction between the channel layer 40 and the barrier layer 50 (shown in phantom in the figure). In the present embodiment, the material of the channel layer 40 and the barrier layer 50 may be, for example, an intrinsic semiconductor without other elements, but other elements may be doped depending on the characteristics of the element. For example, the element cerium (Si) may be doped therein, and the concentration of the two-dimensional electron gas layer is adjusted by the doping element concentration, and the completed process intermediate structure is as shown in FIG. 3A.

於形成通道層40及障壁層50之後即完成磊晶疊層形成步驟，接著再於障壁層50上形成圖案化的暫時性遮罩層50’。於本實施例中，如第3B圖所示，於形成障壁層50後，先於障壁層50表面形成一層原生(in situ)的原生氮化矽層504。原生氮化矽層504在本實施例中係與障壁層50於相同的製程機台中形成，可以作為暫時性遮罩層50’的第一部分，也同時可用以存在於障壁層50表面做為後續製程的護層。接著，如第3C圖所示，於原生氮化矽層504的表面相對應於後續閘極電極90的位置形成圖案化光阻90’。接著，再如第3D圖所示，於圖案化光阻90’存在下形成第二層外生氮化矽層505做為暫時性遮罩層50’的第二部分。接著移除圖案化光阻90’，便完成如第3D圖所示，由殘留的第二層外生氮化矽層505以及原生氮化矽層504所組合而成的暫時性遮罩層50’的結構。暫時性遮罩層50’例如以與前述磊晶疊層形成步驟相似的磊晶成長方式於相同的磊晶機台中形成，或是分別於不同的機台另外形成。而暫時性遮罩層50’的材料例如可以是氮化矽(SiN_x )、氧化矽(SiO₂ )、氮氧化矽(SiON)、氧化鋁(Al₂ O₃ )等介電層，但並不以此為限，亦可以是由不同的介電層形成的混和疊層。After the formation of the channel layer 40 and the barrier layer 50, the epitaxial layer formation step is completed, and then the patterned temporary mask layer 50' is formed on the barrier layer 50. In the present embodiment, as shown in FIG. 3B, after the barrier layer 50 is formed, a layer of native native tantalum nitride layer 504 is formed on the surface of the barrier layer 50. The native tantalum nitride layer 504 is formed in the same process machine as the barrier layer 50 in this embodiment, and can be used as the first portion of the temporary mask layer 50', and can also be used as the surface of the barrier layer 50 as a follow-up. The protective layer of the process. Next, as shown in FIG. 3C, a patterned photoresist 90' is formed at a position of the surface of the native tantalum nitride layer 504 corresponding to the subsequent gate electrode 90. Next, as shown in FIG. 3D, a second layer of exogenous tantalum nitride layer 505 is formed as a second portion of the temporary mask layer 50' in the presence of the patterned photoresist 90'. Then, the patterned photoresist 90' is removed, and the temporary mask layer 50 composed of the remaining second layer of exogenous tantalum nitride layer 505 and the native tantalum nitride layer 504 is completed as shown in FIG. 3D. 'Structure. The temporary mask layer 50' is formed in the same epitaxial machine stage, for example, in an epitaxial growth mode similar to the above-described epitaxial layer formation step, or separately formed on different machine stages. The material of the temporary mask layer 50' may be, for example, a dielectric layer such as tantalum nitride (SiN _x ), yttrium oxide (SiO ₂ ), lanthanum oxynitride (SiON), or aluminum oxide (Al ₂ O ₃ ). Not limited thereto, it may also be a mixed laminate formed of different dielectric layers.

在形成圖案化的暫時性遮罩層50’後，接著進行鎂佈植製程，如第3E圖中所示，在此先將不要佈植鎂的障壁層50上方區域，即相對應於後續要生成源極電極70及汲極電極80的位置區域上方，以一厚膜光阻100分別進行圖案化的保護後，透過暫時性遮罩層50’以一次性地佈植製程將鎂植入障壁層50中。在這邊，厚膜光阻100也可被視為一暫時性遮罩層，於該次佈植的製程中對植入障壁層50中的鎂佈植特徵產生調控的效果。值得注意的是，在此使用厚膜光阻100的用意是藉由厚膜光阻100的厚度來避免鎂佈植於障壁層50中相對應於厚膜光阻100下方的位置，即鎂不佈植於相對應於後續生成源極電極70及汲極電極80區域的障壁層50位置。然而，本領域具有通常知識者可以了解，本揭露並不以此實施例為限，也可因不同元件功能需求，透過減薄厚膜光阻100的厚度使鎂佈植特徵可調整地植入其下方的障壁層50中。After forming the patterned temporary mask layer 50', the magnesium implantation process is followed, as shown in FIG. 3E, where the area above the barrier layer 50 of magnesium is not implanted first, that is, corresponding to the subsequent Above the positional region where the source electrode 70 and the drain electrode 80 are formed, after a thick film photoresist 100 is patterned and protected, the magnesium is implanted into the barrier through the temporary mask layer 50' in a one-time implantation process. In layer 50. Here, the thick film photoresist 100 can also be regarded as a temporary mask layer, which exerts a regulating effect on the magnesium implant features implanted in the barrier layer 50 during the implantation process. It should be noted that the use of the thick film photoresist 100 is intended to prevent the magnesium from being implanted in the barrier layer 50 corresponding to the position below the thick film photoresist 100 by the thickness of the thick film photoresist 100, that is, magnesium is not The implant is placed at a position corresponding to the barrier layer 50 in the region where the source electrode 70 and the drain electrode 80 are subsequently formed. However, those skilled in the art will appreciate that the present disclosure is not limited to this embodiment, and that the magnesium implant feature can be implantably adjusted by thinning the thickness of the thick film photoresist 100 due to the functional requirements of different components. In the lower barrier layer 50.

完成鎂佈植製程後，再移除厚膜光阻100以及暫時性遮罩層50’，其結構將如如第3F圖所示。由於圖案化的暫時性遮罩層50’於不同位置會具有不同的厚度，在一次性使用相同能量的鎂佈植製程中，會使相對應位於不同厚度的暫時性遮罩層50’下被鎂佈植的區域具有不同的鎂佈植特徵，例如是鎂植入的平均佈植濃度、平均佈植深度、最高鎂佈植濃度、或最大鎂佈植深度等，並不以本實施例為限。以本實施例為例，由於暫時性遮罩層50’位於相對應於後續閘極電極90位置下方的厚度(只具有原生氮化矽層504)較位於後續源極電極70與閘極電極90間及位於後續汲極電極80與閘極電極90間的厚度(同時具有原生氮化矽層504及外生氮化矽層505)薄，因此在一次性的鎂佈植製程後，於障壁層50內部會形成具有兩種不同鎂佈植特徵的區域。第一區域501相對應於後續閘極電極90位置的下方，具有較高的最高鎂佈植濃度、較深的鎂佈植深度等；第二區域502所包含的子區域5021及5022分別位於相對應於源極電極70與閘極電極90之間、及汲極電極80與閘極電極90之間的位置，具有比第一區域501低的鎂平均佈植濃度、較小的鎂平均佈植深度等。而被厚膜光阻100所遮蓋的區域則實質上沒有鎂佈植。After the magnesium implantation process is completed, the thick film photoresist 100 and the temporary mask layer 50' are removed, and the structure will be as shown in Fig. 3F. Since the patterned temporary mask layer 50' will have different thicknesses at different positions, in the magnesium implantation process using the same energy at one time, the temporary mask layer 50' corresponding to different thicknesses will be correspondingly The magnesium implanted areas have different magnesium implant characteristics, such as the average implant concentration of the magnesium implant, the average implant depth, the highest magnesium implant concentration, or the maximum magnesium implant depth, etc., and are not in this embodiment. limit. Taking this embodiment as an example, since the temporary mask layer 50' is located below the position corresponding to the position of the subsequent gate electrode 90 (having only the native tantalum nitride layer 504), it is located at the subsequent source electrode 70 and the gate electrode 90. And the thickness between the subsequent gate electrode 80 and the gate electrode 90 (both with the native tantalum nitride layer 504 and the exogenous tantalum nitride layer 505) is thin, so after the disposable magnesium cloth implantation process, in the barrier layer The interior of 50 will form an area with two different magnesium implant features. The first region 501 corresponds to the lower position of the subsequent gate electrode 90, has a higher highest magnesium implant concentration, a deeper magnesium implant depth, and the like; the second region 502 includes sub-regions 5021 and 5022 respectively located at the phase Corresponding to the position between the source electrode 70 and the gate electrode 90 and between the gate electrode 80 and the gate electrode 90, the average magnesium implant concentration is lower than the first region 501, and the average magnesium implant is smaller. Depth and so on. The area covered by the thick film photoresist 100 is substantially free of magnesium implants.

接著，於障壁層50上方分別形成源極電極70、汲極電極80與閘極電極90以作為與外部電性連接的端點。其中源極電極70、汲極電極80分別位於障壁層50的兩端，而閘極電極90則位於源極電極70與汲極電極80之間。在本實施例中，可以藉由選擇適當的源極電極70與汲極電極80的材料，以及/或者藉由製程(如，熱退火)以使源極電極70與汲極電極80和障壁層50之間形成歐姆接觸。類似地，也可藉由選擇適當的閘極電極90的材料，使得閘極電極90與障壁層50間形成蕭特基接觸或歐姆接觸。源極電極70、汲極電極80的材料可以選自鈦(Ti)、鋁(Al)，閘極電極90的材料可以選自鎳(Ni)、金(Au)、鎢(W)、氮化鈦(TiN)。Next, a source electrode 70, a drain electrode 80, and a gate electrode 90 are formed over the barrier layer 50 as end points electrically connected to the outside. The source electrode 70 and the drain electrode 80 are respectively located at two ends of the barrier layer 50 , and the gate electrode 90 is located between the source electrode 70 and the drain electrode 80 . In this embodiment, the source electrode 70 and the drain electrode 80 and the barrier layer can be made by selecting the appropriate source electrode 70 and the material of the drain electrode 80, and/or by a process such as thermal annealing. An ohmic contact is formed between 50. Similarly, Schottky or ohmic contact can be formed between the gate electrode 90 and the barrier layer 50 by selecting the material of the appropriate gate electrode 90. The material of the source electrode 70 and the drain electrode 80 may be selected from titanium (Ti) and aluminum (Al), and the material of the gate electrode 90 may be selected from nickel (Ni), gold (Au), tungsten (W), and nitride. Titanium (TiN).

最後，如第2B圖所示，於形成電極後，形成保護層60覆蓋於包含有源極電極70、汲極電極80與閘極電極90的半導體功率元件單元E1整體表面，接著再蝕刻部分保護層60，以露出部分源極電極70、汲極電極80與閘極電極90，即源極電極70、汲極電極80與閘極電極90有一部份表面未被保護層60所覆蓋，以提供元件與外界電性連接的區域，便完成如前述第2B圖所示之半導體功率元件單元E1的結構。保護層60係用以防止障壁層50的電性受到影響。其中，保護層60可以是氧化物或者氮化物或者氮氧化物，如氧化矽或氧化鋁等氧化物，也可以是氮化矽或氮化鎵等氮化物，或氮氧化矽等氮氧化物。於另一實施例中，半導體功率元件單元亦可不包含保護層60 。Finally, as shown in FIG. 2B, after forming the electrode, the protective layer 60 is formed to cover the entire surface of the semiconductor power device unit E1 including the source electrode 70, the gate electrode 80 and the gate electrode 90, and then partially etched. The layer 60 exposes a portion of the source electrode 70, the drain electrode 80 and the gate electrode 90, that is, a portion of the surface of the source electrode 70, the drain electrode 80 and the gate electrode 90 is not covered by the protective layer 60 to provide The area of the semiconductor power element unit E1 as shown in the aforementioned FIG. 2B is completed in the region where the element is electrically connected to the outside. The protective layer 60 serves to prevent the electrical properties of the barrier layer 50 from being affected. The protective layer 60 may be an oxide or a nitride or an oxynitride such as an oxide such as ruthenium oxide or aluminum oxide, or a nitride such as tantalum nitride or gallium nitride, or an oxynitride such as ruthenium oxynitride. In another embodiment, the semiconductor power device unit may also not include the protective layer 60.

此外，在形成源極電極70、汲極電極80與閘極電極90之前，也可以選擇性地於源極電極70與汲極電極80間形成如介電層(圖未示)或氮化鎵帽層(圖未示)於障壁層50的上表面之上，用以維持障壁層50上表面的品質，並減少障壁層50的上表面因氧化產生的缺陷影響元件操作性能的可能。當介電層或氮化鎵帽層位於閘極電極90的下方時，能進一步降低閘極電極90的漏電流，更可提高閘極電極90操作偏壓範圍，提升元件可靠度。介電層例如是氮化矽或氮化鎵等氮化物、氧化鋁或氧化矽等氧化物、氮氧化矽等氮氧化物材料或其組合。然而本發明不以此為限，於其他實施例中亦可不形成介電層或氮化鎵帽層。In addition, before forming the source electrode 70, the drain electrode 80 and the gate electrode 90, a dielectric layer (not shown) or gallium nitride may be selectively formed between the source electrode 70 and the gate electrode 80. A cap layer (not shown) is disposed on the upper surface of the barrier layer 50 to maintain the quality of the upper surface of the barrier layer 50 and to reduce the possibility that the upper surface of the barrier layer 50 may affect the operational performance of the component due to defects caused by oxidation. When the dielectric layer or the gallium nitride cap layer is located under the gate electrode 90, the leakage current of the gate electrode 90 can be further reduced, and the operating bias range of the gate electrode 90 can be further improved to improve the reliability of the device. The dielectric layer is, for example, a nitride such as tantalum nitride or gallium nitride, an oxide such as alumina or ruthenium oxide, or an oxynitride material such as ruthenium oxynitride or a combination thereof. However, the invention is not limited thereto, and in other embodiments, a dielectric layer or a gallium nitride cap layer may not be formed.

如第4A圖至第4C圖所示，顯示為模擬本揭露第一實施例結構於一次鎂佈植製程後，移除厚膜光阻100之前如第4D圖所示的中間結構I1剖面示意圖中，在標示之區域A1、B1、C1處鎂分佈特徵模擬圖。如圖中所示，區域A1包含部分暫時性遮罩層50’、第一區域501、及部分未被佈植的障壁層50，區域B1包含部分暫時性遮罩層50’、部份第二區域502、及部分未被佈植的障壁層50，區域C1包含部分厚膜光阻100。其中，圖中的橫軸座標所代表的是鎂佈植的深度，深度的位置自中間結構I1的表面開始垂直向下計算，深度單位為奈米(nm)，於區域A1、B1是自暫時性遮罩層50’表面，於區域C1則是自厚膜光阻100表面開始計算；而圖中的縱軸座標所代表的是鎂的佈植濃度，以每立方公分鎂的個數為單位(counts/cm³ ) 。在此值得注意的是，由於當鎂佈植於半導體層內後，可能會改變其特性，以離子、原子、錯合物等狀態存在於半導體層內。因此，在本發明中所指的鎂佈植濃度，係指以二次離子質譜儀(Secondary Ion Mass Spectrometry, SIMS)對元件半導體層進行量測後可測得的鎂濃度，並不以離子狀態為限。As shown in FIG. 4A to FIG. 4C, it is shown in the cross-sectional schematic view of the intermediate structure I1 shown in FIG. 4D before the removal of the thick film photoresist 100 after the first embodiment is constructed. , a simulation map of magnesium distribution characteristics at the marked areas A1, B1, and C1. As shown in the figure, the area A1 includes a partial temporary mask layer 50', a first area 501, and a portion of the unimplanted barrier layer 50. The area B1 includes a portion of the temporary mask layer 50' and a portion of the second layer. A region 502, and a portion of the barrier layer 50 that is not implanted, the region C1 includes a portion of the thick film photoresist 100. Among them, the horizontal axis coordinates in the figure represent the depth of the magnesium planting, and the depth position is calculated vertically from the surface of the intermediate structure I1, the depth unit is nanometer (nm), and the regions A1 and B1 are self-temporary. The surface of the mask layer 50' is calculated from the surface of the thick film photoresist 100 in the region C1; the vertical axis coordinates in the figure represent the concentration of magnesium implanted in units of magnesium per cubic centimeter. (counts/cm ³ ). It is worth noting here that since the magnesium cloth may be changed in its characteristics after being implanted in the semiconductor layer, it may exist in the semiconductor layer in the state of ions, atoms, and complexes. Therefore, the magnesium implant concentration referred to in the present invention refers to the magnesium concentration which can be measured by measuring the element semiconductor layer by a secondary ion mass spectrometer (SIMS), and is not in an ion state. Limited.

於本實施例中，暫時性遮罩層50’的材料為氮化矽，相對應於第一區域501的暫時性遮罩層50’厚度設定為10奈米、相對應於第二區域502的暫時性遮罩層50’厚度設定為22奈米、於其上的厚膜光阻100厚度為0.2微米、障壁層50的厚度為25奈米。在鎂佈植的能量9KeV，佈植傾角為7度的條件下，可以發現於一次鎂佈植製程後，於區域A1中，第一區域501鎂之分佈狀況如第4A圖所示，由於區域A1的暫時性遮罩層50’的厚度較薄，於本實施例中例如為10奈米的氮化矽，因而於第一區域501中，會有一鎂佈植深度，於本實施例中為自暫時性遮罩層50’至障壁層50總深度35奈米。且在障壁層50第一區域501中鎂佈植淨深度為20奈米，未被佈植的障壁層50厚度約為5奈米，且於障壁層50第一區域501中，在鄰近暫時性遮罩層50’處有一最高鎂佈植濃度，於本實施例中例如約為8x10⁵ counts/cm³ ；於區域B1中，第二區域502鎂之分佈狀況如第4B圖所示，由於上方的暫時性遮罩層50’的厚度較厚，於本實施例中例如為22奈米的氮化矽；因而第二區域502中會有一較第一區域501的鎂佈植深度小的鎂佈植深度，於本實施例中為自暫時性遮罩層50’至障壁層50總深度37奈米。且在障壁層50中鎂佈植淨深度為15奈米，未被佈植的障壁層50厚度約為10奈米，且於障壁層50第二區域502中，鄰近暫時性遮罩層50’處，具有一最高鎂佈植濃度，但此處的最高鎂佈植濃度較第一區域501的最高鎂佈植濃度低，於本實施例中例如為2x10⁵ counts/cm³ ；而相對應於厚膜光阻100下方的位置，也就是於第4D圖結構中區域C1的位置，鎂之分佈狀況如第4C圖所示，此區域的鎂皆停留於厚膜光阻100內，並未被佈植入障壁層50內。In the present embodiment, the material of the temporary mask layer 50' is tantalum nitride, and the thickness of the temporary mask layer 50' corresponding to the first region 501 is set to 10 nm, corresponding to the second region 502. The thickness of the temporary mask layer 50' was set to 22 nm, the thickness of the thick film photoresist 100 thereon was 0.2 μm, and the thickness of the barrier layer 50 was 25 nm. Under the condition that the energy of the magnesium cloth is 9KeV and the inclination angle of the planting is 7 degrees, it can be found that in the area A1, the distribution of magnesium in the first region 501 is as shown in Fig. 4A, due to the area of the magnesium implantation process. The thickness of the temporary mask layer 50' of A1 is relatively thin, and is, for example, 10 nm of tantalum nitride in this embodiment, so that in the first region 501, there is a magnesium implantation depth, which is in this embodiment. The total depth from the temporary mask layer 50' to the barrier layer 50 is 35 nm. And in the first region 501 of the barrier layer 50, the implantation depth of the magnesium cloth is 20 nm, the thickness of the unshielded barrier layer 50 is about 5 nm, and in the first region 501 of the barrier layer 50, adjacent to the temporary The mask layer 50' has a maximum magnesium implant concentration, which is, for example, about 8× ^{10 5} counts/cm ³ in the embodiment; in the region B1, the distribution of the second region 502 magnesium is as shown in FIG. 4B, due to the upper portion. The thickness of the temporary mask layer 50' is relatively thick, and is, for example, 22 nm of tantalum nitride in this embodiment; thus, the second region 502 has a magnesium cloth having a smaller magnesium implantation depth than the first region 501. The depth of the implant, in this embodiment, is from the temporary mask layer 50' to the total depth of the barrier layer 50 of 37 nm. And the magnesium cloth has a clear depth of 15 nm in the barrier layer 50, the unshielded barrier layer 50 has a thickness of about 10 nm, and in the second layer 502 of the barrier layer 50, adjacent to the temporary mask layer 50' Where, there is a highest magnesium implant concentration, but the highest magnesium implant concentration here is lower than the highest magnesium implant concentration of the first region 501, which is, for example, 2x10 ⁵ counts/cm ³ in the present embodiment; The position under the thick film photoresist 100, that is, the position of the region C1 in the structure of the 4D, the distribution of magnesium is as shown in FIG. 4C, and the magnesium in this region stays in the thick film photoresist 100, and is not The cloth is implanted in the barrier layer 50.

第5A圖顯示為本揭露一第二實施例之半導體功率元件單元E2的剖面示意圖。由於本實施例與第一實施例間除了鎂佈植條件外其餘結構皆相同，因此，除第一區域及第二區域外，其餘結構皆以相同標號表示，在此不再贅述。如第5B圖及第5C圖所示，其分別顯示在第5A圖中半導體功率元件單元E2標示之區域B’及區域A’處的能帶模擬圖。區域B’及區域A’皆包含自通道層40表面向下延伸的區域。如第5B圖至第5C圖的能帶模擬圖所示，圖中的橫軸座標所代表的是深度，深度的位置自通道層40的表面開始垂直向下計算，深度單位為奈米(nm)；而圖中的縱軸座標所代表的是能量，以電子伏特(eV)單位，E_c 為電子傳導帶能階，E_f 為費米能階，E_v 為電子價帶能階。由圖中的模擬結果可顯示，在一般的鎂佈植製程條件下，當鎂佈植濃度例如為1x10¹⁸ counts/cm³ ~1x10²⁰ counts/cm³ ，可達成半導體功率元件單元E2為一常關型高電子遷移率電晶體。如本實施例中的模擬結果所示，在本實施例中，障壁層50的厚度為25奈米，而鎂的佈植結果設定如下：於第一區域501’的最高鎂佈植深度為15奈米，鎂起始佈植濃度設定為1x10¹⁹ counts/cm³ ，假定鎂活化率為3%時(一般活化率例如為3-5%)，則於第一區域501’中鎂的活化濃度最高則例如為3x10¹⁷ -5x10¹⁷ counts/cm³ ，而相對應於第一區域501’下剩餘未被佈植的障壁層50厚度則為10奈米；於第二區域502’ (包含子區域5021’及5022’)的最高鎂佈植深度為5奈米，佈植濃度的條件設定為與第一區域501’相同，約為1x10¹⁹ counts/cm³ ；假定鎂活化率為3%時(一般活化率例如為3-5%)，則於第二區域502’中鎂的活化濃度最高則例如為3x10¹⁷ -5x10¹⁷ counts/cm³ ，而相對應於第二區域502’下剩餘未被佈植的障壁層50厚度為20奈米。能帶模擬圖結果如第5B圖所示，當於閘極電極90施加0伏特電壓時，相對應於第5A圖區域B’中，因鎂最終佈植深度相對於區域A’來得低，因此區域B’內鄰近障壁層50及通道層40間仍具有二維電子氣層存在(電子傳導帶能階E_c 的最低位置低於費米能階E_f )；於相同條件下，相對應於區域A’的能帶模擬圖則如第5C圖所示，因具有較大的鎂佈植深度，鄰近障壁層50及通道層40間的二維電子氣層已經被耗盡(電子傳導帶能階E_c 的最低位置高於費米能階E_f )。FIG. 5A is a cross-sectional view showing a semiconductor power device unit E2 according to a second embodiment of the present disclosure. The structure of the present embodiment is the same as the first embodiment except for the first region and the second region, and the rest of the structures are denoted by the same reference numerals and will not be described again. As shown in FIGS. 5B and 5C, the energy band simulations at the region B' and the region A' indicated by the semiconductor power device unit E2 in FIG. 5A are respectively shown. Both the region B' and the region A' include regions extending downward from the surface of the channel layer 40. As shown in the energy band simulation diagrams of FIGS. 5B to 5C, the horizontal axis coordinates in the figure represent the depth, and the depth position is calculated vertically from the surface of the channel layer 40, and the depth unit is nanometer (nm). The vertical axis coordinates in the figure represent energy, in electron volts (eV) units, E _c is the electron conduction band energy level, E _f is the Fermi energy level, and E _v is the electron valence band energy level. From the simulation results in the figure, it can be shown that under the general magnesium cloth processing conditions, when the magnesium implantation concentration is, for example, 1×10 ¹⁸ counts/cm ³ to 1×10 ²⁰ counts/cm ³ , the semiconductor power component unit E2 can be achieved as a common Off-type high electron mobility transistors. As shown by the simulation results in this embodiment, in the present embodiment, the thickness of the barrier layer 50 is 25 nm, and the implantation result of magnesium is set as follows: the highest magnesium implantation depth in the first region 501' is 15 Nano, magnesium initial implant concentration is set to 1x10 ¹⁹ counts / cm ³ , assuming magnesium activation rate of 3% (general activation rate is, for example, 3-5%), then the activation concentration of magnesium in the first region 501 ' The highest is, for example, 3x10 ¹⁷ -5x10 ¹⁷ counts/cm ³ , and the thickness of the barrier layer 50 remaining unimplanted corresponding to the first region 501' is 10 nm; and the second region 502' (including the sub-region) The highest magnesium implant depth of 5021' and 5022') is 5 nm, and the implantation concentration is set to be the same as the first region 501', about 1 x 10 ¹⁹ counts/cm ³ ; assuming that the magnesium activation rate is 3% ( Generally, the activation rate is, for example, 3-5%), and the highest activation concentration of magnesium in the second region 502' is, for example, 3×10 ¹⁷ -5×10 ¹⁷ counts/cm ³ , and the remaining portion corresponding to the second region 502 ′ is not. The implanted barrier layer 50 has a thickness of 20 nm. The energy band simulation result is as shown in FIG. 5B. When the voltage of 0 volt is applied to the gate electrode 90, the final implantation depth of magnesium is lower than that of the region A' corresponding to the region B' of the 5A map. There is still a two-dimensional electron gas layer between the adjacent barrier layer 50 and the channel layer 40 in the region B' (the lowest position of the electron conduction band energy level E _c is lower than the Fermi energy level E _f ); under the same conditions, corresponding to The energy band simulation of the area A' is as shown in Fig. 5C. Because of the large magnesium implantation depth, the two-dimensional electron gas layer between the adjacent barrier layer 50 and the channel layer 40 has been depleted (electron conduction band energy) The lowest position of the order E _c is higher than the Fermi level E _f ).

於本揭露的兩個實施例中，由於半導體功率元件單元E1及E2中的障壁層50具有以鎂進行淺層佈植的第二區域502(502’)，當對閘極電極90施加正電壓，在元件進行順向導通操作(即對汲極電極80相對應於源極電極70施加高電壓；V_DS ＞0)時，在佈植有鎂的障壁層50表面便會形成一個通道，使障壁層50表面因為缺陷或其他原因被捕捉的多餘電子會順向流入閘極電極90再被導出。後續，於元件重複操作時或高壓操作時，可減少因缺陷造成電子被捕捉造成元件導通電流時產生的電流下降。即，可以改善因電流崩潰(current collapse)現象導致的元件輸出功率降低的問題。In the two embodiments of the present disclosure, since the barrier layer 50 in the semiconductor power device units E1 and E2 has the second region 502 (502') which is shallowly implanted with magnesium, when a positive voltage is applied to the gate electrode 90 When the component performs a forward conduction operation (ie, a high voltage is applied to the drain electrode 80 corresponding to the source electrode 70; V _DS >0), a channel is formed on the surface of the barrier layer 50 on which the magnesium is implanted, so that a channel is formed. Excess electrons trapped on the surface of the barrier layer 50 due to defects or other reasons may flow into the gate electrode 90 and be led out. Subsequently, during repeated operation of the component or during high-voltage operation, the current drop caused by the electron trapped by the defect caused by the conduction current of the component can be reduced. That is, it is possible to improve the problem that the output power of the element is lowered due to the current collapse phenomenon.

除此之外，在元件進行反向操作(即對源極電極70相對應於汲極電極80施加高電壓；V_DS ＜0)時，被淺佈植的第二區域502(502’)會產生擴張的空乏區，可以抑制元件漏電流以達到提高元件崩潰電壓的效果。In addition, when the component is reverse operated (ie, a high voltage is applied to the source electrode 70 corresponding to the gate electrode 80; V _DS <0), the second region 502 (502') that is shallowly implanted will The expansion of the depletion zone can suppress the component leakage current to achieve the effect of increasing the component breakdown voltage.

接著，請參閱第6A圖及第6B圖所示本揭露第三實施例之一半導體功率元件單元E3的結構。半導體功率元件單元E3之上視圖和半導體功率元件單元E1相同，半導體功率元件S中的半導體功率元件單元E1可由半導體功率元件單元E3置換之。為了清楚說明半導體功率元件單元E3的細部結構，第6A圖繪示了半導體功率元件單元E3之局部放大上視示意圖，而第6B圖繪示了第6A圖沿剖線GG’之剖面示意圖。半導體功率元件單元E3例如為又一種常關型高電子遷移率電晶體，包括一基板310、一成核層320、一緩衝結構330、一通道層340、一障壁層350、一保護層360、一帽層3605、一源極電極370、一汲極電極380、一閘極電極390。其中，成核層320與緩衝結構330依序位於基板310的上方；通道層340具有第一能隙，且位於緩衝結構330上方；障壁層350位於通道層340上方，具有第二能隙，且第二能隙大於第一能隙；帽層3605位於障壁層350上方；障壁層350及帽層3605包含具有第一鎂佈植特徵的第一區域3501，位置相對應於閘極電極390的下方；以及具有第二鎂佈植特徵的第二區域3502，而第二區域又包含子區域35021及35022，其位置分別相對應於源極電極370與閘極電極390之間的下方以及汲極電極380與閘極電極390之間的下方；保護層360則配置於源極電極370與閘極電極390之間以及汲極電極380與閘極電極390之間。此外，第一區域3501分別與第二區域3502所包含的子區域35021及35022相連接，而於第一區域3501中的第一鎂佈植特徵大於於第二區域3502中的第二鎂佈植特徵。於本實施例中，鎂佈植特徵例如是最高鎂佈植濃度及/或最大鎂佈植深度等物理性特徵，詳細內容將於後續進行描述。Next, please refer to the structure of the semiconductor power device unit E3 of the third embodiment of the present disclosure shown in FIGS. 6A and 6B. The upper view of the semiconductor power element unit E3 is the same as the semiconductor power element unit E1, and the semiconductor power element unit E1 in the semiconductor power element S can be replaced by the semiconductor power element unit E3. In order to clearly illustrate the detailed structure of the semiconductor power device unit E3, FIG. 6A is a partially enlarged top view of the semiconductor power device unit E3, and FIG. 6B is a cross-sectional view taken along line GG' of FIG. 6A. The semiconductor power device unit E3 is, for example, another normally-off type high electron mobility transistor, and includes a substrate 310, a nucleation layer 320, a buffer structure 330, a channel layer 340, a barrier layer 350, and a protective layer 360. A cap layer 3605, a source electrode 370, a drain electrode 380, and a gate electrode 390. The nucleation layer 320 and the buffer structure 330 are sequentially located above the substrate 310; the channel layer 340 has a first energy gap and is located above the buffer structure 330; the barrier layer 350 is located above the channel layer 340, and has a second energy gap, and The second energy gap is greater than the first energy gap; the cap layer 3605 is located above the barrier layer 350; the barrier layer 350 and the cap layer 3605 comprise a first region 3501 having a first magnesium implant feature, the position corresponding to the lower side of the gate electrode 390 And a second region 3502 having a second magnesium implant feature, and the second region further includes sub-regions 35021 and 35022, the positions of which correspond to the lower portion between the source electrode 370 and the gate electrode 390 and the drain electrode, respectively. The lower side between the 380 and the gate electrode 390; the protective layer 360 is disposed between the source electrode 370 and the gate electrode 390 and between the drain electrode 380 and the gate electrode 390. In addition, the first region 3501 is connected to the sub-regions 35021 and 35022 included in the second region 3502, respectively, and the first magnesium implant feature in the first region 3501 is greater than the second magnesium implant in the second region 3502. feature. In the present embodiment, the magnesium implant characteristics are, for example, physical characteristics such as the highest magnesium implant concentration and/or the maximum magnesium implant depth, and the details will be described later.

由於本實施例的製程步驟與前述半導體功率元件單元E1相似，於相同的製程步驟部分在此便不多加贅述。不同的是，於本實施例中，於完成障壁層350後，可以利用物理氣相沉積磊晶法 (physical vapor deposition, PVD)、原子層沉積法(atomic layer deposition, ALD)、金屬有機物化學氣相沉積法(metal-organic chemical vapor deposition, MOCVD)、或分子束磊晶法(molecular-beam epitaxy, MBE)將帽層3605成長於障壁層350上方。於本實施例中，帽層3605大致覆蓋障壁層350之表面，避免障壁層350因氧化等反應而產生表面劣化，並可以改善表面漏電流現象。於本實施例中，帽層3605例如為未摻雜氮化鎵(u-GaN)半導體層。值得注意的是，為了使後續成長的電極結構(源極電極370、汲極電極380、閘極電極390)與障壁層350間維持良好的電性接觸，帽層3605較佳的厚度為1~2奈米之間，以使電子可於帽層3605間穿隧通過。Since the process steps of the present embodiment are similar to those of the foregoing semiconductor power device unit E1, the description of the same process steps will not be repeated here. The difference is that, in this embodiment, after the barrier layer 350 is completed, physical vapor deposition (PVD), atomic layer deposition (ALD), metal organic chemical gas can be utilized. The cap layer 3605 is grown above the barrier layer 350 by metal-organic chemical vapor deposition (MOCVD) or molecular-beam epitaxy (MBE). In the present embodiment, the cap layer 3605 substantially covers the surface of the barrier layer 350, avoiding surface deterioration of the barrier layer 350 due to oxidation or the like, and improving surface leakage current. In the present embodiment, the cap layer 3605 is, for example, an undoped gallium nitride (u-GaN) semiconductor layer. It should be noted that in order to maintain good electrical contact between the subsequently grown electrode structure (source electrode 370, drain electrode 380, gate electrode 390) and barrier layer 350, cap layer 3605 preferably has a thickness of 1~ Between 2 nm, so that electrons can pass through the cap layer 3605.

參考第7A圖至第7D圖，第7D圖為本揭露第三實施例之半導體功率元件單元E3於一次鎂佈植製程後，移除厚膜光阻3100之前的一中間結構I2的剖面示意圖；第7A圖至第7C圖顯示為模擬本揭露第7D圖所示的中間結構I2中標示之區域A2、B2、C2處鎂分佈特徵模擬圖。區域A2包含部分暫時性遮罩層350’、部分帽層3605、第一區域3501、及部分未被佈植的障壁層350，區域B2包含部分暫時性遮罩層350’、部分帽層3605、部份第二區域3502、及部分障壁層350，區域C2包含部分厚膜光阻3100。其中，圖中的橫軸座標所代表的是鎂佈植的深度，深度單位為奈米(nm)；深度的位置自中間結構I2的表面開始垂直向下計算，其中於區域A2、B2是自暫時性遮罩層350’表面，於區域C2則是自厚膜光阻3100表面開始計算；而圖中的縱軸座標所代表的是鎂的佈植濃度，以每立方公分鎂的個數為單位(counts/cm³ )。Referring to FIGS. 7A to 7D, FIG. 7D is a cross-sectional view showing an intermediate structure I2 of the semiconductor power device unit E3 of the third embodiment before the removal of the thick film photoresist 3100 after a magnesium implantation process; 7A to 7C are graphs showing simulations of magnesium distribution characteristics at regions A2, B2, and C2 indicated in the intermediate structure I2 shown in Fig. 7D of the present disclosure. The area A2 includes a partial temporary mask layer 350', a partial cap layer 3605, a first area 3501, and a partially unimplanted barrier layer 350. The area B2 includes a partial temporary mask layer 350', a partial cap layer 3605, A portion of the second region 3502 and a portion of the barrier layer 350, the region C2 comprising a portion of the thick film photoresist 3100. Wherein, the horizontal axis coordinates in the figure represent the depth of the magnesium implant, and the depth unit is nanometer (nm); the depth position is calculated vertically from the surface of the intermediate structure I2, wherein the regions A2 and B2 are The surface of the temporary mask layer 350' is calculated from the surface of the thick film photoresist 3100 in the region C2; and the vertical axis coordinates in the figure represent the implant concentration of magnesium, and the number of magnesium per cubic centimeter is Unit (counts/cm ³ ).

於本實施例中，暫時性遮罩層350’的材料為氮化矽，相對應於第一區域3501的暫時性遮罩層350’厚度設定為10奈米、相對應於第二區域3502的暫時性遮罩層350’厚度設定為25奈米、於其上的的厚膜光阻3100厚度為0.2微米。在鎂佈植的能量10KeV，佈植傾角為7度的條件下，可以得到於一次鎂佈植製程後，於區域A2中，第一區域3501鎂之分佈狀況如第7A圖所示，由於上方的暫時性遮罩層350’的厚度較薄，於本實施例中例如為10奈米的氮化矽，因而於第一區域3501中，會具有一最高鎂佈植濃度，於本實施例中例如為5~6x10⁵ counts/cm³ ，以及一鎂佈植深度，於本實施例中例如為深入障壁層350內25奈米；於區域B2中，第二區域3502鎂之分佈狀況如第7B圖所示，由於上方的暫時性遮罩層350’的厚度較厚，於本實施例中例如為25奈米的氮化矽；因而第二區域3502會有一最高鎂佈植濃度，但此處的最高鎂佈植濃度較第一區域3501的最高鎂佈植濃度低，於本實施例中例如為小於1x10⁵ counts/cm³ ，及較第一區域3501的鎂佈植深度小的鎂佈植深度，於本實施例中例如為深入障壁層350內約8奈米；而相對應於厚膜光阻3100下方的位置，也就是相對應於第7D圖結構中區域C2的位置，鎂之分佈狀況如第7C圖所示，此區域的鎂皆停留於厚膜光阻3100內，並未被佈植入其下方的障壁層350內。In the present embodiment, the material of the temporary mask layer 350 ′ is tantalum nitride, and the thickness of the temporary mask layer 350 ′ corresponding to the first region 3501 is set to 10 nm, corresponding to the second region 3502. The temporary mask layer 350' has a thickness set at 25 nm and a thick film photoresist 3100 thereon has a thickness of 0.2 microns. Under the condition that the energy of the magnesium cloth is 10KeV and the inclination angle of the planting is 7 degrees, it can be obtained in the region A2, and the distribution of magnesium in the first region 3501 is as shown in Fig. 7A. The thickness of the temporary mask layer 350' is relatively thin, and is, for example, 10 nm of tantalum nitride in this embodiment, so that in the first region 3501, there is a highest magnesium implant concentration, in this embodiment. ^3, for example, magnesium and a depth of implant ⁵ ~ 6x10 5 counts / cm, in the present embodiment, for example, the barrier layer further 35,025 nm; in region B2, a second distribution area of 3502 as magnesium 7B As shown in the figure, since the thickness of the upper temporary mask layer 350' is thick, in the present embodiment, for example, 25 nm of tantalum nitride; therefore, the second region 3502 has a maximum magnesium implant concentration, but here The highest magnesium implant concentration is lower than the highest magnesium implant concentration of the first region 3501, and is, for example, less than 1×10 ⁵ counts/cm ³ in the present embodiment, and a magnesium implant having a smaller magnesium implantation depth than the first region 3501. The depth is, for example, about 8 nm deep into the barrier layer 350 in this embodiment; and corresponds to a thick film The position under the photoresist 3100, that is, the position corresponding to the region C2 in the 7D structure, the distribution of magnesium is as shown in Fig. 7C, and the magnesium in this region stays in the thick film photoresist 3100, and is not The cloth is implanted in the barrier layer 350 below it.

第8A圖顯示為本揭露第四實施例之一半導體功率元件單元E4的剖面示意圖。由於本實施例與第三實施例間除了鎂佈植條件外其餘結構皆相同，因此，除第一區域及第二區域外，其餘結構皆以相同標號表示，在此不再贅述。如第8B圖及第8C圖所示，分別顯示為在第8A圖中半導體功率元件單元E4標示之區域B”及區域A”處的能帶模擬圖。區域B”及區域A”為自通道層40表面向下延伸的區域。如第8B圖至第8C圖的能帶模擬圖所示，圖中的橫軸座標所代表的是深度，深度的位置自通道層40的表面開始垂直向下計算，深度單位為奈米(nm)；而圖中的縱軸座標所代表的是能量，以電子伏特(eV)為單位，E_c 為電子傳導帶能階，E_f 為費米能階，E_v 為電子價帶能階。由圖中的模擬結果可顯示，在一般的鎂佈植製程條件下，當鎂佈植濃度例如為1x10¹⁸ counts/cm³ ~1x10²⁰ counts/cm³ ，可達成半導體功率元件單元E4為一常關型高電子遷移率電晶體。如本實施例中的模擬結果所示，在本實施例中，帽層3605例如為具有4奈米厚度的未摻雜氮化鎵(u-GaN)半導體層，而障壁層350之厚度為25奈米，而鎂的佈植結果設定如下：於第一區域3501’的最高鎂佈植深度為包含帽層3605全部4奈米及其下方障壁層350內深度15奈米，鎂佈植濃度為1x10¹⁹ counts/cm³ ，假定鎂活化率為3%時(一般活化率例如為3-5%)，則於第一區域3501’中鎂的活化濃度最高則例如為3x10¹⁷ counts/cm³ ，而相對應於第一區域3501’下，剩餘未被鎂佈植的障壁層350厚度則為10奈米；於第二區域3502’(包含子區域35021’及35022’)的最高鎂佈植深度為深入所有4奈米厚度的帽層3605內，並且深入障壁層350內1奈米深度，佈植濃度與第一區域3501’相同，約為1x10¹⁹ counts/cm³ ，假定鎂活化率為3%時(一般活化率例如為3-5%)，則於第二區域3502’中鎂的活化濃度最高則例如為3x10¹⁷ counts/cm³ ，相對應於第二區域3502’下剩餘未被佈植的障壁層350厚度為24奈米。能帶模擬圖結果如第8B圖所示，當於閘極電極390施加0伏特電壓時，相對應於第8A圖區域B”中，因鎂的最終佈植深度相對於區域A’’來得小，因此區域B”內鄰近障壁層350及通道層340間仍具有二維電子氣層存在(電子傳導帶能階E_c 最低位置低於費米能階E_f )；於相同條件下，相對應於區域A”的能帶模擬圖則如第8C圖所示，顯示此區域內因具有較大的鎂佈植深度，鄰近障壁層350及通道層340間的二維電子氣層已經被耗盡(電子傳導帶能階E_c 最低位置高於費米能階E_f )。FIG. 8A is a cross-sectional view showing a semiconductor power device unit E4 according to a fourth embodiment of the present disclosure. The structure is the same except for the first region and the second region, and the rest of the structures are denoted by the same reference numerals, and will not be described again. As shown in Figs. 8B and 8C, the energy band simulations at the regions B" and A" indicated by the semiconductor power element unit E4 in Fig. 8A are shown. The area B" and the area A" are areas extending downward from the surface of the channel layer 40. As shown in the energy band simulation diagrams of Figs. 8B to 8C, the horizontal axis coordinates in the figure represent the depth, and the position of the depth is calculated vertically from the surface of the channel layer 40, and the depth unit is nanometer (nm The vertical axis coordinates in the figure represent energy, in electron volts (eV), E _c is the electron conduction band energy level, E _f is the Fermi energy level, and E _v is the electron valence band energy level. From the simulation results in the figure, it can be shown that under the general magnesium plating process conditions, when the magnesium implantation concentration is, for example, 1×10 ¹⁸ counts/cm ³ to 1×10 ²⁰ counts/cm ³ , the semiconductor power component unit E4 can be achieved as a common Off-type high electron mobility transistors. As shown in the simulation results in this embodiment, in the present embodiment, the cap layer 3605 is, for example, an undoped gallium nitride (u-GaN) semiconductor layer having a thickness of 4 nm, and the barrier layer 350 has a thickness of 25 Nano, and the results of magnesium implantation are set as follows: the highest magnesium implant depth in the first region 3501' is the depth of 15 nm including the cap layer 3605 all 4 nm and the lower barrier layer 350. The magnesium implant concentration is 1x10 ¹⁹ counts/cm ³ , assuming that the magnesium activation rate is 3% (the general activation rate is, for example, 3-5%), the highest activation concentration of magnesium in the first region 3501' is, for example, 3×10 ¹⁷ counts/cm ³ . Corresponding to the first region 3501', the thickness of the barrier layer 350 remaining without magnesium implantation is 10 nm; and the highest magnesium implantation depth for the second region 3502' (including sub-regions 35021' and 35022') to further inner cap layer 3605 all 4 nm thickness, and a further barrier layer within a depth of 350 nm, and the concentration of the first implant region 3501 'are the same, about 1x10 ¹⁹ counts / cm ^3, is assumed to activate the magnesium was 3 When % (the general activation rate is, for example, 3-5%), the highest activation concentration of magnesium in the second region 3502' is, for example, 3 x 10 ¹⁷ counts/cm ³ . The barrier layer 350, which corresponds to the remaining unplanted under the second region 3502', has a thickness of 24 nm. The energy band simulation result is as shown in Fig. 8B. When a voltage of 0 volt is applied to the gate electrode 390, corresponding to the region B" of the 8A image, the final implantation depth of magnesium is small relative to the region A''. Therefore, there is still a two-dimensional electron gas layer between the adjacent barrier layer 350 and the channel layer 340 in the region B" (the lowest position of the electron conduction band energy level E _c is lower than the Fermi energy level E _f ); under the same conditions, corresponding The energy band simulation map of the area A" is as shown in Fig. 8C, showing that the two-dimensional electron gas layer between the adjacent barrier layer 350 and the channel layer 340 has been exhausted due to the large magnesium implantation depth in this region ( The lowest position of the electron conduction band energy level E _c is higher than the Fermi level E _f ).

藉由本揭露精神的實施方式，在經由一次鎂佈植的製程下，可以同時達到形成常關型高電子遷移率電晶體、改善因電流崩潰(current collapse)現象導致的元件輸出功率降低的問題、並且達成提高元件崩潰電壓的效果，具有產業利用性。以上所述之實施例僅係為說明本揭露之技術思想及特點，其目的在使熟習此項技藝之人士能夠瞭解本揭露之內容並據以實施，當不能以之限定本揭露之專利範圍，即大凡依本揭露所揭示之精神所作之均等變化或修飾，仍應涵蓋在本揭露之專利範圍內。According to the embodiment of the present disclosure, under the process of primary magnesium implantation, the formation of a normally-off high electron mobility transistor can be simultaneously achieved, and the problem of a decrease in output power of the device due to a current collapse phenomenon can be improved. In addition, the effect of improving the component breakdown voltage is achieved, and industrial utilization is achieved. The embodiments described above are only for explaining the technical idea and the features of the disclosure, and the purpose of the present invention is to enable those skilled in the art to understand the contents of the disclosure and to implement the invention. That is, the equivalent changes or modifications made by the spirit of the present disclosure should still be covered by the scope of the present disclosure.

10、310‧‧‧基板10, 310‧‧‧ substrate

20、320‧‧‧成核層20, 320‧‧‧ nucleation layer

30、330‧‧‧緩衝結構30, 330‧‧‧ buffer structure

3605‧‧‧帽層3605‧‧‧Cap

40、340‧‧‧通道層40, 340‧‧‧ channel layer

50、350‧‧‧障壁層50, 350‧‧ ‧ barrier layer

50’、350’‧‧‧暫時性遮罩層50', 350'‧‧‧ temporary masking layer

501、501’、3501、3501’‧‧‧第一區域501, 501', 3501, 3501'‧‧‧ first area

502、502’、3502、3502’‧‧‧第二區域502, 502’, 3502, 3502’‧‧‧ second area

5021、5022、35021、35022、5021’、5022’、35021’、35022’‧‧‧子區域5021, 5022, 35021, 35022, 5021', 5022', 35021', 35022'‧‧‧ sub-areas

504‧‧‧原生氮化矽層504‧‧‧Natural tantalum nitride layer

505‧‧‧外生氮化矽層505‧‧‧External tantalum nitride layer

60、360‧‧‧保護層60, 360‧‧‧ protective layer

70、370‧‧‧源極電極70, 370‧‧‧ source electrode

80、380‧‧‧汲極電極80, 380‧‧‧汲electrode

90、390‧‧‧閘極電極90, 390‧‧‧ gate electrode

90’‧‧‧圖案化光阻90'‧‧‧ patterned photoresist

100、3100‧‧‧厚膜光阻100, 3100‧‧‧ thick film photoresist

A1、B1、C1、A2、B2、C2、A’、B’、A”、B”‧‧‧區域A1, B1, C1, A2, B2, C2, A', B', A", B" ‧ ‧ areas

E1、E2、E3、E4‧‧‧半導體功率元件單元E1, E2, E3, E4‧‧‧ semiconductor power component unit

I1、I2‧‧‧中間結構I1, I2‧‧‧ intermediate structure

S‧‧‧半導體功率元件S‧‧‧Semiconductor Power Components

S70‧‧‧源極墊S70‧‧‧Source pad

S80‧‧‧汲極墊S80‧‧‧汲pad

S90‧‧‧閘極墊S90‧‧‧ gate pad

FF’ 、GG’‧‧‧剖線FF’, GG’‧‧‧ cut line

第1圖係本揭露第一實施例之半導體功率元件的上視圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a top plan view of a semiconductor power device of the first embodiment.

第2A圖係本揭露第一實施例之半導體功率元件單元的局部放大上視示意圖。2A is a partially enlarged top plan view showing the semiconductor power device unit of the first embodiment.

第2B圖係第2A圖沿剖線FF’之剖面示意圖。Fig. 2B is a schematic cross-sectional view taken along line FF' of Fig. 2A.

第3A圖至第3F圖係本揭露第一實施例之半導體功率元件單元中間製程步驟圖。3A to 3F are diagrams showing an intermediate process step of the semiconductor power device unit of the first embodiment.

第4A圖係顯示本揭露第一實施例之半導體功率元件單元鎂佈植製程中間結構區域A1鎂分佈特徵模擬圖。4A is a simulation diagram showing the magnesium distribution characteristic of the intermediate structure region A1 of the magnesium wiring process of the semiconductor power device unit of the first embodiment of the present disclosure.

第4B圖係顯示本揭露第一實施例之半導體功率元件單元鎂佈植製程中間結構區域B1鎂分佈特徵模擬圖。4B is a simulation diagram showing the magnesium distribution characteristic of the intermediate structure region B1 of the magnesium wiring process of the semiconductor power device unit of the first embodiment.

第4C圖係顯示本揭露第一實施例之半導體功率元件單元鎂佈植製程中間結構區域C1鎂分佈特徵模擬圖。4C is a simulation diagram showing the magnesium distribution characteristic of the intermediate structure region C1 of the magnesium wiring process of the semiconductor power device unit of the first embodiment.

第4D圖係顯示本揭露第一實施例之半導體功率元件單元鎂佈植製程中間結構的剖面示意圖。4D is a cross-sectional view showing the intermediate structure of the magnesium wiring process of the semiconductor power device unit of the first embodiment.

第5A圖係顯示本揭露第一實施例之半導體功率元件單元的剖面示意圖。Fig. 5A is a schematic cross-sectional view showing the semiconductor power device unit of the first embodiment of the present disclosure.

第5B圖係顯示本揭露第一實施例之半導體功率元件單元區域A’的能帶模擬圖。Fig. 5B is a view showing the energy band simulation of the semiconductor power element unit area A' of the first embodiment of the present disclosure.

第5C圖係顯示本揭露第一實施例之半導體功率元件單元區域B’的能帶模擬圖。Fig. 5C is a view showing the energy band simulation of the semiconductor power element unit region B' of the first embodiment of the present disclosure.

第6A圖係本揭露第三實施例之半導體功率元件單元的局部放大上視示意圖。Fig. 6A is a partially enlarged plan view showing the semiconductor power device unit of the third embodiment.

第6B圖係第6A圖沿剖線GG’之剖面示意圖。Fig. 6B is a schematic cross-sectional view taken along line GG' of Fig. 6A.

第7A圖係顯示本揭露第三實施例之半導體功率元件單元鎂佈植製程中間結構區域A2鎂分佈特徵模擬圖。FIG. 7A is a view showing a magnesium distribution characteristic diagram of the intermediate structure region A2 of the magnesium wiring process of the semiconductor power device unit according to the third embodiment of the present disclosure.

第7B圖係顯示本揭露第三實施例之半導體功率元件單元鎂佈植製程中間結構區域B2鎂分佈特徵模擬圖。FIG. 7B is a simulation diagram showing the magnesium distribution characteristic of the intermediate structure region B2 of the magnesium wiring process of the semiconductor power device unit according to the third embodiment of the present disclosure.

第7C圖係顯示本揭露第三實施例之半導體功率元件單元鎂佈植製程中間結構區域C2鎂分佈特徵模擬圖。FIG. 7C is a view showing a magnesium distribution characteristic diagram of the intermediate structure region C2 of the magnesium wiring process of the semiconductor power device unit of the third embodiment.

第7D圖係顯示本揭露第三實施例之半導體功率元件單元鎂佈植製程中間結構的剖面示意圖。7D is a cross-sectional view showing the intermediate structure of the magnesium wiring process of the semiconductor power device unit of the third embodiment.

第8A圖係顯示本揭露第四實施例之半導體功率元件單元的剖面示意圖。Figure 8A is a cross-sectional view showing the semiconductor power device unit of the fourth embodiment of the present disclosure.

第8B圖係顯示本揭露第四實施例之半導體功率元件單元區域A”的能帶模擬圖。Fig. 8B is a view showing the energy band simulation of the semiconductor power device unit region A" of the fourth embodiment of the present disclosure.

第8C圖係顯示本揭露第四實施例之半導體功率元件單元區域B”的能帶模擬圖。Fig. 8C is a view showing the energy band simulation of the semiconductor power device unit region B" of the fourth embodiment.

無no

Claims

一種半導體功率元件單元，包含：一基板；一通道層，位於該基板上；一障壁層，位於該通道層上；一二維電子氣層，位於該通道層內，且鄰近該通道層與該障壁間之一介面；一汲極電極、一閘極電極、以及一源極電極，分別位於該障壁層上，且該閘極電極位於該汲極電極及該源極電極之間；一第一區域，包含一第一鎂佈植特徵，位於該障壁層內相對應於該閘極電極的下方；以及一第二區域，包含一第二鎂佈植特徵，位於該障壁層內相對應於該汲極電極與該閘極電極之間及/或該源極電極與該閘極電極之間；其中，該第一區域與該第二區域相連接；其中，該第一鎂佈植特徵大於該第二鎂佈植特徵。A semiconductor power component unit comprising: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a two-dimensional electron gas layer located in the channel layer adjacent to the channel layer and the An interface between the barrier ribs; a drain electrode, a gate electrode, and a source electrode are respectively disposed on the barrier layer, and the gate electrode is located between the drain electrode and the source electrode; a region including a first magnesium implant feature located below the gate electrode in the barrier layer; and a second region including a second magnesium implant feature in the barrier layer corresponding to the Between the drain electrode and the gate electrode and/or between the source electrode and the gate electrode; wherein the first region is connected to the second region; wherein the first magnesium implant feature is greater than the The second magnesium implant feature.

如申請專利範圍第1項所述之半導體功率元件單元，其中該第一鎂佈植特徵包含一第一最高鎂佈植濃度及一第一最大鎂佈植深度；該第二鎂佈植特徵包含一第二最高鎂佈植濃度及一第二最大鎂佈植深度；其中，該第一最高鎂佈植濃度大於該第二最高鎂佈植濃度及/或該第一最大鎂佈植深度大於該第二最大鎂佈植深度。The semiconductor power component unit of claim 1, wherein the first magnesium implant feature comprises a first highest magnesium implant concentration and a first maximum magnesium implant depth; the second magnesium implant feature comprises a second highest magnesium implant concentration and a second maximum magnesium implant depth; wherein the first highest magnesium implant concentration is greater than the second highest magnesium implant concentration and/or the first maximum magnesium implant depth is greater than the The second largest magnesium planting depth.

如申請專利範圍第1項所述之半導體功率元件單元，其中該第一區域與該閘極電極之間更包含一保護層、一介電層或一氮化鎵帽層。The semiconductor power device unit of claim 1, wherein the first region and the gate electrode further comprise a protective layer, a dielectric layer or a gallium nitride cap layer.

如申請專利範圍第1項所述之半導體功率元件單元，其中該閘極電極與該第一區域間為蕭特基接觸。The semiconductor power device unit of claim 1, wherein the gate electrode is in Schottky contact with the first region.

如申請專利範圍第1項所述之半導體功率元件單元，其中該汲極電極與源極電極的材料係選自鈦(Ti)、鋁(Al)等金屬或其組合。The semiconductor power device unit according to claim 1, wherein the material of the drain electrode and the source electrode is selected from a metal such as titanium (Ti) or aluminum (Al) or a combination thereof.

一種半導體功率元件單元的製造方法，包含：提供一基板；形成一磊晶疊層於該基板上，該磊晶疊層包含：一通道層；一障壁層；及一二維電子氣層，位於該通道層，且鄰近該通道層與該電子障壁層間之一介面；形成一暫時性遮罩層於該障壁層上；透過該暫時性遮罩層對該障壁層進行一一次鎂佈植，並藉由該一次鎂佈植步驟以使得該障壁層具有一第一區域以及一第二區域；及形成一源極電極、一閘極電極、以及一汲極電極於該障壁層上；其中，該閘極電極位於該源極電極及該汲極電極之間；其中，該第一區域與該第二區域相連接；其中，該第一區域具有一第一鎂佈植特徵，該第二區域具有一第二鎂佈植特徵，且該第一鎂佈植特徵大於該第二鎂佈植特徵。A method of fabricating a semiconductor power device unit, comprising: providing a substrate; forming an epitaxial layer on the substrate, the epitaxial layer stack comprising: a channel layer; a barrier layer; and a two-dimensional electron gas layer The channel layer is adjacent to one of the channel layer and the electron barrier layer; forming a temporary mask layer on the barrier layer; and the barrier layer is subjected to magnesium implantation once through the temporary mask layer. And the primary barrier layer has a first region and a second region; and a source electrode, a gate electrode, and a drain electrode are formed on the barrier layer; The gate electrode is located between the source electrode and the drain electrode; wherein the first region is connected to the second region; wherein the first region has a first magnesium implant feature, the second region Having a second magnesium implant feature, and the first magnesium implant feature is greater than the second magnesium implant feature.

如申請專利範圍第6項所述之半導體功率元件單元的製造方法，其中該第一鎂佈植特徵包含一第一最高鎂佈植濃度及一第一最大鎂佈植深度；該第二鎂佈植特徵包含一第二最高鎂佈植濃度及一第二最大鎂佈植深度；其中，該第一最高鎂佈植濃度大於該第二最高鎂佈植濃度及/或該第一最大鎂佈植深度大於該第二最大鎂佈植深度。The method for manufacturing a semiconductor power device unit according to claim 6, wherein the first magnesium implanting feature comprises a first highest magnesium implant concentration and a first maximum magnesium implant depth; the second magnesium cloth The planting feature comprises a second highest magnesium implant concentration and a second maximum magnesium implant depth; wherein the first highest magnesium implant concentration is greater than the second highest magnesium implant concentration and/or the first maximum magnesium implant The depth is greater than the second maximum magnesium implant depth.

如申請專利範圍第6項所述之半導體功率元件單元的製造方法，其中形成該暫時性遮罩層的方法包含形成一具有不同厚度的介電層。The method of fabricating a semiconductor power device unit according to claim 6, wherein the method of forming the temporary mask layer comprises forming a dielectric layer having a different thickness.

如申請專利範圍第6項所述之半導體功率元件單元的製造方法，更包含於該一次鎂佈植後移除該暫時性遮罩層。The method for manufacturing a semiconductor power device unit according to claim 6, further comprising removing the temporary mask layer after the primary magnesium implantation.

如申請專利範圍第6項所述之半導體功率元件單元的製造方法，其中更包含形成一介電層或一氮化鎵帽層於該第一區域與該閘極電極之間。The method of fabricating a semiconductor power device unit according to claim 6, further comprising forming a dielectric layer or a gallium nitride cap layer between the first region and the gate electrode.