TWI602301B - 鰭式場效電晶體裝置結構及其形成方法 - Google Patents

鰭式場效電晶體裝置結構及其形成方法 Download PDF

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TWI602301B
TWI602301B TW104134169A TW104134169A TWI602301B TW I602301 B TWI602301 B TW I602301B TW 104134169 A TW104134169 A TW 104134169A TW 104134169 A TW104134169 A TW 104134169A TW I602301 B TWI602301 B TW I602301B
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fin
epitaxial
height
finfet
field effect
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TW201626571A (zh
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張哲豪
程潼文
陳建穎
張哲誠
張永融
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台灣積體電路製造股份有限公司
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Description

鰭式場效電晶體裝置結構及其形成方法
本發明有關於積體電路元件，特別是有關於鰭式場效電晶體(FinFET)裝置及其形成方法。
半導體裝置應用於各種電子產品，例如個人電腦、行動電話、數位相機和其他電子設備。通常藉由在半導體基底上方依序沉積絕緣或介電層、導電層和半導體材料層以及使用微影技術圖案化各個材料層以在各個材料層上形成電路構件和元件來製造半導體裝置。在單一個半導體晶圓上通常會製造許多積體電路，並且藉由沿著在積體電路之間的切割線(scribe line)切開以分割晶圓上的單獨的晶粒。例如，單獨的晶粒通常以多晶片模組或其他種類的封裝技術來進行封裝。
隨著半導體工業為了尋求更高的裝置密度、更高的性能和更低的成本而進入奈米技術節點，來自製造和設計問題已經導致半導體裝置的三維設計，例如鰭式場效電晶體(FinFET)的發展面臨挑戰。FinFET為具有從基底延伸的薄垂直“鰭”(或鰭結構)，在該垂直鰭中形成FinFET的通道。在鰭上方提供閘極。FinFET的優勢可以包括降低短通道效應和更高的電流。
雖然現有的FinFET裝置以及FinFET裝置的製造方 法對於它們的預期目的通常已經足夠，但是它們不是在所有方面完全令人滿意。
本發明一實施例提供一種鰭式場效電晶體(FinFET)裝置結構，包括：基底；鰭結構，延伸於上述基底之上方；磊晶結構，形成在上述鰭結構上，其中上述磊晶結構具有第一高度；鰭側壁間隔物，鄰接上述磊晶結構，其中上述鰭側壁間隔物具有第二高度，並且上述第一高度大於上述第二高度，並且其中上述鰭側壁間隔物設置用以控制上述磊晶結構的體積和上述第一高度。
本發明一實施例一種鰭式場效電晶體(FinFET)裝置結構，包括：基底；鰭結構，延伸於上述基底之上方；隔離結構，形成在上述基底上，其中上述鰭結構嵌入於上述隔離結構中；以及第一磊晶結構，形成於上述鰭結構上，其中上述第一磊晶結構和上述鰭結構之間的界面位於上述隔離結構的頂面下方，並且沒有形成鄰接上述第一磊晶結構的鰭側壁間隔物。
本發明一實施例提供一種鰭式場效電晶體(FinFET)裝置結構的形成方法，包括：提供基底；在上述基底之上形成鰭結構；在上述鰭結構的中心部分上方形成閘極堆疊結構；在上述閘極堆疊結構的頂面和側壁上形成閘極側壁間隔物，並且在上述鰭結構的頂面和側壁上形成鰭側壁間隔物；去除上述閘極側壁間隔物的頂部和上述鰭側壁間隔物的頂部以暴露上述閘極堆疊結構的頂部和上述鰭結構的頂部；去除一 部分的上述鰭側壁間隔物，其中，上述鰭側壁間隔物具有第二高度；凹陷化一部的上述鰭結構的以形成溝槽；以及由上述溝槽磊晶成長磊晶結構，其中在上述鰭結構上方形成上述磊晶結構，並且其中上述磊晶結構具有第一高度，並且上述第一高度大於上述第二高度。
10‧‧‧鰭式場效電晶體裝置結構
15‧‧‧N型FinFET裝置結構(NMOS)
25‧‧‧P型FinFET裝置結構(PMOS)
102‧‧‧基底
104‧‧‧鰭結構
105‧‧‧鰭側壁間隔物
108‧‧‧隔離結構
110‧‧‧閘極
112‧‧‧第一硬罩幕
114‧‧‧第二硬罩幕
115‧‧‧閘極側壁間隔物
202‧‧‧底部抗反射塗層
210、212、214‧‧‧磊晶結構
210A、210B、210C、210D‧‧‧小平面
212A、212B、212C、212D‧‧‧小平面
214A、214B、214C、214D‧‧‧小平面
204a、204b、304‧‧‧溝槽
H1‧‧‧鰭側壁間隔物第一高度
H2‧‧‧鰭側壁間隔物的第二高度
Ht1‧‧‧磊晶結構210的高度
Ht2‧‧‧磊晶結構212的高度
Ht3‧‧‧磊晶結構214的高度
W1‧‧‧磊晶結構210的寬度
W2‧‧‧磊晶結構212的寬度
W3‧‧‧磊晶結構214的寬度
D1‧‧‧溝槽的深度
D2‧‧‧溝槽的深度
S‧‧‧磊晶結構之間的間距
θ 1‧‧‧鰭結構的頂面與鰭側壁間隔物側壁的角度
θ 2、θ 3‧‧‧鰭結構的頂面與隔離結構側壁的角度
第1圖顯示根據本發明的一些實施例的鰭式場效電晶體(FinFET)裝置結構的立體圖。
第2A圖至第2F圖顯示根據本發明的一些實施例的形成鰭式場效電晶體(FinFET)裝置結構的各個階段的側視圖。
第2G圖是根據本發明的一些實施例的第2F圖的區域A的放大圖。
第3A圖至第3B圖顯示根據本發明的一些實施例的形成鰭式場效電晶體(FinFET)裝置結構的各個階段的側視圖。
第3C圖是根據本發明的一些實施例的第3B圖的區域B的放大圖。
第4A圖至第4D圖顯示根據本發明的一些實施例的形成鰭式場效電晶體(FinFET)裝置結構的各個階段的側視圖。
第4E圖是根據本發明的一些實施例的第4D圖的區域C的放大圖。
下述內容提供的不同實施例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本 發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明之多種實例將重複標號及/或符號以簡化並清楚說明。不同實施例中具有相同標號的元件並不必然具有相同的對應關係及/或排列。標號重複僅為了簡化並清楚說明，並不代表不同實施例及/或排列中具有相同標號的元件具有類似的相對關係。
提供用以形成鰭式場效應電晶體(FinFET)裝置結構的實施例。第1圖顯示了根據本發明的一些實施例的鰭式場效電晶體(FinFET)裝置結構10的立體圖。FinFET裝置結構10包括N型FinFET裝置結構(NMOS)15和P型FinFET裝置結構(PMOS)25。
FinFET裝置結構10包括基底102。基底102可以由矽或其他半導體材料製成。取而代之地或額外地，基底102可以包括例如鍺的其他元素半導體材料。在一些實施例中，基底102由例如碳化矽、砷化鎵、砷化銦或磷化銦的化合物半導體製成。在一些實施例中，基底102由例如矽鍺、碳化矽鍺、磷砷化鎵或磷化鎵銦的合金半導體製成。在一些實施例中，基底102包括磊晶層。例如，基底102具有位於塊狀半導體上的磊晶層。
在一些實施例中，可以藉由使用例如微影和蝕刻步驟的合適的步驟形成鰭結構104。在一些實施例中，藉由使用乾蝕刻或電漿步驟從基底102蝕刻得到鰭結構104。
在一些其他實施例中，可以藉由雙重圖案化微影 (DPL)製程以形成鰭結構104。DPL是一種藉由將圖案分成兩個交錯圖案而在基底上構造圖案的方法。DPL允許高的圖樣(例如，鰭)密度。
形成例如淺溝槽隔離(STI)結構的隔離結構108以圍繞鰭結構104。如第1圖所示，在一些實施例中，隔離結構108圍繞鰭結構104的下部，並且鰭結構104的上部凸出於隔離結構108。換句話說，鰭結構104的部分嵌入在隔離結構108中。此隔離結構108能夠防止電性干擾或串音(crosstalk)。
FinFET裝置結構10還包括閘極堆疊結構，閘極堆疊結構包括閘極110和閘極介電層(未顯示)。閘極堆疊結構形成在鰭結構104的中心部分上方。在一些其他實施例中，多個閘極堆疊結構形成在鰭結構104上方。
在一些其他實施例中，閘極堆疊結構是偽閘極堆疊並且在實施高熱預算步驟之後由金屬閘極(MG)代替。
閘極介電層(未顯示)可以包括例如氧化矽、氮化矽、氮氧化矽、具有高介電常數(高k)的介電材料或其組合的介電材料。高k介電材料的實例包括氧化鉿、氧化鋯、氧化鋁、二氧化鉿-氧化鋁合金、氧化鉿矽、氮氧化鉿矽、氧化鉿鉭、氧化鉿鈦、氧化鉿鋯等或其組合。
閘極110可以包括多晶矽或金屬。金屬包括氮化鉭(TaN)、矽化鎳(NiSi)、矽化鈷(CoSi)、目(Mo)、銅(Cu)、鎢(W)、鋁(Al)、鈷(Co)、鋯(Zr)、鉑(Pt)或其他適用的材料。可以在後閘極步驟(或閘極替代步驟)中形成閘極110。在一些實施例中，閘極堆疊結構包括例如介面 層、覆蓋層、擴散/阻障層或其他適用的層的額外的層。
藉由沉積步驟、微影製程和蝕刻步驟形成閘極堆疊結構。沉積步驟包括化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、高密度電漿CVD(HDPCVD)、金屬有機CVD(MOCVD)、遠端電漿CVD(RPCVD)、電漿增強CVD(PECVD)、鍍膜、其他合適的方法和/或其組合。微影步驟包括光阻塗佈(例如，旋塗)、軟烘烤、罩幕對準、曝光、曝光後烘烤、顯影光阻、沖洗和乾燥(例如，硬烘烤)。蝕刻步驟包括乾蝕刻步驟或濕蝕刻步驟。在另一實施例中，由例如無罩幕微影、電子束寫入和離子束寫入的其他適當的方法實施或代替微影製程。
第2A圖至第2F圖顯示根據本發明的一些實施例的形成鰭式場效電晶體(FinFET)裝置結構的各個階段的側視圖。第2A圖至第2F圖顯示沿著第1圖的箭頭1截取的側視圖，並且箭頭1平行於X軸。
參照第2A圖及第1圖，在閘極110上形成第一硬罩幕層112，並且在第一硬罩幕層112上形成第二硬罩幕層114。在一些實施例中，第一硬罩幕層112由氧化矽、氮化矽、氮氧化矽或其他適用的材料製成。在一些實施例中，第二硬罩幕層114由氧化矽、氮化矽、氮氧化矽或其他適用的材料製成。
在閘極110的相對側壁上形成閘極側壁間隔物115，在鰭結構104的相對側壁上形成鰭側壁間隔物105。然後，在閘極側壁間隔物115上形成底部抗反射塗層(BARC)202。BARC層202使用於光阻層底部，以在圖案化過程中提升圖案轉 印於硬罩幕層112、114的效果。在一些實施例中，當進行N型FinFET裝置結構(NMOS)15植入步驟時，在閘極110上形成BARC 202和光阻層(未顯示)(光阻層形成在BARC 202上)以覆蓋P型FinFET裝置結構(PMOS)25中的閘極110。
然後，如圖2B所示，根據本發明的一些實施例，藉由蝕刻步驟去除光阻層(未顯示)和BARC 202。蝕刻步驟可以是乾蝕刻步驟或濕蝕刻步驟。在一些實施例中，為約3毫托至約50毫托的範圍的壓力下操作乾蝕刻步驟。以下又稱此步驟為第一乾蝕刻步驟。在一些實施例中，在第一乾蝕刻步驟中使用的氣體包括甲烷(CH4)、氮氣(N2)、氦氣(He)、氧氣(O2)或其組合。在一些實施例中，以約50W至約1000W的範圍的功率操作第一乾蝕刻步驟。在一些實施例中，為約20℃至約80℃的範圍的溫度下操作第一乾蝕刻步驟。
如圖2C所示，根據本發明的一些實施例，在去除BARC 202之後，去除部分的閘極側壁間隔物115和部分的鰭側壁間隔物105。更具體地，去除閘極側壁間隔物115的頂部以暴露第二硬罩幕層114。去除鰭側壁間隔物105的頂部以暴露鰭結構104。
在一些實施例中，當閘極側壁間隔物115和鰭側壁間隔物105由氮化矽製成時，進行蝕刻步驟以去除氮化矽。在一些實施例中，此蝕刻步驟是乾蝕刻步驟，以下又稱此蝕刻步驟為”第二乾蝕刻步驟”，第二乾蝕刻步驟在約3毫托至約50毫托的範圍的壓力下操作。在一些實施例中，在第二乾蝕刻步驟中使用的氣體包括氟甲烷(CH3F)、二氟甲烷(CH2F2)、 甲烷(CH4)、氬氣(Ar)、溴化氫(HBr)、氮氣(N2)、氦氣(He)、氧氣(O2)或其組合。在一些實施例中，以約50W至約1000W的範圍的功率操作第二乾蝕刻步驟。在一些實施例中，在約20℃至約70℃的範圍的溫度下操作第二乾蝕刻步驟。
在第二乾蝕刻步驟之後，每個鰭側壁間隔物105均具有第一高度H1。在一些實施例中，第一高度H1為約0.1nm至約100nm的範圍。
如圖2D所示，根據本發明的一些實施例，在前述去除一部分的閘極側壁間隔物115和一部分的鰭側壁間隔物105之後，再進一步去除一部分留下的鰭側壁間隔物105。亦即，藉由乾蝕刻步驟或濕蝕刻步驟去除鰭側壁間隔物105的上部。
在一些實施例中，此蝕刻步驟為乾蝕刻步驟，以下又稱此乾蝕刻步驟為”第三乾蝕刻步驟”，在一些實施例中，第三乾蝕刻步驟可以在約3毫托至約50毫托的範圍的壓力下操作，且在第三乾蝕刻步驟中使用的氣體包括氟甲烷(CH3F)、二氟甲烷(CH2F2)、甲烷(CH4)、氬氣(Ar)、溴化氫(HBr)、氮氣(N2)、氦氣(He)、氧氣(O2)或其組合。在一些實施例中，以約50W至約1000W的範圍的功率操作第三乾蝕刻步驟。在一些實施例中，在約20℃至約70℃的範圍的溫度下操作第三乾蝕刻步驟。
在第三乾蝕刻步驟之後，鰭側壁間隔物105的高度從第一高度H1降低至第二高度H2。在一些實施例中，第二高度 H2為約0.1nm至約90nm的範圍。
值得注意的是，鰭側壁間隔物105的第二高度H2可決定磊晶結構(例如圖2E中的磊晶結構210)是至關重要的。磊晶結構的高度和體積受到鰭側壁間隔物105的第二高度H2的影響。換句話說，鰭側壁間隔物105形成是能夠控制磊晶結構210的體積和高度。
如圖2E所示，根據本發明的一些實施例，在第三乾蝕刻步驟之後，去除一部分的鰭結構104。去除鰭結構104的步驟是藉由例如乾蝕刻步驟或濕蝕刻步驟來進行。如圖2E所示，留下的鰭結構104的頂面與隔離結構108的頂面大致上齊平。藉由使位於隔離結構108之上的鰭結構104的部分凹陷以形成溝槽204a。溝槽204a的側壁是垂直於隔於留下的鰭結構104的頂面，並且彼此平行。在一些實施例中，溝槽204a的側壁和鰭結構104的頂面之間的角度θ 1為約90度。
如第2F圖所示，根據本發明的一些實施例，去除一部分的鰭結構104之後，在溝槽204a中形成磊晶結構210。
磊晶結構210包括源極/汲極磊晶結構。在一些實施例中，當想要形成N型FET(NFET)元件時，源極/汲極磊晶結構包括磊晶成長的矽(磊晶Si)。另一方面，當想要形成P型FET(PFET)元件時，源極/汲極磊晶結構包括磊晶成長的矽鍺(SiGe)。
第2G圖是根據本發明的一些實施例的第2F圖的區域A的放大圖。如第2G圖所示，磊晶結構210具有菱形上部和柱狀下部。磊晶結構210的菱形上部具有四個小平面210A、 210B、210C和210D。每個小平面均具有(111)結晶方位(orientation)。磊晶結構210的柱狀下部具有底面和鄰接底面的側壁。底面和側壁之間的角度θ 1為約90度。此外，磊晶結構210的柱狀下部的底面與隔離結構108的頂面基本齊平。
如第2G圖所示，磊晶結構210具有高度Ht1和寬度W1。在一些實施例中，高度Ht1為約10nm至約300nm的範圍。如果高度Ht1太大，則電阻將變低。如果高度Ht1太小，則電阻變高而影響元件的操作速度。在一些實施例中，寬度W1為約10nm至約100nm的範圍。如果寬度W1太大，則磊晶結構210可能會與相鄰的磊晶結構210合併而引起短路效應。如果寬度W1太小，則用於與磊晶結構210接觸的接觸面積將變窄，並且因此可以破壞電路效應。
此外，磊晶結構210的高度Ht1與鰭側壁間隔物105的高度H2的比例(Ht1/H2)為約1.5至約10的範圍。如果比例太小，則鰭側壁不能對EPI高度提供有效支撐並且引起短EPI結構。
第3A圖至第3B圖顯示根據本發明的一些實施例的形成鰭式場效電晶體(FinFET)裝置結構的各個階段的側視圖。
如第3A圖所示，在一些實施例中，留下的鰭結構104的頂面低於隔離結構108的頂面。藉由使位於隔離結構108下方的鰭結構104的部分凹陷以形成溝槽204b。在一些其他實施例中，溝槽204b的側壁和鰭結構104的頂面之間的角度θ 2為約90度。溝槽204b從隔離結構108的頂面延伸至深度D1，深度D1為約0.1nm至約50nm的範圍。
如第3B圖所示，根據本發明的一些實施例，在去除一部分的鰭結構104之後，在溝槽204b中形成磊晶結構212。磊晶結構212包括源極/汲極磊晶結構。在一些實施例中，當想要形成N型FET(NFET)元件時，源極/汲極磊晶結構包括磊晶成長的矽(磊晶Si)。另一方面，當想要形成P型FET(PFET)元件時，源極/汲極磊晶結構包括磊晶成長的矽鍺(SiGe)。
第3C圖是根據本發明的一些實施例的第3B圖的區域B的放大圖。如第3C圖所示，磊晶結構212具有菱形上部和柱狀下部。磊晶結構212的菱形上部具有四個小平面212A、212B、212C和212D。每個小平面均具有(111)結晶方位。磊晶結構212的柱狀下部具有底面和鄰接底面的側壁。底面和側壁之間的角度θ 2為約90度。此外，磊晶結構212的柱狀下部的底面低於隔離結構108的頂面。
如第3C圖所示，磊晶結構212具有高度Ht2和寬度W2。高度Ht1小於高度Ht2，並且寬度W1大於寬度W2。在一些實施例中，高度Ht2為約15nm至約150nm的範圍。在一些實施例中，寬度W2為約10nm至約100nm的範圍。
磊晶結構210和磊晶結構212各自地包括例如鍺(Ge)或矽(Si)的單元素半導體材料；或例如砷化鎵(GaAs)、砷化鋁鎵(AlGaAs)的化合物半導體材料；或例如矽鍺(SiGe)、磷砷化鎵(GaAsP)的半導體合金。
藉由磊晶步驟形成磊晶結構210和212。磊晶步驟包括選擇性磊晶成長(SEG)步驟、CVD沉積技術(例如，氣相磊晶(VPE)和/或超高真空CVD(UHV-CVD))、分子束 磊晶或其他適用的磊晶步驟。
可以在磊晶過程中，臨場摻雜(in-situ)或未臨場摻雜磊晶結構210和212。例如，磊晶成長的SiGe磊晶結構可以摻雜有硼；並且磊晶成長的Si磊晶結構可以摻雜有碳以形成Si：C磊晶結構、摻雜有磷以形成Si：P磊晶結構，或摻雜有碳和磷以形成SiCP磊晶結構。可以藉由離子植入步驟、電漿浸潤離子植入(PIII)步驟、氣體和/或固體源擴散製程、或其他合適的製程來進行摻雜。磊晶結構210和212可以進一步進行例如快速熱退火步驟的退火步驟。
如果未臨場摻雜磊晶結構210和212，則進行第二植入步驟(即，接面(junction)植入步驟)以摻雜磊晶結構210和212。
鰭結構104包括由閘極110圍繞或包裹的通道區(未顯示)。磊晶結構210和212的晶格常數與基底102的晶格常數不同，通道區被應變或施加應力以提高FinFET裝置結構的載子遷移率並且提高FinFET裝置結構性能。
值得注意的是，藉由調整鰭側壁間隔物105的高度H2和/或深度D1來控制磊晶結構210和212的體積和高度Ht1、Ht2。一旦磊晶結構210和212的體積和高度Ht1、Ht2受到良好地控制，則可以進一步改良FinFET裝置結構。例如，FinFET裝置結構改善時，元件遷移率(Id_Sat)將增大。
第4A圖至第4D圖顯示根據本發明的一些實施例的形成鰭式場效電晶體(FinFET)裝置結構的各個階段的側視圖。第4E圖是根據本發明的一些實施例的第4D圖的區域C的放 大圖。第4A圖至第4D圖顯示沿著第1圖的箭頭1截取的側視圖，並且箭頭1平行於X軸方向。
參照第4A圖，在閘極110的相對側壁上形成閘極側壁間隔物115，在鰭結構104的相對側壁上形成鰭側壁間隔物105。
然後，如第4B圖所示，根據本發明的一些實施例，完全去除鰭側壁間隔物105。結果，暴露鰭結構104的頂面和側壁的部分。在鰭結構104上沒有形成鰭側壁間隔物105。
如第4C圖所示，根據本發明的一些實施例，在完全去除鰭側壁間隔物105之後，去除一部分的鰭結構104。結果，藉由使一部分的鰭結構104凹陷以形成溝槽304。
溝槽304具有位於隔離結構108下方的深度D2。在一些實施例中，深度D2為約0.1nm至約50nm的範圍。在一些實施例中，溝槽304的側壁和鰭結構104的頂面之間的角度θ 3為約90度。
如第4D圖所示，根據本發明的一些實施例，在去除一部分的鰭結構104之後，在溝槽304中且在鰭結構104上形成磊晶結構214。
磊晶結構214包括例如鍺(Ge)或矽(Si)的單元素半導體材料；或例如砷化鎵(GaAs)、砷化鋁鎵(AlGaAs)的化合物半導體材料；或例如矽鍺(SiGe)、磷砷化鎵(GaAsP)的半導體合金。
藉由磊晶步驟形成磊晶結構214。磊晶步驟可以包括選擇性磊晶成長(SEG)步驟、CVD沉積技術(例如，氣相 磊晶(VPE)和/或超高真空CVD(UHV-CVD))、分子束磊晶或其他適用的磊晶步驟。
與磊晶結構210和212相同，磊晶結構214具有菱形上部和柱狀下部。磊晶結構214的菱形上部具有四個小平面214A、214B、214C和214D。每個小平面均具有(111)結晶方位。
值得注意的是，與第2G圖和第3C圖相比，在鄰近第4E圖中的磊晶結構214處，沒有形成鰭側壁間隔物。因此，可藉由調整溝槽304(第4C圖中顯示)的深度來控制磊晶結構214的體積和高度。此外，由於沒有鰭側壁間隔物抑制磊晶結構214的成長，所以磊晶結構214傾向於在X軸的方向上成長。因此，磊晶結構214的寬度W3大於鰭結構104的寬度W4。
磊晶結構214具有高度Ht3和寬度W3。磊晶結構214的高度Ht3小於磊晶結構212的高度Ht2，而磊晶結構212的寬度W2大於磊晶結構214的寬度W3。此外，磊晶結構214的高度Ht3小於磊晶結構210的高度Ht1，並且磊晶結構210的寬度W1大於磊晶結構214的寬度W3。
再次參照第4D圖，兩個鄰近的磊晶結構214之間的間距S為約0.1nm至約100nm的範圍。在一些實施例中，磊晶結構214的寬度W3為約10nm至約100nm的範圍。在一些實施例中，磊晶結構214的高度Ht3為約10nm至約300nm的範圍。在一些實施例中，磊晶結構214的高度與寬度的比例(Ht3/W3)為約0.1至約10的範圍。
然後，FinFET裝置結構可以繼續進行其他步驟以 形成其他結構或元件。在一些實施例中，金屬化包括例如傳統的通孔或接觸物的垂直內連線以及例如金屬線的水平的內連線。各種內連線可以採用包括銅、鎢和/或矽化物的各種導電材料。
提供鰭式場效電晶體(FinFET)裝置結構的形成方法的一些實施例。FinFET裝置結構包括延伸於基底之上的鰭結構以及形成在鰭結構上方的磊晶結構。在一些實施例中，形成鰭側壁間隔物以鄰接磊晶結構。鰭側壁間隔物是設置來控制磊晶結構的體積和高度。在一些其他實施例中，不形成鄰接磊晶結構的鰭側壁間隔物，而是藉由調整溝槽的深度來控制磊晶結構的體積和高度，其中藉由使鰭結構的頂部凹陷以形成溝槽。一旦磊晶結構的體積和高度受到控制，就進一步改良FinFET裝置結構的性能。
提供鰭式場效電晶體(FinFET)裝置結構的一些實施例。FinFET結構包括基底和在基底之上延伸的鰭結構。FinFET結構包括形成在鰭結構上的磊晶結構，並且磊晶結構具有第一高度。FinFET結構也包括形成為鄰近磊晶結構的鰭側壁間隔物。鰭側壁間隔物具有第二高度，並且第一高度大於第二高度，並且鰭側壁間隔物配置為控制磊晶結構的體積和第一高度。
在一些實施例中，提供了一種鰭式場效電晶體(FinFET)裝置結構。FinFET結構包括基底和在基底之上延伸的鰭結構。FinFET結構也包括形成在基底上的隔離結構，並且鰭結構嵌入在隔離結構中。FinFET結構還包括形成在鰭結構上 的第一磊晶結構，第一磊晶結構和鰭結構之間的介面位於隔離結構的頂面下方，並且沒有形成鄰接第一磊晶結構的鰭側壁間隔物。
在一些實施例中，提供了一種鰭式場效電晶體(FinFET)裝置結構的形成方法。該方法包括提供基底以及在基底之上形成鰭結構。該方法也包括在鰭結構的中心部分上方形成閘極堆疊結構以及在閘極堆疊結構的頂面和側壁上形成閘極側壁間隔物，以及在鰭結構的頂面和側壁上形成鰭側壁間隔物。該方法還包括去除閘極側壁間隔物的頂部和鰭側壁間隔物的頂部以暴露閘極堆疊結構的頂部和鰭結構的頂部。該方法包括去除一部分的鰭側壁間隔物，並且鰭側壁間隔物具有第二高度。該方法還包括凹陷化鰭結構的部分以形成溝槽。該方法也包括由溝槽磊晶成長磊晶結構，並且在鰭結構上方形成磊晶結構，並且磊晶結構具有第一高度，並且第一高度大於第二高度。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本申請案作為基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明之精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
10‧‧‧鰭式場效電晶體裝置結構
15‧‧‧N型FinFET裝置結構(NMOS)
25‧‧‧P型FinFET裝置結構(PMOS)
102‧‧‧基底
104‧‧‧鰭結構
105‧‧‧鰭側壁間隔物
108‧‧‧隔離結構
110‧‧‧閘極
112‧‧‧第一硬罩幕
114‧‧‧第二硬罩幕
115‧‧‧閘極側壁間隔物

Claims (9)

  1. 一種鰭式場效電晶體(FinFET)裝置結構，包括：基底；鰭結構，延伸於上述基底之上方；磊晶結構，形成在上述鰭結構上，其中上述磊晶結構具有第一高度，並且上述磊晶結構包括源極/汲極結構；以及鰭側壁間隔物，鄰接上述磊晶結構，其中上述鰭側壁間隔物具有第二高度，並且上述第一高度大於上述第二高度，並且其中上述鰭側壁間隔物設置用以控制上述磊晶結構的體積和上述第一高度。
  2. 如申請專利範圍第1項所述之鰭式場效電晶體(FinFET)裝置結構，更包括：閘極堆疊結構，形成在上述鰭結構的中心部分上方，其中，上述磊晶結構形成為鄰接上述鰭結構的中心部分。
  3. 如申請專利範圍第1項所述之鰭式場效電晶體(FinFET)裝置結構，其中，上述第二高度為約0.1nm至約100nm的範圍。
  4. 如申請專利範圍第1項所述之鰭式場效電晶體(FinFET)裝置結構，還包括：隔離結構，其中，上述鰭結構嵌入在上述隔離結構中。
  5. 如申請專利範圍第4項所述之鰭式場效電晶體(FinFET)裝置結構，其中，上述磊晶結構的底面與上述隔離結構的頂面大致上齊平。
  6. 如申請專利範圍第4項所述之鰭式場效電晶體(FinFET)裝置結構，其中，上述磊晶結構的底面低於上述隔離結構的 頂面。
  7. 如申請專利範圍第6項所述之鰭式場效電晶體(FinFET)裝置結構，其中，上述磊晶結構從上述隔離結構的頂面延伸至約0.1nm至約50nm的範圍的深度。
  8. 一種鰭式場效電晶體(FinFET)裝置結構，包括：基底；鰭結構，延伸於上述基底之上方；隔離結構，形成在上述基底上，其中上述鰭結構嵌入於上述隔離結構中；以及磊晶結構，形成於上述鰭結構上，其中上述磊晶結構和上述鰭結構之間的界面位於上述隔離結構的頂面下方，並且沒有形成鄰接上述磊晶結構的鰭側壁間隔物，並且上述磊晶結構包括源極/汲極結構。
  9. 一種鰭式場效電晶體(FinFET)裝置結構的形成方法，包括：提供基底；在上述基底之上形成鰭結構；在上述鰭結構的中心部分上方形成閘極堆疊結構；在上述閘極堆疊結構的頂面和側壁上形成閘極側壁間隔物，並且在上述鰭結構的頂面和側壁上形成鰭側壁間隔物；去除上述閘極側壁間隔物的頂部和上述鰭側壁間隔物的頂部以暴露上述閘極堆疊結構的頂部和上述鰭結構的頂部；去除一部分的上述鰭側壁間隔物，其中，上述鰭側壁間隔物具有第二高度；凹陷化一部的上述鰭結構的以形成溝槽；以及 由上述溝槽磊晶成長磊晶結構，其中在上述鰭結構上方形成上述磊晶結構，並且其中上述磊晶結構具有第一高度，並且上述第一高度大於上述第二高度。
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