TWI598596B - Testing probe card for integrated circuit - Google Patents
Testing probe card for integrated circuit Download PDFInfo
- Publication number
- TWI598596B TWI598596B TW105140128A TW105140128A TWI598596B TW I598596 B TWI598596 B TW I598596B TW 105140128 A TW105140128 A TW 105140128A TW 105140128 A TW105140128 A TW 105140128A TW I598596 B TWI598596 B TW I598596B
- Authority
- TW
- Taiwan
- Prior art keywords
- fan
- probe card
- integrated circuit
- out structure
- test probe
- Prior art date
Links
- 239000000523 sample Substances 0.000 title claims description 152
- 238000012360 testing method Methods 0.000 title claims description 69
- 239000010410 layer Substances 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 13
- 238000003825 pressing Methods 0.000 claims description 8
- 230000007246 mechanism Effects 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 6
- 239000013013 elastic material Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 230000003139 buffering effect Effects 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910021389 graphene Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000009719 polyimide resin Substances 0.000 claims description 3
- 229920001296 polysiloxane Polymers 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 2
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 230000001629 suppression Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 6
- 230000008439 repair process Effects 0.000 description 5
- 230000008054 signal transmission Effects 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 241000270295 Serpentes Species 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
- G01R1/07371—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate card or back card with apertures through which the probes pass
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07357—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with flexible bodies, e.g. buckling beams
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Measuring Leads Or Probes (AREA)
Description
本發明係關於一種測試探針卡，特別是關於一種積體電路之測試探針卡。 The present invention relates to a test probe card, and more particularly to a test probe card for an integrated circuit.
隨著電子產品朝精密化與多功能化發展，在電子產品內的積體電路之晶片結構趨於複雜，而且該晶片結構的操作頻率也大幅提高，以用於更高頻率波段的電子產品領域。例如是圖1所示之積體電路的探針卡結構，一般稱為水平式探針卡(或是稱為cantilever probe card)，包括印刷電路板10、設置於該印刷電路板的固定環12、以及焊錫20焊接於印刷電路板10與的固定環12的多根排列探針14，該水平式探針卡透過垂直向下電性接觸晶圓16上晶片(未圖示)的接觸墊18，以測試每一晶片的功能是否正常。然而，每一探針係以人工焊接製作，而且由於受測晶片的尺寸日益縮減，其腳位的間距也一起縮小，相對地，探針之間的間距必須縮小，故探針的焊接施工更為不易，製作的時間更久。此外，當水平式探針卡使用一段時間之後，探針的磨耗而必須維修或是更換時，間距過度緊密的探針，不容易維修。因此需要提出一種新式的測試探針卡，以解決上述之問題。 As electronic products are becoming more sophisticated and multi-functional, the wafer structure of integrated circuits in electronic products tends to be complex, and the operating frequency of the wafer structure is also greatly increased for use in electronic products in higher frequency bands. . For example, the probe card structure of the integrated circuit shown in FIG. 1 is generally referred to as a horizontal probe card (also referred to as a cantilever probe card), and includes a printed circuit board 10 and a fixing ring 12 disposed on the printed circuit board. And a plurality of alignment probes 14 soldered to the printed circuit board 10 and the fixing ring 12, the horizontal probe card transmitting the contact pads 18 of the wafer (not shown) on the wafer 16 through the vertical downward electrical contact. To test whether the function of each wafer is normal. However, each probe is made by hand soldering, and since the size of the wafer under test is decreasing, the pitch of the pins is also reduced. In contrast, the spacing between the probes must be reduced, so the welding of the probe is more complicated. It's not easy, it takes longer to make. In addition, when the horizontal probe card is used for a period of time, the probe is worn out and must be repaired or replaced, the probe with too tight spacing is not easy to repair. Therefore, a new type of test probe card needs to be proposed to solve the above problems.
本發明之一目的在於提供一種積體電路之測試探針卡，藉由 一探針座與一扇出結構之連接構成新式的探針卡結構(Modifying Cantilever Probe Card,MCPC)，以縮短現有水平式探針卡(Cantilever Probe Card,CPC)的製作時間，並且容易維修測試探針卡及其裝設的探針。 An object of the present invention is to provide a test probe card for an integrated circuit by using The connection between a probe holder and a fan-out structure constitutes a new Modification Cantilever Probe Card (MCPC) to shorten the production time of the existing Cantilever Probe Card (CPC) and is easy to repair and test. Probe card and its installed probe.
本發明之另一目的在於提供一種積體電路之測試探針卡，藉由在探針訊號的傳輸路徑中設計應用電路及/或做阻抗控制，使本發明的探針卡結構適用於高頻/高速訊號傳輸作應用。 Another object of the present invention is to provide a test probe card for an integrated circuit, which is adapted to a high frequency by designing an application circuit and/or impedance control in a transmission path of a probe signal. / High-speed signal transmission for applications.
本發明之又一目的在於提供一種積體電路之探針卡，藉由測試探針卡的探針以垂直方向朝晶片的測試點，故可避免產生橫向刮痕，有助於後段封裝作業的良率提升。 Another object of the present invention is to provide a probe card for an integrated circuit. By testing the probe of the probe card in a vertical direction toward the test point of the wafer, lateral scratches can be avoided, which is helpful for the post-packaging operation. Yield improvement.
為達成上述目的，本發明之一實施例中積體電路的測試探針卡，包括一探針座，設有複數插孔以及插接於該些插孔中的複數探針；以及一扇出結構，電性連接該探針座，包括：一電路載體，固接於該探針座；及複數線路，設置於該電路載體上，每一該些線路包括一第一接觸墊、一第二接觸墊、以及電性連接該第一接觸墊與該第二接觸墊之間的一連接線，該些探針在該電路載體上相對應電性抵住於該扇出結構的該些第一接觸墊，其中相鄰兩探針之第一間距小於該些線路的相鄰兩個第二接觸墊之第二間距；一電路板，該扇出結構設置於該探針座與該電路板之間，該電路板設有複數層間導通孔結構，用以電性連接該些線路的該些第二接觸墊；以及一壓制機構，設置於該扇出結構上並且相鄰該探針座，用以固定該扇出結構於該電路板上。 In order to achieve the above object, a test probe card of an integrated circuit according to an embodiment of the present invention includes a probe holder, a plurality of jacks and a plurality of probes inserted into the jacks; and a fan-out The structure is electrically connected to the probe holder, and includes: a circuit carrier fixed to the probe holder; and a plurality of lines disposed on the circuit carrier, each of the lines including a first contact pad and a second a contact pad, and a connection line electrically connected between the first contact pad and the second contact pad, the probes correspondingly electrically resisting the first of the fan-out structures on the circuit carrier a contact pad, wherein a first pitch of adjacent two probes is smaller than a second pitch of adjacent two second contact pads of the lines; a circuit board, the fan-out structure is disposed on the probe holder and the circuit board The circuit board is provided with a plurality of interlayer via structures for electrically connecting the second contact pads of the lines; and a pressing mechanism disposed on the fan-out structure and adjacent to the probe holder. To fix the fan-out structure on the circuit board.
在一實施例中，每一該些探針包括第一端部以及相對於該第一端部的第二端部，該第二端部以該垂直方向電性抵住於一晶片的測試點。 In one embodiment, each of the probes includes a first end and a second end opposite the first end, the second end electrically resisting a test point of a wafer in the vertical direction .
在一實施例中，每一該些探針的第一端部以垂直方向電性抵住每一該些線路的第一接觸墊。 In one embodiment, the first ends of each of the probes electrically resist the first contact pads of each of the lines in a vertical direction.
在一實施例中，該扇出結構的該連接線係設置於該電路載體的表面上並且介於該探針座與該扇出結構之間。 In an embodiment, the connecting line of the fan-out structure is disposed on a surface of the circuit carrier and between the probe holder and the fan-out structure.
在一實施例中，該扇出結構還包括一調諧電路，設置於該些線路之間，用以調諧該些探針的特性阻抗。 In one embodiment, the fan-out structure further includes a tuning circuit disposed between the lines for tuning the characteristic impedance of the probes.
在一實施例中，該調諧電路包括一電容元件或是一接地區域，以電性連接於該第一接觸墊與第二接觸墊之間。 In one embodiment, the tuning circuit includes a capacitive element or a grounding region electrically connected between the first contact pad and the second contact pad.
在一實施例中，該些線路的材質係為導電材質。 In an embodiment, the materials of the lines are made of a conductive material.
在一實施例中，該導電材質係為金屬或石墨烯材質。 In one embodiment, the conductive material is a metal or graphene material.
在一實施例中，該金屬材質係選自銅、銀以及金所組成的族群。 In one embodiment, the metal material is selected from the group consisting of copper, silver, and gold.
在一實施例中，該扇出結構還包括一保護層，設置於該電路載體上，用以保護該些線路。 In an embodiment, the fan-out structure further includes a protective layer disposed on the circuit carrier to protect the lines.
在一實施例中，該保護層的材質包括環氧樹脂或是聚亞醯胺樹脂。 In an embodiment, the material of the protective layer comprises an epoxy resin or a polyimide resin.
在一實施例中，該扇出結構係為單層電路板或是多層電路板。 In one embodiment, the fan-out structure is a single layer circuit board or a multilayer circuit board.
在一實施例中，該電路板的每一該些層間導通孔結構包括一第三接觸墊以及一第四接觸墊，該第三接觸墊用以電性連接該扇出結構的該些第二接觸墊，以使該些探針的訊號經由該第三接觸墊以及該第四接觸墊傳輸至一測試機台。 In one embodiment, each of the inter-layer via structures of the circuit board includes a third contact pad and a fourth contact pad, the third contact pad electrically connecting the second portions of the fan-out structure The pads are contacted to transmit signals of the probes to the test machine via the third contact pads and the fourth contact pads.
在一實施例中，該電路板還包括一防焊層，用以覆蓋該電路板的表面，並且曝露該些層間導通孔結構的複數第四接觸墊。 In one embodiment, the circuit board further includes a solder mask for covering the surface of the circuit board and exposing the plurality of fourth contact pads of the interlayer via structures.
在一實施例中，該壓制機構還包括一第一螺絲組，用以固定該扇出結構於該電路板上。 In an embodiment, the pressing mechanism further includes a first set of screws for fixing the fan-out structure on the circuit board.
在一實施例中，測試探針卡還包括一緩衝層，設置於該扇出結構的該電路載體與該電路板之間，用以緩衝該扇出結構受到該探針座所施加的外力。 In one embodiment, the test probe card further includes a buffer layer disposed between the circuit carrier of the fan-out structure and the circuit board for buffering an external force applied by the probe housing.
在一實施例中，測試探針卡還包括一第二螺絲組，用以固定該扇出結構與該探針座。 In an embodiment, the test probe card further includes a second set of screws for securing the fan-out structure and the probe holder.
在一實施例中，測試探針卡還包括一彈性材質層，設置於該探針座與該扇出結構之間，以提高該探針座與該扇出結構之間的壓制效果。 In one embodiment, the test probe card further includes an elastic material layer disposed between the probe holder and the fan-out structure to improve the pressing effect between the probe holder and the fan-out structure.
在一實施例中，該彈性材質層係為矽膠或是橡膠。 In one embodiment, the elastic material layer is silicone or rubber.
10‧‧‧印刷電路板 10‧‧‧Printed circuit board
12‧‧‧固定環 12‧‧‧Fixed ring
14‧‧‧探針 14‧‧‧ probe
16‧‧‧晶圓 16‧‧‧ Wafer
18‧‧‧接觸墊 18‧‧‧Contact pads
20‧‧‧焊錫 20‧‧‧ solder
200‧‧‧探針座 200‧‧‧ probe holder
202‧‧‧扇出結構 202‧‧‧Fan-out structure
204‧‧‧插孔 204‧‧‧ jack
206‧‧‧探針 206‧‧‧Probe
206a‧‧‧第一端部 206a‧‧‧First end
206b‧‧‧第二端部 206b‧‧‧second end
208‧‧‧晶片 208‧‧‧ wafer
210‧‧‧測試點 210‧‧‧Test points
212‧‧‧電路載體 212‧‧‧Circuit carrier
214‧‧‧線路 214‧‧‧ lines
214a‧‧‧第一接觸墊 214a‧‧‧First contact pad
214b‧‧‧第二接觸墊 214b‧‧‧second contact pad
214c‧‧‧連接線 214c‧‧‧Connecting line
214d‧‧‧調諧電路 214d‧‧‧Tune circuit
214e‧‧‧線路區域 214e‧‧‧Line area
214f‧‧‧接地區域 214f‧‧‧ Grounding area
216‧‧‧壓制機構 216‧‧‧Compression institutions
220‧‧‧電路板 220‧‧‧Circuit board
220a‧‧‧第三接觸墊 220a‧‧‧3rd contact pad
220b‧‧‧第四接觸墊 220b‧‧‧fourth contact pad
221‧‧‧層間導通孔結構 221‧‧‧Interlayer via structure
222‧‧‧緩衝層 222‧‧‧buffer layer
223‧‧‧防焊層 223‧‧‧ solder mask
224a‧‧‧第一螺絲組 224a‧‧‧First Screw Set
224b‧‧‧第二螺絲組 224b‧‧‧Second screw set
226‧‧‧傳輸路徑 226‧‧‧Transmission path
400‧‧‧測點 400‧‧‧Measurement points
P1‧‧‧第一間距 P1‧‧‧ first spacing
P2‧‧‧第二間距 P2‧‧‧Second spacing
VD‧‧‧垂直方向 VD‧‧‧ vertical direction
為了更清楚地說明本發明實施例中的技術方案，下面將對實施例描述中所需要使用的附圖作簡單地介紹： In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below:
圖1繪示習知技術的積體電路的探針卡結構。 FIG. 1 illustrates a probe card structure of an integrated circuit of the prior art.
圖2繪示本發明實施例中積體電路的測試探針卡之示意圖。 2 is a schematic diagram of a test probe card of an integrated circuit in an embodiment of the present invention.
圖3A-3B繪示本發明實施例中測試探針卡的扇出結構之示意圖。 3A-3B are schematic diagrams showing the fan-out structure of the test probe card in the embodiment of the present invention.
圖4A-4D繪示本發明實施例中積體電路的測試點類型之示意圖。 4A-4D are schematic diagrams showing types of test points of an integrated circuit in an embodiment of the present invention.
請參照圖式，其中相同的元件符號代表相同的元件或是相似 的元件，本發明的原理是以實施在適當的運算環境中來舉例說明。以下的說明是基於所例示的本發明具體實施例，其不應被視為限制本發明未在此詳述的其它具體實施例。 Please refer to the drawings, in which the same component symbols represent the same components or similar The elements of the invention are illustrated by the implementation of the appropriate computing environment. The following description is based on the specific embodiments of the invention, which are not to be construed as limiting the invention.
參考圖2以及圖3，圖2繪示本發明實施例中積體電路的測試探針卡之示意圖，圖3A繪示本發明實施例中測試探針卡的扇出結構之示意圖。該積體電路例如是具有測試點210的晶片208。積體電路的測試探針卡包括探針座200、扇出結構202、電路板220以及壓制機構216。該測試探針卡上的探針座200設有複數插孔204以及相對應插接於該些插孔204中的複上數探針206。在一實施例中，每一探針206包括第一端部206a以及一第二端部206b，其中第一端部206a以及第二端部206b分別定位於探針座200下方以及上方的插孔204中，其中定位方式例如是探針206卡接於插孔204，並且當晶片208的測試點210接觸該第二端部206b時，該探針206在探針座200中產生撓性移動，使探針206的第二端部206b頂住該測試點210，提供更佳的接觸，以檢測該晶片的電氣特性。在一較佳實施例中，每一探針206的第二端部206b以該垂直方向VD電性抵住於一晶片208的測試點210，藉由測試探針卡的探針206以垂直方向VD朝晶片208的測試點210，有效避免測試點210產生橫向(即水平方向)的刮痕，以確保晶片208的測試點210之完整性，有助於後段封裝作業的良率提升。 Referring to FIG. 2 and FIG. 3, FIG. 2 is a schematic diagram of a test probe card of an integrated circuit according to an embodiment of the present invention, and FIG. 3A is a schematic diagram showing a fan-out structure of a test probe card according to an embodiment of the present invention. The integrated circuit is, for example, a wafer 208 having test points 210. The test probe card of the integrated circuit includes a probe holder 200, a fan-out structure 202, a circuit board 220, and a pressing mechanism 216. The probe holder 200 on the test probe card is provided with a plurality of jacks 204 and a plurality of probes 206 correspondingly plugged into the jacks 204. In one embodiment, each probe 206 includes a first end 206a and a second end 206b, wherein the first end 206a and the second end 206b are respectively positioned below and above the probe holder 200 204, wherein the positioning mode is, for example, that the probe 206 is engaged with the insertion hole 204, and when the test point 210 of the wafer 208 contacts the second end portion 206b, the probe 206 generates a flexible movement in the probe holder 200, The second end 206b of the probe 206 is placed against the test point 210 to provide better contact to detect the electrical characteristics of the wafer. In a preferred embodiment, the second end 206b of each probe 206 electrically resists the test point 210 of a wafer 208 in the vertical direction VD, by testing the probe 206 of the probe card in a vertical direction. The VD faces the test point 210 of the wafer 208, effectively preventing the test point 210 from producing lateral (i.e., horizontal) scratches to ensure the integrity of the test point 210 of the wafer 208, which contributes to the yield improvement of the back-end packaging operation.
如圖2以及圖3A所示，扇出結構202電性連接該探針座200，扇出結構202包括電路載體212以及複數線路214，電路載體212例如是電路基板，複數線路214設置於該電路載體212上，每一線路214包括一第一接觸墊214a、一第二接觸墊214b、以及電性連接該第一接觸墊214a與該第二接觸 墊214b之間的一連接線214c，該些探206針在該電路載體212上(例如是上表面)相對應電性抵住於該扇出結構202的該些第一接觸墊214a，其中相鄰兩探針206之第一間距P1小於該些線路214的相鄰兩個第二接觸墊214b之第二間距P2。 As shown in FIG. 2 and FIG. 3A, the fan-out structure 202 is electrically connected to the probe holder 200. The fan-out structure 202 includes a circuit carrier 212 and a plurality of circuits 214. The circuit carrier 212 is, for example, a circuit board, and the plurality of lines 214 are disposed on the circuit. Each of the lines 214 includes a first contact pad 214a, a second contact pad 214b, and electrically connected to the first contact pad 214a and the second contact. A connecting line 214c between the pads 214b, the probes 206 are electrically corresponding to the first contact pads 214a of the fan-out structure 202 on the circuit carrier 212 (for example, the upper surface), wherein the phases The first pitch P1 of the adjacent two probes 206 is smaller than the second pitch P2 of the adjacent two second contact pads 214b of the lines 214.
如圖2以及圖3A所示，該扇出結構202設置於該探針座200與該電路板220之間，該電路板220設有複數層間導通孔結構221，用以電性連接該些線路的該些第二接觸墊214b。壓制機構216設置於該扇出結構202上並且相鄰該探針座200，用以固定該扇出結構202於該電路板220上。 As shown in FIG. 2 and FIG. 3A, the fan-out structure 202 is disposed between the probe base 200 and the circuit board 220. The circuit board 220 is provided with a plurality of interlayer via structures 221 for electrically connecting the lines. The second contact pads 214b. The pressing mechanism 216 is disposed on the fan-out structure 202 and adjacent to the probe holder 200 for fixing the fan-out structure 202 on the circuit board 220.
在一較佳實施例中，該探針座200係以一垂直方向VD電性結合於該扇出結構202，使每一該些探針206的第一端部206a以該垂直方向VD電性抵住於每一線路214的每一第一接觸墊214a。在一實施例中，圖3A所示之扇出結構202係以半導體微影製程加工方式形成，以依據電路設計需求形成不同配置方式的線路214。其中相鄰的該些探針206之第一間距P1小於該些線路214的相鄰該些第二接觸墊214b之第二間距P2有助於在電路板220設計出所需要的層間導通孔結構221，以形成探針206、線路214以及層間導通孔結構221訊號傳輸路徑。 In a preferred embodiment, the probe holder 200 is electrically coupled to the fan-out structure 202 in a vertical direction VD, such that the first end portion 206a of each of the probes 206 is electrically connected to the vertical direction. Each first contact pad 214a of each line 214 is received. In one embodiment, the fan-out structure 202 illustrated in FIG. 3A is formed in a semiconductor lithography process to form lines 214 of different configurations in accordance with circuit design requirements. The first pitch P1 of the adjacent probes 206 is smaller than the second pitch P2 of the adjacent second contact pads 214b of the lines 214 to help design the required interlayer via structure 221 on the circuit board 220. To form the probe 206, the line 214, and the interlayer via structure 221 signal transmission path.
在一實施例中，本發明可透過人工植針或是自動化植針方式將探針206定位於探針座200，改善習知技術中探針206的磨耗而必須維修或是更換間距過度緊密的探針，造成不容易維修之問題。更重要的是，本發明之積體電路之測試探針卡，藉由一探針座200與一扇出結構202之電性連接構成新式的探針卡結構(MCPC)，以縮短現有水平式探針卡(CPC)的製作時間，並且容易維修測試探針卡。在不同的實施例中，探針206可為市場上 各種樣式的探針組成探針座200，例如是彈簧針、線針、眼鏡蛇型態(cobra)探針、以及微機電技術(MEMS)所製造而成的探針，以與本發明的結構組合成新式的探針卡結構(MCPC)。 In one embodiment, the present invention can position the probe 206 to the probe base 200 by means of manual needle implantation or automated needle implantation, which improves the wear of the probe 206 in the prior art and must be repaired or replaced with an excessively tight pitch. The probe causes problems that are not easy to repair. More importantly, the test probe card of the integrated circuit of the present invention is electrically connected to a fan-out structure 202 to form a new probe card structure (MCPC) to shorten the existing horizontal level. The probe card (CPC) is produced at a time and the test probe card is easy to repair. In various embodiments, the probe 206 can be on the market Probes of various styles constitute probe holder 200, such as a spring pin, a wire needle, a cobra probe, and a probe fabricated by microelectromechanical technology (MEMS) to combine with the structure of the present invention. A new probe card structure (MCPC).
如圖2以及圖3A所示，該扇出結構202的該連接線214c係設置於該電路載體212的表面上並且介於該探針座200與該扇出結構202之間。如圖2以及圖3B所示，圖3B繪示本發明實施例中測試探針卡的扇出結構202之示意圖，該扇出結構202還包括一調諧(tuning)電路214d，設置於該些線路214之間，用以調諧該些探針206的特性阻抗，讓終端的晶片208的阻抗值達到匹配的狀態。在一實施例中，該調諧電路214d包括線路區域214e以及/或是接地區域214f，以供電子零件(例如電容、電感以及電阻等零件)擺放，以電性連接於該第一接觸墊214a與第二接觸墊214b之間。本發明之積體電路之測試探針卡，藉由在探針訊號的傳輸路徑中設計應用電路及/或做阻抗控制，使本發明的探針卡結構適用於高頻/高速訊號傳輸作應用。如圖2、圖3A以及圖3B所示，該些線路214的材質係為導電材質，該導電材質係為金屬或石墨烯材質，而該金屬材質係選自銅、銀以及金所組成的族群。該扇出結構202還包括一保護層(未圖示)，設置於該電路載體212上(例如是上表面)，用以保護該些線路，該保護層的材質例如是環氧樹脂(epoxy)或是聚亞醯胺樹脂(polyimide)，但不限於此。如圖2所示，該扇出結構係為單層電路板。在另一實施例中，該扇出結構202係為多層電路板。例如當晶片208的腳位間距縮小或是測點數目增加時，或是扇出結構202的佈線空間不足時，透過增加扇出結構的層數來進行不同腳位間距的轉換，其中該扇出結構202的該些不同層之間例如是以盲孔(即層與層之間的通孔)來建立連接結 構。 As shown in FIG. 2 and FIG. 3A, the connecting line 214c of the fan-out structure 202 is disposed on the surface of the circuit carrier 212 and interposed between the probe holder 200 and the fan-out structure 202. As shown in FIG. 2 and FIG. 3B, FIG. 3B is a schematic diagram of a fan-out structure 202 of a test probe card according to an embodiment of the present invention. The fan-out structure 202 further includes a tuning circuit 214d disposed on the lines. Between 214, the characteristic impedance of the probes 206 is tuned to bring the impedance values of the wafer 208 of the terminal to a matching state. In one embodiment, the tuning circuit 214d includes a line region 214e and/or a ground region 214f for electronic components (such as capacitors, inductors, and resistors) to be electrically connected to the first contact pad 214a. Between the second contact pad 214b. The test probe card of the integrated circuit of the present invention applies the application circuit and/or impedance control in the transmission path of the probe signal, so that the probe card structure of the invention is suitable for high frequency/high speed signal transmission application. . As shown in FIG. 2, FIG. 3A and FIG. 3B, the materials of the lines 214 are made of a conductive material, and the conductive material is made of metal or graphene, and the metal material is selected from the group consisting of copper, silver and gold. . The fan-out structure 202 further includes a protective layer (not shown) disposed on the circuit carrier 212 (for example, an upper surface) for protecting the wires. The material of the protective layer is, for example, epoxy. Or polyimide resin, but is not limited to this. As shown in FIG. 2, the fan-out structure is a single-layer circuit board. In another embodiment, the fan-out structure 202 is a multilayer circuit board. For example, when the pitch of the pad 208 is reduced or the number of measuring points is increased, or when the wiring space of the fan-out structure 202 is insufficient, the pitch of different pin positions is converted by increasing the number of layers of the fan-out structure, wherein the fan-out The connection between the different layers of the structure 202 is, for example, a blind via (ie, a via between the layers). Structure.
繼續參考圖2，該電路板220的每一該些層間導通孔結構221包括一第三接觸墊220a以及一第四接觸墊220b，該第三接觸墊220a用以電性連接該扇出結構202的該些第二接觸墊214b，以使該些探針206的訊號經由該第三接觸墊220a以及該第四接觸墊220b透過傳輸路徑226傳輸至一測試機台(未圖示)。該電路板220還包括一防焊層223，用以覆蓋該電路板220的表面，並且曝露該些層間導通孔結構221的複數第四接觸墊220b以供該測試機台連接。該扇出結構202的表面亦可提供後續應用電路上的焊接零件之運用。 With reference to FIG. 2, each of the inter-layer via structures 221 of the circuit board 220 includes a third contact pad 220a and a fourth contact pad 220b. The third contact pad 220a is electrically connected to the fan-out structure 202. The second contact pads 214b are configured to transmit the signals of the probes 206 to the test machine (not shown) through the transmission path 226 via the third contact pads 220a and the fourth contact pads 220b. The circuit board 220 further includes a solder resist layer 223 for covering the surface of the circuit board 220 and exposing the plurality of fourth contact pads 220b of the interlayer via structures 221 for the test machine to be connected. The surface of the fan-out structure 202 can also provide for the use of soldered parts on subsequent application circuits.
繼續參考圖2，該壓制機構216還包括第一螺絲組224a，用以固定該扇出結構202於該電路板220上。在一實施例中，測試探針卡還包括緩衝層222，設置於該扇出結構202的該電路載體212與該電路板220之間，用以緩衝該扇出結構202受到該探針座200所施加的外力，該緩衝層222例如是具有預定厚度的薄膜或是支撐板件。在一實施例中，測試探針卡還包括第二螺絲組224b，用以固定該扇出結構202與該探針座200，或是固定該扇出結構202、緩衝層222以及該探針座200，如圖2所示。在一實施例中，測試探針卡還包括一彈性材質層(未圖示)，設置於該探針座200與該扇出結構202之間，以提高該探針座200與該扇出結構202之間的壓制效果。該彈性材質層例如是矽膠或是橡膠。 With continued reference to FIG. 2, the pressing mechanism 216 further includes a first set of screws 224a for securing the fan-out structure 202 to the circuit board 220. In one embodiment, the test probe card further includes a buffer layer 222 disposed between the circuit carrier 212 of the fan-out structure 202 and the circuit board 220 for buffering the fan-out structure 202 from the probe holder 200. The buffer layer 222 is, for example, a film having a predetermined thickness or a support plate member. In one embodiment, the test probe card further includes a second set of screws 224b for fixing the fan-out structure 202 and the probe holder 200, or fixing the fan-out structure 202, the buffer layer 222, and the probe holder. 200, as shown in Figure 2. In an embodiment, the test probe card further includes an elastic material layer (not shown) disposed between the probe holder 200 and the fan-out structure 202 to improve the probe holder 200 and the fan-out structure. The suppression effect between 202. The elastic material layer is, for example, silicone or rubber.
圖4A-4D繪示本發明實施例中積體電路的測試點類型之示意圖。周邊型積體電路(例如是晶片208)的測點400例如是兩邊並列形狀，如圖4A所示之周邊型積體電路。或是周邊型積體電路(例如是晶片208)的測點 400例如是四邊之方形排列形狀，如圖4B所示。例如是圖4C所示之測點400的陣列形狀，或是圖4D所示之測點400的類陣列形狀。上述之測點400可為任意形狀。在其他實施例中，測點400可為圓形排列形狀(未圖示)，但是不限於此。 4A-4D are schematic diagrams showing types of test points of an integrated circuit in an embodiment of the present invention. The measuring point 400 of the peripheral integrated circuit (for example, the wafer 208) is, for example, a side-by-side shape, as shown in FIG. 4A. Or a measuring point of a peripheral integrated circuit (for example, wafer 208) 400 is, for example, a square arrangement shape of four sides as shown in FIG. 4B. For example, the array shape of the measuring point 400 shown in FIG. 4C or the array-like shape of the measuring point 400 shown in FIG. 4D. The aforementioned measuring point 400 can be any shape. In other embodiments, the measuring point 400 may be a circular array shape (not shown), but is not limited thereto.
綜上所述，本發明之積體電路之測試探針卡，藉由一探針座與一扇出結構之連接構成新式的探針卡結構(MCPC)，以縮短現有水平式探針卡(CPC)的製作時間，並且容易維修測試探針卡及其裝設的探針。並且利用在探針訊號的傳輸路徑中設計應用電路及/或做阻抗控制，使本發明的探針卡結構適用於高頻/高速訊號傳輸作應用。同時藉由測試探針卡的探針以垂直方向朝晶片的測試點，故可避免產生橫向刮痕，有助於後段封裝作業的良率提升。 In summary, the test probe card of the integrated circuit of the present invention forms a new probe card structure (MCPC) by connecting a probe holder and a fan-out structure to shorten the existing horizontal probe card ( CPC) production time, and easy to repair the test probe card and its installed probe. Moreover, the application of the application circuit and/or the impedance control in the transmission path of the probe signal makes the probe card structure of the present invention suitable for high frequency/high speed signal transmission applications. At the same time, by testing the probe card's probe in the vertical direction toward the test point of the wafer, lateral scratches can be avoided, which helps the yield of the back-end packaging operation.
雖然本發明已用較佳實施例揭露如上，然其並非用以限定本發明，本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the invention has been described above in terms of the preferred embodiments, the invention is not intended to limit the invention, and the invention may be practiced without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.
200‧‧‧探針座 200‧‧‧ probe holder
202‧‧‧扇出結構 202‧‧‧Fan-out structure
204‧‧‧插孔 204‧‧‧ jack
206‧‧‧探針 206‧‧‧Probe
206a‧‧‧第一端部 206a‧‧‧First end
206b‧‧‧第二端部 206b‧‧‧second end
208‧‧‧晶片 208‧‧‧ wafer
210‧‧‧測試點 210‧‧‧Test points
212‧‧‧電路載體 212‧‧‧Circuit carrier
214‧‧‧線路 214‧‧‧ lines
214a‧‧‧第一接觸墊 214a‧‧‧First contact pad
214b‧‧‧第二接觸墊 214b‧‧‧second contact pad
214c‧‧‧連接線 214c‧‧‧Connecting line
216‧‧‧壓制機構 216‧‧‧Compression institutions
220‧‧‧電路板 220‧‧‧Circuit board
220a‧‧‧第三接觸墊 220a‧‧‧3rd contact pad
220b‧‧‧第四接觸墊 220b‧‧‧fourth contact pad
221‧‧‧層間導通孔結構 221‧‧‧Interlayer via structure
222‧‧‧緩衝層 222‧‧‧buffer layer
223‧‧‧防焊層 223‧‧‧ solder mask
224a‧‧‧第一螺絲組 224a‧‧‧First Screw Set
224b‧‧‧第二螺絲組 224b‧‧‧Second screw set
226‧‧‧傳輸路徑 226‧‧‧Transmission path
P1‧‧‧第一間距 P1‧‧‧ first spacing
P2‧‧‧第二間距 P2‧‧‧Second spacing
VD‧‧‧垂直方向 VD‧‧‧ vertical direction
Claims (19)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105140128A TWI598596B (en) | 2016-12-05 | 2016-12-05 | Testing probe card for integrated circuit |
| CN201710066112.0A CN108152544A (en) | 2016-12-05 | 2017-02-06 | Probe card for testing integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105140128A TWI598596B (en) | 2016-12-05 | 2016-12-05 | Testing probe card for integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI598596B true TWI598596B (en) | 2017-09-11 |
| TW201821808A TW201821808A (en) | 2018-06-16 |
Family
ID=60719491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW105140128A TWI598596B (en) | 2016-12-05 | 2016-12-05 | Testing probe card for integrated circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108152544A (en) |
| TW (1) | TWI598596B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI690253B (en) * | 2018-11-06 | 2020-04-01 | 鈺橋半導體股份有限公司 | Interconnect substrate having stress modulator and flip chip assembly thereof and manufacturing methods thereof |
| CN111721979B (en) * | 2019-03-18 | 2023-05-23 | 台湾中华精测科技股份有限公司 | Probe card testing device and signal switching module thereof |
| CN111722093A (en) * | 2019-03-18 | 2020-09-29 | 中华精测科技股份有限公司 | Probe card testing device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6246245B1 (en) * | 1998-02-23 | 2001-06-12 | Micron Technology, Inc. | Probe card, test method and test system for semiconductor wafers |
| US6160412A (en) * | 1998-11-05 | 2000-12-12 | Wentworth Laboratories, Inc. | Impedance-matched interconnection device for connecting a vertical-pin integrated circuit probing device to integrated circuit test equipment |
| CN101551406A (en) * | 2008-04-02 | 2009-10-07 | 旺矽科技股份有限公司 | Probe card |
| CN101676733A (en) * | 2008-09-17 | 2010-03-24 | 汉民测试***科技股份有限公司 | Structure of probe card for integrated circuit test |
| CN102062794B (en) * | 2009-11-13 | 2014-05-14 | 旺矽科技股份有限公司 | Vertical probe card |
| US8878560B2 (en) * | 2010-12-30 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | High frequency probing structure |
| TWI560452B (en) * | 2012-09-28 | 2016-12-01 | Hermes Epitek Corp | Probe card for circuit-testing |
| TW201437642A (en) * | 2013-03-26 | 2014-10-01 | Mpi Corp | Manufacturing method of space converter for probe card |
-
2016
- 2016-12-05 TW TW105140128A patent/TWI598596B/en not_active IP Right Cessation
-
2017
- 2017-02-06 CN CN201710066112.0A patent/CN108152544A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CN108152544A (en) | 2018-06-12 |
| TW201821808A (en) | 2018-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI620936B (en) | Testing probe card for integrated circuit | |
| US10459007B2 (en) | Probe card | |
| TWI596346B (en) | Probe device of vertical probe card | |
| JP3343549B2 (en) | Contact structure having silicon finger contactor and integrated assembly structure using the same | |
| JP4862017B2 (en) | Relay board, manufacturing method thereof, probe card | |
| CN102012470B (en) | Electrical test adapter plate of sealing base plate and method thereof | |
| TWI483361B (en) | Chip packaging substrate and chip packaging structure | |
| TW201831909A (en) | Probe card for high-frequency applications | |
| TWI598596B (en) | Testing probe card for integrated circuit | |
| TW201606322A (en) | Socket for testing semiconductor device | |
| JP4343256B1 (en) | Manufacturing method of semiconductor device | |
| JP2005010147A (en) | Module with inspection function, and its inspection method | |
| US20140333336A1 (en) | Testing of electronic devices through capacitive interface | |
| KR101683016B1 (en) | Test socket and method for manufacturing thereof | |
| JP4944982B2 (en) | Semiconductor wafer inspection method and semiconductor device manufacturing method | |
| US8988092B2 (en) | Probing apparatus for semiconductor devices | |
| JP2001127256A (en) | Semiconductor device | |
| TWM553422U (en) | Vertical probe card and probe head for wafer test | |
| KR101416477B1 (en) | Probe card | |
| JP2011038930A (en) | Probe card and test method of device to be inspected | |
| JP4492976B2 (en) | Semiconductor device | |
| JP2010098046A (en) | Probe card and method for manufacturing semiconductor device | |
| KR101199704B1 (en) | Contacting apparatus for testing a semiconductor device | |
| JP5185686B2 (en) | Probe and probe manufacturing method | |
| JP4877465B2 (en) | Semiconductor device, semiconductor device inspection method, semiconductor wafer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |