TW201821808A - Testing probe card for integrated circuit - Google Patents

Testing probe card for integrated circuit Download PDF

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Publication number
TW201821808A
TW201821808A TW105140128A TW105140128A TW201821808A TW 201821808 A TW201821808 A TW 201821808A TW 105140128 A TW105140128 A TW 105140128A TW 105140128 A TW105140128 A TW 105140128A TW 201821808 A TW201821808 A TW 201821808A
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TW
Taiwan
Prior art keywords
probe card
fan
out structure
integrated circuit
item
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Application number
TW105140128A
Other languages
Chinese (zh)
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TWI598596B (en
Inventor
李文聰
林承銳
謝開傑
Original Assignee
中華精測科技股份有限公司
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Priority to TW105140128A priority Critical patent/TWI598596B/en
Priority to CN201710066112.0A priority patent/CN108152544A/en
Application granted granted Critical
Publication of TWI598596B publication Critical patent/TWI598596B/en
Publication of TW201821808A publication Critical patent/TW201821808A/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
    • G01R1/07371—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate card or back card with apertures through which the probes pass
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07357—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with flexible bodies, e.g. buckling beams

Abstract

A testing probe card for an integrated circuit is described. The manufacturing time of a conventional cantilever probe card (CPC) is minimized using a modifying cantilever probe card (MCPC) which is constructed by a probing housing and a fan-out structure. Furthermore, it is quite convenient to maintain the probe card for increasing the efficiency of a testing procedure. In addition, an application circuit and/or impedance control is configured to a signal transmission path of the probe device so that the probe card can be used in an application field of the high frequency/high speed. Moreover, the probe device of the probe card is perpendicular to the test pad of the chip to avoid scratches of the chip and thus to increase the yield rate during a backend packaging procedure.

Description

積體電路之測試探針卡    Test probe card for integrated circuit   

本發明係關於一種測試探針卡，特別是關於一種積體電路之測試探針卡。 The invention relates to a test probe card, in particular to a test probe card of an integrated circuit.

隨著電子產品朝精密化與多功能化發展，在電子產品內的積體電路之晶片結構趨於複雜，而且該晶片結構的操作頻率也大幅提高，以用於更高頻率波段的電子產品領域。例如是圖1所示之積體電路的探針卡結構，一般稱為水平式探針卡(或是稱為cantilever probe card)，包括印刷電路板10、設置於該印刷電路板的固定環12、以及焊錫20焊接於印刷電路板10與的固定環12的多根排列探針14，該水平式探針卡透過垂直向下電性接觸晶圓16上晶片(未圖示)的接觸墊18，以測試每一晶片的功能是否正常。然而，每一探針係以人工焊接製作，而且由於受測晶片的尺寸日益縮減，其腳位的間距也一起縮小，相對地，探針之間的間距必須縮小，故探針的焊接施工更為不易，製作的時間更久。此外，當水平式探針卡使用一段時間之後，探針的磨耗而必須維修或是更換時，間距過度緊密的探針，不容易維修。因此需要提出一種新式的測試探針卡，以解決上述之問題。 With the development of electronic products toward precision and multi-functionalization, the chip structure of integrated circuits in electronic products tends to be complicated, and the operating frequency of the chip structure is also greatly increased for use in the electronic product field of higher frequency bands. . For example, the probe card structure of the integrated circuit shown in FIG. 1 is generally called a horizontal probe card (or a cantilever probe card), and includes a printed circuit board 10 and a fixing ring 12 provided on the printed circuit board. And a plurality of probes 14 arranged with solder 20 soldered to the printed circuit board 10 and the fixing ring 12. The horizontal probe card electrically contacts the wafer (not shown) 18 on the wafer 16 through the contact pads 18 vertically downward. To test the function of each chip. However, each probe is made by manual welding, and as the size of the wafer under test is shrinking, the spacing between its pins is also shrinking. In contrast, the spacing between the probes must be reduced, so the welding of the probes is even more complicated. To make it difficult, it takes longer to make. In addition, when the horizontal probe card is used for a period of time and the probe wears out and must be repaired or replaced, an excessively close-spaced probe is not easy to repair. Therefore, a new type of test probe card is needed to solve the above problems.

本發明之一目的在於提供一種積體電路之測試探針卡，藉由 一探針座與一扇出結構之連接構成新式的探針卡結構(Modifying Cantilever Probe Card,MCPC)，以縮短現有水平式探針卡(Cantilever Probe Card,CPC)的製作時間，並且容易維修測試探針卡及其裝設的探針。 One object of the present invention is to provide a test probe card for integrated circuits, which forms a new type of Modifying Cantilever Probe Card (MCPC) by connecting a probe base and a fan-out structure to shorten the current level. Manufacturing time of the Cantilever Probe Card (CPC), and easy to repair the test probe card and its installed probe.

本發明之另一目的在於提供一種積體電路之測試探針卡，藉由在探針訊號的傳輸路徑中設計應用電路及/或做阻抗控制，使本發明的探針卡結構適用於高頻/高速訊號傳輸作應用。 Another object of the present invention is to provide a test probe card for an integrated circuit. By designing an application circuit and / or impedance control in a transmission path of a probe signal, the probe card structure of the present invention is suitable for high frequency / High-speed signal transmission for applications.

本發明之又一目的在於提供一種積體電路之探針卡，藉由測試探針卡的探針以垂直方向朝晶片的測試點，故可避免產生橫向刮痕，有助於後段封裝作業的良率提升。 Another object of the present invention is to provide a probe card for an integrated circuit. By testing the probe card's probe head in a vertical direction toward a test point of a wafer, lateral scratches can be avoided, which facilitates subsequent packaging operations. Yield improvement.

為達成上述目的，本發明之一實施例中積體電路的測試探針卡，包括一探針座，設有複數插孔以及插接於該些插孔中的複數探針；以及一扇出結構，電性連接該探針座，包括：一電路載體，固接於該探針座；及複數線路，設置於該電路載體上，每一該些線路包括一第一接觸墊、一第二接觸墊、以及電性連接該第一接觸墊與該第二接觸墊之間的一連接線，該些探針在該電路載體上相對應電性抵住於該扇出結構的該些第一接觸墊，其中相鄰兩探針之第一間距小於該些線路的相鄰兩個第二接觸墊之第二間距；一電路板，該扇出結構設置於該探針座與該電路板之間，該電路板設有複數層間導通孔結構，用以電性連接該些線路的該些第二接觸墊；以及一壓制機構，設置於該扇出結構上並且相鄰該探針座，用以固定該扇出結構於該電路板上。 To achieve the above object, a test probe card for an integrated circuit according to an embodiment of the present invention includes a probe base provided with a plurality of jacks and a plurality of probes inserted in the jacks; and a fan-out The structure, which is electrically connected to the probe base, includes: a circuit carrier fixedly connected to the probe base; and a plurality of lines disposed on the circuit carrier, each of these lines including a first contact pad and a second A contact pad, and a connection line electrically connected between the first contact pad and the second contact pad, the probes on the circuit carrier correspondingly electrically resist the first contacts of the fan-out structure A contact pad, wherein a first distance between two adjacent probes is smaller than a second distance between two adjacent second contact pads of the lines; a circuit board, and the fan-out structure is disposed between the probe base and the circuit board The circuit board is provided with a plurality of interlayer vias structures for electrically connecting the second contact pads of the lines; and a pressing mechanism disposed on the fan-out structure and adjacent to the probe base, The fan-out structure is fixed on the circuit board.

在一實施例中，每一該些探針包括第一端部以及相對於該第一端部的第二端部，該第二端部以該垂直方向電性抵住於一晶片的測試點。 In one embodiment, each of the probes includes a first end portion and a second end portion opposite to the first end portion, and the second end portion electrically resists a test point of a wafer in the vertical direction. .

在一實施例中，每一該些探針的第一端部以垂直方向電性抵住每一該些線路的第一接觸墊。 In one embodiment, the first ends of each of the probes electrically resist the first contact pads of each of the circuits in a vertical direction.

在一實施例中，該扇出結構的該連接線係設置於該電路載體的表面上並且介於該探針座與該扇出結構之間。 In one embodiment, the connection line of the fan-out structure is disposed on a surface of the circuit carrier and is interposed between the probe base and the fan-out structure.

在一實施例中，該扇出結構還包括一調諧電路，設置於該些線路之間，用以調諧該些探針的特性阻抗。 In one embodiment, the fan-out structure further includes a tuning circuit disposed between the lines for tuning the characteristic impedance of the probes.

在一實施例中，該調諧電路包括一電容元件或是一接地區域，以電性連接於該第一接觸墊與第二接觸墊之間。 In one embodiment, the tuning circuit includes a capacitive element or a ground region, and is electrically connected between the first contact pad and the second contact pad.

在一實施例中，該些線路的材質係為導電材質。 In one embodiment, the materials of the lines are conductive materials.

在一實施例中，該導電材質係為金屬或石墨烯材質。 In one embodiment, the conductive material is made of metal or graphene.

在一實施例中，該金屬材質係選自銅、銀以及金所組成的族群。 In one embodiment, the metal material is selected from the group consisting of copper, silver and gold.

在一實施例中，該扇出結構還包括一保護層，設置於該電路載體上，用以保護該些線路。 In one embodiment, the fan-out structure further includes a protection layer disposed on the circuit carrier to protect the circuits.

在一實施例中，該保護層的材質包括環氧樹脂或是聚亞醯胺樹脂。 In one embodiment, the material of the protective layer includes epoxy resin or polyurethane resin.

在一實施例中，該扇出結構係為單層電路板或是多層電路板。 In one embodiment, the fan-out structure is a single-layer circuit board or a multi-layer circuit board.

在一實施例中，該電路板的每一該些層間導通孔結構包括一第三接觸墊以及一第四接觸墊，該第三接觸墊用以電性連接該扇出結構的該些第二接觸墊，以使該些探針的訊號經由該第三接觸墊以及該第四接觸墊傳輸至一測試機台。 In an embodiment, each of the interlayer via structures of the circuit board includes a third contact pad and a fourth contact pad, and the third contact pad is used to electrically connect the second ones of the fan-out structure. The contact pads, so that the signals of the probes are transmitted to a testing machine through the third contact pads and the fourth contact pads.

在一實施例中，該電路板還包括一防焊層，用以覆蓋該電路板的表面，並且曝露該些層間導通孔結構的複數第四接觸墊。 In one embodiment, the circuit board further includes a solder mask layer to cover the surface of the circuit board and expose the plurality of fourth contact pads of the interlayer via structures.

在一實施例中，該壓制機構還包括一第一螺絲組，用以固定該扇出結構於該電路板上。 In one embodiment, the pressing mechanism further includes a first screw set for fixing the fan-out structure on the circuit board.

在一實施例中，測試探針卡還包括一緩衝層，設置於該扇出結構的該電路載體與該電路板之間，用以緩衝該扇出結構受到該探針座所施加的外力。 In one embodiment, the test probe card further includes a buffer layer disposed between the circuit carrier and the circuit board of the fan-out structure to buffer the fan-out structure from external force applied by the probe base.

在一實施例中，測試探針卡還包括一第二螺絲組，用以固定該扇出結構與該探針座。 In one embodiment, the test probe card further includes a second screw set for fixing the fan-out structure and the probe base.

在一實施例中，測試探針卡還包括一彈性材質層，設置於該探針座與該扇出結構之間，以提高該探針座與該扇出結構之間的壓制效果。 In one embodiment, the test probe card further includes an elastic material layer disposed between the probe base and the fan-out structure to improve the pressing effect between the probe base and the fan-out structure.

在一實施例中，該彈性材質層係為矽膠或是橡膠。 In one embodiment, the elastic material layer is silicon rubber or rubber.

10‧‧‧印刷電路板 10‧‧‧printed circuit board

12‧‧‧固定環 12‧‧‧ retaining ring

14‧‧‧探針 14‧‧‧ Probe

16‧‧‧晶圓 16‧‧‧ wafer

18‧‧‧接觸墊 18‧‧‧ contact pad

20‧‧‧焊錫 20‧‧‧Soldering

200‧‧‧探針座 200‧‧‧ Probe Block

202‧‧‧扇出結構 202‧‧‧fan-out structure

204‧‧‧插孔 204‧‧‧jack

206‧‧‧探針 206‧‧‧ Probe

206a‧‧‧第一端部 206a‧‧‧first end

206b‧‧‧第二端部 206b‧‧‧Second end

208‧‧‧晶片 208‧‧‧Chip

210‧‧‧測試點 210‧‧‧test points

212‧‧‧電路載體 212‧‧‧circuit carrier

214‧‧‧線路 214‧‧‧ route

214a‧‧‧第一接觸墊 214a‧‧‧First contact pad

214b‧‧‧第二接觸墊 214b‧‧‧Second contact pad

214c‧‧‧連接線 214c‧‧‧connecting cable

214d‧‧‧調諧電路 214d‧‧‧ Tuning Circuit

214e‧‧‧線路區域 214e‧‧‧ route area

214f‧‧‧接地區域 214f‧‧‧ Grounding area

216‧‧‧壓制機構 216‧‧‧Repression Agency

220‧‧‧電路板 220‧‧‧Circuit Board

220a‧‧‧第三接觸墊 220a‧‧‧Third contact pad

220b‧‧‧第四接觸墊 220b‧‧‧Fourth contact pad

221‧‧‧層間導通孔結構 221‧‧‧Interlayer via structure

222‧‧‧緩衝層 222‧‧‧Buffer layer

223‧‧‧防焊層 223‧‧‧Solder mask

224a‧‧‧第一螺絲組 224a‧‧‧first screw set

224b‧‧‧第二螺絲組 224b‧‧‧Second screw set

226‧‧‧傳輸路徑 226‧‧‧Transmission path

400‧‧‧測點 400‧‧‧ measuring points

P1‧‧‧第一間距 P1‧‧‧First pitch

P2‧‧‧第二間距 P2‧‧‧Second Pitch

VD‧‧‧垂直方向 VD‧‧‧Vertical

為了更清楚地說明本發明實施例中的技術方案，下面將對實施例描述中所需要使用的附圖作簡單地介紹： In order to explain the technical solution in the embodiment of the present invention more clearly, the drawings used in the description of the embodiment will be briefly introduced below:

圖1繪示習知技術的積體電路的探針卡結構。 FIG. 1 illustrates a probe card structure of a conventional integrated circuit.

圖2繪示本發明實施例中積體電路的測試探針卡之示意圖。 FIG. 2 is a schematic diagram of a test probe card for an integrated circuit according to an embodiment of the present invention.

圖3A-3B繪示本發明實施例中測試探針卡的扇出結構之示意圖。 3A-3B are schematic diagrams illustrating a fan-out structure of a test probe card according to an embodiment of the present invention.

圖4A-4D繪示本發明實施例中積體電路的測試點類型之示意圖。 4A-4D are schematic diagrams illustrating types of test points of an integrated circuit according to an embodiment of the present invention.

請參照圖式，其中相同的元件符號代表相同的元件或是相似 的元件，本發明的原理是以實施在適當的運算環境中來舉例說明。以下的說明是基於所例示的本發明具體實施例，其不應被視為限制本發明未在此詳述的其它具體實施例。 Please refer to the drawings, wherein the same component symbols represent the same components or similar components. The principle of the present invention is exemplified by implementation in a suitable computing environment. The following description is based on the exemplified specific embodiments of the present invention, which should not be construed as limiting other specific embodiments of the present invention which are not described in detail herein.

參考圖2以及圖3，圖2繪示本發明實施例中積體電路的測試探針卡之示意圖，圖3A繪示本發明實施例中測試探針卡的扇出結構之示意圖。該積體電路例如是具有測試點210的晶片208。積體電路的測試探針卡包括探針座200、扇出結構202、電路板220以及壓制機構216。該測試探針卡上的探針座200設有複數插孔204以及相對應插接於該些插孔204中的複上數探針206。在一實施例中，每一探針206包括第一端部206a以及一第二端部206b，其中第一端部206a以及第二端部206b分別定位於探針座200下方以及上方的插孔204中，其中定位方式例如是探針206卡接於插孔204，並且當晶片208的測試點210接觸該第二端部206b時，該探針206在探針座200中產生撓性移動，使探針206的第二端部206b頂住該測試點210，提供更佳的接觸，以檢測該晶片的電氣特性。在一較佳實施例中，每一探針206的第二端部206b以該垂直方向VD電性抵住於一晶片208的測試點210，藉由測試探針卡的探針206以垂直方向VD朝晶片208的測試點210，有效避免測試點210產生橫向(即水平方向)的刮痕，以確保晶片208的測試點210之完整性，有助於後段封裝作業的良率提升。 Referring to FIG. 2 and FIG. 3, FIG. 2 is a schematic diagram of a test probe card of an integrated circuit in an embodiment of the present invention, and FIG. 3A is a schematic diagram of a fan-out structure of a test probe card in an embodiment of the present invention. The integrated circuit is, for example, a wafer 208 having a test point 210. The test probe card of the integrated circuit includes a probe base 200, a fan-out structure 202, a circuit board 220, and a pressing mechanism 216. The probe base 200 on the test probe card is provided with a plurality of jacks 204 and a plurality of probes 206 correspondingly inserted in the jacks 204. In one embodiment, each probe 206 includes a first end portion 206a and a second end portion 206b, wherein the first end portion 206a and the second end portion 206b are respectively positioned under the probe socket 200 and above the sockets. In 204, the positioning method is, for example, that the probe 206 is snapped into the socket 204, and when the test point 210 of the wafer 208 contacts the second end portion 206b, the probe 206 generates a flexible movement in the probe holder 200. The second end portion 206b of the probe 206 is pressed against the test point 210 to provide better contact to detect the electrical characteristics of the wafer. In a preferred embodiment, the second end portion 206b of each probe 206 electrically resists the test point 210 of a chip 208 in the vertical direction VD, and the probe 206 of the probe card is tested in the vertical direction. The VD is directed toward the test point 210 of the wafer 208, which can effectively prevent the test point 210 from scratching horizontally (that is, horizontally) to ensure the integrity of the test point 210 of the wafer 208 and help improve the yield of the subsequent packaging operation.

如圖2以及圖3A所示，扇出結構202電性連接該探針座200，扇出結構202包括電路載體212以及複數線路214，電路載體212例如是電路基板，複數線路214設置於該電路載體212上，每一線路214包括一第一接觸墊214a、一第二接觸墊214b、以及電性連接該第一接觸墊214a與該第二接觸 墊214b之間的一連接線214c，該些探206針在該電路載體212上(例如是上表面)相對應電性抵住於該扇出結構202的該些第一接觸墊214a，其中相鄰兩探針206之第一間距P1小於該些線路214的相鄰兩個第二接觸墊214b之第二間距P2。 As shown in FIG. 2 and FIG. 3A, the fan-out structure 202 is electrically connected to the probe holder 200. The fan-out structure 202 includes a circuit carrier 212 and a plurality of lines 214. The circuit carrier 212 is, for example, a circuit substrate, and the plurality of lines 214 are disposed on the circuit. On the carrier 212, each circuit 214 includes a first contact pad 214a, a second contact pad 214b, and a connection line 214c electrically connecting the first contact pad 214a and the second contact pad 214b. The probe 206 pins corresponding to the first contact pads 214a of the fan-out structure 202 on the circuit carrier 212 (for example, the upper surface), wherein the first distance P1 between two adjacent probes 206 is smaller than the A second pitch P2 between two adjacent second contact pads 214b of the lines 214.

如圖2以及圖3A所示，該扇出結構202設置於該探針座200與該電路板220之間，該電路板220設有複數層間導通孔結構221，用以電性連接該些線路的該些第二接觸墊214b。壓制機構216設置於該扇出結構202上並且相鄰該探針座200，用以固定該扇出結構202於該電路板220上。 As shown in FIG. 2 and FIG. 3A, the fan-out structure 202 is disposed between the probe base 200 and the circuit board 220. The circuit board 220 is provided with a plurality of interlayer via structures 221 for electrically connecting the lines. The second contact pads 214b. The pressing mechanism 216 is disposed on the fan-out structure 202 and is adjacent to the probe base 200 to fix the fan-out structure 202 on the circuit board 220.

在一較佳實施例中，該探針座200係以一垂直方向VD電性結合於該扇出結構202，使每一該些探針206的第一端部206a以該垂直方向VD電性抵住於每一線路214的每一第一接觸墊214a。在一實施例中，圖3A所示之扇出結構202係以半導體微影製程加工方式形成，以依據電路設計需求形成不同配置方式的線路214。其中相鄰的該些探針206之第一間距P1小於該些線路214的相鄰該些第二接觸墊214b之第二間距P2有助於在電路板220設計出所需要的層間導通孔結構221，以形成探針206、線路214以及層間導通孔結構221訊號傳輸路徑。 In a preferred embodiment, the probe base 200 is electrically coupled to the fan-out structure 202 with a vertical VD, so that the first ends 206a of each of the probes 206 are electrically connected with the vertical VD. Abut each of the first contact pads 214 a of each of the lines 214. In one embodiment, the fan-out structure 202 shown in FIG. 3A is formed by a semiconductor lithography process, so as to form lines 214 in different configurations according to circuit design requirements. The first pitch P1 of the adjacent probes 206 is smaller than the second pitch P2 of the adjacent second contact pads 214b of the lines 214, which helps to design the required interlayer via structure 221 on the circuit board 220. To form a signal transmission path of the probe 206, the line 214, and the interlayer via structure 221.

在一實施例中，本發明可透過人工植針或是自動化植針方式將探針206定位於探針座200，改善習知技術中探針206的磨耗而必須維修或是更換間距過度緊密的探針，造成不容易維修之問題。更重要的是，本發明之積體電路之測試探針卡，藉由一探針座200與一扇出結構202之電性連接構成新式的探針卡結構(MCPC)，以縮短現有水平式探針卡(CPC)的製作時間，並且容易維修測試探針卡。在不同的實施例中，探針206可為市場上 各種樣式的探針組成探針座200，例如是彈簧針、線針、眼鏡蛇型態(cobra)探針、以及微機電技術(MEMS)所製造而成的探針，以與本發明的結構組合成新式的探針卡結構(MCPC)。 In one embodiment, the present invention can position the probe 206 on the probe base 200 by means of manual or automatic needle implantation. In order to improve the wear of the probe 206 in the conventional technology, it is necessary to repair or replace the closely spaced Probes cause problems that are not easy to repair. More importantly, the test probe card of the integrated circuit of the present invention forms a new type of probe card structure (MCPC) by electrically connecting a probe base 200 and a fan-out structure 202 to shorten the existing horizontal type. Probe card (CPC) manufacturing time and easy maintenance of test probe cards. In different embodiments, the probe 206 may be a probe holder 200 of various styles on the market, such as a pogo pin, a wire needle, a cobra probe, and a micro-electromechanical technology (MEMS) institute. The manufactured probe is combined with the structure of the present invention into a novel probe card structure (MCPC).

如圖2以及圖3A所示，該扇出結構202的該連接線214c係設置於該電路載體212的表面上並且介於該探針座200與該扇出結構202之間。如圖2以及圖3B所示，圖3B繪示本發明實施例中測試探針卡的扇出結構202之示意圖，該扇出結構202還包括一調諧(tuning)電路214d，設置於該些線路214之間，用以調諧該些探針206的特性阻抗，讓終端的晶片208的阻抗值達到匹配的狀態。在一實施例中，該調諧電路214d包括線路區域214e以及/或是接地區域214f，以供電子零件(例如電容、電感以及電阻等零件)擺放，以電性連接於該第一接觸墊214a與第二接觸墊214b之間。本發明之積體電路之測試探針卡，藉由在探針訊號的傳輸路徑中設計應用電路及/或做阻抗控制，使本發明的探針卡結構適用於高頻/高速訊號傳輸作應用。如圖2、圖3A以及圖3B所示，該些線路214的材質係為導電材質，該導電材質係為金屬或石墨烯材質，而該金屬材質係選自銅、銀以及金所組成的族群。該扇出結構202還包括一保護層(未圖示)，設置於該電路載體212上(例如是上表面)，用以保護該些線路，該保護層的材質例如是環氧樹脂(epoxy)或是聚亞醯胺樹脂(polyimide)，但不限於此。如圖2所示，該扇出結構係為單層電路板。在另一實施例中，該扇出結構202係為多層電路板。例如當晶片208的腳位間距縮小或是測點數目增加時，或是扇出結構202的佈線空間不足時，透過增加扇出結構的層數來進行不同腳位間距的轉換，其中該扇出結構202的該些不同層之間例如是以盲孔(即層與層之間的通孔)來建立連接結 構。 As shown in FIG. 2 and FIG. 3A, the connection line 214 c of the fan-out structure 202 is disposed on the surface of the circuit carrier 212 and is interposed between the probe base 200 and the fan-out structure 202. As shown in FIG. 2 and FIG. 3B, FIG. 3B shows a schematic diagram of the fan-out structure 202 of the test probe card in the embodiment of the present invention. The fan-out structure 202 further includes a tuning circuit 214d disposed on the lines. Between 214, it is used to tune the characteristic impedance of the probes 206, so that the impedance value of the chip 208 at the terminal reaches a matched state. In one embodiment, the tuning circuit 214d includes a line area 214e and / or a ground area 214f, and is arranged with power supply sub-components (such as capacitors, inductors, and resistors), and is electrically connected to the first contact pad 214a. And the second contact pad 214b. The test probe card of the integrated circuit of the present invention makes the probe card structure of the present invention suitable for high-frequency / high-speed signal transmission by designing an application circuit and / or impedance control in the transmission path of the probe signal. . As shown in FIG. 2, FIG. 3A and FIG. 3B, the material of the lines 214 is a conductive material, the conductive material is a metal or graphene material, and the metal material is selected from the group consisting of copper, silver and gold. . The fan-out structure 202 further includes a protective layer (not shown), which is disposed on the circuit carrier 212 (for example, the upper surface) to protect the circuits. The material of the protective layer is, for example, epoxy. It is also polyimide, but it is not limited to this. As shown in FIG. 2, the fan-out structure is a single-layer circuit board. In another embodiment, the fan-out structure 202 is a multilayer circuit board. For example, when the pin pitch of the chip 208 is reduced or the number of measurement points is increased, or when the wiring space of the fan-out structure 202 is insufficient, the number of layers of the fan-out structure is increased to perform different pin pitch conversions. The different layers of the structure 202 may be connected via blind holes (ie, vias between layers).

繼續參考圖2，該電路板220的每一該些層間導通孔結構221包括一第三接觸墊220a以及一第四接觸墊220b，該第三接觸墊220a用以電性連接該扇出結構202的該些第二接觸墊214b，以使該些探針206的訊號經由該第三接觸墊220a以及該第四接觸墊220b透過傳輸路徑226傳輸至一測試機台(未圖示)。該電路板220還包括一防焊層223，用以覆蓋該電路板220的表面，並且曝露該些層間導通孔結構221的複數第四接觸墊220b以供該測試機台連接。該扇出結構202的表面亦可提供後續應用電路上的焊接零件之運用。 With continued reference to FIG. 2, each of the interlayer via structures 221 of the circuit board 220 includes a third contact pad 220 a and a fourth contact pad 220 b. The third contact pad 220 a is used to electrically connect the fan-out structure 202. The second contact pads 214b, so that the signals of the probes 206 are transmitted to a test machine (not shown) through the transmission path 226 through the third contact pad 220a and the fourth contact pad 220b. The circuit board 220 further includes a solder mask layer 223 for covering the surface of the circuit board 220 and exposing the plurality of fourth contact pads 220 b of the interlayer via structures 221 for connection to the test machine. The surface of the fan-out structure 202 can also provide the use of welding parts on subsequent application circuits.

繼續參考圖2，該壓制機構216還包括第一螺絲組224a，用以固定該扇出結構202於該電路板220上。在一實施例中，測試探針卡還包括緩衝層222，設置於該扇出結構202的該電路載體212與該電路板220之間，用以緩衝該扇出結構202受到該探針座200所施加的外力，該緩衝層222例如是具有預定厚度的薄膜或是支撐板件。在一實施例中，測試探針卡還包括第二螺絲組224b，用以固定該扇出結構202與該探針座200，或是固定該扇出結構202、緩衝層222以及該探針座200，如圖2所示。在一實施例中，測試探針卡還包括一彈性材質層(未圖示)，設置於該探針座200與該扇出結構202之間，以提高該探針座200與該扇出結構202之間的壓制效果。該彈性材質層例如是矽膠或是橡膠。 With continued reference to FIG. 2, the pressing mechanism 216 further includes a first screw group 224 a for fixing the fan-out structure 202 on the circuit board 220. In one embodiment, the test probe card further includes a buffer layer 222 disposed between the circuit carrier 212 and the circuit board 220 of the fan-out structure 202 to buffer the fan-out structure 202 from the probe base 200. For the external force applied, the buffer layer 222 is, for example, a film having a predetermined thickness or a supporting plate. In one embodiment, the test probe card further includes a second screw set 224b for fixing the fan-out structure 202 and the probe base 200, or fixing the fan-out structure 202, the buffer layer 222, and the probe base. 200, as shown in Figure 2. In one embodiment, the test probe card further includes an elastic material layer (not shown) disposed between the probe base 200 and the fan-out structure 202 to improve the probe base 200 and the fan-out structure. The suppression effect between 202. The elastic material layer is, for example, silicone or rubber.

圖4A-4D繪示本發明實施例中積體電路的測試點類型之示意圖。周邊型積體電路(例如是晶片208)的測點400例如是兩邊並列形狀，如圖4A所示之周邊型積體電路。或是周邊型積體電路(例如是晶片208)的測點 400例如是四邊之方形排列形狀，如圖4B所示。例如是圖4C所示之測點400的陣列形狀，或是圖4D所示之測點400的類陣列形狀。上述之測點400可為任意形狀。在其他實施例中，測點400可為圓形排列形狀(未圖示)，但是不限於此。 4A-4D are schematic diagrams illustrating types of test points of an integrated circuit according to an embodiment of the present invention. The measurement point 400 of the peripheral integrated circuit (for example, the chip 208) is, for example, a side-by-side parallel shape, as shown in FIG. 4A. Alternatively, the measuring points 400 of the peripheral integrated circuit (for example, the chip 208) are, for example, a square array with four sides, as shown in FIG. 4B. For example, it is the array shape of the measuring point 400 shown in FIG. 4C, or the array-like shape of the measuring point 400 shown in FIG. 4D. The measurement points 400 described above can be of any shape. In other embodiments, the measurement points 400 may be in a circular array shape (not shown), but it is not limited thereto.

綜上所述，本發明之積體電路之測試探針卡，藉由一探針座與一扇出結構之連接構成新式的探針卡結構(MCPC)，以縮短現有水平式探針卡(CPC)的製作時間，並且容易維修測試探針卡及其裝設的探針。並且利用在探針訊號的傳輸路徑中設計應用電路及/或做阻抗控制，使本發明的探針卡結構適用於高頻/高速訊號傳輸作應用。同時藉由測試探針卡的探針以垂直方向朝晶片的測試點，故可避免產生橫向刮痕，有助於後段封裝作業的良率提升。 In summary, the test probe card of the integrated circuit of the present invention forms a new type of probe card structure (MCPC) by connecting a probe base and a fan-out structure to shorten the existing horizontal probe card ( (CPC) production time, and easy to repair the test probe card and its installed probe. In addition, by designing an application circuit and / or performing impedance control in the transmission path of the probe signal, the probe card structure of the present invention is suitable for high-frequency / high-speed signal transmission for applications. At the same time, by testing the probes of the probe card in a vertical direction toward the test points of the wafer, lateral scratches can be avoided, which helps to improve the yield of the subsequent packaging operation.

雖然本發明已用較佳實施例揭露如上，然其並非用以限定本發明，本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains may make various changes and modifications without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.

Claims (20)

一種積體電路的測試探針卡，包括：一探針座，設有複數插孔以及插接於該些插孔中的複數探針；以及一扇出結構，電性連接該探針座，包括：一電路載體，固接於該探針座；及複數線路，設置於該電路載體上，每一該些線路包括一第一接觸墊、一第二接觸墊、以及電性連接該第一接觸墊與該第二接觸墊之間的一連接線，該些探針在該電路載體上相對應電性抵住於該扇出結構的該些第一接觸墊，其中相鄰兩探針之第一間距小於該些線路的相鄰兩個第二接觸墊之第二間距；一電路板，該扇出結構設置於該探針座與該電路板之間，該電路板設有複數層間導通孔結構，用以電性連接該些線路的該些第二接觸墊；以及一壓制機構，設置於該扇出結構上並且相鄰該探針座，用以固定該扇出結構於該電路板上。     A test probe card for an integrated circuit includes: a probe base provided with a plurality of jacks and a plurality of probes inserted in the jacks; and a fan-out structure electrically connected to the probe base, The circuit carrier includes: a circuit carrier fixedly connected to the probe base; and a plurality of circuits disposed on the circuit carrier, each of the circuits including a first contact pad, a second contact pad, and an electrical connection to the first A connection line between the contact pad and the second contact pad, the probes correspondingly electrically resist the first contact pads of the fan-out structure on the circuit carrier, and two adjacent probes The first distance is smaller than the second distance between two adjacent second contact pads of the lines; a circuit board, the fan-out structure is disposed between the probe base and the circuit board, and the circuit board is provided with a plurality of interlayer conduction A hole structure for electrically connecting the second contact pads of the lines; and a pressing mechanism disposed on the fan-out structure and adjacent to the probe base for fixing the fan-out structure to the circuit board on.     如申請專利範圍第1項所述之積體電路的測試探針卡，其中每一該些探針包括第一端部以及相對於該第一端部的第二端部，該第二端部以該垂直方向電性抵住於一晶片的測試點。     The test probe card for an integrated circuit according to item 1 of the scope of patent application, wherein each of the probes includes a first end portion and a second end portion opposite to the first end portion, and the second end portion Electrically resist the test point of a wafer in the vertical direction.     如申請專利範圍第2項所述之積體電路的測試探針卡，其中每一該些探針的第一端部以垂直方向電性抵住每一該些線路的第一接觸墊。     According to the test probe card of the integrated circuit described in item 2 of the scope of patent application, the first ends of each of the probes electrically resist the first contact pads of each of the circuits in a vertical direction.     如申請專利範圍第1項所述之積體電路的測試探針卡，其中該扇出結構的該連接線係設置於該電路載體的表面上並且介於該探針座與該扇出結構之間。     The test probe card of the integrated circuit according to item 1 of the patent application scope, wherein the connection line of the fan-out structure is disposed on the surface of the circuit carrier and interposed between the probe base and the fan-out structure. between.     如申請專利範圍第1項所述之積體電路的測試探針卡，其中該扇出結構還包括一調諧電路，設置於該些線路之間，用以調諧該些探針的特性阻抗。     According to the test probe card of the integrated circuit described in item 1 of the patent application scope, the fan-out structure further includes a tuning circuit disposed between the lines for tuning the characteristic impedance of the probes.     如申請專利範圍第5項所述之積體電路的測試探針卡，其中該調諧電路包括一線路區域或是一接地區域，以電性連接於該第一接觸墊與該第二接觸墊之間。     The test probe card of the integrated circuit according to item 5 of the scope of patent application, wherein the tuning circuit includes a line area or a ground area, and is electrically connected to the first contact pad and the second contact pad. between.     如申請專利範圍第1項所述之積體電路的測試探針卡，其中該些線路的材質係為導電材質。     The test probe card of the integrated circuit as described in the first item of the patent application scope, wherein the materials of the circuits are conductive materials.     如申請專利範圍第7項所述之積體電路的測試探針卡，其中該導電材質係為金屬或是石墨烯材質。     The test probe card for an integrated circuit as described in item 7 of the scope of patent application, wherein the conductive material is a metal or a graphene material.     如申請專利範圍第8項所述之積體電路的測試探針卡，其中該金屬材質係選自銅、銀以及金所組成的族群。     The test probe card for an integrated circuit as described in item 8 of the scope of patent application, wherein the metal material is selected from the group consisting of copper, silver, and gold.     如申請專利範圍第1項所述之積體電路的測試探針卡，其中該扇出結構還包括一保護層，設置於該電路載體上，用以保護該些線路。     According to the integrated circuit test probe card described in item 1 of the patent application scope, wherein the fan-out structure further includes a protection layer disposed on the circuit carrier to protect the circuits.     如申請專利範圍第10項所述之積體電路的測試探針卡，其中該保護層的材質包括環氧樹脂或是聚亞醯胺樹脂。     According to the integrated circuit test probe card of claim 10, the material of the protective layer includes epoxy resin or polyurethane resin.     如申請專利範圍第1項所述之積體電路的測試探針卡，其中該扇出結構係為單層電路板。     The test probe card for an integrated circuit as described in item 1 of the patent application scope, wherein the fan-out structure is a single-layer circuit board.     如申請專利範圍第1項所述之積體電路的測試探針卡，其中該扇出結構係為多層電路板。     The test probe card of the integrated circuit according to item 1 of the patent application scope, wherein the fan-out structure is a multilayer circuit board.     如申請專利範圍第1項所述之積體電路的測試探針卡，其中該電路板的每一該些層間導通孔結構包括一第三接觸墊以及一第四接觸墊，該第 三接觸墊用以電性連接該扇出結構的該些第二接觸墊，以使該些探針的訊號經由該第三接觸墊以及該第四接觸墊傳輸至一測試機台。     The test probe card for an integrated circuit according to item 1 of the scope of patent application, wherein each of the interlayer via structures of the circuit board includes a third contact pad and a fourth contact pad, and the third contact pad It is used to electrically connect the second contact pads of the fan-out structure, so that the signals of the probes are transmitted to a test machine via the third contact pad and the fourth contact pad.     如申請專利範圍第14項所述之積體電路的測試探針卡，其中該電路板還包括一防焊層，用以覆蓋該電路板的表面，並且曝露該些層間導通孔結構的複數第四接觸墊。     The test probe card for an integrated circuit according to item 14 of the scope of the patent application, wherein the circuit board further includes a solder resist layer to cover the surface of the circuit board and expose a plurality of interlayer via structures Four contact pads.     如申請專利範圍第1項所述之積體電路的測試探針卡，其中該壓制機構還包括一第一螺絲組，用以固定該扇出結構於該電路板上。     According to the integrated circuit test probe card described in item 1 of the patent application scope, the pressing mechanism further includes a first screw group for fixing the fan-out structure on the circuit board.     如申請專利範圍第1項所述之積體電路的測試探針卡，還包括一緩衝層，設置於該扇出結構的該電路載體與該電路板之間，用以緩衝該扇出結構受到該探針座所施加的外力。     The test probe card for an integrated circuit as described in item 1 of the scope of the patent application, further comprising a buffer layer disposed between the circuit carrier of the fan-out structure and the circuit board to buffer the fan-out structure. External force applied by the probe base.     如申請專利範圍第1項所述之積體電路的測試探針卡，還包括一第二螺絲組，用以固定該扇出結構與該探針座。     The test probe card for integrated circuits as described in the first item of the patent application scope further includes a second screw set for fixing the fan-out structure and the probe base.     如申請專利範圍第18項所述之積體電路的測試探針卡，還包括一彈性材質層，設置於該探針座與該扇出結構之間，以提高該探針座與該扇出結構之間的壓制效果。     The test probe card of the integrated circuit according to item 18 of the scope of the patent application, further comprising an elastic material layer disposed between the probe base and the fan-out structure to improve the probe base and the fan-out Suppressive effects between structures.     如申請專利範圍第19項所述之積體電路的測試探針卡，其中該彈性材質層係為矽膠或是橡膠。     According to the integrated circuit test probe card described in item 19 of the patent application scope, wherein the elastic material layer is silicon rubber or rubber.    
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI690253B (en) * 2018-11-06 2020-04-01 鈺橋半導體股份有限公司 Interconnect substrate having stress modulator and flip chip assembly thereof and manufacturing methods thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111721979B (en) * 2019-03-18 2023-05-23 台湾中华精测科技股份有限公司 Probe card testing device and signal switching module thereof
CN111722093A (en) * 2019-03-18 2020-09-29 中华精测科技股份有限公司 Probe card testing device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6246245B1 (en) * 1998-02-23 2001-06-12 Micron Technology, Inc. Probe card, test method and test system for semiconductor wafers
US6160412A (en) * 1998-11-05 2000-12-12 Wentworth Laboratories, Inc. Impedance-matched interconnection device for connecting a vertical-pin integrated circuit probing device to integrated circuit test equipment
CN101551406A (en) * 2008-04-02 2009-10-07 旺矽科技股份有限公司 Probe card
CN101676733A (en) * 2008-09-17 2010-03-24 汉民测试***科技股份有限公司 Structure of probe card for integrated circuit test
CN102062794B (en) * 2009-11-13 2014-05-14 旺矽科技股份有限公司 Vertical probe card
US8878560B2 (en) * 2010-12-30 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. High frequency probing structure
TWI560452B (en) * 2012-09-28 2016-12-01 Hermes Epitek Corp Probe card for circuit-testing
TW201437642A (en) * 2013-03-26 2014-10-01 Mpi Corp Manufacturing method of space converter for probe card

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI690253B (en) * 2018-11-06 2020-04-01 鈺橋半導體股份有限公司 Interconnect substrate having stress modulator and flip chip assembly thereof and manufacturing methods thereof

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