TWI595585B - 暫時性複合式載板 - Google Patents
暫時性複合式載板 Download PDFInfo
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- TWI595585B TWI595585B TW105101709A TW105101709A TWI595585B TW I595585 B TWI595585 B TW I595585B TW 105101709 A TW105101709 A TW 105101709A TW 105101709 A TW105101709 A TW 105101709A TW I595585 B TWI595585 B TW I595585B
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- 239000002131 composite material Substances 0.000 title claims description 71
- 239000000758 substrate Substances 0.000 claims description 140
- 239000000463 material Substances 0.000 claims description 37
- 239000011521 glass Substances 0.000 claims description 25
- 239000010410 layer Substances 0.000 claims description 21
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- 239000011889 copper foil Substances 0.000 claims description 18
- -1 cemented carbide Chemical compound 0.000 claims description 17
- 229920000642 polymer Polymers 0.000 claims description 15
- 239000010935 stainless steel Substances 0.000 claims description 14
- 229910001220 stainless steel Inorganic materials 0.000 claims description 14
- 239000012790 adhesive layer Substances 0.000 claims description 12
- 229910045601 alloy Inorganic materials 0.000 claims description 12
- 239000000956 alloy Substances 0.000 claims description 12
- 239000010936 titanium Substances 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- 229910001374 Invar Inorganic materials 0.000 claims description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 10
- 229910052719 titanium Inorganic materials 0.000 claims description 10
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 9
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000000034 method Methods 0.000 description 26
- 239000000047 product Substances 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 8
- 230000008602 contraction Effects 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 238000001179 sorption measurement Methods 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000010420 art technique Methods 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 2
- 239000012050 conventional carrier Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000005086 pumping Methods 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
- B32B7/02—Physical, chemical or physicochemical properties
- B32B7/027—Thermal properties
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
- B32B7/04—Interconnection of layers
- B32B7/12—Interconnection of layers using interposed adhesives or interposed materials with bonding properties
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09136—Means for correcting warpage
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24777—Edge feature
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thermal Sciences (AREA)
- Laminated Bodies (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Description
本發明涉及半導體製程所使用的暫時性載板(temporary carrier),特別是一種暫時性複合式載板(Temporary Composite Carrier)。
圖1A顯示傳統載板1為單層材料所製成,載板1的上方提供半導體製程處理區域,圖中顯示一系列的增層(build-up layer)10製作於載板1的上表面。圖1A的範例顯示增層10包含電路15與介電材料16。其他不同產品,例如多晶片封裝的處理(圖中未表示)也可以放置在載板1上面,進行加工處理。在後續的程式中,成品或是半成品,會自載板1上方剝離,進行其他的處理常式,然後,載板1可以回收,再重新利用。
圖1B顯示更多增層10被製作了,形成增層105。載板1以及上面的增層105,在半導體製程中都必須經過多次加熱以及冷卻的過程;由於不同材料之間的熱膨脹係數(Coefficient of Thermal Expansion,CTE)不匹配的原因,於是,板翹(warpage)現象便會發生。如圖中所示,載板1以及上面的增層105呈現向上弧形彎曲的狀態。
圖1C顯示上面的增層105,在剝離載板1之後,仍然呈現向上弧形彎曲的狀態。這種彎曲的狀態,導致於後續製程在對位(registration)上的困難度大增,尤其是在半導體的愈來愈精細的製程中,例如納米(nano meter,nm)製程中,影響很大。
另外,傳統載板破裂時,大量碎片會對製程腔室(chamber)造成重大污染,一個更安全、無污染或是極少污染的更好載板,一直是半導體
研發工程師所關注並且企求尋找、改善的事情。
圖2顯示美國專利US8,893,378揭露的解決板翹的一個先前技藝,包含載板1以及真空吸附系統;真空吸附系統上方提供載板1放置用,真空吸附系統將載板1吸附使得載板1在後續製程中,經過多次加熱與冷卻,也可以保持平整,不會上下彎曲。利用載板本身的平整強度,克服或是減少上方產品在製程中產生板翹可能性。
載板1上方提供半導體製程使用,例如半導體增層(build-up)製程,可以在載板1上方製作。圖中真空吸附系統具有板架3於上方,抗熱密封材料11安置於板架3上方,載板1放置在抗熱密封材料11的上方;板架3具有通孔5。真空吸附系統具有氣體通道7,抽氣幫浦9抽氣時,氣體A經由通孔5、通道7流出去,而將載板1吸附著保持平整。此一先前技藝的缺點是設備複雜、體積大且昂貴,它至少包含了板架3與抽氣幫浦9;一個更簡單易行的方法被期待開發了。
針對現有技術的上述不足,根據本發明的實施例,希望提供一種在半導體製程中,用來抵抗上方製品的板翹現象,使其減少或是免除「板翹」(warpage)的暫時性複合式載板。
根據實施例,本發明提供的一種暫時性複合式載板,包含上層基板、下層基板和黏著層,其中:上層基板不具有電路,其材料選自於下述族群中的一種:因瓦合金、矽、合金42、氮化鋁、燒結碳化物、鋁、氧化鋁、鈦、二氧化鋯、玻璃、銅箔基板以及不銹鋼...等材料;下層基板亦不具有電路,其材料選自於下述族群中的一種:因瓦合金、矽、合金42、氮化鋁、燒結碳化物、鋁、氧化鋁、鈦、二氧化鋯、玻璃、銅箔基板以及不銹鋼...等材料。黏著
層設置於上層基板與下層基板的中間,使上層基板與下層基板互相黏合。
根據一個實施例,本發明前述暫時性複合式載板中,上層基板的厚度與下層基板的厚度相同。
根據一個實施例,本發明前述暫時性複合式載板中,上層基板的厚度比下層基板的厚度薄。
根據一個實施例,本發明前述暫時性複合式載板中,上層基板的厚度比下層基板的厚度厚。
根據一個實施例,本發明前述暫時性複合式載板中,上層基板的熱膨脹係數為1-4ppm,下層基板的熱膨脹係數為4.5-18ppm;或者下層基板的熱膨脹係數為1-4ppm,上層基板的熱膨脹係數為4.5-18ppm。
根據一個實施例,本發明前述暫時性複合式載板中,上層基板的材料選自於下述族群中的一種:因瓦合金、矽、玻璃和銅箔基板,下層基板的材料選自於下述族群中的一種:合金42、氮化鋁、燒結碳化物、鋁、氧化鋁、鈦、二氧化鋯、玻璃、銅箔基板以及不銹鋼;或者下層基板的材料選自於下述族群中的一種:因瓦合金、矽、玻璃和銅箔基板,上層基板的材料選自於下述族群中的一種:合金42、氮化鋁、燒結碳化物、鋁、氧化鋁、鈦、二氧化鋯、玻璃、銅箔基板以及不銹鋼。
根據一個實施例,本發明前述暫時性複合式載板中,進一步包含高分子聚合物,高分子聚合物包覆複合式載板周邊,自載板周邊向外圓滑凸出。
根據一個實施例,本發明前述暫時性複合式載板中,高分子聚合物具有一個高度與載板厚度切齊。
根據一個實施例,本發明前述暫時性複合式載板中,載板周邊板材轉角做倒角處理。
根據一個實施例,本發明前述暫時性複合式載板中,倒角呈斜面倒角或是弧面倒角。
相對於現有技術,本發明利用下層基板的熱膨脹係數(CTE)接近或是等於載板上方製品的熱膨脹係數(CTE),用來抵抗上方製品的板翹現象,使其減少或是免除「板翹」(warpage)。依據本發明,提供一個半導體製程的加工區域,使得一個成品、半成品、或是半導體增層的板翹問題可以被克服。本發明暫時性複合式載板包含至少兩片基材黏合在一起,這兩片基材具有的CTE不同。例如:上層基板具有相對較低的CTE、而下層基板具有相對較高的CTE。這樣的組合,下層基板的膨脹收縮可以接近上方製程的物品的膨脹收縮,而使得板翹程度可以減少或是免除。
本發明優點之一是安全,本發明暫時性複合式載板受撞擊以後,碎裂材料仍然會被中間黏合材料黏合在一起,不會污染製程小室(chamber)空間。
本發明優點之二是可以克服上方製品的板翹問題,本發明暫時性複合式載板的組合,例如:上層基板具有相對較低的CTE、而下層基板具有相對較高的CTE。這樣的組合,下層基板的膨脹收縮可以接近上方製程的物品的膨脹收縮,而使得板翹程度可以減少或是免除。
本發明優點之三是不同組合的選擇性,可以克服上方不同製品的板翹問題,本發明暫時性複合式載板的組合,可以選擇具有不同CTE的材料製成,用以匹配不同製程產品的CTE需求,而可以得到良好的克服板翹的效果。
15‧‧‧電路
16‧‧‧介電材料
20‧‧‧增層
200‧‧‧複合式載板
201‧‧‧複合式載板
202‧‧‧複合式載板
205‧‧‧增層
21T‧‧‧上層基板
21B‧‧‧下層基板
22‧‧‧黏著層
23‧‧‧上方區域
24‧‧‧高度
31T‧‧‧上層基板
31B‧‧‧下層基板
35T‧‧‧上層基板
35B‧‧‧下層基板
38‧‧‧高分子聚合物
392‧‧‧斜面
393‧‧‧弧面
圖1A-1C為傳統載板的結構示意圖。
圖2為解決板翹的一個先前技藝的示意圖。
圖3A-3C為增層製程在本發明的複合式載板上製作的狀態示意圖。
圖4A為本發明暫時性複合式載板第一實施例的結構示意圖。
圖4B為本發明暫時性複合式載板第二實施例的結構示意圖。
圖4C為本發明暫時性複合式載板第三實施例的結構示意圖。
圖5為本發明暫時性複合式載板第四實施例的結構示意圖。
圖6為本發明暫時性複合式載板第五實施例的結構示意圖。
圖7為本發明暫時性複合式載板第六實施例的結構示意圖。
圖8A-8C為本發明暫時性複合式載板的修飾版實施例的結構示意圖。
下面結合附圖和具體實施例,進一步闡述本發明。這些實施例應理解為僅用於說明本發明而不用於限制本發明的保護範圍。在閱讀了本發明記載的內容之後,本領域技術人員可以對本發明作各種改動或修改,這些等效變化和修改同樣落入本發明權利要求所限定的範圍。
圖3A-3C顯示增層製程在本發明的複合式載板上製作的狀態。
圖3A顯示增層(build-up layer)20製作於本發明的複合式載板200上,增層20包含有電路15與介電材料16,這通常是製作電路的起始步驟。
圖3B顯示更多增層製作於本發明的暫時性複合式載板200上,形成增層205於複合式載板200上方,其中,增層205包含有電路15與介電材料16。複合式載板200的上層基板21T與下層基板21B選用不同材料,例如:上層基板21T選用材料的CTE小於下層基板21B選用材料的CTE,且下層基板21B的CTE約略近似於上方增層205製品的整體CTE,則板翹
便可以被克服至最小,或是完全無板翹發生。
增層205製程只是一個範例說明而已,其中的金屬導線電路15的CTE約等於17ppm,介電材料16例如使用聚苯惡唑(Polybenzoxazole;PBO)、聚醯亞胺(Polyimide,PI)、或是苯環丁烯(benzocyclobutene,BCB),則它們的CTE約等於30ppm.整個增層205的CTE約等於20ppm。
本發明便是選擇適當的基板材料,使得下層基板21B的CTE接近上方增層205的整體CTE;並選用CTE比下層基板21B小的基板材料作為上層基板21T,使得下層基板21B與上方增層205的膨脹收縮至少有部分可以互相抵銷,使得製品205剝離複合式載板200之前,能夠減少或是免除「板翹」或是電路扭曲現象。
可以作為本發明基板的材料具有CTE在1-18ppm者,至少包含下述各種材料:因瓦合金(Invar,1ppm)、矽(Si,3ppm)、合金42(Alloy 42,4.8ppm)、氮化鋁(AlN,5ppm)、燒結碳化物(Cemented Carbide,5.5ppm)、鋁(Alumina,7.2ppm)、氧化鋁(Al2O3,7ppm)、鈦(Ti,8.6ppm)、二氧化鋯(Zirconia,10.5ppm)、玻璃(Glass,0-10ppm)、銅箔基板(CCL,1-17ppm)、以及不銹鋼(stainless steel,10-18ppm)。
其中具有較寬範圍的CTE,包含玻璃(Glass,0-10ppm)、銅箔基板(CCL,1-17ppm)、以及不銹鋼(stainless steel,10-18ppm)...等,具有一個CTE範圍區間者,乃系其個別可以依據不同的配方製成不同CTE的產品,因此,使用者可以選擇使用不同的CTE產品,例如選擇CTE為7-8ppm的產品使用。
圖3C顯示增層205自載板200剝離以後的狀態,比對於右邊的圖1C,圖3C產品減少了板翹如高度24所示,其中圖1C是在習知技藝的載板1上製作的增層105。
圖4A顯示本發明複合式載板的第一實施例。
圖4A顯示複合式載板200包含有上層基板21T、黏著層22、
與下層基板21B;其中,上層基板21T藉著黏著層22與下層基板21B黏合再一起,構成本發明的複合式載板。本發明的上層基板21T不具有電路。
本發明的下層基板21B,亦不具有電路。材料可以與上層基板21T相同或是不同。
本發明的複合式載板若是受到撞擊、不慎破裂時,由於中央黏著層22的黏著特性,沒有碎片會脫落或是只有極少碎片會脫落,不會對製程腔室(chamber)造成重大污染。
圖4B顯示本發明複合式載板的第二實施例。
圖4B顯示複合式載板201,具有上層基板21T、下層基板31B、以及黏著層22;其中,黏著層22位於中間,將上層基板21T與下層基板31B黏合再一起,形成一片安全基板。下層基板31B的厚度大於上層基板21T的厚度。較厚的下層基板31B,提供較強的抵抗力,用以克服上層基板21T上方區域23製程前後的物品所產生的板翹或是電路變形。
圖4C顯示本發明複合式載板的第三實施例。
圖4C顯示複合式載板202,具有上層基板31T、下層基板21B、以及黏著層22;其中,黏著層22位於中間,將上層基板31T與下層基板21B黏合再一起,形成一片安全基板。下層基板21B的厚度小於上層基板31T的厚度。較厚的上層基板31T,提供較強的抵抗力,用以克服上層基板31T上方區域23製程前後的物品所產生的板翹或是變形。
圖5顯示本發明複合式載板的第四實施例。
圖5顯示複合式載板的上層基板35T或是下層基板35B,可以選擇的基材包含一種具有CTE在1-18ppm者;上層基板35T以及下層基板35B可以是相同的材料或是不同的材料。
圖6顯示本發明複合式載板的第五實施例。
圖6顯示複合式載板的上層基板35T與下層基板35B,使用不同CTE的材料,圖中顯示上層基板35T選擇CTE在1-4ppm的材料、下
層基板35B選擇CTE在4.5-18ppm的材料。
CTE在1-4ppm的材料,包含:因瓦合金(Invar,1ppm)、矽(Si,3ppm)、玻璃(Glass,0-10ppm)、以及銅箔基板(CCL,1-17ppm);其中,玻璃(Glass,0-10ppm)系選擇其中的1-4ppm的玻璃,銅箔基板(CCL,1-17ppm)系選擇其中的1-4ppm的材料。
CTE在4.5-18ppm的材料,包含:合金42(Alloy 42,4.8ppm)、氮化鋁(AlN,5ppm)、燒結碳化物(Cemented Carbide,5.5ppm)、鋁(Alumina,7.2ppm)、氧化鋁(Al2O3,7ppm)、鈦(Ti,8.6ppm)、二氧化鋯(Zirconia,10.5ppm)、玻璃(Glass,0-10ppm)、銅箔基板(CCL,1-17ppm)、以及不銹鋼(stainless steel,10-18ppm)。其中,玻璃(Glass,0-10ppm)系選擇其中的4.8-10ppm的玻璃,銅箔基板(CCL,1-17ppm)系選擇其中的4.8-17ppm的材料。
圖7顯示本發明複合式載板的第六實施例。
圖7顯示複合式載板的上層基板35T與下層基板35B,使用不同CTE的材料,圖中顯示上層基板35T選擇CTE在4.5-18ppm的材料、下層基板35B選擇CTE在1-4ppm的材料。
圖8A-8C顯示本發明複合式載板的修飾版實施例。
圖8A顯示複合式載板的上層基板35T與下層基板35B的周邊截面,使用高分子聚合物38包覆著提高整體堅固特性。高分子聚合物38自載板周邊向外圓滑凸出,具有一個高度h與載板厚度t切齊。
圖8B顯示複合式載板的上層基板35T與下層基板35B的周邊截面轉角,做倒角(chamfer)處理。圖中顯示倒角為斜面392。
圖8C顯示複合式載板的上層基板35T與下層基板35B的周邊截面轉角,做倒角(chamfer)處理。圖中顯示倒角為弧面393。
22‧‧‧黏著層
23‧‧‧上方區域
35T‧‧‧上層基板
35B‧‧‧下層基板
Claims (17)
- 一種暫時性複合式載板,其特徵是,包含上層基板、下層基板和黏著層,其中:上層基板不具有電路,其材料選自於下述族群中的一種:因瓦合金、矽、合金42、氮化鋁、燒結碳化物、鋁、氧化鋁、鈦、二氧化鋯、玻璃、銅箔基板以及不銹鋼;下層基板不具有電路,其材料選自於下述族群中的一種:因瓦合金、矽、合金42、氮化鋁、燒結碳化物、鋁、氧化鋁、鈦、二氧化鋯、玻璃、銅箔基板以及不銹鋼;黏著層設置於上層基板與下層基板的中間,使上層基板與下層基板互相黏合。
- 如權利要求1所述的暫時性複合式載板,其特徵是,上層基板的厚度與下層基板的厚度相同。
- 如權利要求1所述的暫時性複合式載板,其特徵是,上層基板的厚度比下層基板的厚度薄。
- 如權利要求1所述的暫時性複合式載板,其特徵是,上層基板的厚度比下層基板的厚度厚。
- 如權利要求1所述的暫時性複合式載板,其特徵是,上層基板的熱膨脹係數為1-4ppm,下層基板的熱膨脹係數為4.5-18ppm;或者下層基板的熱膨脹係數為1-4ppm,上層基板的熱膨脹係數為4.5-18ppm。
- 如權利要求5所述的暫時性複合式載板,其特徵是,上層基板的材料選自於下述族群中的一種:因瓦合金、矽、玻璃和銅箔基板,下層基板的材料選自於下述族群中的一種:合金42、氮化鋁、燒結碳化物、鋁、氧化鋁、鈦、二氧化鋯、玻璃、銅箔基板以及不銹鋼;或者下層基板的材料選自於下述族群中的一種:因瓦合金、矽、玻璃和銅箔基板;上層基板的材料選自於下述族群中的一種:合金42、氮化鋁、燒結碳化物、鋁、氧化鋁、鈦、 二氧化鋯、玻璃、銅箔基板以及不銹鋼。
- 如權利要求6所述的暫時性複合式載板,其特徵是,上層基板的厚度與下層基板的厚度相同。
- 如權利要求6所述的暫時性複合式載板,其特徵是,上層基板的厚度比下層基板的厚度薄。
- 如權利要求6所述的暫時性複合式載板,其特徵是,上層基板的厚度比下層基板的厚度厚。
- 如權利要求1所述的暫時性複合式載板,其特徵是,進一步包含高分子聚合物,高分子聚合物包覆複合式載板周邊,自載板周邊向外圓滑凸出。
- 如權利要求10所述的暫時性複合式載板,其特徵是,高分子聚合物具有一個高度與載板厚度切齊。
- 如權利要求10所述的暫時性複合式載板,其特徵是,載板周邊板材轉角做倒角處理。
- 如權利要求12所述的暫時性複合式載板,其特徵是,倒角呈斜面倒角或是弧面倒角。
- 如權利要求6所述的暫時性複合式載板,其特徵是,進一步包含高分子聚合物,高分子聚合物包覆載板周邊垂直截面處,自載板周邊向外圓滑凸出。
- 如權利要求14所述的暫時性複合式載板,其特徵是,高分子聚合物具有一個高度與載板厚度切齊。
- 如權利要求14所述的暫時性複合式載板,其特徵是,載板周邊板材轉角做倒角處理。
- 如權利要求16所述的暫時性複合式載板,其特徵是,倒角呈斜面倒角或是弧面倒角。
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US20160254233A1 (en) | 2016-09-01 |
CN105931997A (zh) | 2016-09-07 |
US20190013280A1 (en) | 2019-01-10 |
US10304786B2 (en) | 2019-05-28 |
CN105931997B (zh) | 2019-02-05 |
US10109598B2 (en) | 2018-10-23 |
TW201631688A (zh) | 2016-09-01 |
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