TWI593065B - 封裝半導體裝置的方法及封裝的半導體裝置 - Google Patents
封裝半導體裝置的方法及封裝的半導體裝置 Download PDFInfo
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- TWI593065B TWI593065B TW103128557A TW103128557A TWI593065B TW I593065 B TWI593065 B TW I593065B TW 103128557 A TW103128557 A TW 103128557A TW 103128557 A TW103128557 A TW 103128557A TW I593065 B TWI593065 B TW I593065B
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- Prior art keywords
- barrier structure
- molding material
- integrated circuit
- dies
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Description
半導體裝置用於不同的電子應用中,例如個人電腦、手機、數位相機以及其他電子設備。典型係藉由在半導體基板上連續沉積絕緣或介電層、傳導層以及半導體材料層,並且使用微影製程將不同材料層圖案化,以於其上形成電路組件與元件,而製造半導體裝置。
在單一半導體晶圓上,典型製造數十或數百個積體電路。沿著切割線,藉由鋸該積體電路而將個別晶粒切單。而後,例如,分別將該個別晶粒封裝於多晶片模組或其他形式的封裝中。
半導體工業藉由持續縮小最小特徵尺寸,使得在給定面積中可集成較多組件,而持續改良不同電子組件(例如,電晶體、二極體、電阻器、電容器等)的積體密度。在一些應用中,這些較小的電子組件,例如積體電路晶粒,亦需要較小的封裝,相較於傳統的封裝,其使用較小的面積。晶片等級封裝(CSP)是一種較小的封裝技術形式。
本發明之一實施例描述一種封裝半導體裝置的方法,該方法包括:形成阻障結構於複數個晶粒上,接近該複數個晶粒的邊緣區域;使成型材料位於該複數個晶粒附近;以及移除該成型材料的頂部部分以及該阻障結構的頂部部分。
在一實施例中,其中移除該成型材料的該頂部部分與該阻障結
構之該頂部部分係包括研磨製程或化學機械拋光(CMP)製程。
在一實施例中,其中移除該成型材料的該頂部部分係包括移除接近該阻障結構之該成型材料的部分。
在一實施例中,其方法更包括在該複數個晶粒與該成型材料上方,形成互連結構。
在一實施例中,其方法更包括耦合複數個連接器至該互連結構。
在一實施例中,其中形成該互連結構係包括形成扇出區域。
在一實施例中,其中形成該互連結構係包括形成鈍化後互連(PPI)結構或是重佈層(RDL)。
本發明之一實施例描述一種封裝半導體裝置的方法,該方法包括:耦合複數個晶粒至載體;形成阻障結構於該複數個晶粒的每一個晶粒上,接近該複數個晶粒的邊緣區域;使成型材料位於該複數個晶粒附近的該載體上方;移除該成型材料的頂部部分與該阻障結構的頂部部分;形成互連結構於該複數個晶粒與該成型材料上方;移除該載體;以及切割該成型材料與該互連結構,形成複數個封裝的半導體裝置。
在一實施例中,其中在耦合該複數個晶粒至該載體之前,進行形成該阻障結構,或其中在耦合該複數個晶粒至該載體之後,進行形成該阻障結構。
在一實施例中,其中形成該阻障結構係包括選自於實質上由接合製程、微影製程、旋塗製程、沉積製程、層壓製程、形成該複數個晶粒之材料層的製程以及其組合所組成之群組的製程。
在一實施例中,其中該複數個晶粒的每一個晶粒係包括複數個接觸墊位於其上,該複數個接觸墊係包括第一高度,以及其中形成該阻障結構係包括形成具有第二高度的阻障結構,該第二高度係大於該
第一高度。
在一實施例中,其中移除該阻障結構的該頂部部分係包括形成具有第三高度的阻障結構,該第三高度係大於或約等同於該第一高度。
本發明之一實施例描述一種封裝的半導體裝置,包括:積體電路晶粒,其包含複數個接觸墊與阻障結構位於其上,該阻障結構係位於該複數個接觸墊附近,接近該積體電路晶粒的邊緣區域;成型材料,其係位於該積體電路晶粒與該阻障結構的附近;以及互連結構,其係位於該積體電路晶粒與該成型材料上方。
在一實施例中,其中該複數個接觸墊係包括第一高度,以及其中該阻障結構係包括第二高度,該第二高度係大於或約等同於該第一高度。
在一實施例中,其中該成型材料係實質包括接近該阻障結構的該第二高度。
在一實施例中,其中該積體電路晶粒係包括第一表面以及與該第一表面對立的第二表面,其中該複數個接觸墊與該阻障結構係位於該積體電路晶粒的該第一表面上,其中該成型材料係位於該積體電路晶粒的該第一表面上方,以及其中該成型材料係實質上與該積體電路晶粒的該第二表面共平面。
在一實施例中,其中該阻障結構係包括選自於由聚亞醯胺(PI)、聚苯噁唑(PBO)、底部填充(underfill,UF)材料、可圖案化的環氧化合物、不可移除的光阻、阻焊材料以及其組合所組成之群組的材料。
在一實施例中,其中該阻障結構係包括密封環結構。
在一實施例中,其中該阻障結構係包括實質上為直的側壁或錐形側壁。
在一實施例中,所述之封裝的半導體裝置更包括複數個該積體
電路晶粒,其中該成型材料係位於該複數個積體電路晶粒附近以及該複數個積體電路晶粒之間,以及其中該互連結構係位於該複數個積體電路晶粒與該成型材料上方。
前文已頗為廣泛地概述本發明之特徵及技術優勢以便可更好地理解隨後的本發明之詳細描述。本發明之額外特徵及優勢將在下文中加以描述,且形成本發明之申請專利範圍的主題。熟習此項技術者應瞭解,所揭示之概念及特定實施例可易於用作修改或設計其他結構或程序以用於進行本發明之同樣目的之基礎。熟習此項技術者亦應認識到,此等等效構造並不脫離如隨附申請專利範圍中所闡明之本發明之精神及範疇。
100‧‧‧積體電路晶粒
102‧‧‧基板
104‧‧‧接觸墊
106‧‧‧絕緣材料
110‧‧‧載體
112‧‧‧薄膜
114‧‧‧黏著劑
120‧‧‧阻障結構
120’‧‧‧阻障結構
122‧‧‧成型材料
124‧‧‧凹陷區域
126‧‧‧角部區域
128‧‧‧區域
129a‧‧‧第一表面
129b‧‧‧第二表面
130‧‧‧互連結構
130M‧‧‧傳導線
130M’‧‧‧傳導線
130D‧‧‧介電層
130V‧‧‧傳導孔
132’‧‧‧切割線
140‧‧‧半導體裝置
140’‧‧‧半導體裝置
142‧‧‧連接器
150‧‧‧工具
152‧‧‧成型框台
154‧‧‧成型框台
156‧‧‧活塞
由以下詳細說明與附隨圖式得以最佳了解本申請案揭示內容之各方面。注意,根據產業之標準實施方式,各種特徵並非依比例繪示。實際上,為了清楚討論,可任意增大或縮小各種特徵的尺寸。
圖1A與圖1B係根據本申請案揭示內容之一些實施方式說明將被封裝之積體電路晶粒的橫切面圖。
圖2至圖9係根據本申請案揭示內容之一些實施方式說明封裝半導體裝置之方法中各種階段的橫切面圖。
圖10係根據本申請案揭示內容之一些實施方式說明成型材料形成製程的橫切面圖。
圖11係根據本申請案揭示內容之一些實施方式說明封裝的半導體裝置之橫切面圖。
圖12A與圖12B係根據本申請案揭示內容之一些實施方式說明在積體電路晶粒上形成的阻障結構之俯視圖。
上文已經概略地敍述本揭露之技術特徵及優點,俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之
其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應可瞭解,下文揭示之概念與特定實施例可作為基礎而相當輕易地予以修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應可瞭解,這類等效的建構並無法脫離後附之申請專利範圍所提出之本揭露的精神和範圍。
以下揭示內容提供許多不同的實施方式或範例,用於實施本申請案之不同特徵。元件與配置的特定範例之描述如下,以簡化本申請案之揭示內容。當然,這些僅為範例,並非用於限制本申請案。例如,以下描述在第二特徵上或上方形成第一特徵可包含形成直接接觸的第一與第二特徵之實施方式,亦可包含在該第一與第二特徵之間形成其他特徵的實施方式,因而該第一與第二特徵並非直接接觸。此外,本申請案可在不同範例中重複元件符號與/或字母。此重複係為了簡化與清楚之目的,而非支配不同實施方式與/或所討論架構之間的關係。
再者,本申請案可使用空間對應語詞,例如「之下」、「低於」、「較低」、「高於」、「較高」等類似語詞之簡單說明,以描述圖式中一元件或特徵與另一元件或特徵的關係。空間對應語詞係用以包括除了圖式中描述的位向之外,裝置於使用或操作中之不同位向。裝置或可被定位(旋轉90度或是其他位向),並且可相應解釋本申請案使用的空間對應描述。
本申請案揭示內容之實施方式提供封裝半導體裝置的新方法及其結構,其中在晶粒附近形成成型材料之前,在接近積體電路晶粒的邊緣區域形成阻障結構。該阻障結構確保在該晶粒附近將施用足夠量的成型材料,改良後續互連結構的形成。
圖1A係根據本申請案揭示內容的一些實施方式說明將被封裝的半導體裝置之橫切面圖。為了封裝半導體裝置,首先,提供該半導體裝置。該半導體裝置包含積體電路晶粒100。例如,可先在半導體晶圓上製造積體電路晶粒100,並且該晶圓被切單或切割形成複數個積體電路晶粒100。積體電路晶粒100包含具有半導體材料的基板102,以及包含製造於其內與/或其上的電路、組件、接線及其他元件(未繪示)。例如,積體電路晶粒100係用於進行預定功能,例如邏輯、記憶、處理或其他功能、或其組合。在本申請案中,積體電路晶粒100亦係指晶粒100。
晶粒100包含複數個接觸墊104形成通過其頂部表面。複數個接觸墊104係位於基板102的表面上。接觸墊104電性耦合至部分的基板102。例如,接觸墊104包括傳導材料,例如銅、鋁、其他金屬、或合金或其多層。或者,接觸墊104可包括其他材料。
絕緣材料106係位於積體電路晶粒100之暴露的頂部表面上方以及部份的接觸墊104上方。絕緣材料106可包括一或多個絕緣材料層,例如二氧化矽、氮化矽、聚合物材料或其他材料。使用微影製程或其他製程將絕緣材料106圖案化,在接觸墊104的頂部表面上方形成開口,因而可形成與接觸墊104的電性連接。例如,在一些實施方式中,絕緣材料106包括鈍化層。
圖2、3、4、6、8與9係根據一些實施方式說明封裝半導體裝置之方法的各種階段之橫切面圖。圖5係更詳細繪示部分的圖4,以及圖7係更詳細繪示部分的圖6。
接著,參閱圖2,複數個晶粒100耦合至載體110。手動或使用例如撿放機器之自動機器,將積體電路晶粒100耦合至載體110。載體110具有薄膜112形成於其上。例如,薄膜112包括光熱轉換(LTHC)材料或其他材料。在一些實施方式中,未包含薄膜112。使用黏著劑114
或晶粒接合薄膜(DAF),將積體電路晶粒100耦合至載體110。例如,載體110可包括玻璃、氧化矽、氧化鋁或半導體晶圓。載體110亦可包括其他材料。
在一些實施方式中,積體電路晶粒100係耦合至載體110,並且被封裝於個別封裝中(請見圖9)。在其他實施方式中,可將二或多個積體電路晶粒100封裝再一起(請見圖11)。例如,根據一些實施方式,可將包括相同或不同功能的複數個積體電路晶粒100封裝在一起。
接著參閱圖3,根據本申請案揭示內容的一些實施方式,新的阻障結構120係位於晶粒100的第一表面129a上。該阻障結構120係形成於該複數個晶粒100的每一個上,接近該複數個晶粒100的邊緣區域。阻障結構120係位於接近積體電路晶粒100之邊緣區域的每一個晶粒100之複數個接觸墊104附近。複數個接觸墊104與阻障結構120係位於體電路晶粒100的第一表面129a上。接觸墊104包括含有尺寸d1的高度或厚度,其中在一些實施方式中,該尺寸d1包括約3微米或更小。或者,接觸墊104可包括其他尺寸。在本申請案中,例如在一些請求項中,尺寸d1亦係稱為第一高度。阻障結構120包括在晶粒100的每一邊緣處或靠近每一邊緣所形成之密封環結構。
在一些實施方式中,阻障結構120包括例如聚亞醯胺(PI)、聚苯噁唑(PBO)、底部填充(underfill,UF)材料、可圖案化的環氧化合物、不可移除的光阻、阻焊材料、或其組合物或多層之材料。在一些實施方式中,阻障結構120包括絕緣材料。或者,阻障結構120可包括傳導或半導體材料。阻障結構120包括形成在晶粒100附近的環,具有尺寸為d2的高度或厚度,其中在一些實施方式中,尺寸d2包括約3微米或更大。例如,在一些實施方式中,尺寸d2係大於接觸墊104的尺寸d1。在本申請案中,例如在一些請求項中,尺寸d2亦稱為第二高度。環形阻障結構120的側邊包括尺寸為d3的寬度,其中在一些實施
方式中,尺寸d3包括約2至10微米。或者,阻障結構120可包括其他材料與尺寸。
在圖1A、2與3所示的實施方式中,在晶粒100附接至載體110之後,阻障結構120附接或形成於晶粒100上。例如,在耦合複數個晶粒100至載體110之後,進行形成阻障結構120。或者,在其他實施方式中,在晶粒100附接至載體110之前,阻障結構120可附接或形成於晶粒100上。
例如,可提供圖1B所示的積體電路晶粒100,其已經具有阻障結構120形成於其上。例如,當晶粒100仍為晶圓形式或是在晶粒100切單之後,阻障結構120可形成於積體電路晶粒100上。而後,如圖3所示,含有阻障結構120的複數個晶粒100附接至載體110。因此,在一些實施方式中,在耦合複數個晶粒100至載體110之前,進行形成阻障結構120。
圖1B亦說明阻障結構120可具有錐形側壁或是實質上直的側壁,如圖1B中模擬(例如,虛線處)所示。在本申請案揭示內容的其他圖式中,繪示具有錐形側壁的阻障結構120;然而,或者,在每一圖式中的阻障結構120可具有實質上為直的側壁。例如,阻障結構120的錐形側壁之底部較頂部寬,然而,該實質上為直的側壁之底部與頂部則具有實質相同的寬度。
例如,無論在附接晶粒100至載體110之後(圖1A、2與3)或之前(圖1B與3)將阻障結構120形成於晶粒100上,可使用附接製程、微影製程、旋塗製程、沉積製程、層壓製程、形成複數個晶粒100之材料層的製程、以及/或其組合,將阻障結構120形成於晶粒100上。可使用黏著劑、膠帶、層壓或其他物質,預先形成或預先製造阻障結構120。或者,可使用例如化學蒸氣沉積(CVD)之沉積製程、旋塗製程、層壓阻障結構之材料、或其他方法,形成阻障結構120。而後,
使用微影製程、直接蝕刻製程或其他方法,將該材料圖案化,而將阻障結構120形成所欲之形狀。亦可使用其他方法形成阻障結構120。
而後,在積體電路晶粒100與阻障結構120附近,沉積成型材料122,如圖4所示。該成型材料122形成於載體110的暴露部分上方(例如,載體110上的薄膜112上方)、積體電路晶粒100的側壁上方、接近晶粒100之邊緣區域的阻障結構120外部的晶粒100之第一表面129a暴露部分上方,以及背向晶粒100之中心區的阻障結構120之側壁上方。例如,可使用壓縮成型、轉移成型或其他方法,將成型材料122成型。例如,成型材料122封裝積體電路晶粒100與阻障結構120。成型材料122可包括環氧化合物、有機聚合物、或是具有或不具有添加二氧化矽為基底或玻璃填充物之聚合物。在一些實施方式中,成型材料122包括液體成型化合物(LMC),其使用時係為膠體形式液體。使用時,成型材料122亦可包括液體或固體。或者,成型材料122可包括其他絕緣與/或封裝材料。
在使用成型材料122的過程中,阻障結構120係作為密封環。因此,成型材料122延伸至阻障結構120的側壁之頂部表面,其係背向晶粒100之中心區域。阻障結構120亦防止成型材料122到達晶粒100之中心區域中晶粒100的頂部表面,或是減少到達中心區域中晶粒100的頂部表面之成型材料量。
接著,在一些實施方式中,使用硬化製程,將成型材料122硬化。該硬化製程可包括使用退火製程或是其他加熱製程,將成型材料122加熱至預定溫度達一段預定時間。該硬化製程亦可包括紫外(UV)光暴露製程、紅外線(IR)能量暴露製程、其組合、或具有加熱製程之組合。或者,可使用其他方法硬化成型材料122。在一些實施方式中,未包含硬化製程。
在硬化製程過程中,成型材料122可能皺縮,如圖4所示。由於
新月效應,相較於與阻障結構120間隔之區域,成型材料122可皺縮而較不接近阻障結構120,形成凹陷區域124。例如,在一些實施方式中,在凹陷區域124中,凹部的量可包括尺寸d4,其中尺寸d4包括約5微米至約15微米。或者,尺寸d4可包括其他值。凹陷區域124亦可形成作為成型材料122之應用製程結果,例如,在實施方式中,成型材料122使用時係為液體或膠體。
晶粒100的角部區域126之更詳細橫切面圖係如圖5所示。有利的是由於封裝中包含阻障結構120,因此晶粒100的基板102之角部受到成型材料122覆蓋。即使是在凹陷區域124中,成型材料122的量有利地位於積體電路晶粒100的第一表面129a的上方(例如,位於晶粒100之基板102的表面上方)。位在積體電路晶粒100的第一表面129a上方之成型材料122的量係包括尺寸d5,其中例如在一些實施方式中,尺寸d5包括約2微米至約5微米。或者,尺寸d5可包括其他值。在封裝製程過程中以及在後續形成互連結構的過程中,位於晶粒100之第一表面129a上方的成型材料122對於晶粒100提供保護。成型材料122亦位於角部區域126中,並且對於晶粒100的角部提供保護。成型材料122亦位於角部區域126中,並且對於晶粒100的角部提供保護。成型材料122實質上與晶粒100的第二表面129b共平面,然而該第二表面129b係與晶粒100的第一表面129a對立。
而後,移除成型材料122的頂部與阻障結構120的頂部,如圖6所示。在圖式中,在移除阻障結構120的頂部之後,阻障結構120被標示為120’。例如,在一些實施方式中,使用研磨製程,移除成型材料122的頂部與阻障結構120的頂部。例如,研磨製程可包括類似用於木頭的砂磨製程之製程,使用旋轉磨砂機。例如,研磨製程可包括將排列適當材料或用於研磨成型材料122與阻障結構之材料120的材料之轉盤旋轉至預定高度。例如,該轉盤可排列鑽石。例如,在一些實施方
式中,使用化學機械拋光(CMP)製程,移除成型材料122的頂部與阻障結構120的頂部。亦可使用研磨製程與CMP製程的組合。或者,可使用其他方法,移除成型材料122的頂部與阻障結構120的頂部。
在一些實施方式中,在研磨與/或CMP製程之後,阻障結構120’包括具有尺寸d6的高度或厚度,其中尺寸d6包括約1微米至約2微米。例如,尺寸d6係小於尺寸d2。在一些實施方式中,尺寸d6係大於或約等同於包括接觸墊104之第一高度的尺寸d1。或者,尺寸d6可包括其他值以及其他相對值。
在本申請案中,例如在一些請求項中,尺寸d6亦稱為第二高度或第三高度。例如,在研磨與/或CMP製程之前,當尺寸d2係指第二高度,其係為阻障結構120的高度,則在研磨與/或CMP製程之後,尺寸d6係指第三高度並且包括第三高度,其係阻障結構120’的高度。在另一範例中,比較包括尺寸d1的接觸墊104之第一高度與在研磨及/或CMP製程之後的阻障結構120’之高度,尺寸d6係指第二高度並且包括第二高度。
移除成型材料122的頂部與阻障結構120的頂部,形成具有縮減高度的阻障結構120’,相對於具有減縮高度的阻障結構120’之頂部表面,亦有利地造成凹陷區域124中凹部的量減少。在研磨與/或CMP製程之後,凹陷區域124中的凹部包括尺寸d7,其中例如尺寸d7包括約0微米至約10微米。在一些實施方式中,尺寸d7包括0,有利的是完全移除凹陷區域124中的凹部,形成實質平面表面用於互連結構的形成。或者,尺寸d7可包括其他值或其他對應值。
圖6的角部區域126之更詳細橫切面圖係如圖7所示。在一些實施方式中,移除成型材料122的頂部表面包括移除接近阻障結構120’之部分的成型材料122。在一些實施方式中,在接近阻障結構120’的區域128中進行研磨與/或CMP製程之後,移除成型材料122的頂部導致
成型材料實質上與阻障結構120’的頂部表面共平面。在研磨與/或CMP製程之後,成型材料122實質上包括尺寸d6。因此,例如在使用研磨與/或CMP製程移除成型材料122的頂部與阻障結構120的頂部之後,成型材料122實質上包括尺寸d6,其包括阻障結構120’的第二高度,其接近阻障結構120’。
接著,參閱圖8,在載體110上方形成互連結構130,例如在成型材料122與晶粒100的上方形成互連結構130。例如,在一些實施方式中,互連結構130包括鈍化後互連(PPI)結構或是重佈層(RDL)。例如,在一些實施方式中,互連結構130包含扇出區域,其將晶粒100上的接觸墊104足跡延伸為用於封裝之更大的足跡。
互連結構130包含複數個介電層130D與傳導線130M以及/或形成於介電層130D內的傳導孔130V,以提供電性連接至基板102上的接觸墊104。例如,藉由任何合適的方法,例如旋轉、CVD與/或電漿CVD(PECVD),可由低介電常數(低K)介電材料形成介電層130D,低介電常數介電材料例如磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽(BPSG)、氟化的矽酸鹽玻璃(FSG)、SiOxCy、懸塗式玻璃、懸塗式聚合物、矽碳材料、其化合物、其複合物、其組合物或類似物。例如,傳導線130M與傳導孔130V可包括銅、銅合金、其他金屬或合金、或其組合或多層。例如,可使用刪減與/或鑲嵌技術,形成傳導線130M與傳導孔130V。
用介電層130D其中之一的材料,填充凹陷區域124。同樣地,用介電層130D其中之一的絕緣材料,填充在阻障結構120’、接觸墊104與絕緣材料106之間的基板102上方之區域。
移除載體110與薄膜112,以及於切割線區域132上將已封裝的半導體裝置140切單或切割,形成複數個封裝的半導體裝置140,如圖9所示。例如,在一些實施方式中,沿著切割線132,切割成型材料122
與互連結構130,形成複數個封裝的半導體裝置140。
例如,在圖9所示的實施方式中,封裝一個晶粒100。或者,如圖11所示,二或多個晶粒100可被封裝在已封裝的半導體裝置140’中,將描述如下。
圖9亦說明在一些實施方式中,複數個連接器142可耦合至部分的互連結構130。例如,互連結構130的最頂層可包含接觸墊(未繪示)形成於其上,以及連接器142係耦合至接觸墊。連接器142可包括共熔材料,例如焊料。在一些實施方式中,共熔材料可包括焊球或焊膏,其配置為球柵陣列(BGA)或其他配置。藉由將共熔材料加熱至共熔材料的熔點而將其迴焊,而後使共熔材料冷卻與重新固化,形成連接器142。連接器142可包含其他形式的電性連接器,例如微凸塊、可控塌陷晶片連接(controlled collapse chip connection,C4)凸塊或柱狀物,以及可包含傳導材料,例如Cu、Sn、Ag、Pb或類似物。在一些實施方式中,封裝中未包含連接器134。在一些實施方式中,連接器142可包括接合凸塊,作為另一範例。在一些實施方式中,連接器142未包含於封裝上。
圖10係根據一些實施方式說明成型工具150之橫切面圖,其說明成型材料122形成製程。為了形成成型材料122,將附接複數個晶粒100的載體110放置於成型工具150的底部成型框台152。將膠體、液體或固體形式的成型材料122放置於工具150的負載埠上,以及將具有釋放薄膜鉗的頂部成型框台154放置於載體110上方。開啟工具150的真空器,以及啟動活塞156以推進成型材料122且將成型材料122注入填充成型框台152與154。而後,硬化成型材料122或使其硬化,開啟頂部成型框台154,以及移除載體110而與底部成型框台152分離。
圖11係根據一些實施方式說明已封裝的半導體裝置140’之橫切面圖,其中該已封裝的半導體裝置140’包含封裝在一起的複數個積體電
路晶粒100。可使用本申請案所描述的方法,將二或多個積體電路晶粒100封裝在一起,而後於切割線132’將其切單,形成封裝的半導體裝置140’。部分的互連結構130對於積體電路晶粒100提供水平電性連接。例如,一些傳導線130M’與傳導孔130V可包括二或多個晶粒100之間的接線。連接器142(請參閱圖9)可耦合至部分的互連結構130,或是可不耦合至部分的互連結構130。
圖12A與12B係根據一些實施方式說明形成於積體電路晶粒100上的阻障結構120’之俯視圖。晶粒100典型為正方形或長方形。在圖12A中,晶粒100為正方形,以及阻障結構120’係直接形成於晶粒100的邊緣上。阻障結構120’包括實質上為正方形環,其係依照晶粒100的形狀。在圖12B中,晶粒100為長方形,以及阻障結構120’實質上亦為長方形。然而,阻障結構120’之位置係接近晶粒100的邊緣,並且與該晶粒100之邊緣相隔預定距離。例如,在一些實施方式中,阻障結構120’可與晶粒100的邊緣相隔數微米。圖12B亦說明阻障結構120’的角部可不為直角,而可包括其他形狀,例如有角度的。或者,阻障結構120’的角部可為圓形的或其他形狀。例如,晶粒100與阻障結構120’亦可包括其他形狀以及相對形狀與尺寸。
本申請案揭示內容的一些實施方式包含封裝半導體裝置之方法。其他實施方式包含封裝的半導體裝置,其係使用本申請案所描述之新方法而封裝的半導體裝置。
本申請案揭示內容的實施方式之一些優點包含提供封裝方法,其包含用於成型材料覆蓋之新設計。阻障結構造成可施用更多的成型材料接近晶粒,因而晶粒的角部區域受到成型材料保護。使用研磨與/或CMP製程降低阻障結構的高度,減少或排除成型材料頂部表面中的凹部。成型材料頂部表面之改良的平坦性造成用於形成互連結構之改良的表面,這改良裝置效能與封裝產率。在成型材料應用製程的過
程中,阻障結構亦減少或防止成型材料在晶粒表面溢出。再者,在製造與封裝製程中,容易實施本申請案所述之新的封裝方法與結構。
在一些實施方式中,封裝半導體裝置之方法包含形成阻障結構於複數個晶粒上,接近複數個晶粒之邊緣區域,使成型材料位於該複數個晶粒附近,以及該成型材料之頂部部分與該阻障結構之頂部部分。
在一些實施方式中,封裝半導體裝置的方法包含耦合複數個晶粒至載體,形成阻障結構於各個該複數個晶粒上,接近該複數個晶粒之邊緣區域,以及使成型材料位於該載體與該複數個晶粒上方。該方法包含移除該成型材料的頂部部份以及該阻障結構的頂部部分,以及形成互連結構於該複數個晶粒與該成型材料上方。移除該載體,以及將該成型材料與該互連結構切單,形成複數個封裝的半導體裝置。
在其他實施方式中,已封裝的半導體裝置包含積體電路晶粒,其包含複數個接觸墊與阻障結構位於其上,該阻障結構係位於該複數個接觸墊附近,接近該積體電路晶粒的邊緣區域。成型材料係位於該積體電路晶粒與該阻障結構附近。互連結構係位於該積體電路晶粒與該成型材料上方。
前述內容概述一些實施方式的特徵,因而熟知此技藝之人士可更加理解本申請案揭示內容之各方面。熟知此技藝之人士應理解可輕易使用本申請案揭示內容作為基礎,用於設計或修飾其他製程與結構而實現與本申請案所述之實施例具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本申請案揭示內容的精神與範圍,以及熟知此技藝之人士可進行各種變化、取代與替換,而不脫離本申請案揭示內容之精神與範圍。
100‧‧‧積體電路晶粒
102‧‧‧基板
104‧‧‧接觸墊
106‧‧‧絕緣材料
120’‧‧‧阻障結構
122‧‧‧成型材料
124‧‧‧凹陷區域
128‧‧‧區域
130‧‧‧互連結構
130M‧‧‧傳導線
130M’‧‧‧傳導線
130D‧‧‧介電層
130V‧‧‧傳導孔
132’‧‧‧切割線
140’‧‧‧半導體裝置
Claims (10)
- 一種封裝半導體裝置的方法,該方法包括:形成複數個接觸墊於複數個晶粒之各者上;形成阻障結構於該複數個晶粒之各者上,接近該複數個晶粒的邊緣區域,該阻障結構沿著該等晶粒之各者之複數個接觸墊之周圍及附近延伸;使成型材料位於該複數個晶粒附近;以及移除該成型材料的頂部部分以及該阻障結構的頂部部分。
- 如請求項1所述之方法,其中移除該成型材料的該頂部部分與該阻障結構之該頂部部分係包括研磨製程或化學機械拋光(CMP)製程。
- 如請求項1所述之方法,其中移除該成型材料的該頂部部分係包括移除接近該阻障結構之該成型材料的部分。
- 一種封裝的半導體裝置,包括:積體電路晶粒,其包含複數個接觸墊與阻障結構位於其上,該阻障結構係位於該複數個接觸墊附近,接近該積體電路晶粒的邊緣區域,並且沿著該複數個接觸墊之周圍及附近延伸;成型材料,其係位於該積體電路晶粒與該阻障結構的附近;以及互連結構,其係位於該積體電路晶粒與該成型材料上方。
- 如請求項4所述之封裝的半導體裝置,其中該複數個接觸墊係包括第一高度,以及其中該阻障結構係包括第二高度,該第二高度係大於或約等同於該第一高度。
- 如請求項5所述之封裝的半導體裝置,其中該成型材料係實質包括接近該阻障結構的該第二高度。
- 如請求項4所述之封裝的半導體裝置,其中該積體電路晶粒係包括 第一表面以及與該第一表面對立的第二表面,其中該複數個接觸墊與該阻障結構係位於該積體電路晶粒的該第一表面上,其中該成型材料係位於該積體電路晶粒的該第一表面上方,以及其中該成型材料係實質上與該積體電路晶粒的該第二表面共平面。
- 如請求項4所述之封裝的半導體裝置,其中該阻障結構係包括密封環結構。
- 如請求項4所述之封裝的半導體裝置,其中該阻障結構係包括實質上為直的側壁或錐形側壁。
- 如請求項4所述之封裝的半導體裝置,更包括複數個該積體電路晶粒,其中該成型材料係位於該複數個積體電路晶粒附近以及該複數個積體電路晶粒之間,以及其中該互連結構係位於該複數個積體電路晶粒與該成型材料上方。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11075173B2 (en) | 2018-10-31 | 2021-07-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming same |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10276421B2 (en) * | 2016-03-15 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out package, integrated fan-out package array, and method of manufacturing integrated fan-out packages |
US20170271734A1 (en) * | 2016-03-17 | 2017-09-21 | Multek Technologies Limited | Embedded cavity in printed circuit board by solder mask dam |
US10170671B2 (en) * | 2016-05-25 | 2019-01-01 | Chen-Fu Chu | Methods of filling a flowable material in a gap of an assembly module |
US10712398B1 (en) | 2016-06-21 | 2020-07-14 | Multek Technologies Limited | Measuring complex PCB-based interconnects in a production environment |
US10229865B2 (en) * | 2016-06-23 | 2019-03-12 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
CN105977224A (zh) * | 2016-06-23 | 2016-09-28 | 华天科技(西安)有限公司 | 一种防止表面溢塑封料的封装件围坝结构及其制造方法 |
US10062654B2 (en) * | 2016-07-20 | 2018-08-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semicondcutor structure and semiconductor manufacturing process thereof |
KR101952862B1 (ko) | 2016-08-30 | 2019-02-27 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
US10499500B2 (en) | 2016-11-04 | 2019-12-03 | Flex Ltd. | Circuit board with embedded metal pallet and a method of fabricating the circuit board |
CN108168444B (zh) | 2016-11-17 | 2021-03-30 | 马尔泰克技术有限公司 | 用于pcb应用的在空气悬浮上的在线计量 |
US10297478B2 (en) * | 2016-11-23 | 2019-05-21 | Rohinni, LLC | Method and apparatus for embedding semiconductor devices |
US10460987B2 (en) * | 2017-05-09 | 2019-10-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package device with integrated antenna and manufacturing method thereof |
IT201700055942A1 (it) * | 2017-05-23 | 2018-11-23 | St Microelectronics Srl | Procedimento per fabbricare dispositivi a semiconduttore, dispositivo e circuito corrispondenti |
US10541228B2 (en) | 2017-06-15 | 2020-01-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages formed using RDL-last process |
US10490472B2 (en) | 2017-08-30 | 2019-11-26 | Qualcomm Incorporated | Air cavity mold |
US10522440B2 (en) * | 2017-11-07 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of manufacturing the same |
US10283461B1 (en) | 2017-11-22 | 2019-05-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Info structure and method forming same |
US10629554B2 (en) * | 2018-04-13 | 2020-04-21 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
KR102570902B1 (ko) * | 2018-11-23 | 2023-08-25 | 삼성전자주식회사 | 반도체 패키지 |
US11022580B1 (en) | 2019-01-31 | 2021-06-01 | Flex Ltd. | Low impedance structure for PCB based electrodes |
US11668686B1 (en) | 2019-06-17 | 2023-06-06 | Flex Ltd. | Batteryless architecture for color detection in smart labels |
KR102203649B1 (ko) * | 2019-09-10 | 2021-01-15 | (주)라이타이저 | 서브 픽셀 csp, 서브 픽셀 csp의 제조 방법, 디스플레이 장치의 제조 방법 및 그 방법에 의해 제조되는 디스플레이 장치 |
US11128268B1 (en) | 2020-05-28 | 2021-09-21 | Nxp Usa, Inc. | Power amplifier packages containing peripherally-encapsulated dies and methods for the fabrication thereof |
US11469197B2 (en) * | 2020-08-26 | 2022-10-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit package and method |
CN113078104A (zh) * | 2021-03-29 | 2021-07-06 | 青岛科技大学 | 一种制造微电子集成电路元件的方法 |
US11894343B2 (en) * | 2021-05-24 | 2024-02-06 | Western Digital Technologies, Inc. | Vertical semiconductor device with side grooves |
CN113644046B (zh) * | 2021-07-19 | 2022-10-14 | 太极半导体(苏州)有限公司 | 一种nand闪存芯片的边缘封装工艺及其结构 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5936932A (ja) * | 1983-05-25 | 1984-02-29 | Hitachi Ltd | 半導体集積回路 |
JPH0493051A (ja) | 1990-08-08 | 1992-03-25 | Nec Corp | 薄型モジュール |
US5583378A (en) * | 1994-05-16 | 1996-12-10 | Amkor Electronics, Inc. | Ball grid array integrated circuit package with thermal conductor |
US5866953A (en) * | 1996-05-24 | 1999-02-02 | Micron Technology, Inc. | Packaged die on PCB with heat sink encapsulant |
KR100343432B1 (ko) | 2000-07-24 | 2002-07-11 | 한신혁 | 반도체 패키지 및 그 패키지 방법 |
JP3651413B2 (ja) | 2001-05-21 | 2005-05-25 | 日立電線株式会社 | 半導体装置用テープキャリア及びそれを用いた半導体装置、半導体装置用テープキャリアの製造方法及び半導体装置の製造方法 |
US20080136004A1 (en) | 2006-12-08 | 2008-06-12 | Advanced Chip Engineering Technology Inc. | Multi-chip package structure and method of forming the same |
US7910404B2 (en) | 2008-09-05 | 2011-03-22 | Infineon Technologies Ag | Method of manufacturing a stacked die module |
US8021930B2 (en) * | 2009-08-12 | 2011-09-20 | Stats Chippac, Ltd. | Semiconductor device and method of forming dam material around periphery of die to reduce warpage |
JP2011233854A (ja) | 2010-04-26 | 2011-11-17 | Nepes Corp | ウェハレベル半導体パッケージ及びその製造方法 |
US8877567B2 (en) * | 2010-11-18 | 2014-11-04 | Stats Chippac, Ltd. | Semiconductor device and method of forming uniform height insulating layer over interposer frame as standoff for semiconductor die |
CN102543767B (zh) * | 2010-12-07 | 2015-04-08 | 万国半导体(开曼)股份有限公司 | 一种在晶圆级封装的塑封工序中避免晶圆破损的方法 |
JP5927756B2 (ja) * | 2010-12-17 | 2016-06-01 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法 |
US8492181B2 (en) * | 2011-12-22 | 2013-07-23 | Stmicroelectronics Pte Ltd. | Embedded wafer level optical package structure and manufacturing method |
US8975726B2 (en) | 2012-10-11 | 2015-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | POP structures and methods of forming the same |
-
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- 2014-07-08 US US14/326,228 patent/US9847317B2/en active Active
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11075173B2 (en) | 2018-10-31 | 2021-07-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming same |
TWI735992B (zh) * | 2018-10-31 | 2021-08-11 | 台灣積體電路製造股份有限公司 | 半導體裝置及其製造方法 |
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