CN105244289A - 封装半导体器件的方法和封装的半导体器件 - Google Patents

封装半导体器件的方法和封装的半导体器件 Download PDF

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Publication number
CN105244289A
CN105244289A CN201410490820.3A CN201410490820A CN105244289A CN 105244289 A CN105244289 A CN 105244289A CN 201410490820 A CN201410490820 A CN 201410490820A CN 105244289 A CN105244289 A CN 105244289A
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tube core
moulding material
dam structure
integrated circuit
dam
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CN105244289B (zh
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余振华
刘重希
陈孟泽
黄晖闵
黄致凡
郑明达
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了封装半导体器件的方法和封装的半导体器件。在一些实施例中,封装半导体器件的方法包括:在管芯上形成接近管芯的边缘区的坝结构。在管芯周围设置模塑材料,以及去除模塑材料的顶部和坝结构的顶部。

Description

封装半导体器件的方法和封装的半导体器件
技术领域
本发明总体涉及半导体领域,更具体地,涉及半导体器件的封装方法。
背景技术
半导体器件用于各种电子应用中,作为实例,诸如个人电脑、手机、数码相机和其他电子设备。半导体器件通常通过以下步骤制造:在半导体衬底上方依次地沉积绝缘层或介电层、导电层和半导体材料层,以及使用光刻来图案化各个材料层以在半导体衬底上形成电路部件和元件。
通常在单个半导体晶圆上制造数十或数百个集成电路。通过沿着划线锯切集成电路来分割单独的管芯。然后,封装单独的管芯,例如,以独立封装的形式、以多芯片模块的形式或以其他类型的封装形式来封装。
半导体工业通过持续减小最小特征尺寸而不断地提高各种电子部件(例如,晶体管、二极管、电阻器、电容器等)的集成度,这允许更多的部件集成到给定区域。在一些应用中,诸如集成电路管芯的这些较小的电子部件也需要比之前的封装占用更小区域的较小的封装。芯片级封装(CSP)是一种更小的封装技术。
发明内容
根据本发明的一个方面,提供了一种封装半导体器件的方法,该方法包括:在多个管芯上形成接近所述多个管芯的边缘区的坝结构;在所述多个管芯周围设置模塑材料;以及去除所述模塑材料的顶部和所述坝结构的顶部。
优选地,去除所述模塑材料的顶部和所述坝结构的顶部包括研磨工艺或化学机械抛光(CMP)工艺。
优选地,去除所述模塑材料的顶部包括去除所述模塑材料中接近所述坝结构的一部分。
优选地,该方法还包括:在多个管芯和模塑材料上方形成互连结构。
优选地,该方法还包括:将多个连接件连接至互连结构。
优选地,形成互连结构包括形成扇出区域。
优选地,形成互连结构包括形成钝化后互连(PPI)结构或再分布层(RDL)。
根据本发明的另一方面,提供了一种封装半导体器件的方法,该方法包括:将多个管芯连接至载体;在多个管芯的每个管芯上都形成接近多个管芯的边缘区的坝结构;在多个管芯周围的载体上方设置模塑材料;去除模塑材料的顶部和坝结构的顶部;在多个管芯和模塑材料上方形成互连结构;去除载体;以及切割模塑材料和互连结构以形成多个封装的半导体器件。
优选地,在将多个管芯连接至载体之前形成坝结构,或者,在将多个管芯连接至载体之后形成坝结构。
优选地,形成坝结构包括选自基本上由附接工艺、光刻工艺、旋涂工艺、沉积工艺、层压工艺、用于形成多个管芯的材料层的工艺和它们的组合组成的组的工艺。
优选地,多个管芯的每个管芯均包括设置在管芯上的多个接触焊盘,多个接触焊盘包括第一高度,并且形成坝结构包括形成包括第二高度的坝结构,第二高度大于第一高度。
优选地,去除坝结构的顶部包括形成包括第三高度的坝结构,第三高度大于第一高度或者与第一高度大约相同。
根据本发明的又一方面,提供了一种封装的半导体器件,包括:集成电路管芯,包括设置在集成电路管芯上的多个接触焊盘和坝结构,坝结构设置在多个接触焊盘周围且接近集成电路管芯的边缘区;模塑材料,设置在集成电路管芯和坝结构周围;以及互连结构,设置在集成电路管芯和模塑材料上方。
优选地,多个接触焊盘包括第一高度,而坝结构包括第二高度,第二高度大于第一高度或者与第一高度大约相同。
优选地,接近坝结构的模塑材料包括大致第二高度。
优选地,集成电路管芯包括第一表面和与第一表面相对的第二表面,多个接触焊盘和坝结构设置在集成电路管芯的第一表面上,模塑材料设置在集成电路管芯的第一表面之上,并且模塑材料与集成电路管芯的第二表面基本上共面。
优选地,坝结构包括选自基本上由聚酰亚胺(PI)、聚苯并恶唑(PBO)、底部填充(UF)材料、可图案化的环氧树脂、不可去除的光刻胶、阻焊材料和它们的组合组成的组的材料。
优选地,坝结构包括密封环结构。
优选地,坝结构包括基本上竖直的侧壁或锥形侧壁。
优选地,该封装的半导体器件还包括:多个集成电路管芯,其中,模塑材料设置在多个集成电路管芯周围以及多个集成电路管芯之间,并且互连结构设置在多个集成电路管芯和模塑材料上方。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1A和图1B是根据本发明的一些实施例的将被封装的集成电路管芯的截面图。
图2至图9是根据一些实施例的示出封装半导体器件的方法在各个阶段的截面图。
图10是根据一些实施例的模塑材料形成工艺的截面图。
图11示出了根据一些实施例的封装的半导体器件的截面图。
图12A和图12B是根据一些实施例的示出在集成电路管芯上形成的坝结构的顶视图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或些)元件或部件的关系。空间相对术语旨在包括器件在使用或操作中的除了图中所示的方位外的不同方位。装置可以以其他方位定向(旋转90度或在其他方位上),并且本文中使用的空间相对描述符可以同样地作出相应的解释。
本发明的实施例提供了封装半导体器件的新方法及其结构,其中,在管芯周围形成模塑材料之前,在集成电路管芯的边缘区附近形成坝结构。该坝结构确保了在管芯周围将施加足够量的模塑材料,这改进了随后的互连结构的形成。
图1A是根据本发明的一些实施例的将被封装的半导体器件的截面图。为了封装该半导体器件,首先,提供了该半导体器件。半导体器件包括集成电路管芯100。例如,可以预先在半导体晶圆上制造集成电路管芯100,然后分割或切割晶圆以形成多个集成电路管芯100。集成电路管芯100包括衬底102,衬底102包括半导体材料并且包括在其内部和/或其上制造的电路、部件、布线和其他元件(未示出)。集成电路管芯100适合于执行一项或多项预定功能,作为实例,诸如逻辑、存储、处理、其他功能或它们的组合。集成电路管芯100在本文中也称为管芯100。
管芯100包括遍布其顶面而形成的多个接触焊盘104。多个接触焊盘104设置在衬底102的表面上。接触焊盘104电连接至衬底102的各部分。作为实例,接触焊盘104包括导电材料,诸如,铜、铝、其他金属或它们的合金或多层。可选地,接触焊盘104可以包括其他材料。
绝缘材料106设置在集成电路管芯100的暴露顶面上方和各接触焊盘104的一部分上方。绝缘材料106可以包括诸如二氧化硅、氮化硅、聚合物材料或其他材料的一个或多个绝缘材料层。使用光刻工艺或其他工艺来图案化绝缘材料106以在各接触焊盘104的顶面上方分别形成开口,从而可以形成至接触焊盘104的电连接。例如,在一些实施例中,绝缘材料106包括钝化层。
图2、图3、图4、图6、图8和图9是根据一些实施例示出了封装半导体器件的方法在各个阶段的截面图。图5是图4的局部细化视图,而图7是图6的局部细化视图。
接下来,参照图2,多个管芯100连接至载体110。手动地或使用诸如贴片机的自动机器将集成电路管芯100连接至载体110。在一些实施例中,载体110具有在其上形成的薄膜112。例如,薄膜112包括光热转换(LTHC)材料或其他材料。在一些实施例中,不包括薄膜112。使用粘合剂或管芯附着膜(DAF)114来将集成电路管芯100连接至载体110。作为实例,载体110可以包括玻璃、氧化硅、氧化铝或半导体晶圆。载体110也可以包括其他材料。
在一些实施例中,各集成电路管芯100连接至载体110并且分别封装在单独的封装件中(见图9)。在其他实施例中,两个以上的集成电路管芯100可以封装在一起(见图11)。例如,根据一些实施例,包括相同或不同功能的多个集成电路管芯100可以封装在一起。
接下来,参照图3,根据本发明的一些实施例,新型的坝结构120设置在管芯100的第一表面129a上。坝结构120形成在多个管芯100的每个上并且接近多个管芯100的边缘区。坝结构120设置在每个管芯100的多个接触焊盘104周围并且接近集成电路管芯100的边缘区。多个接触焊盘104和坝结构120设置在集成电路管芯100的第一表面129a上。接触焊盘104包括尺寸为d1的高度或厚度,其中,在一些实施例中,尺寸d1包括约3μm或3μm以下。可选地,接触焊盘104可以包括其他尺寸。尺寸d1在本文中(例如,在一些权利要求中)也称为第一高度。坝结构120包括在管芯100的每个边缘处或接近管芯100的每个边缘处而形成的密封环结构。
在一些实施例中,坝结构120包括各种材料,诸如,聚酰亚胺(PI)、聚苯并恶唑(PBO)、底部填充(UF)材料、可图案化的环氧化物、不可去除的光刻胶、阻焊材料或它们的组合或多层。在一些实施例中,坝结构120包括绝缘材料。可选地,坝结构120可以包括导电材料或半导电材料。在一些实施例中,坝结构120包括在管芯100周围形成且高度或厚度为尺寸d2的环形件,其中,尺寸d2包括约3μm或3μm以上。例如,在一些实施例中,尺寸d2大于接触焊盘104的尺寸d1。尺寸d2在本文中(例如,在一些权利要求中)也称为第二高度。在一些实施例中,环形坝结构120的两侧之间的宽度为尺寸d3,其中,尺寸d3包括约2μm至10μm。可选地,坝结构120可以包括其他材料和尺寸。
在图1A、图2和图3示出的实施例中,在管芯100附接至载体110之后,坝结构120附接至管芯100或形成在管芯100上。例如,在将多个管芯100连接至载体110之后,形成坝结构120。可选地,在其他实施例中,在管芯100附接至载体110之前,坝结构120可以附接至管芯100或形成在管芯100上。
例如,可以提供图1B中示出的集成电路管芯100,其已经具有在其上形成的坝结构120。例如,当管芯100仍然为晶圆的形式或在分割管芯100之后,坝结构120可以形成在集成电路管芯100上。如图3所示,然后将包括坝结构120的多个管芯100附接至载体110。因此,在一些实施例中,在将多个管芯100连接至载体110之前,形成坝结构120。
图1B还示出了坝结构120可以具有锥形侧壁或如图1B中的虚影(例如,虚线)所示的基本上竖直的侧壁。在本发明的其他图中,示出了具有锥形侧壁的坝结构120;然而,可选地,每个图中的坝结构120均可以具有基本上竖直的侧壁。例如,坝结构120的锥形侧壁的底部宽于顶部,然而,基本上竖直的侧壁在底部和顶部具有基本上相同的宽度。
不管在将管芯100附接至载体110之后(图2和图3)还是在将管芯100附接至载体110之前(图1A和图1B)在管芯100上形成坝结构120,作为实例,可以使用附接工艺、光刻工艺、旋涂工艺、沉积工艺、层压工艺、用于形成多个管芯100的材料层的工艺和/或它们的组合在管芯100上形成坝结构120。坝结构120可以预先形成或预先制造,并且可以使用粘合剂、胶带、层压或其他物质附接至管芯100。可选地,可以使用诸如化学汽相沉积(CVD)、旋涂工艺的沉积工艺、层压坝结构120的材料或其他方法来形成坝结构120。然后使用光刻工艺、直接蚀刻工艺或其他方法来图案化该材料,将坝结构120形成为期望的形状。也可以使用其他方法形成坝结构120。
如图4所示,然后在集成电路管芯100和坝结构120周围设置模塑材料122。模塑材料122形成在载体110的暴露部分上方(例如,载体110上的薄膜112上方)、集成电路管芯100的侧壁上方、管芯100的第一表面129a中位于坝结构120外侧且接近管芯100的边缘区的暴露部分的上方、以及坝结构120中背朝管芯100的中心区的侧壁的上方。例如,可以使用压缩模塑、传递模塑或其他方法来模制模塑材料122。例如,模塑材料122包封集成电路管芯100和坝结构120。作为实例,模塑材料122可以包括环氧树脂、有机聚合物或者添加或未添加硅基或玻璃填料的聚合物。在一些实施例中,模塑材料122包括施加时为凝胶型液体的液态模塑料(LMC)。模塑材料122还可以包括施加时为液体或固体的材料。可选地,模塑材料122可以包括其他绝缘和/或包封材料。
在施加模塑材料122期间,坝结构120用作密封环。因此,模塑材料122延伸至坝结构120中背朝管芯100的中心区的侧壁的顶面。坝结构120还防止模塑材料122到达管芯100的中心区中的管芯100的顶面,或者减少到达中心区中的管芯100的顶面的模塑材料122的量。
接下来,在一些实施例中,使用固化工艺来固化模塑材料122。固化工艺可以包括使用退火工艺或其他加热工艺将模塑材料122加热至预定温度并保持预定的一段时间。固化工艺还可以包括紫外(UV)光曝光工艺、红外(IR)能量曝光工艺、它们的组合或者加热工艺与它们的组合。可选地,可以使用其他方法来固化模塑材料122。在一些实施例中,不包括固化工艺。
如图4所示,在固化工艺期间,模塑材料122可以收缩。由于新月效应(meniscuseffect),模塑材料122在接近坝结构120处比在远离坝结构120的区域处可收缩得更少,从而形成凹进区域124。例如,在一些实施例中,凹进区域124中的凹进的量可以包括尺寸d4,其中,尺寸d4为约5μm至约15μm。可选地,尺寸d4可以包括其他值。凹进区域124也可以由于模塑材料122的施加工艺而形成,例如,在模塑材料122施加时为液体或凝胶的实施例中。
图5中示出了管芯100的拐角区126的更详细的截面图。有利地,由于在封装件中包括坝结构120,管芯100的衬底102的拐角被模塑材料122覆盖。甚至在凹进区域124中,大量的模塑材料122有利地位于或设置在集成电路芯片100的第一表面129a之上(例如,设置在管芯100的衬底102的表面之上)。例如,在一些实施例中,设置在集成电路芯片100的第一表面129a之上的模塑材料122的量包括尺寸d5,其中,尺寸d5为约2μm至约5μm。可选地,尺寸d5可以包括其他值。设置在芯片100的第一表面129a之上的模塑材料122在封装工艺期间以及在随后形成互连结构的期间为管芯100提供保护。模塑材料122还设置在拐角区域126中并且为管芯100的拐角提供保护。模塑材料122与管芯100的第二表面129b基本共平面,其中,第二表面129b与管芯100的第一表面129a相对。
如图6所示,然后去除模塑材料122的顶部和坝结构120的顶部。在坝结构120的顶部的去除之后,坝结构120在图中标记为120’。例如,在一些实施例中,使用研磨工艺去除模塑材料122的顶部和坝结构120的顶部。例如,研磨工艺可以包括与砂磨工艺类似的工艺,其中,砂磨工艺使用旋转砂磨机用于木材。例如,研磨工艺可以包括旋转衬有适当的一种或多种材料的圆盘以将模塑材料122的材料和坝结构120的材料研磨至预定高度。例如,圆盘可以衬有金刚石。在一些实施例中,例如,可以使用化学机械抛光(CMP)工艺去除模塑材料122的顶部和坝结构120的顶部。还可以使用研磨工艺和CMP工艺的组合。可选地,可以使用其他方法去除模塑材料122的顶部和坝结构120的顶部。
在一些实施例中,在研磨和/或CMP工艺之后的坝结构120’包括尺寸为d6的高度或厚度,其中,尺寸d6为约1μm至约2μm。例如,尺寸d6小于尺寸d2。在一些实施例中,尺寸d6大于尺寸为d1的接触焊盘104的第一高度或者与尺寸d1大约相同。可选地,尺寸d6可以包括其他值和其他相对值。
尺寸d6在本文中(例如,在一些权利要求中)也称为第二高度或第三高度。例如,当尺寸d2(在研磨和/或CMP工艺之前的坝结构120的高度)称为第二高度时,尺寸d6(在研磨和/或CMP工艺之后的坝结构120’的高度)称为第三高度并且包括第三高度。作为另一实例,在尺寸为d1的接触焊盘104的第一高度与在研磨和/或CMP工艺之后的坝结构120’的高度比较时,尺寸d6称为第二高度并且包括第二高度。
去除模塑材料122的顶部和坝结构120的顶部(从而形成高度减小的坝结构120’)还有利地使得凹进区域124中的凹进的量相对于高度减小的坝结构120’的顶面而减小。在研磨和/或CMP工艺之后的凹进区域124中的凹进包括尺寸d7,其中,作为实例,尺寸d7为约0μm至约10μm。例如,尺寸d7小于尺寸d4。在尺寸d7包括0的实施例中,有利地将凹进区域124中的凹进完全去除,形成用于互连结构的形成的基本上平坦的表面。可选地,尺寸d7可以包括其他值和其他相对值。
图7中示出了图6的拐角区126的更详细的截面图。在一些实施例中,去除模塑材料122的顶部包括去除模塑材料122中接近坝结构120’的部分。在一些实施例中,去除模塑材料122的顶部使得在研磨和/或CMP工艺之后接近坝结构120’的区域128中的模塑材料122与坝结构120’的顶面基本共面。在研磨和/或CMP工艺之后,模塑材料122包括大体尺寸d6。因此,例如,在用于去除模塑材料122的顶部和坝结构120的顶部的研磨和/或CMP工艺之后,接近坝结构120’的模塑材料122基本上包括尺寸d6,尺寸d6包括坝结构120’的第二高度。
接下来参照图8,然后在载体110上方形成互连结构130,例如,在模塑材料122和管芯100上方形成互连结构130。例如,在一些实施例中,互连结构130包括钝化后互连(PPI)结构或再分布层(RDL)。例如,在一些实施例中,互连结构130包括将管芯100上的接触焊盘104的封装区扩展至更大的封装区的扇出区域以适于封装。
互连结构130包括多个介电层130D以及在介电层130D内部形成的金属线130M和/或金属通孔130V以提供至衬底102上的接触焊盘104的电连接。例如,介电层130D可以通过任何合适的方法(诸如,旋压、CVD和/或等离子体增强CVD(PECVD))由低介电常数(低K)介电材料(诸如,磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟化硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等)形成。作为实例,导线130M和导电通孔130V可以包括铜、铜合金、其他金属或合金、或它们的组合或多层。作为实例,可以使用消减(subtractive)和/或镶嵌技术来形成导电线130M和通孔130V。
用各介电层130D中的一层的绝缘材料填充凹进区域124。同样地,用各介电130D中的一层的绝缘材料填充位于衬底102上方且在坝结构120’、接触焊盘104和绝缘材料106之间的各区域。
如图9所示,去除载体110和薄膜112,并且在划线区132上分割或切割封装的半导体器件140以形成多个封装的半导体器件140。例如,在一些实施例中,沿着划线132切割模塑材料122和互连结构130以形成多个封装的半导体器件140。
例如,在图9中示出的实施例中,封装了一个管芯100。可选地,如图11所示,可以将两个或两个以上的管芯100封装在一个封装的半导体器件140’中,这在本文中将进一步描述。
图9还示出了在一些实施例中可以将多个连接件142连接至互连结构130的各部分。例如,互连结构130的最顶层可以包括在其上形成的接触焊盘(未示出),并且连接件142连接至接触焊盘。例如,连接件142可以包括诸如焊料的共熔材料。在一些实施例中,共熔材料可以包括布置为球栅阵列(BGA)或其他布置的焊球或焊膏。通过将共熔材料加热至共熔材料的熔解温度来回流共熔材料,然后允许共熔材料冷却并重新凝固,从而形成连接件142。连接件142可以包括诸如微凸块、可控塌陷芯片连接(C4)凸块或柱状物的其他类型的电连接件,并且可以包括诸如Cu、Sn、Ag、Pb等的导电材料。作为另一实例,在一些实施例中,连接件142可以包括连接凸块。在一些实施例中,在封装件上不包括连接件142。
图10是根据一些实施例的示出模塑材料122形成工艺的模塑工具150的截面图。为了形成模塑材料122,在模塑工具150的底部包封模具152上放置载体110,其中,多个管芯100附接至载体110。在工具150的加载端口上放置凝胶、液体或固体形式的模塑材料122,并且在载体110上方放置具有离型膜夹具的顶部包封模具154。打开工具150的真空装置,并且驱动压料柱塞156以推送模塑材料122并且注入模塑材料122以用模塑材料122填充包封模具152和154。然后固化模塑材料122或允许模塑材料122固化,打开顶部包封模具154,并且从底部包封模具152处去除载体110。
图11示出了根据一些实施例的包括多个封装在一起的集成电路管芯100的封装的半导体器件140’的截面图。可以使用本文中描述的方法将两个或两个以上的集成电路管芯100封装在一起,然后在划线132’处将其分割以形成封装的半导体器件140’。互连结构130的各部分为集成电路管芯100提供水平电连接。例如,一些导线130M’和通孔130V可以包括在两个或两个以上的管芯100之间的布线。连接件142(见图9)可以或可以不连接至互连结构130的各部分。
图12A和图12B是根据一些实施例的示出在集成电路管芯100上形成的坝结构120’的顶视图。管芯100的形状通常为正方形或矩形。在图12A中,管芯100是正方形,并且坝结构120’直接形成在管芯100的边缘上。坝结构120’包括符合管芯100的形状的大致方环形状。在图12B中,管芯100是矩形,因此坝结构120’的形状也大致是矩形。然而,坝结构120’接近管芯100的边缘,但是仍与管芯100的边缘间隔开预定距离。例如,在一些实施例中,坝结构120’可以与管芯100的边缘间隔开若干微米。图12B还示出了坝结构120’的各拐角可以不是正方形的,但是可以包括诸如形成角度的其他形状。可选地,坝结构120’的拐角可以为圆形或其他形状。例如,管芯100和坝结构120’还可以包括其他形状以及相对形状和尺寸。
本发明的一些实施例包括封装半导体器件的方法。其他实施例包括已经使用本文中描述的新方法来封装的封装后的半导体器件。
本发明的实施例的一些优点包括提供包括用于模塑材料覆盖的新设计的封装方法。坝结构使得更多的模塑材料被施加到接近管芯处,从而使得管芯的各拐角区由模塑材料保护。使用研磨和/或CMP工艺来降低坝结构的高度从而降低或消除模塑材料顶面中的凹进。模塑材料顶面的平面性的改进使得用于形成互连结构的表面得以改进,这使得器件性能和封装产量改进。在施加模塑材料工艺期间,坝结构还减少或防止模塑材料的溢出在管芯的表面上。此外,本文中描述的新封装方法和结构可在制造和封装工艺流程中容易实现。
在一些实施例中,一种封装半导体器件的方法包括:在多个管芯上形成接近多个管芯的边缘区的坝结构,在多个管芯周围设置模塑材料,以及去除模塑材料的顶部和坝结构的顶部。
在一些实施例中,一种封装半导体器件的方法包括:将多个管芯连接至载体,在多个管芯的每个管芯上形成接近多个管芯的边缘区的坝结构,以及在多个管芯周围的载体上方设置模塑材料。该方法包括:去除模塑材料的顶部和坝结构的顶部,以及在多个管芯和模塑材料上方形成互连结构。去除载体,并且分割模塑材料和互连结构以形成多个封装的半导体器件。
在其他实施例中,一种封装的半导体器件包括集成电路管芯,集成电路管芯包括设置在其上的多个接触焊盘和坝结构,坝结构设置在多个接触焊盘周围并且接近集成电路管芯的边缘区。模塑材料设置在集成电路管芯和坝结构周围。互连结构设置在集成电路管芯和模塑材料上方。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他过程和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种封装半导体器件的方法,所述方法包括:
在多个管芯上形成接近所述多个管芯的边缘区的坝结构;
在所述多个管芯周围设置模塑材料;以及
去除所述模塑材料的顶部和所述坝结构的顶部。
2.根据权利要求1所述的方法,其中,去除所述模塑材料的顶部和所述坝结构的顶部包括研磨工艺或化学机械抛光(CMP)工艺。
3.根据权利要求1所述的方法,其中,去除所述模塑材料的顶部包括去除所述模塑材料中接近所述坝结构的一部分。
4.根据权利要求1所述的方法,还包括:在所述多个管芯和所述模塑材料上方形成互连结构。
5.根据权利要求4所述的方法,还包括:将多个连接件连接至所述互连结构。
6.根据权利要求4所述的方法,其中,形成所述互连结构包括形成扇出区域。
7.根据权利要求4所述的方法,其中,形成所述互连结构包括形成钝化后互连(PPI)结构或再分布层(RDL)。
8.一种封装半导体器件的方法,所述方法包括:
将多个管芯连接至载体;
在所述多个管芯的每个管芯上都形成接近所述多个管芯的边缘区的坝结构;
在所述多个管芯周围的所述载体上方设置模塑材料;
去除所述模塑材料的顶部和所述坝结构的顶部;
在所述多个管芯和所述模塑材料上方形成互连结构;
去除所述载体;以及
切割所述模塑材料和所述互连结构以形成多个封装的半导体器件。
9.一种封装的半导体器件,包括:
集成电路管芯,包括设置在所述集成电路管芯上的多个接触焊盘和坝结构,所述坝结构设置在所述多个接触焊盘周围且接近所述集成电路管芯的边缘区;
模塑材料,设置在所述集成电路管芯和所述坝结构周围;以及
互连结构,设置在所述集成电路管芯和所述模塑材料上方。
10.根据权利要求9所述的封装的半导体器件,其中,所述多个接触焊盘包括第一高度,而所述坝结构包括第二高度,所述第二高度大于所述第一高度或者与所述第一高度大约相同。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105977224A (zh) * 2016-06-23 2016-09-28 华天科技(西安)有限公司 一种防止表面溢塑封料的封装件围坝结构及其制造方法
CN110379776A (zh) * 2018-04-13 2019-10-25 力成科技股份有限公司 封装结构及其制造方法
CN113078104A (zh) * 2021-03-29 2021-07-06 青岛科技大学 一种制造微电子集成电路元件的方法
CN113644046A (zh) * 2021-07-19 2021-11-12 太极半导体(苏州)有限公司 一种nand闪存芯片的边缘封装工艺及其结构
CN113809018A (zh) * 2020-08-26 2021-12-17 台湾积体电路制造股份有限公司 集成电路器件及其形成方法

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10276421B2 (en) * 2016-03-15 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package, integrated fan-out package array, and method of manufacturing integrated fan-out packages
US20170271734A1 (en) * 2016-03-17 2017-09-21 Multek Technologies Limited Embedded cavity in printed circuit board by solder mask dam
CN109314164B (zh) * 2016-05-25 2022-04-15 朱振甫 半导体连续阵列层
US10712398B1 (en) 2016-06-21 2020-07-14 Multek Technologies Limited Measuring complex PCB-based interconnects in a production environment
US10229865B2 (en) * 2016-06-23 2019-03-12 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US10062654B2 (en) * 2016-07-20 2018-08-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor structure and semiconductor manufacturing process thereof
KR101952862B1 (ko) 2016-08-30 2019-02-27 삼성전기주식회사 팬-아웃 반도체 패키지
US10499500B2 (en) 2016-11-04 2019-12-03 Flex Ltd. Circuit board with embedded metal pallet and a method of fabricating the circuit board
CN108168444B (zh) 2016-11-17 2021-03-30 马尔泰克技术有限公司 用于pcb应用的在空气悬浮上的在线计量
US10297478B2 (en) * 2016-11-23 2019-05-21 Rohinni, LLC Method and apparatus for embedding semiconductor devices
US10460987B2 (en) * 2017-05-09 2019-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated antenna and manufacturing method thereof
IT201700055942A1 (it) * 2017-05-23 2018-11-23 St Microelectronics Srl Procedimento per fabbricare dispositivi a semiconduttore, dispositivo e circuito corrispondenti
US10541228B2 (en) 2017-06-15 2020-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packages formed using RDL-last process
US10490472B2 (en) * 2017-08-30 2019-11-26 Qualcomm Incorporated Air cavity mold
US10522440B2 (en) * 2017-11-07 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US10283461B1 (en) 2017-11-22 2019-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure and method forming same
US11075173B2 (en) 2018-10-31 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming same
KR102570902B1 (ko) * 2018-11-23 2023-08-25 삼성전자주식회사 반도체 패키지
US11022580B1 (en) 2019-01-31 2021-06-01 Flex Ltd. Low impedance structure for PCB based electrodes
US11668686B1 (en) 2019-06-17 2023-06-06 Flex Ltd. Batteryless architecture for color detection in smart labels
KR102203649B1 (ko) * 2019-09-10 2021-01-15 (주)라이타이저 서브 픽셀 csp, 서브 픽셀 csp의 제조 방법, 디스플레이 장치의 제조 방법 및 그 방법에 의해 제조되는 디스플레이 장치
US11128268B1 (en) 2020-05-28 2021-09-21 Nxp Usa, Inc. Power amplifier packages containing peripherally-encapsulated dies and methods for the fabrication thereof
US11894343B2 (en) * 2021-05-24 2024-02-06 Western Digital Technologies, Inc. Vertical semiconductor device with side grooves

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5583378A (en) * 1994-05-16 1996-12-10 Amkor Electronics, Inc. Ball grid array integrated circuit package with thermal conductor
CN101996894A (zh) * 2009-08-12 2011-03-30 新科金朋有限公司 半导体器件和围绕管芯周边形成坝材料以减小翘曲的方法
US20120153462A1 (en) * 2010-12-17 2012-06-21 Sony Corporation Semiconductor device and method of manufacturing semiconductor device
US20130164867A1 (en) * 2011-12-22 2013-06-27 Stmicroelectronics Pte Ltd. Embedded wafer level optical package structure and manufacturing method

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936932A (ja) * 1983-05-25 1984-02-29 Hitachi Ltd 半導体集積回路
JPH0493051A (ja) 1990-08-08 1992-03-25 Nec Corp 薄型モジュール
US5866953A (en) * 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
KR100343432B1 (ko) 2000-07-24 2002-07-11 한신혁 반도체 패키지 및 그 패키지 방법
JP3651413B2 (ja) 2001-05-21 2005-05-25 日立電線株式会社 半導体装置用テープキャリア及びそれを用いた半導体装置、半導体装置用テープキャリアの製造方法及び半導体装置の製造方法
US20080136004A1 (en) 2006-12-08 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chip package structure and method of forming the same
US7910404B2 (en) 2008-09-05 2011-03-22 Infineon Technologies Ag Method of manufacturing a stacked die module
JP2011233854A (ja) 2010-04-26 2011-11-17 Nepes Corp ウェハレベル半導体パッケージ及びその製造方法
US8877567B2 (en) * 2010-11-18 2014-11-04 Stats Chippac, Ltd. Semiconductor device and method of forming uniform height insulating layer over interposer frame as standoff for semiconductor die
CN102543767B (zh) * 2010-12-07 2015-04-08 万国半导体(开曼)股份有限公司 一种在晶圆级封装的塑封工序中避免晶圆破损的方法
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5583378A (en) * 1994-05-16 1996-12-10 Amkor Electronics, Inc. Ball grid array integrated circuit package with thermal conductor
CN101996894A (zh) * 2009-08-12 2011-03-30 新科金朋有限公司 半导体器件和围绕管芯周边形成坝材料以减小翘曲的方法
US20120153462A1 (en) * 2010-12-17 2012-06-21 Sony Corporation Semiconductor device and method of manufacturing semiconductor device
US20130164867A1 (en) * 2011-12-22 2013-06-27 Stmicroelectronics Pte Ltd. Embedded wafer level optical package structure and manufacturing method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105977224A (zh) * 2016-06-23 2016-09-28 华天科技(西安)有限公司 一种防止表面溢塑封料的封装件围坝结构及其制造方法
CN110379776A (zh) * 2018-04-13 2019-10-25 力成科技股份有限公司 封装结构及其制造方法
CN110379776B (zh) * 2018-04-13 2021-07-06 力成科技股份有限公司 封装结构及其制造方法
CN113809018A (zh) * 2020-08-26 2021-12-17 台湾积体电路制造股份有限公司 集成电路器件及其形成方法
CN113078104A (zh) * 2021-03-29 2021-07-06 青岛科技大学 一种制造微电子集成电路元件的方法
CN113644046A (zh) * 2021-07-19 2021-11-12 太极半导体(苏州)有限公司 一种nand闪存芯片的边缘封装工艺及其结构
CN113644046B (zh) * 2021-07-19 2022-10-14 太极半导体(苏州)有限公司 一种nand闪存芯片的边缘封装工艺及其结构

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US20180108637A1 (en) 2018-04-19
US10510719B2 (en) 2019-12-17
US10043778B2 (en) 2018-08-07
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US9847317B2 (en) 2017-12-19
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