TWI589059B - 電子封裝件 - Google Patents

電子封裝件 Download PDF

Info

Publication number
TWI589059B
TWI589059B TW105109663A TW105109663A TWI589059B TW I589059 B TWI589059 B TW I589059B TW 105109663 A TW105109663 A TW 105109663A TW 105109663 A TW105109663 A TW 105109663A TW I589059 B TWI589059 B TW I589059B
Authority
TW
Taiwan
Prior art keywords
carrier
electronic
electronic package
spacer
package
Prior art date
Application number
TW105109663A
Other languages
English (en)
Other versions
TW201735437A (zh
Inventor
邱志賢
蔡屺濱
石啓良
蔡明汎
陳嘉揚
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW105109663A priority Critical patent/TWI589059B/zh
Priority to CN201610217126.3A priority patent/CN107240761B/zh
Priority to US15/181,489 priority patent/US10074621B2/en
Application granted granted Critical
Publication of TWI589059B publication Critical patent/TWI589059B/zh
Publication of TW201735437A publication Critical patent/TW201735437A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/24—Supports; Mounting means by structural association with other equipment or articles with receiving set
    • H01Q1/241—Supports; Mounting means by structural association with other equipment or articles with receiving set used in mobile communications, e.g. GSM
    • H01Q1/242—Supports; Mounting means by structural association with other equipment or articles with receiving set used in mobile communications, e.g. GSM specially adapted for hand-held use
    • H01Q1/243—Supports; Mounting means by structural association with other equipment or articles with receiving set used in mobile communications, e.g. GSM specially adapted for hand-held use with built-in antennas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6611—Wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48101—Connecting bonding areas at the same height, e.g. horizontal bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48265—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Details Of Aerials (AREA)
  • Support Of Aerials (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

電子封裝件
本發明係有關一種電子封裝件，尤指一種具天線結構之電子封裝件。
隨著電子產業的蓬勃發展，目前無線通訊技術已廣泛應用於各式各樣的消費性電子產品以利接收或發送各種無線訊號。為了滿足消費性電子產品的外觀設計需求，無線通訊模組之製造與設計係朝輕、薄、短、小之需求作開發，其中，平面天線(Patch Antenna)因具有體積小、重量輕與製造容易等特性而廣泛利用在手機(cell phone)、個人數位助理(Personal Digital Assistant,PDA)等電子產品之無線通訊模組中。
第1圖係習知無線通訊模組之立體示意圖。如第1圖所示，該無線通訊模組1係包括：一封裝基板10、複數電子元件11、一天線結構12以及封裝膠體13。該封裝基板10係為電路板並呈矩形狀。該電子元件11係設於該封裝基板10上且電性連接該封裝基板10。該天線結構12係為平面型且具有一天線本體120與一導電跡線121，該天線本體120藉由該導電跡線121電性連接該電子元件11。該 封裝膠體13係覆蓋該電子元件11與該部分導電跡線121。
前述之習知無線通訊模組1中，由於該天線結構12係為平面型，故需於該封裝基板10之表面上增加佈設區域(未形成封裝膠體13之區域)以形成該導電跡線121，致使該封裝基板10之寬度難以縮減，因而難以縮小該無線通訊模組1的寬度，而使該無線通訊模組1無法達到微小化之需求。
因此，如何克服上述習知技術之問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係揭露一種電子封裝件，係包括：一承載件；至少一電子元件，係設於該承載件上；以及至少一天線結構，係設於該承載件上並具有複數間隔件與至少一銲線，且該銲線連接任二相鄰之該間隔件。
前述之電子封裝件中，該間隔件係藉由另一銲線電性連接該電子元件。
本發明亦揭露一種電子封裝件，係包括：一承載件；至少一電子元件，係設於該承載件上；以及至少一天線結構，係設於該承載件上並具有至少一間隔件與至少一銲線，且該銲線連接該電子元件與該間隔件。
前述之兩種電子封裝件中，該電子元件係電性連接該承載件。
前述之兩種電子封裝件中，該間隔件係具有至少一電 性接觸墊，以令該銲線連結該電性接觸墊。
前述之兩種電子封裝件中，該間隔件係接置於該承載件上。
前述之兩種電子封裝件中，該間隔件中具有至少一電性連接該承載件之導電柱。
前述之兩種電子封裝件中，該間隔件係藉由另一銲線電性連接該承載件。
前述之兩種電子封裝件中，該承載件上設有被動元件。例如，該被動元件係藉由另一銲線電性連接該間隔件或電子元件。
前述之兩種電子封裝件中，該間隔件係接置於該電子元件上。
前述之兩種電子封裝件中，復包括形成於該承載件上並覆蓋該電子元件與該天線結構之封裝層。例如，該封裝層完全覆蓋該天線結構、或者該間隔件外露於該封裝層。
由上可知，本發明之電子封裝件中，係藉由打線方式將該銲線形成於該承載件上方，使該天線結構呈立體式天線，因而無需於該承載件之設置表面上增加佈設區域之面積，故相較於習知技術，本發明之承載件之寬度較短，因而能縮小該電子封裝件的寬度，致使該電子封裝件達到微小化之需求。
1‧‧‧無線通訊模組
10‧‧‧封裝基板
11,21,21’,41‧‧‧電子元件
12,22,22’,32,42,52‧‧‧天線結構
120‧‧‧天線本體
121‧‧‧導電跡線
13‧‧‧封裝膠體
2,2’,2”,3,3’,3”,4,4’,5,5’‧‧‧電子封裝件
20‧‧‧承載件
200‧‧‧線路層
210‧‧‧導線
210’‧‧‧導電凸塊
220,220’,220”,420‧‧‧間隔件
220a‧‧‧電性接觸墊
221,222,322‧‧‧銲線
222’‧‧‧導電柱
23‧‧‧封裝層
23a‧‧‧第一表面
23b‧‧‧第二表面
23c‧‧‧側面
30‧‧‧被動元件
第1圖係為習知無線通訊模組之立體示意圖；第2A圖係為本發明之電子封裝件之第一實施例的剖 面示意圖；第2A’圖係為第2A圖的另一實施例的剖面示意圖；第2A”圖係為第2A圖的另一實施例的立體圖第2B圖係為第2A圖(省略封裝層)的局部立體圖；第2B’及2B”圖係為第2B圖的其它不同實施例的局部立體圖；第3A圖係為本發明之電子封裝件之第二實施例的剖面示意圖；第3A’及3A”圖係為第3A圖的其它不同實施例的剖面示意圖；第3B圖係為第3A圖(省略封裝層)的局部立體圖；第4A圖係為本發明之電子封裝件之第三實施例的剖面示意圖；第4A’圖係為第4A圖的另一實施例的剖面示意圖；第4B圖係為第4A圖(省略封裝層)的局部立體圖；第4B’圖係為第4A’圖(省略封裝層)的局部立體圖；以及第5A及5B圖係為本發明之電子封裝件之第四實施例的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小 等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A、2A’、2A”、2B、2B’及2B”圖係為本發明之電子封裝件2,2’,2”之第一實施例的示意圖。
如第2A、2A’、2A”、2B、2B’及2B”圖所示，所述之電子封裝件2,2’,2”係至少由一承載件20、設於該承載件20上之至少一電子元件21,21’以及設於該承載件20上之至少一天線結構22,22’所構成。
於本實施例中，該電子封裝件2,2’,2”係為系統級封裝(System in package，簡稱SiP)之無線通訊模組。
所述之承載件20係為電路板或陶瓷板，且該承載件20具有線路層(圖略)。應可理解地，有關承載件之種類繁多，並不限於圖示者。
所述之電子元件21,21’係為主動元件、被動元件、封裝元件或其三者之組合，其中，該主動元件係例如半導體晶片，該被動元件係例如電阻、電容及電感，該封裝元件 係包含晶片及包覆該晶片之封裝膠體。
於本實施例中，該電子元件21,21’係為主動元件。具體地，如第2A及2B圖所示，該電子元件21係藉由複數導線210以打線方式電性連接該承載件20之線路層；或者，如第2A’圖所示，該電子元件21’係藉由複數導電凸塊210’以覆晶方式電性連接該承載件20之線路層。
所述之天線結構22,22’係具有複數設於該承載件20上之間隔件220,220’與至少一銲線221，且該銲線221透過打線方式連接於各該間隔件220,220’之間。
於本實施例中，該間隔件220,220’可為具有至少一電性接觸墊220a(如第2B、2B’及2B”圖所示)之元件，例如，晶片、承載件、陶瓷板、鐵素體(ferrite)、封裝元件、電子組件、中介板(interposer)或其它電子構件等，以令該銲線221連接該些間隔件220,220’之電性接觸墊220a。
再者，如第2A及2B圖所示，該間隔件220係於其電性接觸墊220a上藉由至少一銲線222以打線方式電性連接該電子元件21。或者，如第2A’圖所示，至少一該間隔件220’中具有至少一貫穿之導電柱222’，且該導電柱222’之上、下兩端分別電性連接該銲線221與該承載件20。
又，如第2B及2B’圖所示，該些銲線221,222及電性接觸墊200a之佈設可依需求調整，且如第2B”圖所示，該間隔件220,220’,220”之數量亦可依需求調整。
另外，所述之電子封裝件2,2’,2”係可選擇性包括一 封裝層23，如第2A、2A’及2A”圖所示。所述之封裝層23係形成於該承載件20上並覆蓋該電子元件21,21’與該天線結構22,22’，且其具有相對之第一表面23a與第二表面23b，使該封裝層23以其第一表面23a結合該承載件20。
於本實施例中，形成該封裝層23之材質係為絕緣材，例如，聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝膠體(molding compound)。
再者，該封裝層23可完全覆蓋該天線結構22,22’；或者，如第2A”圖所示之電子封裝件2”，該間隔件220亦可選擇外露於該封裝層23之側面23c，其中，該側面23c係鄰接該第一表面23a與第二表面23b。
第3A、3A’、3A”及3B圖係為本發明之電子封裝件3,3’,3”之第二實施例的示意圖。本實施例與第一實施例的主要差異在於增設至少一被動元件30，故以下僅說明相異處，而不再贅述相同處。
如第3A、3A’、3A”及3B圖所示，於該承載件20上設有至少一被動元件30。
於一實施例中，如第3A及3B圖所示，該電子元件21藉由至少一導線210以打線方式電性連接該承載件20之線路層200，且該天線結構22’之至少一該間隔件220’之導電柱222’係藉由該承載件20之線路層200電性連接該被動元件30。
於一實施例中，如第3A’圖所示，該電子元件21藉由至少一導線210以打線方式電性連接該承載件20之線路 層200，且該天線結構32之至少一間隔件220係藉由銲線322以打線方式電性連接該承載件20之線路層200，而該被動元件30電性連接該承載件20之線路層200。
於一實施例中，如第3A”圖所示，該電子元件21藉由至少一導線210以打線方式電性連接該被動元件30，且該天線結構32之至少一間隔件220係藉由銲線322以打線方式電性連接該被動元件30，而該被動元件30電性連接該承載件20之線路層200。
第4A、4A’、4B及4B’圖係為本發明之電子封裝件4,4’之第三實施例的示意圖。本實施例與上述實施例的差異在於間隔件420之位置，故以下僅說明相異處，而不再贅述相同處。
如第4A、4A’、4B及4B’圖所示，該間隔件420係設於該電子元件21’,41上。
於一實施例中，如第4A及4B圖所示，該電子封裝件4包括複數電子元件21,21’，且該天線結構42之其中一間隔件420設於其中一電子元件21’上。
於一實施例中，如第4A’及4B’圖所示，該電子封裝件4’包括複數電子元件41,21’與被動元件30，其中一電子元件41係為封裝元件，且該天線結構42之各該間隔件420分別設於各該電子元件41,21’上，而各該間隔件420與該電子元件41係以打線方式(藉由該銲線322與該導線210)電性連接該承載件20之線路層200與被動元件30。
第5A及5B圖係為本發明之電子封裝件之第四實施例 的剖面示意圖。本實施例與第一實施例的差異在於銲線之佈設，故以下僅說明相異處，而不再贅述相同處。
如第5A圖所示，該電子封裝件5之天線結構52係包括至少一間隔件220與至少一銲線222，且該間隔件220係藉由至少一銲線222以打線方式電性連接該電子元件21，故各該間隔件220之間沒有以打線方式互相電性連接。應可理解地，如第5B圖所示，該電子封裝件5’之間隔件220可設於該電子元件21上。
另一方面，應可理解地，於其它實施例中，該電子封裝件可包括複數個天線結構。
綜上所述，本發明之電子封裝件2,2’,2”,3,3’,3”,4,4’,5,5’中，係利用打線方式形成該銲線221,222,322，以取代習知導電跡線，以於製程中，該天線結構22,22’,32,42,52能與該些電子元件21,21’,41整合製作，亦即一同進行封裝，使該封裝層23能覆蓋該些電子元件21,21’,41與該天線結構22,22’,32,42,52，故封裝製程用之模具能對應該承載件20之尺寸，因而有利於封裝製程。
再者，該銲線221,222,322設於該承載件20上方而使該天線結構22,22’,32,42,52呈立體式天線，因而可將該天線結構22,22’,32,42,52佈設於與該些電子元件21,21’之相同之區域(即形成封裝層23之區域)，而無需於該承載件20之表面上增加佈設區域，故相較於習知技術，本發明之承載件20之寬度較短，因而能縮小該電子封裝件2,2’,2”,3,3’,3”,4,4’,5,5’的寬度，致使該電子封裝件 2,2’,2”,3,3’,3”,4,4’,5,5’達到微小化之需求。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20‧‧‧承載件
21‧‧‧電子元件
210‧‧‧導線
22‧‧‧天線結構
220‧‧‧間隔件
221、222‧‧‧銲線
23‧‧‧封裝層
23a‧‧‧第一表面
23b‧‧‧第二表面

Claims (15)

  1. 一種電子封裝件，係包括：一承載件；至少一電子元件，係設於該承載件上；以及至少一天線結構，係設於該承載件上並具有複數間隔件與至少一銲線，且該銲線連接任二相鄰之該間隔件。
  2. 一種電子封裝件，係包括：一承載件；至少一電子元件，係設於該承載件上；以及至少一天線結構，係設於該承載件上並具有至少一間隔件與至少一銲線，且該銲線連接該電子元件與該間隔件。
  3. 如申請專利範圍第1或2項所述之電子封裝件，其中，該電子元件係電性連接該承載件。
  4. 如申請專利範圍第1或2項所述之電子封裝件，其中，該間隔件係具有至少一電性接觸墊，以令該銲線連結該電性接觸墊。
  5. 如申請專利範圍第1或2項所述之電子封裝件，其中，該間隔件係接置於該承載件上。
  6. 如申請專利範圍第1項所述之電子封裝件，其中，該間隔件係藉由另一銲線電性連接該電子元件。
  7. 如申請專利範圍第1或2項所述之電子封裝件，其中，該間隔件中具有至少一電性連接該承載件之導電柱。
  8. 如申請專利範圍第1或2項所述之電子封裝件，其中，該間隔件係藉由另一銲線電性連接該承載件。
  9. 如申請專利範圍第1或2項所述之電子封裝件，其中，該承載件上設有被動元件。
  10. 如申請專利範圍第9項所述之電子封裝件，其中，該被動元件係藉由另一銲線電性連接該間隔件。
  11. 如申請專利範圍第9項所述之電子封裝件，其中，該被動元件係藉由另一銲線電性連接該電子元件。
  12. 如申請專利範圍第1或2項所述之電子封裝件，其中，該間隔件係接置於該電子元件上。
  13. 如申請專利範圍第1或2項所述之電子封裝件，復包括形成於該承載件上並覆蓋該電子元件與該天線結構之封裝層。
  14. 如申請專利範圍第13項所述之電子封裝件，其中，該封裝層完全覆蓋該天線結構。
  15. 如申請專利範圍第13項所述之電子封裝件，其中，該間隔件外露於該封裝層。
TW105109663A 2016-03-28 2016-03-28 電子封裝件 TWI589059B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW105109663A TWI589059B (zh) 2016-03-28 2016-03-28 電子封裝件
CN201610217126.3A CN107240761B (zh) 2016-03-28 2016-04-08 电子封装件
US15/181,489 US10074621B2 (en) 2016-03-28 2016-06-14 Electronic package with antenna structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW105109663A TWI589059B (zh) 2016-03-28 2016-03-28 電子封裝件

Publications (2)

Publication Number Publication Date
TWI589059B true TWI589059B (zh) 2017-06-21
TW201735437A TW201735437A (zh) 2017-10-01

Family

ID=59688242

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105109663A TWI589059B (zh) 2016-03-28 2016-03-28 電子封裝件

Country Status (3)

Country Link
US (1) US10074621B2 (zh)
CN (1) CN107240761B (zh)
TW (1) TWI589059B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3449502B1 (en) 2016-04-26 2021-06-30 Linear Technology LLC Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
TWI673510B (zh) 2018-07-17 2019-10-01 昇雷科技股份有限公司 具打線互連結構之都普勒雷達
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
CN113725100A (zh) * 2020-03-27 2021-11-30 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6630372B2 (en) * 1997-02-14 2003-10-07 Micron Technology, Inc. Method for routing die interconnections using intermediate connection elements secured to the die face
US7295161B2 (en) * 2004-08-06 2007-11-13 International Business Machines Corporation Apparatus and methods for constructing antennas using wire bonds as radiating elements
US7586193B2 (en) * 2005-10-07 2009-09-08 Nhew R&D Pty Ltd Mm-wave antenna using conventional IC packaging
US20110233753A1 (en) * 2010-03-26 2011-09-29 Zigmund Ramirez Camacho Integrated circuit packaging system with leads and method of manufacture thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7607586B2 (en) * 2005-03-28 2009-10-27 R828 Llc Semiconductor structure with RF element
TWI562455B (en) * 2013-01-25 2016-12-11 Siliconware Precision Industries Co Ltd Electronic package and method of forming the same
JP2014217014A (ja) * 2013-04-30 2014-11-17 株式会社東芝 無線装置
KR101483553B1 (ko) * 2013-09-06 2015-01-21 주식회사 바른전자 근거리 무선통신용 페라이트 안테나를 구비하는 반도체 패키지 및 그의 제조 방법
TWI546928B (zh) * 2014-03-17 2016-08-21 矽品精密工業股份有限公司 電子封裝件及其製法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6630372B2 (en) * 1997-02-14 2003-10-07 Micron Technology, Inc. Method for routing die interconnections using intermediate connection elements secured to the die face
US7295161B2 (en) * 2004-08-06 2007-11-13 International Business Machines Corporation Apparatus and methods for constructing antennas using wire bonds as radiating elements
US7586193B2 (en) * 2005-10-07 2009-09-08 Nhew R&D Pty Ltd Mm-wave antenna using conventional IC packaging
US20110233753A1 (en) * 2010-03-26 2011-09-29 Zigmund Ramirez Camacho Integrated circuit packaging system with leads and method of manufacture thereof

Also Published As

Publication number Publication date
CN107240761A (zh) 2017-10-10
CN107240761B (zh) 2020-02-21
US10074621B2 (en) 2018-09-11
TW201735437A (zh) 2017-10-01
US20170278807A1 (en) 2017-09-28

Similar Documents

Publication Publication Date Title
TWI589059B (zh) 電子封裝件
TWI655719B (zh) 電子模組
KR102576764B1 (ko) 비대칭 칩 스택들을 가지는 반도체 패키지
TWI663701B (zh) 電子封裝件及其製法
US10037938B2 (en) Semiconductor packages
TWI593165B (zh) 電子封裝件
TWI611542B (zh) 電子封裝結構及其製法
CN110828429B (zh) 电子封装件
KR20100112446A (ko) 적층형 반도체 패키지 및 그 제조 방법
TWI528632B (zh) 電子封裝件及其製法
TWI553732B (zh) 電子封裝件
US8703535B2 (en) Integrated circuit packaging system with warpage preventing mechanism and method of manufacture thereof
TWI624113B (zh) 電子模組
TWI517494B (zh) 電子封裝件
TW201446089A (zh) 半導體封裝件及其製法
TWI515865B (zh) 多晶片堆疊封裝結構及其製造方法
TWI549359B (zh) 電子組件
CN107622981B (zh) 电子封装件及其制法
TWI613767B (zh) 電子封裝件及其製法
TWI604593B (zh) 半導體封裝件及其製法
CN107819188B (zh) 电子封装件
TWI768322B (zh) 電子裝置及其製法
TWI672783B (zh) 電子封裝件
TWI527306B (zh) 電子組件
TWI558286B (zh) 封裝結構及其製法