TWI581403B - Semiconductor device and method of fabricating the semiconductor device and data storage device having computer executable program instructions stored thereon for rendering layout of the semiconductor device - Google Patents
Semiconductor device and method of fabricating the semiconductor device and data storage device having computer executable program instructions stored thereon for rendering layout of the semiconductor device Download PDFInfo
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L21/8232—Field-effect technology
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Description
本發明係關於一種半導體裝置。The present invention relates to a semiconductor device.
吾人已知光學微影在193 nm光波長和1.35數值孔徑（NA, numerical aperture）浸沒系統已達到其能力的終點。這個設備的最小直線解析能力係大約40 nm以及大約80 nm的特徵部間節距。低於約80 nm的特徵部間節距需求，則需要一給定晶片階層內一給定結構型態的多重圖案化步驟。此外，隨著將微影推向其解析度的極限，線端解析度變得更具挑戰性。在半導體裝置佈局中，於32 nm關鍵尺寸之典型金屬線節距係大約100 nm。為了達到特徵部縮放（feature scaling）的成本效益，期望有0.7至0.75的縮放因數（scaling factor）。為達到22 nm關鍵尺寸之約0.75的縮放因數，將需要約75 nm的金屬線節距，這節距低於目前單一曝光微影系統和技術的能力。在此背景下產生本發明。It is known that optical lithography has reached the end of its ability at 193 nm wavelength and 1.35 numerical aperture (NA) immersion systems. The minimum linear resolution capability of this device is approximately 40 nm and an inter-feature pitch of approximately 80 nm. An inter-feature pitch requirement of less than about 80 nm requires a multiple patterning step for a given structural pattern within a given wafer hierarchy. In addition, as the lithography pushes to the limit of its resolution, line-end resolution becomes more challenging. In a semiconductor device layout, a typical metal line pitch of a critical dimension of 32 nm is approximately 100 nm. In order to achieve the cost-effectiveness of feature scaling, a scaling factor of 0.7 to 0.75 is desired. To achieve a scaling factor of approximately 0.75 for a 22 nm critical dimension, a wire pitch of approximately 75 nm will be required, which is lower than current single exposure lithography systems and techniques. The present invention has been produced in this context.
在一實施例中，一半導體裝置包含一基板、一第一電晶體、及一第二電晶體。該第一電晶體具有在一第一擴散鰭部之內的一源極區域及一汲極區域。該第一擴散鰭部建構成自該基板的一表面突出。該第一擴散鰭部建構成自該第一擴散鰭部的一第一端部至該第一擴散鰭部的一第二端部在一第一方向上縱向延伸。該第二電晶體具有在一第二擴散鰭部之內的一源極區域及一汲極區域。該第二擴散鰭部建構成自該基板的該表面突出。該第二擴散鰭部建構成自該第二擴散鰭部的一第一端部至該第二擴散鰭部的一第二端部在該第一方向上縱向延伸。該第二擴散鰭部配置成緊鄰該第一擴散鰭部且與該第一擴散鰭部分隔開。此外，該第二擴散鰭部的該第一端部或該第二端部至少其中一者係配置於該第一方向上介於該第一擴散鰭部的該第一端部和該第二端部之間。In one embodiment, a semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor has a source region and a drain region within a first diffusion fin. The first diffusion fin is formed to protrude from a surface of the substrate. The first diffusion fin is formed to extend longitudinally from a first end of the first diffusion fin to a second end of the first diffusion fin in a first direction. The second transistor has a source region and a drain region within a second diffusion fin. The second diffusion fin is configured to protrude from the surface of the substrate. The second diffusion fin is formed to extend longitudinally from the first end of the second diffusion fin to a second end of the second diffusion fin in the first direction. The second diffusion fin is disposed adjacent to the first diffusion fin and spaced apart from the first diffusion fin portion. In addition, at least one of the first end portion or the second end portion of the second diffusion fin portion is disposed in the first direction between the first end portion and the second portion of the first diffusion fin portion Between the ends.
在一個實施例中，揭露一種製造半導體裝置的方法。該方法包含提供一基板。該方法亦包含在該基板上形成一第一電晶體，使得該第一電晶體具有在一第一擴散鰭部之內的一源極區域及一汲極區域，且使得該第一擴散鰭部建構成自該基板的一表面突出，且使得該第一擴散鰭部建構成自該第一擴散鰭部的一第一端部至該第一擴散鰭部的一第二端部在一第一方向上縱向延伸。該方法亦包含在該基板上形成一第二電晶體，使得該第二電晶體具有在一第二擴散鰭部之內的一源極區域及一汲極區域，且使得該第二擴散鰭部建構成自該基板的該表面突出，且使得該第二擴散鰭部建構成自該第二擴散鰭部的一第一端部至該第二擴散鰭部的一第二端部在該第一方向上縱向延伸，且使得該第二擴散鰭部係在緊鄰該第一擴散鰭部且與該第一擴散鰭部分隔開的位置處形成。此外，該第一和第二電晶體係形成為，該第二擴散鰭部的該第一端部或該第二端部至少其中一者係在該第一方向上介於該第一擴散鰭部的該第一端部和該第二端部之間的位置處形成。In one embodiment, a method of fabricating a semiconductor device is disclosed. The method includes providing a substrate. The method also includes forming a first transistor on the substrate such that the first transistor has a source region and a drain region within a first diffusion fin, and the first diffusion fin Constructing a surface protruding from the substrate, and the first diffusion fin is formed from a first end of the first diffusion fin to a second end of the first diffusion fin at a first Longitudinally extending in the direction. The method also includes forming a second transistor on the substrate such that the second transistor has a source region and a drain region within a second diffusion fin, and the second diffusion fin Constructing a surface protruding from the surface of the substrate, and causing the second diffusion fin to be formed from a first end of the second diffusion fin to a second end of the second diffusion fin at the first The direction extends longitudinally and such that the second diffusion fin is formed adjacent to the first diffusion fin and spaced apart from the first diffusion fin portion. In addition, the first and second electro-crystalline systems are formed such that at least one of the first end or the second end of the second diffusion fin is interposed between the first diffusion fin in the first direction A position is formed between the first end portion and the second end portion of the portion.
在一個實施例中，一種資料儲存裝置具有用於提供半導體裝置佈局之電腦可執行程式指令儲存於其上。該資料儲存裝置包含定義在一基板上形成的一第一晶體的電腦程式指令，使得該第一電晶體定義成具有在一第一擴散鰭部之內的一源極區域及一汲極區域，且使得該第一擴散鰭部定義成自該基板的一表面突出，且使得該第一擴散鰭部定義成自該第一擴散鰭部的一第一端部至該第一擴散鰭部的一第二端部在一第一方向上縱向延伸。該資料儲存裝置亦包含定義在該基板上形成的一第二晶體的電腦程式指令，使得該第二電晶體定義成具有在一第二擴散鰭部之內的一源極區域及一汲極區域，且使得該第二擴散鰭部定義成自該基板的該表面突出，且使得該第二擴散鰭部定義成自該第二擴散鰭部的一第一端部至該第二擴散鰭部的一第二端部在該第一方向上縱向延伸，且使得該第二擴散鰭部定義成與該第一擴散鰭部緊鄰且分隔開而加以配置，且使得該第二擴散鰭部定義成其第一端部或其第二端部至少其中一者係配置在該第一方向上介於該第一擴散鰭部的該第一端部和該第二端部之間。In one embodiment, a data storage device has computer executable program instructions for providing a semiconductor device layout stored thereon. The data storage device includes computer program instructions defining a first crystal formed on a substrate such that the first transistor is defined to have a source region and a drain region within a first diffusion fin. And defining the first diffusion fin to protrude from a surface of the substrate, and defining the first diffusion fin to be defined from a first end of the first diffusion fin to the first diffusion fin The second end extends longitudinally in a first direction. The data storage device also includes computer program instructions defining a second crystal formed on the substrate such that the second transistor is defined to have a source region and a drain region within a second diffusion fin And defining the second diffusion fin to protrude from the surface of the substrate, and defining the second diffusion fin to be defined from a first end of the second diffusion fin to the second diffusion fin a second end portion extends longitudinally in the first direction, and the second diffusion fin portion is defined to be disposed adjacent to and spaced apart from the first diffusion fin portion, and the second diffusion fin portion is defined as At least one of the first end portion or the second end thereof is disposed between the first end portion and the second end portion of the first diffusion fin portion in the first direction.
在以下說明中，描述多個特定細節以提供對本發明的完整理解。然而，對熟習此技藝者顯而易見的是，本發明可在不具備若干或全部這些特定細節下加以實施。在其他方面，眾所周知的製程操作不再詳細描述，以免不必要混淆本發明。此外，應理解的是，在此處展示之一特定圖示中所描繪的各種電路及/或佈局特徵部，可與在此處展示之其他圖示中所描繪的其他電路及/或佈局特徵部組合而運用。In the following description, numerous specific details are set forth It will be apparent to those skilled in the art, however, that the invention may be practiced without some or all of these specific details. In other respects, well-known process operations are not described in detail to avoid obscuring the invention. In addition, it should be understood that various circuits and/or layout features depicted in one particular illustration herein may be combined with other circuits and/or layout features depicted in other figures presented herein. Use in combination.
「鰭式場效電晶體」係由垂直的矽島（即鰭部）所建構的電晶體。鰭式場效電晶體亦可稱作三閘極電晶體。此處所使用之術語「鰭式場效電晶體」係關於包含自下層基板向上突出之擴散結構的任何電晶體構造。圖1A及1B顯示根據本發明若干實施例之鰭式場效電晶體100的例示佈局視圖。鰭式場效電晶體100係由擴散鰭部102和閘極電極層104所構成。擴散鰭部102由基板105垂直向上突出，如圖1B所顯示。閘極氧化物層106係配置於擴散鰭部102和閘極電極層104之間。擴散鰭部102可加以摻雜，以形成p型電晶體或n型電晶體。覆蓋擴散鰭部102之閘極電極層104的部分，形成鰭式場效電晶體100的閘極電極。因此，相對於在非鰭式場效電晶體中由一側提供通道的控制，鰭式場效電晶體100的閘極電極可存在於擴散鰭部102的三個以上側邊，藉此提供由三個以上側邊之鰭式場效電晶體通道的控制。此外，在若干實施例中，鰭式場效電晶體形成為「環繞式」電晶體，其中閘極氧化物層106和閘極電極層104亦在擴散鰭部102下方延伸。"Fin field effect transistor" is a transistor constructed by vertical islands (ie, fins). A fin field effect transistor can also be referred to as a three gate transistor. The term "Fin Field Effect Transistor" as used herein relates to any transistor configuration comprising a diffusion structure that protrudes upward from the underlying substrate. 1A and 1B show an exemplary layout view of a fin field effect transistor 100 in accordance with several embodiments of the present invention. The fin field effect transistor 100 is composed of a diffusion fin portion 102 and a gate electrode layer 104. The diffusion fins 102 protrude vertically upward from the substrate 105 as shown in FIG. 1B. The gate oxide layer 106 is disposed between the diffusion fin portion 102 and the gate electrode layer 104. The diffusion fins 102 can be doped to form a p-type transistor or an n-type transistor. A portion of the gate electrode layer 104 of the diffusion fin 102 is covered to form a gate electrode of the FinFET 100. Therefore, the gate electrode of the FinFET 100 may exist on more than three sides of the diffusion fin 102 with respect to the control of providing the channel by one side in the non-fin field effect transistor, thereby providing three Control of the fin field effect transistor channel on the above side. Moreover, in some embodiments, the fin field effect transistor is formed as a "wraparound" transistor, with the gate oxide layer 106 and the gate electrode layer 104 also extending below the diffusion fins 102.
應理解的是，在圖1A及1B中所描繪的例示鰭式場效電晶體100，係以例示為目的而提供，不代表對此處所參照之鰭式場效電晶體的設計及/或製造方式的任何限制。具體而言，在若干實施例中，擴散鰭部（如102）可形成為不同材料的成層，其包含但不限定於Si（矽）、SiGe（矽鍺）、Ge（鍺）、InP（磷化銦）、CNT（奈米碳管）、SiNT（矽奈米管）、或其任何組合。閘極氧化物層106可由許多不同類型的介電材料加以形成。舉例來說，在若干實施例中，閘極氧化物層106可形成為在一二氧化矽層上的一鉿氧化物層。在其他實施例中，閘極氧化物層106可由一種以上其他介電材料加以形成。在若干實施例中，閘極電極層104可由任何數量之導電材料加以形成。舉例來說，在若干實施例中，閘極電極層104可形成為由多晶矽所覆蓋之一TiN（鈦氮化物）膜或一TaN（鉭氮化物）膜。然而，應理解的是，在其他實施例中，閘極電極層104可由其他材料所形成。It should be understood that the exemplary fin field effect transistor 100 depicted in FIGS. 1A and 1B is provided for illustrative purposes and does not represent a design and/or fabrication of the fin field effect transistor referenced herein. Any restrictions. In particular, in several embodiments, the diffusion fins (eg, 102) may be formed as layers of different materials including, but not limited to, Si (germanium), SiGe (germanium), Ge (germanium), InP (phosphorus) Indium), CNT (nanocarbon tube), SiNT (tanometer tube), or any combination thereof. The gate oxide layer 106 can be formed from a number of different types of dielectric materials. For example, in some embodiments, the gate oxide layer 106 can be formed as a tantalum oxide layer on a layer of germanium dioxide. In other embodiments, the gate oxide layer 106 can be formed from more than one other dielectric material. In several embodiments, the gate electrode layer 104 can be formed from any number of electrically conductive materials. For example, in some embodiments, the gate electrode layer 104 can be formed as a TiN (titanium nitride) film or a TaN (yttrium nitride) film covered by polysilicon. However, it should be understood that in other embodiments, the gate electrode layer 104 may be formed of other materials.
此外，雖然將圖1B的例示擴散鰭部102在該垂直剖面視圖A-A中顯示為具有相對於基板105的實質上垂直突出矩形結構，應理解的是，在半導體晶片上於「製造後（as-fabricated）」狀態的擴散鰭部102可能具有或可能不具有相對於基板105的實質上垂直突出矩形結構。舉例來說，在若干實施例中，於其「製造後（as-fabricated）」狀態的擴散鰭部102在垂直剖面視圖A-A中可能具有更為三角形或角錐形的形狀。圖1C顯示鰭式場效電晶體100的變化，其中在垂直剖面視圖A-A中擴散鰭部102係更為角錐形。如圖1C所描繪，在若干實施例中，自基板105向上延伸的擴散鰭部102的側邊，可能以相對於基板105的一個角度自基板向上延伸，以致不垂直於基板105。此外，應理解的是，基板105與自基板105向上延伸之擴散鰭部102側邊之間的此非垂直關係，可能係經設計或者可能係製造的結果。In addition, although the exemplary diffusion fin 102 of FIG. 1B is shown in the vertical cross-sectional view AA as having a substantially vertically protruding rectangular structure with respect to the substrate 105, it should be understood that on the semiconductor wafer after "manufacturing (as- The diffusion fins 102 in the fabricated state may or may not have a substantially vertically protruding rectangular structure relative to the substrate 105. For example, in some embodiments, the diffusion fins 102 in their "as-fabricated" state may have a more triangular or pyramidal shape in the vertical cross-sectional view A-A. 1C shows a variation of the fin field effect transistor 100 in which the diffusion fins 102 are more pyramidal in the vertical cross-sectional view A-A. As depicted in FIG. 1C, in some embodiments, the sides of the diffusion fins 102 that extend upwardly from the substrate 105 may extend upwardly from the substrate at an angle relative to the substrate 105 such that they are not perpendicular to the substrate 105. Moreover, it should be understood that this non-perpendicular relationship between the substrate 105 and the sides of the diffusion fins 102 extending upward from the substrate 105 may be the result of design or possible fabrication.
此外，在若干實施例中，在基板105上方擴散鰭部102的垂直突出距離，在半導體晶片的一個區域範圍內係實質上相等。然而，在其他實施例中，可將若干擴散鰭部102設計成和製造成在半導體晶片的一或多個區域的範圍內於基板105上方具有多個不同的垂直突出距離。因為鰭式場效電晶體100的通道面積係基板105上方擴散鰭部102垂直突出距離的函數，在基板105上方擴散鰭部102垂直突出距離的此變化可用以調整選定鰭式場效電晶體100相對半導體晶片上其他者的驅動強度。在一個範例中，在擴散鰭部102高度的選擇性變化可藉由在製造期間選擇性蝕刻/過蝕刻擴散鰭部102結構而加以提供。Moreover, in several embodiments, the vertical protrusion distance of the diffusion fins 102 above the substrate 105 is substantially equal over a range of regions of the semiconductor wafer. However, in other embodiments, the plurality of diffusion fins 102 can be designed and fabricated to have a plurality of different vertical protrusion distances above the substrate 105 over a range of one or more regions of the semiconductor wafer. Because the channel area of the fin field effect transistor 100 is a function of the vertical protrusion distance of the diffusion fins 102 above the substrate 105, this variation of the vertical protrusion distance of the diffusion fins 102 above the substrate 105 can be used to adjust the selected fin field effect transistor 100 relative to the semiconductor. The drive strength of the other on the wafer. In one example, the selective change in height of the diffusion fins 102 can be provided by selectively etching/over etching the diffusion fins 102 structure during fabrication.
圖1D顯示根據本發明若干實施例之具有數個鰭式場效電晶體100形成於其上的基板105的簡化垂直剖面圖。在鰭式場效電晶體100的製造期間，形成一系列核心部107，以促進該等核心部107每一者的側間隔部109的形成。側間隔部109係用以作為遮罩特徵以促進下方鰭式場效電晶體100的形成。應理解的是，核心部107、側間隔部109、及鰭式場效電晶體100係以平行方式縱向延伸，即如圖1D所示之進入頁面方向延伸。應理解的是，核心部107和側間隔部109最終被移除，而不存在於最終製造後（as-fabricated）半導體晶片/裝置之中。鰭式場效電晶體100彼此間相對間距係核心部107和側間隔部109之尺寸和間距的函數。1D shows a simplified vertical cross-sectional view of a substrate 105 having a plurality of fin field effect transistors 100 formed thereon in accordance with several embodiments of the present invention. During fabrication of the fin field effect transistor 100, a series of core portions 107 are formed to facilitate the formation of the side spacers 109 of each of the core portions 107. The side spacers 109 serve as mask features to facilitate the formation of the lower fin field effect transistor 100. It should be understood that the core portion 107, the side spacer portion 109, and the fin field effect transistor 100 extend longitudinally in a parallel manner, i.e., extend into the page direction as shown in FIG. 1D. It should be understood that core portion 107 and side spacers 109 are ultimately removed and are not present in the as-fabricated semiconductor wafer/device. The relative spacing of the fin field effect transistors 100 from one another is a function of the size and spacing of the core portion 107 and the side spacers 109.
圖1D將核心部107顯示為具有寬度Wb和節距Pb。此外，圖1D將側間隔部109顯示為具有寬度Ws。如此鰭式場效電晶體100可被特徵化為具有一對交替的鰭部節距Ps1、Ps2，其中Ps1係一給定核心部107的側間隔部109之間的平均中心線至中心線節距（Ps1被稱作內鰭部節距），且其中Ps2係相鄰配置的核心部107的相鄰側間隔部109之間的平均中心線至中心線節距（Ps2被稱作外鰭部節距）。假設各個核心部107的寬度Wb、核心部107節距Pb、及側間隔部109寬度Ws係一致的，內鰭部節距Ps1係等於核心部107寬度Wb和側間隔部109寬度Ws的和。並且，外鰭部節距Ps2係等於核心部107節距Pb減去核心部107寬度Wb及側間隔部109寬度Ws的和。因此，內鰭部節距Ps1和外鰭部節距Ps2二者將隨核心部107節距Pb、核心部107寬度Wb、及/或側間隔部109寬度Ws每一者改變而變化。因此，應理解的是，提及一特定的「鰭部節距」，係指一特定鰭部節距的平均，亦即是鰭部節距Ps_ave係等於內鰭部節距Ps1和外鰭部節距Ps2的平均，其中內鰭部節距Ps1和外鰭部節距Ps2每一者本身亦為平均值。圖1D中寬度和節距關係如下： Ps1 = Wb + Ws Ps2 = Pb – Wb – Ws Pb = Ps1 + Ps2 若Ps1 = Ps2 （即一相等鰭部節距），則： Wb + Ws = Pb – Wb – Ws → Pb = 2 (Wb+Ws) Ps1和Ｐs2可隨Pb、Wb、及/或Ws變化而改變。 因此提及一特定的「鰭部節距」，係指一特定鰭部節距的平均，亦即是Ps_ave係等於平均Ps1、和平均Ps2。FIG. 1D shows the core portion 107 as having a width Wb and a pitch Pb. Further, FIG. 1D shows the side spacer 109 as having a width Ws. Such a FinFET 100 can be characterized as having a pair of alternating fin pitches Ps1, Ps2, where Ps1 is the average centerline to centerline pitch between the side spacers 109 of a given core 107 (Ps1 is referred to as inner fin pitch), and wherein Ps2 is an average center line to centerline pitch between adjacent side spacers 109 of the core portion 107 disposed adjacent to each other (Ps2 is referred to as an outer fin section) distance). Assuming that the width Wb of each core portion 107, the pitch Pb of the core portion 107, and the width Ws of the side spacer portion 109 coincide, the inner fin pitch Ps1 is equal to the sum of the width Wb of the core portion 107 and the width Ws of the side spacer portion 109. Further, the outer fin pitch Ps2 is equal to the sum of the core portion 107 pitch Pb minus the core portion 107 width Wb and the side spacer portion 109 width Ws. Therefore, both the inner fin pitch Ps1 and the outer fin pitch Ps2 will vary with each of the core portion 107 pitch Pb, the core portion 107 width Wb, and/or the side spacer portion width Ws. Therefore, it should be understood that reference to a particular "fin pitch" refers to the average of a particular fin pitch, that is, the fin pitch Ps_ave is equal to the inner fin pitch Ps1 and the outer fin. The average of the pitches Ps2, in which the inner fin pitch Ps1 and the outer fin pitch Ps2 themselves are also average values. The width and pitch relationship in Figure 1D is as follows: Ps1 = Wb + Ws Ps2 = Pb – Wb – Ws Pb = Ps1 + Ps2 If Ps1 = Ps2 (ie an equal fin pitch): Wb + Ws = Pb – Wb – Ws → Pb = 2 (Wb+Ws) Ps1 and Ps2 may change with changes in Pb, Wb, and/or Ws. Therefore, a specific "fin pitch" refers to the average of a particular fin pitch, that is, the Ps_ave is equal to the average Ps1 and the average Ps2.
圖1E顯示根據本發明若干實施例的鰭部節距關係的示圖，其中內鰭部節距Ps1係實質上等於外鰭部節距Ps2。元件高度Hc係等於平均鰭部節距乘上一有理數，即乘以整數x和y的比例，其中x係有理數的分子而y係有理數的分母。在圖1E的實例中，其中內鰭部節距Ps1和外鰭部節距Ps2係相等，平均鰭部節距係等於Ps1和Ps2每一者。因此，元件高度Hc係等於內鰭部節距Ps1或外鰭部節距Ps2任一者乘以該有理數。應理解的是，有理數的分母（y）表示一元件的數量，當該數量的元件以鄰接方式配置於元件高度Hc的方向（即垂直於鰭部縱向方向之方向）時需要該數量元件取得鰭部至元件邊界間距的重複。此外，當有理數的分子（x）可被有理數分母（y）整除時，頂部和底部元件邊界在內鰭部節距Ps1和/或外鰭部節距Ps2係對齊（指向至（indexed to））於元件邊界時可具有相同的鰭部至元件邊界間距。圖1E中高度和節距關係如下： Hc = (x/y)(Ps1) 或 Hc = (x/y)(Ps2)，其中x和y係整數 在圖1E的範例中， Ps1 = Ps2 → Pb = 2(Wb+Ws) x=9, y=1 → Hc = (9/1)(Ps1) 或 Hc = (9/1)(Ps2) 因為y=1，鰭部至元件邊界間距係每一元件高度重複一次，並且由於x被y整除，當至少一個鰭部節距（Ps1或Ps2）係與一元件邊界對齊時，頂部和底部元件邊界可具有相同的鰭部至元件邊界間距。1E shows a diagram of a fin pitch relationship in which the inner fin pitch Ps1 is substantially equal to the outer fin pitch Ps2, in accordance with several embodiments of the present invention. The component height Hc is equal to the average fin pitch multiplied by a rational number, ie multiplied by the ratio of the integers x and y, where x is the numerator of the rational number and the y is the denominator of the rational number. In the example of FIG. 1E, where the inner fin pitch Ps1 and the outer fin pitch Ps2 are equal, the average fin pitch is equal to each of Ps1 and Ps2. Therefore, the element height Hc is equal to either the inner fin pitch Ps1 or the outer fin pitch Ps2 multiplied by the rational number. It should be understood that the denominator (y) of the rational number represents the number of elements that are required to be taken when the number of elements are disposed in an abutting manner in the direction of the element height Hc (ie, perpendicular to the longitudinal direction of the fin). Repeat to the component boundary spacing. Furthermore, when the rational number of molecules (x) can be divisible by the rational number denominator (y), the top and bottom element boundaries are aligned at the inner fin pitch Ps1 and/or the outer fin pitch Ps2 (indexed to) The same fin-to-element boundary spacing can be achieved at the element boundaries. The height and pitch relationship in Figure 1E is as follows: Hc = (x/y)(Ps1) or Hc = (x/y)(Ps2), where x and y are integers in the example of Figure 1E, Ps1 = Ps2 → Pb = 2(Wb+Ws) x=9, y=1 → Hc = (9/1)(Ps1) or Hc = (9/1)(Ps2) Since y=1, the fin-to-element boundary is each The element height is repeated once, and since x is divisible by y, the top and bottom element boundaries may have the same fin-to-element boundary spacing when at least one fin pitch (Ps1 or Ps2) is aligned with an element boundary.
圖1F顯示根據本發明若干實施例之圖1E的鰭部節距關係示圖的變化，其中有理數的分母（y）係二。因此，在圖1F中，鰭部至元件邊界間距每二個元件高度Hc會重複。此外，在圖1F的範例中，有理數分子（x）不被有理數分母（y）所整除。因此，當內鰭部節距Ps1和/或外鰭部節距Ps2係對齊（指向（indexed to））於元件邊界時，頂部和底部鰭部至元件邊界間距將會不同。圖1F中高度和節距關係如下： Hc = (x/y)(Ps1) 或 Hc = (x/y)(Ps2)，其中x和y係整數 在圖1F的範例中， Ps1 = Ps2 → Pb = 2(Wb+Ws) x=17, y=2 → Hc = (17/2)(Ps1) 或 Hc = (17/2)(Ps2) 因為y=2，鰭部至元件邊界間距係每二元件高度重複一次，並且由於x無法被y整除，當至少一個鰭部節距（Ps1或Ps2）係與一元件邊界對齊時，頂部和底部元件邊界將具有不同的鰭部至元件邊界間距。1F shows a variation of the fin pitch relationship diagram of FIG. 1E in accordance with several embodiments of the present invention, wherein the denominator (y) of the rational number is two. Therefore, in FIG. 1F, the fin-to-element boundary pitch is repeated every two element heights Hc. Furthermore, in the example of Fig. 1F, the rational number molecule (x) is not divisible by the rational number denominator (y). Therefore, when the inner fin pitch Ps1 and/or the outer fin pitch Ps2 are aligned (indexed to) to the element boundary, the top and bottom fin-to-element boundary spacing will be different. The height and pitch relationship in Figure 1F is as follows: Hc = (x/y)(Ps1) or Hc = (x/y)(Ps2), where x and y are integers in the example of Figure 1F, Ps1 = Ps2 → Pb = 2(Wb+Ws) x=17, y=2 → Hc = (17/2)(Ps1) or Hc = (17/2)(Ps2) Since y=2, the fin-to-element boundary is every two The element height is repeated once, and since x cannot be divisible by y, the top and bottom element boundaries will have different fin-to-element boundary spacing when at least one fin pitch (Ps1 or Ps2) is aligned with an element boundary.
圖1G顯示根據本發明若干實施例之圖1E的鰭部節距關係示圖的變化，其中有理數的分母（y）係三。因此，在圖1G中，鰭部至元件邊界間距每三個元件高度Hc會重複。此外，在圖1G的範例中，有理數分子（x）不被有理數分母（y）所整除。因此，當內鰭部節距Ps1和/或外鰭部節距Ps2係對齊（指向（indexed to））於元件邊界時，頂部和底部鰭部至元件邊界間距將會不同。應理解的是，有理數可由用以取得在元件高度Hc方向任何所欲鰭部至元件邊界間距重複頻率及/或任何所欲鰭部至元件邊界間距規格所需的任何方式加以定義。1G shows a variation of the fin pitch relationship diagram of FIG. 1E in accordance with several embodiments of the present invention, wherein the denominator (y) of the rational number is three. Therefore, in FIG. 1G, the fin-to-element boundary pitch is repeated every three element heights Hc. Furthermore, in the example of Figure 1G, the rational number molecule (x) is not divisible by the rational number denominator (y). Therefore, when the inner fin pitch Ps1 and/or the outer fin pitch Ps2 are aligned (indexed to) to the element boundary, the top and bottom fin-to-element boundary spacing will be different. It should be understood that the rational number may be defined by any means needed to achieve any desired fin-to-element boundary spacing repetition frequency and/or any desired fin-to-element boundary spacing specification in the component height Hc direction.
圖1H顯示根據本發明若干實施例之圖1E的鰭部節距關係示圖的更廣義版本，其中內鰭部節距Ps1和外鰭部節距Ps2係不同。在這個範例中，外鰭部節距Ps2係大於內鰭部節距Ps1。應理解的是，元件高度Hc係等於平均鰭部節距Ps_ave 乘以有理數（x/y），其中x和y係整數。此外，應理解的是，整數y表示在元件高度Hc方向上鰭部至元件邊界間距的重複頻率。此外，應理解的是，當有理數（x/y）化簡為一整數值（即當x被y整除）時，頂部和底部鰭部至元件邊界間距可彼此相等。如果有理數（x/y）不能化簡為一整數值，一特定元件的不同鰭部相位變化可定義於元件庫，其中各個鰭部相位變化對應該特定元件的不同可能的鰭部至元件邊界間距關係。此外，一特定元件的可能鰭部相位變化數量將等於在數學上最簡型式之有理數（x/y）的分母（y）。圖1G中高度和節距關係如下： Hc = (x/y)(Ps1) 或 Hc = (x/y)(Ps2)，其中x和y係整數 在圖1G的範例中， Ps1 = Ps2 → Pb = 2(Wb+Ws) x=25, y=3 → Hc = (25/3)(Ps1) 或 Hc = (25/3)(Ps2) 因為y=3，鰭部至元件邊界間距係每三元件高度重複一次，並且由於x無法被y整除，當至少一個鰭部節距（Ps1或Ps2）係與一元件邊界對齊時，頂部和底部元件邊界將具有不同的鰭部至元件邊界間距。1H shows a broader version of the fin pitch relationship diagram of FIG. 1E in which the inner fin pitch Ps1 and the outer fin pitch Ps2 are different, in accordance with several embodiments of the present invention. In this example, the outer fin pitch Ps2 is greater than the inner fin pitch Ps1. It should be understood that the component height Hc is equal to the average fin pitch Ps_ave multiplied by the rational number (x/y), where x and y are integers. Further, it should be understood that the integer y represents the repetition frequency of the fin-to-element boundary pitch in the element height Hc direction. Furthermore, it should be understood that when the rational number (x/y) is reduced to an integer value (ie, when x is divisible by y), the top and bottom fin-to-element boundary spacings may be equal to each other. If the rational number (x/y) cannot be reduced to an integer value, the different fin phase changes of a particular component can be defined in the component library, where each fin phase change corresponds to a different possible fin-to-element spacing of the particular component. relationship. Furthermore, the number of possible fin phase changes for a particular component will be equal to the denominator (y) of the mathematically simplest rational number (x/y). The height and pitch relationship in Figure 1G is as follows: Hc = (x/y)(Ps1) or Hc = (x/y)(Ps2), where x and y are integers in the example of Figure 1G, Ps1 = Ps2 → Pb = 2(Wb+Ws) x=25, y=3 → Hc = (25/3)(Ps1) or Hc = (25/3)(Ps2) Since y=3, the fin-to-element boundary is every three The element height is repeated once, and since x cannot be divisible by y, the top and bottom element boundaries will have different fin-to-element boundary spacing when at least one fin pitch (Ps1 or Ps2) is aligned with an element boundary.
如以上所探討的，圖1H顯示根據本發明若干實施例使用二個不同的擴散鰭部節距Ps1和Ps2。更具體而言，在圖1H中每隔一對相鄰配置的擴散鰭部結構依據較小的節距Ps1加以配置。在若干實施例中，較大的擴散鰭部節距Ps2係約80奈米（nm）且較小的擴散鰭部節距Ps1係約60 nm。然而，應理解的是，在其他實施例中，較小的擴散鰭部節距Ps1可為任何尺寸，且較大的擴散鰭部Ps2可為任何尺寸。應理解的是，若干實施例在一特定元件或區塊之內可利用超過二個擴散鰭部節距。並且，若干實施例在一特定元件或區塊之內可利用單一擴散鰭部節距。此外，應理解的是，半導體裝置的任何層或其部分，可以類似於此處所述關於擴散鰭部節距的方式加以形成。舉例來說，半導體裝置的一局部內連線層或一高階層內連線層或其部分，可包含以類似於此處所述關於擴散鰭部節距之方式依一個以上對應節距所形成的內連線傳導結構。圖1Ｈ中高度和節距關係如下： Hc = (x/y)(Ps_ave)，其中x和y係整數，且 Ps_ave係平均鰭部節距，例如[(Ps1+Ps2)/2] 在圖1H的範例中， Ps2 ＞ Ps1 x=10, y=1 → Hc = (10/1)(Ps_ave) 因為y=1，鰭部至元件邊界間距係每一元件高度重複一次，並且由於x被y整除，當至少一個鰭部節距（Ps1或Ps2）係與一元件邊界對齊時，頂部和底部元件邊界可具有相同的鰭部至元件邊界間距。As discussed above, Figure 1H shows the use of two different diffuser fin pitches Ps1 and Ps2 in accordance with several embodiments of the present invention. More specifically, every other pair of adjacently disposed diffusing fin structures in FIG. 1H is configured in accordance with a smaller pitch Ps1. In several embodiments, the larger diffusing fin pitch Ps2 is about 80 nanometers (nm) and the smaller diffusing fin pitch Ps1 is about 60 nm. However, it should be understood that in other embodiments, the smaller diffusion fin pitch Ps1 can be any size, and the larger diffusion fin Ps2 can be any size. It should be understood that several embodiments may utilize more than two diffuser fin pitches within a particular component or block. Also, several embodiments may utilize a single diffusing fin pitch within a particular component or block. Moreover, it should be understood that any layer or portion of the semiconductor device can be formed in a manner similar to that described herein with respect to the pitch of the diffusion fins. For example, a portion of the interconnect layer or a high level interconnect layer or portion thereof of the semiconductor device can comprise a plurality of corresponding pitches formed in a manner similar to the diffusion fin pitch described herein. The interconnect structure of the interconnect. The height and pitch relationship in Figure 1H is as follows: Hc = (x/y)(Ps_ave), where x and y are integers, and Ps_ave is the average fin pitch, for example [(Ps1+Ps2)/2] in Figure 1H In the example, Ps2 > Ps1 x=10, y=1 → Hc = (10/1)(Ps_ave) Since y=1, the fin-to-element boundary spacing is repeated once for each component height, and since x is divisible by y When at least one fin pitch (Ps1 or Ps2) is aligned with an element boundary, the top and bottom element boundaries may have the same fin-to-element boundary spacing.
由於閘極氧化物限制及/或源極/汲極漏流定比問題，電晶體縮放在45奈米（nm）關鍵尺寸以下已減緩。鰭式場效電晶體藉由從三側控制鰭式場效電晶體的通道減緩這些問題。在鰭式場效電晶體的通道中增加的電場增進I-on（開啟驅動電流）及I-off（次臨界漏電流）之間的關係。鰭式場效電晶體可應用於22 nm及以下之關鍵尺寸。然而，由於其垂直的突出，鰭式場效電晶體在各種電路佈局中可能有受限制的配置。舉例來說，可能有必要的鰭式場效電晶體之間最小間距、和/或必要的鰭式場效電晶體之間的最小節距等等。此處揭露的元件佈局的實施例，其以改進佈局縮放的方式運用鰭式場效電晶體。Due to gate oxide limitations and/or source/drain leakage ratio problems, transistor scaling has slowed below the 45 nanometer (nm) critical dimension. Fin field effect transistors alleviate these problems by controlling the channels of the fin field effect transistors from three sides. The increased electric field in the channel of the fin field effect transistor enhances the relationship between I-on (on drive current) and I-off (sub-critical leakage current). Fin field effect transistors are available for critical dimensions up to 22 nm. However, due to its vertical protrusion, fin field effect transistors may have a limited configuration in various circuit layouts. For example, it may be necessary to have a minimum spacing between fin field effect transistors, and/or a minimum pitch between the necessary fin field effect transistors, and the like. Embodiments of the component layout disclosed herein utilize a fin field effect transistor in a manner that improves layout scaling.
此處提及之元件（cell），代表邏輯功能的抽象名稱（abstraction），且囊括用以實施此邏輯功能之較低階的積體電路佈局。應理解的是，一特定邏輯功能可以多個元件變型來代表，其中該多個元件變型可以特徵部尺寸、效能以及製程補償技術（PCT）（process compensation technique）處理加以區分。例如，特定邏輯功能用之多個元件變型，係可以藉由功率消耗、訊號時序、漏電流、晶片面積、OPC（光學鄰近修正）、RET（光罩增強技術）等等加以區分。此外，多重元件變化可藉由於此所描述之次佈局序列組合(sub－layout sequence combination)加以區分。也應明瞭的是，每個元件的描述係包括於晶片相關聯的垂直欄之內在晶片之每個階層（或層）中的元件用之佈局，此為執行元件之邏輯功能所需要的。更具體而言，元件之描述係包括，由基板層次延伸通過特定之內連線階層的每一晶片階層中的元件佈局。The cell referred to herein represents the abstract name of the logic function and encompasses the lower order integrated circuit layout used to implement this logic function. It should be understood that a particular logic function can be represented by a plurality of component variations that can be distinguished by feature size, performance, and process compensation technique processing (PCT). For example, a plurality of component variations for a particular logic function can be distinguished by power consumption, signal timing, leakage current, wafer area, OPC (optical proximity correction), RET (mask enhancement technique), and the like. In addition, multiple component variations can be distinguished by the sub-layout sequence combination described herein. It should also be understood that the description of each component includes the layout of the components in each layer (or layer) of the wafer within the associated vertical column of the wafer, which is required for the logic function of the actuator. More specifically, the description of the components includes the layout of the components in each of the wafer levels extending through the substrate hierarchy through a particular interconnect level.
圖2A顯示根據本發明若干實施例之包含鰭式場效電晶體的例示元件佈局。該元件佈局包含一擴散階層，在該階層內定義數個擴散鰭部201A/201B，其用於鰭式場效電晶體和相關聯接線的後續形成。在若干實施例中，在佈局圖（as-drawn layout）狀態中，擴散鰭部201A/201B係線形的。擴散鰭部201A/201B係定向成彼此平行，使得其長度在一第一方向（x）上延伸，且使得其寬度在垂直於該第一方向（x）的一第二方向（y）上延伸。2A shows an exemplary component layout including a fin field effect transistor in accordance with several embodiments of the present invention. The component layout includes a diffusion level in which a plurality of diffusion fins 201A/201B are defined for subsequent formation of the fin field effect transistor and associated link lines. In several embodiments, the diffusion fins 201A/201B are linear in an as-drawn layout state. The diffusion fins 201A/201B are oriented parallel to each other such that their length extends in a first direction (x) such that their width extends in a second direction (y) perpendicular to the first direction (x) .
在若干實施例中，例如圖2A所顯示者，擴散鰭部201A/201B係根據一固定的縱向中心線至縱向中心線節距203而加以配置，節距203係在第二方向（y）上測得。在這個實施例中，擴散鰭部201A/201B的節距203可能相關於在第二方向（y）上測得的元件高度，使得擴散鰭部節距203可跨越元件邊界而持續。在圖2A中，元件毗鄰邊緣係代表平行於擴散鰭部201A/201B的元件邊界。在若干實施例中，多個相鄰的元件的擴散鰭部將根據共同的全域擴散鰭部節距而加以配置，藉此協助在多個元件中擴散鰭部的晶片階層製造。In several embodiments, such as shown in FIG. 2A, the diffusion fins 201A/201B are configured according to a fixed longitudinal centerline to a longitudinal centerline pitch 203, the pitch 203 being in the second direction (y). Measured. In this embodiment, the pitch 203 of the diffusion fins 201A/201B may be related to the element height measured in the second direction (y) such that the diffusion fin pitch 203 may continue across the element boundaries. In FIG. 2A, the adjacent edge of the element represents the element boundary parallel to the diffusion fin 201A/201B. In several embodiments, the diffusion fins of a plurality of adjacent elements will be configured according to a common global diffusion fin pitch, thereby facilitating wafer level fabrication of the diffusion fins in the plurality of elements.
應理解的是，其他實施例可能在一特定元件之內或一群元件之間使用多個擴散鰭部節距。舉例來說，圖2H顯示根據本發明若干實施例之圖2A的元件的變化，其中使用二個不同的擴散鰭部節距203和205。應理解的是，在若干實施例中，擴散鰭部201A/201B可根據一個以上縱向中心線至縱向中心線節距而配置，或者可以相對於縱向中心線至縱向中心線間距無限制的方式加以配置。此外，在若干實施例中，擴散鰭部201A/201B可根據一特定的節距加以配置，且若干節距位置可能關於擴散鰭部配置係未使用的。此外，在若干實施例中，可將擴散鰭部以分隔開、端到端的方式配置於一元件之內的特定擴散鰭部節距位置。It should be understood that other embodiments may use multiple diffusing fin pitches within a particular component or between a group of components. For example, Figure 2H shows a variation of the elements of Figure 2A in accordance with several embodiments of the present invention in which two different diffusion fin pitches 203 and 205 are used. It should be understood that in several embodiments, the diffusion fins 201A/201B may be configured according to more than one longitudinal centerline to longitudinal centerline pitch, or may be provided in an unrestricted manner relative to the longitudinal centerline to longitudinal centerline spacing. Configuration. Moreover, in several embodiments, the diffusion fins 201A/201B can be configured according to a particular pitch, and several pitch locations may be unused with respect to the diffusion fin configuration. Moreover, in several embodiments, the diffusing fins can be disposed in a spaced apart, end-to-end configuration at a particular diffusing fin pitch location within an element.
在此處所示各圖形中，各擴散鰭部（例如圖2A中的擴散鰭部201A/201B）係為n型擴散材料或p型擴散材料。此外，取決於特定的元件實現方式，擴散鰭部的材料類型可加以交換，以取得不同的元件邏輯功能。因此，在圖示中使用類型1擴散鰭部和類型2擴散鰭部標示，以表示擴散鰭部的不同材料類型。舉例來說，若類型1擴散鰭部材料係n型材料，則類型2擴散鰭部材料係p型材料，反之亦然。In each of the figures shown here, each of the diffusion fins (for example, the diffusion fins 201A/201B in FIG. 2A) is an n-type diffusion material or a p-type diffusion material. Furthermore, depending on the particular component implementation, the material types of the diffusion fins can be exchanged to achieve different component logic functions. Thus, Type 1 diffuser fins and Type 2 diffuser fins are used in the illustration to indicate different material types of the diffusing fins. For example, if the Type 1 diffused fin material is an n-type material, then the Type 2 diffused fin material is a p-type material and vice versa.
元件佈局亦包含數個線形閘極電極結構207。線形閘極電極結構207在實質上垂直於擴散鰭部201A/201B的方向延伸，即在第二方向（y）延伸。當製造時，線形閘極電極結構207覆蓋於擴散鰭部201A/201B的上方，以形成鰭式場效電晶體的閘極電極。應理解的是，適當的閘極氧化物材料係佈置（即配置/沉積）於擴散鰭部201Ａ/201B和形成於其上的閘極電極結構207之間。The component layout also includes a plurality of linear gate electrode structures 207. The linear gate electrode structure 207 extends in a direction substantially perpendicular to the diffusion fins 201A/201B, that is, in a second direction (y). When fabricated, a linear gate electrode structure 207 overlies the diffusion fins 201A/201B to form a gate electrode of the fin field effect transistor. It should be understood that a suitable gate oxide material is disposed (ie, configured/deposited) between the diffusion fins 201A/201B and the gate electrode structure 207 formed thereon.
在若干實施例中，將線形閘極電極結構207根據在第一方向（x）上相鄰配置的閘極電極結構207之縱向中心線之間所測得的一固定的閘極節距209加以配置。在若干實施例中，閘極節距209係相關於在第一方向（x）上所測得的元件寬度，使得閘極節距可跨越元件邊界而持續。因此，在若干實施例中，多個相鄰元件的閘極電極結構207可根據一共同的全域閘極節距而加以配置，藉此協助在多個元件中的線形閘極電極結構207的晶片階層製造。In some embodiments, the linear gate electrode structure 207 is based on a fixed gate pitch 209 measured between the longitudinal centerlines of the gate electrode structures 207 disposed adjacent in the first direction (x). Configuration. In several embodiments, the gate pitch 209 is related to the measured component width in the first direction (x) such that the gate pitch can continue across the component boundaries. Thus, in some embodiments, the gate electrode structures 207 of a plurality of adjacent elements can be configured according to a common global gate pitch, thereby assisting the wafer of linear gate electrode structures 207 in the plurality of elements. Class manufacturing.
應理解的是，在一特定元件中若干閘極節距位置可由閘極電極結構207所佔用，而在該特定元件中的其他閘極節距位置則維持未占用。因此，應理解的是，多個閘極電極結構207可以分隔開、端到端的方式在一特定元件之內沿著任何閘極電極節距位置加以配置。更應理解的是，在若干實施例中，可將閘極電極結構207根據一個以上閘極節距加以配置，或者可以相對於閘極節距無限制的方式加以配置。It should be understood that a number of gate pitch locations in a particular component may be occupied by the gate electrode structure 207 while other gate pitch locations in that particular component remain unoccupied. Thus, it should be understood that the plurality of gate electrode structures 207 can be disposed in a spaced apart, end-to-end manner along any gate electrode pitch location within a particular component. It will be further appreciated that in several embodiments, the gate electrode structure 207 can be configured in accordance with more than one gate pitch, or can be configured in an unrestricted manner relative to the gate pitch.
元件佈局亦可包含數個線形水平局部內連線結構（lih）211、及/或數個線形垂直局部內連線結構（liv）213。垂直局部內連線結構213係定向成平行於閘極電極結構207。水平局部內連線結構211係定向成平行於擴散鰭部201A/201B。在若干實施例中，垂直局部內連線結構213的配置，係定義成以半個閘極節距而與閘極電極結構207的配置異相。因此，在這個實施例中，當各垂直局部內連線結構213的相鄰閘極電極結構207係配置於閘極節距上，該垂直局部內連線結構213係位於其相鄰閘極結構207之間的中心。因此，在這個實施例中，相鄰配置的垂直局部內連線結構213將具有與一局部閘極節距或一全域閘極節距相等的中心到中心間距，其中局部閘極節距係適用於一特定元件之內，而全域閘極節距係適用在遍及多個元件的範圍內。The component layout may also include a plurality of linear horizontal local interconnect structures (lih) 211, and/or a plurality of linear vertical local interconnect structures (liv) 213. The vertical partial interconnect structure 213 is oriented parallel to the gate electrode structure 207. The horizontal partial interconnect structure 211 is oriented parallel to the diffusion fins 201A/201B. In some embodiments, the configuration of the vertical local interconnect structure 213 is defined to be out of phase with the configuration of the gate electrode structure 207 at a half gate pitch. Therefore, in this embodiment, when the adjacent gate electrode structures 207 of the respective vertical partial interconnect structures 213 are disposed on the gate pitch, the vertical partial interconnect structures 213 are located in their adjacent gate structures. Center between 207. Thus, in this embodiment, adjacently disposed vertical partial interconnect structures 213 will have a center-to-center spacing equal to a local gate pitch or a global gate pitch, where local gate pitch is applicable. Within a particular component, the global gate pitch is applicable over a range of components.
在若干實施例中，水平局部內連線結構211的配置，係定義成以半個擴散鰭部節距而與擴散鰭部201A/201B的配置異相。因此，在這個實施例中，當水平局部內連線結構211的相鄰擴散鰭部201A/201B係配置於擴散鰭部節距上，該水平局部內連線結構211可位於其相鄰擴散鰭部201A/201B之間的中心。因此，在這個實施例中，相鄰配置的水平局部內連線結構211將具有與一局部擴散鰭部節距或一全域擴散鰭部節距相等的中心到中心間距，其中局部擴散鰭部節距係適用於一特定元件之內，而全域擴散鰭部節距係適用在遍及多個元件的範圍內。In several embodiments, the configuration of the horizontal partial interconnect structure 211 is defined to be out of phase with the configuration of the diffuser fins 201A/201B at a half diffuse fin pitch. Therefore, in this embodiment, when the adjacent diffusion fins 201A/201B of the horizontal partial interconnect structure 211 are disposed on the diffusion fin pitch, the horizontal partial interconnect structure 211 may be located adjacent to the diffusion fins thereof. The center between the parts 201A/201B. Thus, in this embodiment, the adjacently disposed horizontal partial interconnect structures 211 will have a center-to-center spacing equal to a local diffused fin pitch or a global diffused fin pitch, wherein the locally diffused fin sections The distance system is suitable for use within a particular component, and the global diffusion fin pitch is suitable for use over a range of components.
在若干實施例中，元件佈局亦包含數個線形金屬層1（met1）內連線結構215。此met1內連線結構215係定向成平行於擴散鰭部201A/201B且垂直於閘極電極結構207。在若干實施例中，met1內連線結構215的配置，係定義成以半個擴散鰭部節距而與擴散鰭部201A/201B的配置異相。因此，在這個實施例中，雖然在較高的晶片階層內，當各met1內連線結構215的相鄰擴散鰭部係配置於擴散鰭部節距上，該met1內連線結構215係位於其相鄰擴散鰭部之間的中心。因此，在這個實施例中，相鄰配置的met1內連線結構215將具有與一局部擴散鰭部節距或一全域擴散鰭部節距相等的中心到中心間距，其中局部擴散鰭部節距係適用於一特定元件之內，而全域擴散鰭部節距係適用在遍及多個元件的範圍內。在若干實施例中，met1內連線結構215節距，以及由此之擴散軌道節距，係設定於單一曝光微影限制，例如1.35 NA及193 nm波長光用之80 nm。在這個實施例中，不需要雙重曝光微影，即多重圖案化，來製造met1內連線結構215。應理解的是，其他實施例可使用定向成垂直於擴散鰭部201A/201B且平行於閘極電極結構207的met1內連線結構215。In some embodiments, the component layout also includes a plurality of linear metal layer 1 (met1) interconnect structures 215. This met1 interconnect structure 215 is oriented parallel to the diffusion fins 201A/201B and perpendicular to the gate electrode structure 207. In several embodiments, the configuration of the met1 interconnect structure 215 is defined to be out of phase with the configuration of the diffuser fins 201A/201B at a half diffusion fin pitch. Therefore, in this embodiment, although in the higher wafer level, when the adjacent diffusion fins of each of the met1 interconnect structures 215 are disposed on the diffusion fin pitch, the met1 interconnect structure 215 is located. The center between its adjacent diffusing fins. Thus, in this embodiment, the adjacently configured met1 interconnect structures 215 will have a center-to-center spacing equal to a local diffused fin pitch or a global diffused fin pitch, wherein the local diffused fin pitch The system is suitable for use within a particular component, and the global diffusion fin pitch is applicable over a range of components. In several embodiments, the pitch of the me1 interconnect structure 215, and thus the spread track pitch, is set at a single exposure lithography limit, such as 1.3 nm for 1.35 NA and 193 nm wavelength light. In this embodiment, dual exposure lithography, i.e., multiple patterning, is not required to fabricate the me1 interconnect structure 215. It should be understood that other embodiments may use a metl interconnect structure 215 that is oriented perpendicular to the diffusion fins 201A/201B and parallel to the gate electrode structure 207.
元件佈局亦包含數個接觸窗217，其用以將各種met1內連線結構215連接至各種局部內連線結構211/213及閘極電極結構207，藉此提供實行元件邏輯功能所需的各種鰭式場效電晶體之間的電連接。在若干實施例中，接觸窗217係定義成滿足單一曝光微影限制。舉例來說，在若干實施例中，接觸窗217所需連接的佈局特徵部係分隔開到足以進行接觸窗217的單一曝光製造。舉例來說，met1內連線結構215係定義成其用以接受接觸窗217的線端，係與亦接受接觸窗217之相鄰met1內連線結構215的線端足夠分隔開，俾使接觸窗217之間的空間距離大到足以進行接觸窗217的單一曝光微影製程。在若干實施例中，相鄰接觸窗217係以至少1.5倍閘極節距彼此分隔。應理解的是，藉由將met1內連線結構215的對向的線端足夠地分離，可消除雙重曝光微影製程之線端切割（line end cutting）及相關聯的增加費用。應理解的是，取決於在製造過程中的選擇，金屬層上的接觸窗間隔和線端間隔在若干實施例中可相互獨立。The component layout also includes a plurality of contact windows 217 for connecting various met1 interconnect structures 215 to various local interconnect structures 211/213 and gate electrode structures 207, thereby providing the various functions required to perform component logic functions. Electrical connection between fin field effect transistors. In several embodiments, the contact window 217 is defined to satisfy a single exposure lithography limit. For example, in several embodiments, the layout features that the contact window 217 is required to connect are separated into a single exposure fabrication sufficient to make the contact window 217. For example, the met1 interconnect structure 215 is defined as the line end for receiving the contact window 217, which is sufficiently separated from the line end of the adjacent met1 interconnect structure 215 that also receives the contact window 217. The spatial distance between the contact windows 217 is large enough to perform a single exposure lithography process of the contact window 217. In several embodiments, adjacent contact windows 217 are separated from each other by at least 1.5 times the gate pitch. It will be appreciated that by sufficiently separating the opposing line ends of the met1 interconnect structure 215, line end cutting of the double exposure lithography process and associated increased cost can be eliminated. It will be appreciated that the contact window spacing and line end spacing on the metal layer may be independent of each other in several embodiments, depending on the choices made during the manufacturing process.
在若干實施例中，元件佈局也包含數個線形金屬層2（met2）內連線結構219。該met2內連線結構219係定向成平行於閘極電極207且垂直於擴散鰭部201A/201B。met2內連線結構219依實行元件邏輯功能的需要可透過介層窗結構（v1）221與met1內連線結構215物理性連接。雖然圖2A的例示元件顯示以縱向方式延伸垂直於閘極電極結構207的met1內連線結構215以及以縱向方式延伸平行於閘極電極結構207的met2內連線結構219，應理解的是在其他實施例中met1內連線結構215和met2內連線結構219可定義成以任何相對於閘極電極結構207的方向延伸。應理解的是，其他實施例可使用定向成垂直於閘極電極207且平行於擴散鰭部201A/201B的met2內連線結構219。In several embodiments, the component layout also includes a plurality of linear metal layer 2 (met2) interconnect structures 219. The met2 interconnect structure 219 is oriented parallel to the gate electrode 207 and perpendicular to the diffusion fins 201A/201B. The met2 interconnect structure 219 is physically coupled to the met1 interconnect structure 215 via a via structure (v1) 221 as required to perform the logic function of the component. Although the exemplary component of FIG. 2A shows a met1 interconnect structure 215 that extends perpendicular to the gate electrode structure 207 in a longitudinal direction and a met2 interconnect structure 219 that extends parallel to the gate electrode structure 207 in a longitudinal direction, it should be understood that In other embodiments, the met1 interconnect structure 215 and the met2 interconnect structure 219 may be defined to extend in any direction relative to the gate electrode structure 207. It should be understood that other embodiments may use a met2 interconnect structure 219 oriented perpendicular to the gate electrode 207 and parallel to the diffusion fins 201A/201B.
圖2A的元件代表一多輸入邏輯閘，該多輸入邏輯閘具有實質上對齊的輸入閘極電極，亦即是在方向（y）上共同對齊的中心的三個閘極電極結構207。取決於分派至類型1和類型2擴散鰭部的擴散材料類型，圖2A的元件可具有不同的邏輯功能。舉例來說，圖2D顯示圖2A的佈局，其中擴散鰭部201A係由n型擴散材料所形成，而擴散鰭部201B係由p型擴散材料所形成。圖2D的佈局係2輸入NAND閘的佈局。圖2B顯示對應圖2D的2輸入NAND構造的電路圖。圖2E顯示圖2A的佈局，其中擴散鰭部201A係由p型擴散材料所形成，而擴散鰭部201B係由n型擴散材料所形成。圖2E的佈局係2輸入NOR閘的佈局。圖2C顯示對應圖2E的2輸入NOR構造的電路圖。在圖2B-2E中，Ｐ1和Ｐ2每一者標示各自的p型電晶體（如PMOS電晶體），Ｎ1和N2每一者標示各自的n型電晶體（如NMOS電晶體），Ａ和B每一者標示各自的輸入節點，且Ｑ標示一輸出節點。應理解的是，在此處其他圖示中亦使用p型電晶體、n型電晶體、輸入節點、及輸出節點的類似符號。The component of Figure 2A represents a multi-input logic gate having substantially aligned input gate electrodes, i.e., three gate electrode structures 207 that are co-aligned in direction (y). The elements of Figure 2A may have different logic functions depending on the type of diffusing material assigned to the Type 1 and Type 2 diffuser fins. For example, FIG. 2D shows the layout of FIG. 2A in which the diffusion fins 201A are formed of an n-type diffusion material and the diffusion fins 201B are formed of a p-type diffusion material. The layout of Figure 2D is the layout of the 2-input NAND gate. 2B shows a circuit diagram corresponding to the 2-input NAND configuration of FIG. 2D. 2E shows the layout of FIG. 2A in which the diffusion fins 201A are formed of a p-type diffusion material and the diffusion fins 201B are formed of an n-type diffusion material. The layout of Figure 2E is the layout of the 2-input NOR gate. 2C shows a circuit diagram corresponding to the 2-input NOR configuration of FIG. 2E. In FIGS. 2B-2E, each of P1 and P2 indicates a respective p-type transistor (such as a PMOS transistor), and each of N1 and N2 indicates a respective n-type transistor (such as an NMOS transistor), A and B. Each identifies its own input node and Q identifies an output node. It should be understood that similar symbols of p-type transistors, n-type transistors, input nodes, and output nodes are also used in other figures herein.
基於前述，應瞭解的是，特定元件佈局的邏輯功能可藉由將擴散鰭部的材料類型互換而加以改變。因此，對於此處所述的各個元件佈局，應理解的是，可取決於分派至擴散鰭部的n型及p型材料代表多個邏輯功能。Based on the foregoing, it should be appreciated that the logic function of a particular component layout can be varied by swapping the material types of the diffusion fins. Thus, for the various component layouts described herein, it should be understood that a plurality of logic functions may be represented depending on the n-type and p-type materials assigned to the diffusion fins.
圖3至7及11至29顯示根據本發明若干實施例之圖2A佈局的變形。因此，在圖3至7及11至29之中所描繪的元件每一者，係取決於分派至類型1擴散鰭部及類型2擴散鰭部擴散鰭部的n型及p型材料而代表2輸入NAND閘或2輸入NOR閘。在圖2A至7及11至19中所顯示的元件佈局每一者具有以下特徵： l 一多輸入邏輯閘，所有其輸入電極實質上對齊， l 一局部擴散鰭部層電源， l 一全域較高階層內連線電源， l 一水平內連線，用以將閘極電極連接至垂直局部內連線，且用以藉由提供接觸窗配置更大的彈性而促進改善接觸層的可製造性。Figures 3 through 7 and 11 through 29 show variations of the layout of Figure 2A in accordance with several embodiments of the present invention. Thus, each of the elements depicted in Figures 3 through 7 and 11 through 29 represents 2 depending on the n-type and p-type materials assigned to the Type 1 diffuser fin and the Type 2 diffuser fin diffuser fin. Input NAND gate or 2-input NOR gate. The component layouts shown in Figures 2A through 7 and 11 through 19 each have the following characteristics: A multi-input logic gate, all of its input electrodes are substantially aligned, l a partially diffused fin layer power supply, l a global comparison High-level interconnecting power supply, l a horizontal interconnect to connect the gate electrode to the vertical local interconnect and to improve the manufacturability of the contact layer by providing greater flexibility in the contact window .
應瞭解的是，在圖2A至7及11至29的佈局每一者顯示相同邏輯功能的不同實施方式。圖2A的佈局顯示以下特徵： l 二個以上輸入用之閘極電極，該等閘極電極係實質上對齊， l 位於相同擴散類型的擴散鰭部之間的閘極電極的端線間隔， l 相同擴散類型的擴散鰭部之間的閘極電極接觸窗， l 用於局部電源之類型1及類型2擴散鰭部（亦即是至元件的局部內連線），其中met1係用於較高階層內連線（全域）電源，局部和全域電源二者係為相鄰元件所共用， l 類型1和類型2的擴散鰭部供應電流至一局部階層上的元件，且可以規定的間隔連接至較高階層的內連線，例如met1，以支援多重晶片功率對策， l 使用水平局部內連線，以連接至閘極電極， l 將垂直局部內連線層連接至閘極電極層的一實質上水平局部內連線，可用以平移閘極電極接觸窗的位置，藉此能夠增加在接觸窗遮罩圖案上的彈性，這可減輕可能的微影問題。It should be appreciated that the layouts of Figures 2A through 7 and 11 through 29 each show different implementations of the same logic function. The layout of Figure 2A shows the following features: • Two or more input gate electrodes, the gate electrodes are substantially aligned, l the end line spacing of the gate electrodes between the diffusion fins of the same diffusion type, l The gate electrode contact window between the diffusion fins of the same diffusion type, l is used for the type 1 and type 2 diffusion fins of the local power source (that is, the local interconnect to the component), wherein the met1 system is used for higher The intra-level connection (global) power supply, local and global power supply are shared by adjacent components, and the type 1 and type 2 diffusion fins supply current to a local level component and can be connected to the specified interval. Higher levels of interconnects, such as met1, to support multi-chip power countermeasures, l use horizontal local interconnects to connect to gate electrodes, and l connect vertical local interconnect layers to a substantial layer of gate electrodes The upper horizontal local interconnect can be used to translate the position of the gate electrode contact window, thereby increasing the flexibility on the contact window mask pattern, which mitigates possible lithography problems.
根據本發明若干實施例，圖2F顯示圖2A佈局的變形，其中閘極電極結構端部在元件的頂部（如橢圓250所指示）以及在元件的底部（如橢圓251所指示）實質上對齊。2F shows a variation of the layout of FIG. 2A in which the gate electrode structure ends are substantially aligned at the top of the element (as indicated by ellipse 250) and at the bottom of the element (as indicated by ellipse 251), in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖2G顯示圖2A佈局的變形，其中形成接觸窗，以在元件的頂部處（如圓260所指示）以及在元件的底部處（如圓261所指示），於電源軌（power rail）下方自met1內連線結構延伸至水平局部內連線結構。2G shows a variation of the layout of FIG. 2A in which a contact window is formed at the top of the component (as indicated by circle 260) and at the bottom of the component (as indicated by circle 261) at the power source, in accordance with several embodiments of the present invention. Below the rail (power rail) extends from the metro interconnect structure to the horizontal local interconnect structure.
如先前所提及，根據本發明若干實施例，圖2H顯示圖2A之元件的變形，其中使用兩個不同的擴散鰭部節距203和205。As mentioned previously, Figure 2H shows a variation of the elements of Figure 2A in which two different diffusion fin pitches 203 and 205 are used, in accordance with several embodiments of the present invention.
應理解的是，在此處所描繪的各種佈局中於元件頂部和底部處在電源軌下方的擴散鰭部和水平局部內連線結構，係在水平方向（x）上持續地延伸，以應用於多個元件，該等元件係配置在一列之中以及可能配置在相鄰的列之中。為了說明此點，根據本發明若干實施例，圖2I顯示圖2A佈局的變形，其中將在元件頂部和底部處電源軌下方的擴散鰭部和水平局部內連線結構，延伸met1內連線結構215A/215B的全寬度，met1內連線結構215A/215B係作為電源軌。應理解的是，在作為電源軌之215A/215B下方的擴散鰭部和水平局部內連線結構、以及作為電源軌之215A/215B本身，係在（x）方向持續延伸，如箭頭270所示。It should be understood that the diffusing fins and horizontal partial interconnect structures below the power rail at the top and bottom of the component in the various layouts depicted herein are continuously extended in the horizontal direction (x) for application. A plurality of components are arranged in a column and possibly in adjacent columns. To illustrate this, in accordance with several embodiments of the present invention, FIG. 2I shows a variation of the layout of FIG. 2A in which the diffusion fins and horizontal local interconnect structures below the power rails at the top and bottom of the component extend the met1 interconnect structure. The full width of the 215A/215B, the met1 interconnect structure 215A/215B is used as the power rail. It should be understood that the diffuser fins and horizontal partial interconnect structures below the power rails 215A/215B, and the 215A/215B itself as the power rails, continue to extend in the (x) direction, as indicated by arrow 270. .
圖3顯示根據本發明若干實施例之圖2A的佈局之變形，其中將met1電源軌連接至垂直局部內連線，俾使該met1電源軌作為局部電源。應理解的是，met1電源軌可基於元件庫需要而具可變寬度。如同圖2A的佈局，圖3的佈局使用輸入電極實質上對齊之多輸入邏輯閘。3 shows a variation of the layout of FIG. 2A in which a met1 power rail is connected to a vertical local interconnect, such that the met1 power rail is used as a local power source, in accordance with several embodiments of the present invention. It should be understood that the met1 power rail can have a variable width based on the needs of the component library. As with the layout of Figure 2A, the layout of Figure 3 uses a multi-input logic gate with the input electrodes substantially aligned.
圖4顯示根據本發明若干實施例之圖2A的佈局之變形，其中將二維變化的met1內連線結構在元件之內用於元件內繞線。如圖2A的佈局，圖4的佈局使用多輸入邏輯閘，其輸入電極實質上對齊且共用局部和全域電源。在若干實施例中，在met1中的彎曲，即在met1方向上的二維變化，係發生於一固定的格子（grid）。在若干實施例中，這個met1固定的格子可包含水平格線，該等水平格線係配置於該等擴散鰭部之間且平行於擴散鰭部延伸，並且以與擴散鰭部相同的節距加以配置。此外，在若干實施例中，此met1固定格子可包含垂直格線，其垂直於該等擴散鰭部延伸且配置成位於垂直局部內連線的中央。4 shows a variation of the layout of FIG. 2A in which a two-dimensionally varying met1 interconnect structure is used within an element for wire winding within an element, in accordance with several embodiments of the present invention. As with the layout of Figure 2A, the layout of Figure 4 uses a multi-input logic gate with input electrodes that are substantially aligned and share local and global power supplies. In several embodiments, the curvature in met1, i.e., the two-dimensional variation in the met1 direction, occurs in a fixed grid. In some embodiments, the met1 fixed grid may comprise horizontal grid lines disposed between the diffusion fins and extending parallel to the diffusion fins and at the same pitch as the diffusion fins Configure it. Moreover, in some embodiments, the met1 fixed grid can include vertical grid lines that extend perpendicular to the diffusion fins and are configured to be centered in the vertical local interconnects.
圖5顯示根據本發明若干實施例之圖2A的佈局之變形，其中將met1電源軌連接至垂直局部內連線，俾使該等met1電源軌作為局部電源，且其中將二維變化met1內連線結構於元件之內用於元件內繞線。如同圖2A的佈局，圖5的佈局使用輸入電極實質上對齊之多輸入邏輯閘。5 shows a variation of the layout of FIG. 2A in accordance with several embodiments of the present invention, wherein a met1 power rail is connected to a vertical local interconnect, such that the met1 power rail is used as a local power source, and wherein the two-dimensional change is followed by a met1 connection. The wire structure is used within the component for winding within the component. As with the layout of Figure 2A, the layout of Figure 5 uses a multi-input logic gate with the input electrodes substantially aligned.
圖6顯示根據本發明若干實施例之圖2A的佈局之變形，其中使用固定、最小寬度、共用的局部met1電源，以及在元件內用於元件內繞線之二維變化met1內連線結構。如圖2A的佈局，圖6的佈局使用輸入電極實質上對齊之多輸入邏輯閘。6 shows a variation of the layout of FIG. 2A in accordance with several embodiments of the present invention in which a fixed, minimum width, shared local met1 power supply, and a two-dimensional change met1 interconnect structure for in-component windings within the component are used. As with the layout of Figure 2A, the layout of Figure 6 uses a multi-input logic gate with the input electrodes substantially aligned.
圖7顯示根據本發明若干實施例之圖2A的佈局之變形，其具有於元件中具硬接線的共用的局部和全域電源，以及在元件內用於元件內繞線之二維變化met1內連線結構。如圖2A的佈局，圖7的佈局使用輸入電極實質上對齊之多輸入邏輯閘。Figure 7 shows a variation of the layout of Figure 2A in accordance with several embodiments of the present invention having a common local and global power supply with hardwired components in the component, and a two-dimensional variation in the component for the two-dimensional variation in the component. Line structure. As with the layout of Figure 2A, the layout of Figure 7 uses a multi-input logic gate with the input electrodes substantially aligned.
根據本發明若干實施例，圖8A顯示例示標準元件的佈局，其中將輸入接腳配置於相同類型的擴散鰭部之間以減輕繞線擁塞，且其中使用若干擴散鰭部作為內連線導體。圖8C顯示圖8A佈局的電路圖，包含輸入接腳8a、8b、8c、及8d。平面標準元件，即非鰭式場效電晶體的元件，通常具有位於相反類型（即n型相對p型）的擴散特徵部之間、或位於擴散特徵部和相鄰電源軌之間的輸入接腳，藉此在平面元件的局部區域中達到輸入接腳較高的密集度。如圖8A所顯示，藉由利用擴散鰭部以及將若干輸入接腳配置於相同擴散類型的擴散鰭部之間，該等輸入接腳可在一較大區域之上以更均勻的方式分隔開，從而減輕元件的繞線擁塞。此外，如圖8A所顯示，藉由選擇性地移除若干閘極電極結構，如區域8001中所顯示，可將擴散鰭部層運用作為實質水平繞線層，以連接至非相鄰的電晶體或局部內連線。舉例來說，在區域8001中，擴散鰭部8003係用以作為水平繞線導體。8A shows a layout of a standard component in which input pins are disposed between diffusion fins of the same type to mitigate winding congestion, and in which a plurality of diffusion fins are used as interconnect conductors, in accordance with several embodiments of the present invention. Figure 8C shows a circuit diagram of the layout of Figure 8A, including input pins 8a, 8b, 8c, and 8d. Planar standard components, ie, elements of non-fin field effect transistors, typically have input pins between diffusion features of opposite types (ie, n-type versus p-type) or between diffusion features and adjacent power rails Thereby, a higher density of the input pins is achieved in a partial area of the planar element. As shown in FIG. 8A, the input pins can be separated in a more uniform manner over a larger area by utilizing the diffusion fins and arranging the plurality of input pins between the diffusion fins of the same diffusion type. On, thereby reducing the winding congestion of the components. Furthermore, as shown in FIG. 8A, by selectively removing a plurality of gate electrode structures, as shown in region 8001, the diffused fin layer can be utilized as a substantially horizontal winding layer to connect to non-adjacent electricity. Crystal or local interconnects. For example, in region 8001, diffusion fins 8003 are used as horizontal winding conductors.
根據本發明若干實施例，圖8B顯示圖8A的變化，其中使用二個不同的閘極電極節距p1及p2。更具體而言，在圖8B中每隔一對相鄰配置閘極電極結構依據較小的節距p2加以配置。在若干實施例中，較大的閘極電極節距p1係約80奈米（nm）且較小的閘極電極節距p2係約60 nm。應理解的是，若干實施例可利用超過二個閘極電極結構節距於一特定元件或區塊之內。並且，若干實施例可利用單一閘極電極結構節距於特定元件或區塊之內。此外，應理解的是，任何半導體裝置的層或其部分，可以類似於此處所述關於閘極電極節距的方式加以形成。例如，半導體裝置的局部內連線層或更高階層的內連線層或其部分，可包含以類似於此處所述關於閘極電極節距的方式以一個以上對應節距形成的內連線傳導結構。8B shows a variation of FIG. 8A in which two different gate electrode pitches p1 and p2 are used, in accordance with several embodiments of the present invention. More specifically, every other pair of adjacently arranged gate electrode structures in FIG. 8B is configured in accordance with a smaller pitch p2. In several embodiments, the larger gate electrode pitch p1 is about 80 nanometers (nm) and the smaller gate electrode pitch p2 is about 60 nm. It should be understood that several embodiments may utilize more than two gate electrode structures within a particular component or block. Also, several embodiments may utilize a single gate electrode structure to be within a particular component or block. Moreover, it should be understood that any layer or portion of a semiconductor device can be formed in a manner similar to that described herein with respect to the pitch of the gate electrode. For example, a local interconnect layer of a semiconductor device or a higher level interconnect layer or portion thereof, may include interconnects formed with more than one corresponding pitch in a manner similar to the gate electrode pitch described herein. Wire conduction structure.
此外，在半導體裝置的不同層（亦稱階層）中的傳導結構或其部分，可依各自的節距排列而加以配置，其中在不同層的傳導結構節距排列之間存在一確定的關係。舉例來說，在若干實施例中，在擴散鰭部層中的擴散鰭部，係根據可包含一個以上擴散鰭部節距的一擴散鰭部節距排列而加以配置，且在met1層的金屬層1（met1）內連線結構係根據可包含一個以上met1節距的一met1節距排列加以配置，其中一個以上擴散鰭部節距係以有理數（x/y）而關聯於一個以上met1節距，其中x和y係整數。在若干實施例中，擴散鰭部節距和met1節距之間的關係由在（1/4）至（4/1）範圍之內的有理數加以定義。Furthermore, the conductive structures or portions thereof in different layers (also referred to as layers) of the semiconductor device may be arranged according to their respective pitches, wherein there is a certain relationship between the pitch arrangement of the conductive structures of the different layers. For example, in some embodiments, the diffusing fins in the diffused fin layer are configured according to a diffusion fin pitch arrangement that may include more than one diffusing fin pitch, and the metal in the met1 layer The layer 1 (met1) interconnect structure is configured according to a met1 pitch arrangement that may include more than one met1 pitch, where more than one diffused fin pitch is associated with more than one met1 section by a rational number (x/y) Distance, where x and y are integers. In several embodiments, the relationship between the diffusion fin pitch and the met1 pitch is defined by a rational number within the range of (1/4) to (4/1).
此外，在若干實施例中，垂直局部內連線結構（liv）可依據實質上與閘極電極節距相等之垂直局部內連線節距而加以配置。在若干實施例中，閘極電極節距係小於100奈米。此外，以類似於上述關於擴散鰭部節距對於met1節距的關係之方式，在若干實施例中擴散鰭部節距排列可藉由有理數（x/y）而關聯於水平局部內連線節距排列，其中x和y係整數。亦即是，一個以上擴散鰭部節距可藉由有理數（x/y）而關聯於一個以上水平局部內連線節距。Moreover, in some embodiments, the vertical local interconnect structure (liv) can be configured in accordance with a vertical local interconnect pitch that is substantially equal to the gate electrode pitch. In several embodiments, the gate electrode pitch is less than 100 nanometers. Moreover, in a manner similar to that described above with respect to the relationship of the diffusion fin pitch to the met1 pitch, in some embodiments the diffusion fin pitch arrangement may be associated with horizontal local interconnects by a rational number (x/y). Alignment, where x and y are integers. That is, more than one diffusing fin pitch can be associated with more than one horizontal local interconnect pitch by a rational number (x/y).
根據本發明若干實施例，圖9A顯示例示標準元件的佈局，其中將擴散鰭部使用作為內連線導體。圖9C顯示圖9A佈局的電路圖。圖9A的例示標準元件佈局包含在一單一軌道（track）中，例如在閘極電極軌道9001之中，包含多個閘極電極線端。圖9B顯示圖9A的佈局，其中標示三組交叉連接的電晶體。第一組交叉連接的電晶體係由對線cc1a及cc1b加以標示。第二組交叉連接電晶體係由對線cc2a及cc2b加以標示。第三組交叉連接電晶體係由對線cc3a及cc3b加以標示。In accordance with several embodiments of the present invention, FIG. 9A shows a layout illustrating a standard component in which a diffusing fin is used as an interconnect conductor. Figure 9C shows a circuit diagram of the layout of Figure 9A. The exemplary standard component layout of Figure 9A is contained in a single track, such as in gate electrode track 9001, comprising a plurality of gate electrode line ends. Figure 9B shows the layout of Figure 9A in which three sets of cross-connected transistors are labeled. The first set of cross-connected electro-crystalline systems are indicated by pairs of lines cc1a and cc1b. The second set of cross-connected electro-crystalline systems is indicated by pairs of lines cc2a and cc2b. The third set of cross-connected electro-crystalline systems is indicated by pairs of lines cc3a and cc3b.
根據本發明若干實施例，圖10顯示例示標準元件佈局，其中將閘極電極接觸窗實質上配置於擴散鰭部上方，而非擴散鰭部之間。圖10的例示標準元件佈局亦顯示可變寬度met1局部電源結構。在圖10的例示標準元件佈局中，接觸層係在擴散鰭部上方垂直對齊，而非於擴散鰭部之間。這個方法可在沒有虛設擴散鰭部（dummy diffusion fin）的狀況下能夠共用擴散鰭部結構之間的毗鄰邊緣，這提供更有效率的佈局。應理解的是，虛設擴散鰭部係不形成電晶體的擴散鰭部。此外，應瞭解的是，這個將接觸層垂直對齊於擴散鰭部上方的方法，可改變met1內連線結構和擴散鰭部之間的垂直對齊關係。In accordance with several embodiments of the present invention, FIG. 10 shows an exemplary standard component layout in which a gate electrode contact window is disposed substantially above a diffusion fin rather than between diffusion fins. The exemplary standard component layout of Figure 10 also shows a variable width met1 local power supply architecture. In the exemplary standard component layout of Figure 10, the contact layers are vertically aligned above the diffusion fins rather than between the diffusion fins. This method can share adjacent edges between the diffused fin structures without the dummy diffusion fins, which provides a more efficient layout. It should be understood that the dummy diffusion fins do not form a diffusion fin of the transistor. In addition, it should be understood that this method of vertically aligning the contact layer above the diffusion fins can change the vertical alignment between the met1 interconnect structure and the diffusion fins.
根據本發明若干實施例，圖11顯示實現擴散鰭部的例示元件佈局。在圖11的例示佈局中，閘極電極層包含以下特徵： l 實質上線形閘極電極結構， l 在閘極電極層上的三個以上線形閘極電極結構，其中二者係虛設結構（dummy），即不形成電晶體的閘極電極之閘極電極階層結構， l 在閘極電極層上的三個以上閘極電極結構，其具有相同的垂直尺寸（長度），亦即在垂直於擴散鰭部縱向方向（x方向）的y方向上具相同的長度， l 在閘極電極層上的閘極電極結構，其以實質上相等的縱向中心線至縱向中心線節距實質上均勻地分隔開， l 虛設閘極電極結構，其係與在左方及/或右方的相鄰元件共用，及 l 虛設閘極電極結構，其於met1電源軌下方切割（cut）。Figure 11 shows an exemplary component layout for implementing a diffusion fin, in accordance with several embodiments of the present invention. In the illustrated layout of Figure 11, the gate electrode layer comprises the following features: • a substantially linear gate electrode structure, l three or more linear gate electrode structures on the gate electrode layer, wherein the two are dummy structures (dummy ), that is, the gate electrode structure of the gate electrode that does not form the transistor, l three or more gate electrode structures on the gate electrode layer, which have the same vertical dimension (length), that is, perpendicular to the diffusion The fins have the same length in the y direction in the longitudinal direction (x direction), and the gate electrode structure on the gate electrode layer is substantially evenly divided by a substantially equal longitudinal centerline to a longitudinal centerline pitch. Separate, l a dummy gate electrode structure that is shared with adjacent elements on the left and/or right side, and a dummy gate electrode structure that is cut under the met1 power rail.
在圖11的例示佈局中，擴散鰭部包含以下特徵： l 依據實質上相等節距實質上均勻分隔開的擴散鰭部，擴散鰭部可在一格子上，在若干實施例中擴散鰭部節距小於90 nm， l p型及n型每一者之一個以上擴散鰭部，圖11顯示二個n型的擴散鰭部及二個p型的擴散鰭部，但其他實施例可包含任何數量的任一型之擴散鰭部， l 相同數量之p型和n型擴散鰭部，其他實施例可具有p型相對n型不同數量的擴散鰭部， l 在電源軌下方刪除一個以上擴散鰭部 l 在p型和n型段之間刪除一個以上擴散鰭部，及 l 實質上相等寬度和長度的各擴散鰭部。In the illustrated layout of FIG. 11, the diffuser fins include the following features: • The diffuser fins may be on a grid, in some embodiments, in a plurality of diffused fins, substantially uniformly spaced apart by substantially equal pitches. Pitches less than 90 nm, l p-type and n-type each of more than one diffuser fin, Figure 11 shows two n-type diffuser fins and two p-type diffuser fins, but other embodiments may include any The number of diffusing fins of any type, l the same number of p-type and n-type diffusing fins, other embodiments may have a different number of p-type and n-type diffusing fins, l remove more than one diffusing fin below the power rail Portion 1 removes more than one diffusing fin between the p-type and n-type segments, and l respective diffusing fins of substantially equal width and length.
在圖11的例示佈局中，局部內連線包含以下特徵： l 閘極電極和擴散鰭部源極/汲極接線係在不同的導體層上，且這些不同的導體層係互相隔離， l 用於源極汲極接線之平行於閘極的實質上線形導體層；在若干實施例中，係與閘極層有相同節距；且在若干實施例中，這些線形導體層可偏移半個閘極節距。 l 局部內連線與擴散鰭部正重疊（positive overlap）。In the illustrated layout of FIG. 11, the local interconnect includes the following features: • The gate electrode and the diffusion fin source/drain connection are on different conductor layers, and the different conductor layers are isolated from each other, a substantially linear conductor layer parallel to the gate of the source drain connection; in some embodiments, having the same pitch as the gate layer; and in several embodiments, the linear conductor layers may be offset by half Gate pitch. l The local interconnect is positively overlapped with the diffuser fin.
在圖11的例示佈局中，較高階層met1內連線層包含以下特徵： l 介於p型和n型擴散鰭部之間的閘極導體接觸窗， l 在二個方向上皆分格化（gridded）的接觸窗， l 接觸窗將局部內連線和閘極導體連接至上方金屬層， l 實質上線形的金屬層；金屬層係依一節距；金屬層依據與擴散鰭部節距相同的節距且具有垂直方向上半節距的偏移， l 在相同層上的輸入節點和輸出節點接腳， l 在頂部和底部邊緣上寬的電源軌，其每一者係被共用；電源軌係藉由毗鄰部（abutment）連接至左方和右方， l 在最高金屬階層上的輸出和輸入節點；配置於p型和n型擴散鰭部之間的接觸窗，及 l 在頂部和底部與毗鄰元件共用的至局部內連線的電源軌接觸窗。In the illustrated layout of Figure 11, the higher level met1 interconnect layer includes the following features: • Gate conductor contact window between the p-type and n-type diffuser fins, l is divided in both directions (gridded) contact window, l the contact window connects the local interconnect and the gate conductor to the upper metal layer, l the substantially linear metal layer; the metal layer is at a pitch; the metal layer is the same as the diffusion fin pitch The pitch and the offset in the vertical half pitch, l the input node and the output node pin on the same layer, l the wide power rails on the top and bottom edges, each of which is shared; The rail system is connected to the left and right by abutment, the output and input nodes on the highest metal level, the contact window between the p-type and n-type diffusion fins, and l at the top and A power rail contact window to the local interconnect that is shared by the bottom and adjacent components.
根據本發明若干實施例，圖12A/B顯示具有最小寬度met1電源軌的圖11佈局的變形。圖12B顯示與圖12A相同的佈局，其中為了清楚緣故佈局係以合併型式描繪。圖12A/Ｂ的例示佈局亦具有相同寬度、相同節距的所有met1，其包含電源軌。此外，在圖12/B的佈局中，met1係配置於與擴散鰭部節距相同的（y）方向位置。In accordance with several embodiments of the present invention, FIG. 12A/B shows a variation of the layout of FIG. 11 with a minimum width met1 power rail. Figure 12B shows the same layout as Figure 12A, with the layout being depicted in a merged format for clarity. The exemplary layout of Figures 12A/B also has all of the met1 of the same width, the same pitch, including the power rails. Further, in the layout of FIG. 12/B, the met1 system is disposed at the same (y) direction position as the diffusion fin pitch.
根據本發明若干實施例，圖13A/B顯示圖12A/B佈局的變形，其不具有自各個局部內連線和閘極電極結構至met1的接觸窗。圖13B顯示與圖13A相同的佈局，為了清楚緣故佈局係以合併型式描繪。在這個實施例中，met1係形成為與局部內連線結構和閘極電極結構直接連接。此外，在其他實施例中，局部內連線結構或閘極電極結構其中任一者，或局部內連線結構和閘極電極結構二者，可直接連接至met1。In accordance with several embodiments of the present invention, FIGS. 13A/B show a variation of the layout of FIG. 12A/B that does not have contact windows from respective local interconnect and gate electrode structures to met1. Figure 13B shows the same layout as Figure 13A, which is depicted in a merged format for clarity. In this embodiment, the met1 system is formed to be directly connected to the local interconnect structure and the gate electrode structure. Moreover, in other embodiments, either of the local interconnect structure or the gate electrode structure, or both the local interconnect structure and the gate electrode structure, may be directly connected to met1.
根據本發明若干實施例，圖14A/B顯示圖11佈局的變形，其具有最小寬度met1電源軌，且所有met1結構，包含電源軌，具相同的寬度和相同的節距。圖14Ｂ顯示與圖14A相同的佈局，為了清楚緣故佈局係以合併型式描繪。In accordance with several embodiments of the present invention, FIGS. 14A/B show a variation of the layout of FIG. 11 with a minimum width met1 power rail, and all of the met1 structures, including power rails, having the same width and the same pitch. Figure 14B shows the same layout as Figure 14A, which is depicted in a merged format for clarity.
根據本發明若干實施例，圖15A/B顯示圖14A/B佈局的變形，其具有met1繞線結構，該繞線結構配置成各（y）位置具有一met1結構。圖15Ｂ顯示與圖15A相同的佈局，為了清楚緣故佈局係以合併型式描繪。15A/B shows a variation of the layout of FIG. 14A/B having a met1 winding structure configured such that each (y) position has a met1 structure, in accordance with several embodiments of the present invention. Figure 15B shows the same layout as Figure 15A, with the layout being depicted in a merged format for clarity.
根據本發明若干實施例，圖16A/B顯示圖11佈局的變形，其具有配置於p型擴散鰭部之間的閘極電極結構接觸窗。圖16Ｂ顯示與圖16A相同的佈局，為了清楚緣故佈局係以合併型式描繪。圖16A/B的例示佈局亦顯示配置於met1電源軌下方且連接至VSS/VDD的擴散鰭部。此外，擴散鰭部VDD/VSS結構係與上方及/或下方元件所共用。為了易於描述，在圖16A/B的佈局中不顯示接觸層。16A/B shows a variation of the layout of FIG. 11 having a gate electrode structure contact window disposed between p-type diffusion fins, in accordance with several embodiments of the present invention. Figure 16B shows the same layout as Figure 16A, which is depicted in a merged format for clarity. The exemplary layout of Figures 16A/B also shows diffused fins disposed below the met1 power rail and connected to VSS/VDD. In addition, the diffusion fin VDD/VSS structure is shared with the upper and/or lower components. For ease of description, the contact layer is not shown in the layout of FIG. 16A/B.
根據本發明若干實施例，圖17A/B顯示實現擴散鰭部的例示元件佈局。圖17Ｂ顯示與圖17A相同的佈局，為了清楚緣故佈局係以合併型式描繪。在圖17A/B的例示佈局中，閘極電極層包含以下特徵： l 實質上線形的閘極電極結構， l 在閘極電極層上的三個以上線形結構，其中至少二者係虛設結構（dummy）， l 在閘極電極層上的虛設結構係為相同垂直尺寸（長度），即在垂直於擴散鰭部的縱向方向（x方向）之y方向上具相同的長度， l 在x方向上實質上均勻地分隔開及/或相等節距化的閘極電極層上的結構， l 虛設結構係與左方及/或右方相鄰元件共用， l 虛設結構以及閘極電極結構繪製為一單一線，且接著在電源軌下方以及所需之處加以切割；閘極電極結構切割係繪製於不同的層；在圖17A/B中顯示具經切割的最終結果的閘極電極層， l 三段以上的閘極電極，控制二個以上之p型和n型電晶體， l 在相同x位置之多個閘極電極結構，其每一者連接至一不同的連線；且連接至二個不同的輸入連線。In accordance with several embodiments of the present invention, Figures 17A/B show an exemplary component layout that implements a diffusion fin. Figure 17B shows the same layout as Figure 17A, which is depicted in a merged format for clarity. In the illustrated layout of Figures 17A/B, the gate electrode layer comprises the following features: • a substantially linear gate electrode structure, l three or more linear structures on the gate electrode layer, at least two of which are dummy structures ( Dummy), l The dummy structures on the gate electrode layer are of the same vertical dimension (length), ie have the same length in the y direction perpendicular to the longitudinal direction (x direction) of the diffusion fin, l in the x direction a structure that is substantially evenly spaced and/or equally pitched on the gate electrode layer, l the dummy structure is shared with the left and/or right adjacent elements, l the dummy structure and the gate electrode structure are drawn as a single Line, and then cut under the power rail and where needed; the gate electrode structure is drawn in different layers; the gate electrode layer with the final result of the cut is shown in Figure 17A/B, three segments The above gate electrode controls more than two p-type and n-type transistors, l multiple gate electrode structures at the same x position, each of which is connected to a different connection; and connected to two different Input .
在圖17A/B的例示佈局中，擴散鰭部包含以下特徵： l 依據實質上相等的節距而實質上均勻分隔的擴散鰭部，擴散鰭部可在一格子上，擴散鰭部節距在若干實施例中小於90 nm， l p型和n型每一者的一個以上擴散鰭部， l 相同數量的p型和n型擴散鰭部， l 電源軌下方共用的擴散鰭部， l 在p型和n型段之間可將擴散鰭部刪除或不刪除；圖17A/B顯示所有鰭部皆存在， l 擴散鰭部每一者係具有實質上相等寬度和長度，其中擴散鰭部寬度係在y方向上測得，而擴散鰭部長度係在x方向上測得， l 擴散鰭部係繪製為連續的線；個別的切割遮罩係被繪製以將擴散鰭部分割成數段；圖17A/B顯示分割後的擴散鰭部段；應理解的是，在若干實施例中，擴散鰭部線端可利用切割遮罩形成或繪製於擴散鰭部階層佈局。In the illustrated arrangement of Figures 17A/B, the diffusing fins include the following features: • Diffusion fins that are substantially evenly spaced according to substantially equal pitches, the diffusing fins can be on a grid, and the diffusion fin pitch is at In some embodiments less than 90 nm, l p-type and n-type each of more than one diffuser fin, l the same number of p-type and n-type diffuser fins, l shared diffuser fins below the power rail, l in p The diffusing fins may or may not be removed between the type and the n-type segments; Figure 17A/B shows that all fins are present, l the diffusing fins each have substantially equal width and length, wherein the diffuser fin width is Measured in the y direction, and the length of the diffusing fin is measured in the x direction, l the diffusing fins are drawn as continuous lines; individual cutting masks are drawn to divide the diffusing fin into segments; Figure 17A /B displays the split diffuser fin segments; it should be understood that in several embodiments, the diffuser fin line ends may be formed or drawn in a diffused fin hierarchy using a cut mask.
在圖17A/B的例示佈局中，局部內連線包含以下特徵： l 閘極電極和擴散鰭部源極/汲極接線係在不同的導體層上；這些不同的導體層在製造期間可加以合併； l 源極汲極接線用之平行於閘極的實質上線形導體層；在若干實施例中，係依與閘極層相同的節距；並且在若干實施例中，這些線形導體層可偏移半閘極節距。 l 局部內連線與擴散鰭部的正、零、或負重疊， l 將局部內連線直接連接至擴散鰭部源極/汲極和閘極電極結構， l 電源軌下方共用的局部內連線；電源軌下方的局部內連線在若干實施例中可刪除。In the illustrated layout of Figure 17A/B, the local interconnects include the following features: • The gate electrode and the diffuser fin source/drain wiring are on different conductor layers; these different conductor layers can be fabricated during manufacturing Combining; a substantially linear conductor layer parallel to the gate for source drain wiring; in some embodiments, the same pitch as the gate layer; and in several embodiments, the linear conductor layers may Offset half gate pitch. l The positive, zero, or negative overlap of the local interconnect and the diffused fin, l connect the local interconnect directly to the diffused fin source/drain and gate electrode structure, l share the local interconnect below the power rail Line; the local interconnect below the power rail can be removed in several embodiments.
在圖17A/B的例示佈局中，較高階層met1內連線層包含以下特徵： l 擴散鰭部之間的閘極電極結構接觸窗， l 接觸窗係在x和y方向其中之一或二者上分格化（gridded）， l 接觸窗將局部內連線和閘極導體連接至上方金屬層， l 金屬層位置可在x和y方向其中之一或二者上固定， l 在相同層之上的輸出節點和輸入節點接腳， l 在頂部和底部的寬電源軌係被共用的；電源軌藉由毗鄰部連接至左方和右方；至局部內連線的電源軌接觸窗係共用的， l 金屬層可具有彎曲部分。在若干實施例中，在金屬層內連線之中的彎曲部分可位在相鄰擴散鰭部之間的中心。此外，在若干實施例中，在y方向上延伸的金屬層內連線的垂直段可對齊於垂直局部內連線，以在y方向上沿著垂直局部內連線且在垂直局部內連線之上而延伸。In the illustrated layout of Figure 17A/B, the higher level met1 interconnect layer includes the following features: • Gate electrode structure contact window between the diffused fins, l Contact window in one or both of the x and y directions The gridded, l contact window connects the local interconnect and the gate conductor to the upper metal layer, l the metal layer position can be fixed in one or both of the x and y directions, l in the same layer Above the output node and the input node pin, l the wide power rails at the top and bottom are shared; the power rail is connected to the left and right by the adjacent portion; the power rail contact window to the local interconnect The shared, l metal layer can have a curved portion. In several embodiments, the curved portion of the wires within the metal layer can be centered between adjacent diffusing fins. Moreover, in several embodiments, the vertical segments of the interconnects of the metal layers extending in the y-direction may be aligned with the vertical local interconnects to connect along the vertical local interconnects in the y-direction and within the vertical local interconnects. Extend above.
根據本發明若干實施例，圖18A/B顯示圖17A/B佈局的變形，其中接觸窗連接至水平局部內連線，且其中水平局部內連線直接連接至垂直局部內連線。圖18B顯示與圖18A相同的佈局，為了清楚緣故將佈局以合併型式描繪。在圖18A/B的佈局中，未顯示在擴散鰭部、閘極電極、及局部內連線層上的切割。18A/B shows a variation of the layout of FIG. 17A/B, wherein the contact window is connected to a horizontal partial interconnect, and wherein the horizontal partial interconnect is directly connected to the vertical partial interconnect. Figure 18B shows the same layout as Figure 18A, with the layout depicted in a merged format for clarity. In the layout of Fig. 18A/B, the dicing on the diffusion fins, the gate electrodes, and the local interconnect layer is not shown.
根據本發明若干實施例，圖19A/B顯示圖17A/B佈局的變形，其中至局部內連線的電源軌接觸窗係不共用的，且其中在電源軌下方沒有共用的局部內連線。圖19B顯示與圖19A相同的佈局，為了清楚緣故將佈局以合併型式描繪。19A/B shows a variation of the layout of FIG. 17A/B in which the power rail contact window to the local interconnect is not shared, and wherein there is no common local interconnect below the power rail. Figure 19B shows the same layout as Figure 19A, with the layout depicted in a merged format for clarity.
根據本發明若干實施例，圖20A/B顯示圖19A/Ｂ佈局的變形，其中擴散鰭部係相對於元件邊界偏移半個擴散鰭部節距。圖20B顯示與圖20A相同的佈局，為了清楚緣故將佈局以合併型式描繪。圖20A/B的佈局亦包含與met1位置相同之擴散鰭部位置。此外，擴散鰭部在元件的頂部和底部係不共用。圖20A/B亦顯示配置於閘極電極和擴散鰭部之上的接觸窗。圖20A/B也顯示不同的擴散鰭部/局部內連線的重疊。應理解的是，在圖20A/B的特定佈局中，雖然顯示水平局部內連線lih和垂直局部內連線liv在區域2001中彼此重疊，水平局部內連線lih和垂直局部內連線liv在區域2001係不相互接觸。這也在以下的圖21A/B之中的區域2001中成立。然而，亦應理解的是，在若干其他佈局中，可使水平局部內連線lih和垂直局部內連線liv在其彼此交叉的位置處互相接觸。20A/B shows a variation of the layout of FIG. 19A/B in which the diffusing fins are offset by a half of the diffusing fin pitch relative to the element boundary, in accordance with several embodiments of the present invention. Figure 20B shows the same layout as Figure 20A, with the layout depicted in a merged format for clarity. The layout of Figures 20A/B also includes the same diffuse fin position as the met1 position. In addition, the diffusing fins are not shared at the top and bottom of the component. 20A/B also shows a contact window disposed over the gate electrode and the diffusion fin. Figures 20A/B also show the overlap of different diffuser fins/local interconnects. It should be understood that in the particular layout of FIG. 20A/B, although the horizontal local interconnect line lih and the vertical local interconnect line liv are displayed overlapping each other in the area 2001, the horizontal local interconnect line lih and the vertical local interconnect line liv In the area 2001, they are not in contact with each other. This is also established in the area 2001 in FIG. 21A/B below. However, it should also be understood that in several other arrangements, the horizontal partial interconnect line lih and the vertical partial interconnect line liv may be brought into contact with each other at positions where they cross each other.
根據本發明若干實施例，圖21A/B顯示圖20A/B佈局的變形，其具有最小寬度電源軌及擴散鰭部之負垂直局部內連線重疊。圖21B顯示與圖21A相同的佈局，為了清楚緣故將佈局以合併型式描繪。21A/B shows a variation of the layout of FIG. 20A/B with a negative width local interconnect and a negative vertical local interconnect overlap of the diffuser fins, in accordance with several embodiments of the present invention. Figure 21B shows the same layout as Figure 21A, with the layout depicted in a merged format for clarity.
根據本發明若干實施例，圖22A/B顯示圖17A/B佈局的變形，其具有最小寬度電源軌、在電源軌下方不共用的局部內連線及擴散鰭部、及p鰭部和n鰭部之間較大的間距。圖22B顯示與圖22A相同的佈局，為了清楚緣故將佈局以合併型式描繪。22A/B shows a variation of the layout of FIG. 17A/B with a minimum width power rail, local interconnects and diffuser fins that are not shared under the power rail, and p-fin and n-fins, in accordance with several embodiments of the present invention. Large spacing between the sections. Figure 22B shows the same layout as Figure 22A, with the layout depicted in a merged format for clarity.
根據本發明若干實施例，圖23A/B顯示圖17A/B佈局的變形。圖23B顯示與圖23A相同的佈局，為了清楚緣故將佈局以合併型式描繪。圖23A/B的佈局具有以下特徵： l 單方向的金屬層內連線結構，即線形金屬層內連線結構， l 在電源軌下方無共用的局部內連線或鰭部， l 在最高金屬層上的一個輸入接腳，以及在下方金屬層的另一輸入接腳和輸出接腳， l 閘極電極接觸窗係與局部內連線分隔。23A/B shows a variation of the layout of Fig. 17A/B, in accordance with several embodiments of the present invention. Figure 23B shows the same layout as Figure 23A, with the layout depicted in a merged format for clarity. The layout of Fig. 23A/B has the following features: l Unidirectional metal layer interconnect structure, that is, linear metal layer interconnect structure, l no common local interconnect or fin under the power rail, l at the highest metal One input pin on the layer, and the other input pin and output pin on the lower metal layer, l the gate electrode contact window is separated from the local interconnect.
此外，圖23A/B顯示在加以切割於左方和右方邊緣之前的擴散鰭部。In addition, Figures 23A/B show the diffusion fins before being cut to the left and right edges.
根據本發明若干實施例，圖24A/B顯示圖23A/B佈局的變形。圖24B顯示與圖24A相同的佈局，為了清楚緣故將佈局以合併型式描繪。圖24A/B的佈局具有以下特徵： l 擴散鰭部節距小於金屬層節距；擴散鰭部節距係金屬層節距的一半， l 顯示於擴散鰭部之間的閘極電極和局部內連線切割；一替代的實行方式可具有在擴散鰭部切割上方的切割；這將降低在一個以上電晶體中擴散鰭部的數量， l 在最高金屬層上的一個輸入接腳，在下方金屬層上的另一輸入接腳和輸出接腳， l 大於最低限度之p型和n型擴散鰭部之間的間距；在p型和n型擴散鰭部段之間刪除一個以上擴散鰭部， l 配置於擴散鰭部之上的閘極電極接觸窗， l 配置於擴散鰭部之上的局部內連線接觸窗，及 l 在元件之內垂直met2具有在x方向不同的偏移。24A/B shows a variation of the layout of Fig. 23A/B, in accordance with several embodiments of the present invention. Figure 24B shows the same layout as Figure 24A, with the layout depicted in a merged format for clarity. The layout of Figure 24A/B has the following features: • The diffusion fin pitch is less than the metal layer pitch; the diffusion fin pitch is half the pitch of the metal layer, l is shown in the gate electrode and the local portion between the diffusion fins Wire cutting; an alternative implementation may have a cut above the diffusion fin cut; this will reduce the number of diffused fins in more than one transistor, l an input pin on the highest metal layer, and a metal below Another input pin and output pin on the layer, l greater than the minimum spacing between the p-type and n-type diffuser fins; removing more than one diffuser fin between the p-type and n-type diffuser fins, l The gate electrode contact window disposed above the diffuser fin, l the local interconnect contact window disposed above the diffuser fin, and the vertical met2 within the component has a different offset in the x direction.
根據本發明若干實施例，圖25A/B顯示圖23A/B佈局的變形，其中元件在高度上加倍。圖25B顯示與圖25A相同的佈局，為了清楚緣故將佈局以合併型式描繪。圖25A/B的佈局包含二倍於在圖23A/B佈局中總數量的擴散鰭部。在圖25A/B的佈局中顯示擴散鰭部切割。25A/B shows a variation of the layout of Fig. 23A/B in which the elements are doubled in height, in accordance with several embodiments of the present invention. Figure 25B shows the same layout as Figure 25A, with the layout depicted in a merged format for clarity. The layout of Figures 25A/B includes twice the total number of diffused fins in the layout of Figure 23A/B. A diffused fin cut is shown in the layout of Figure 25A/B.
根據本發明若干實施例，圖26A/B顯示實現擴散鰭部的例示元件佈局。圖26B顯示與圖26A相同的佈局，為了清楚緣故將佈局以合併型式描繪。在圖26A/B的例示佈局中，閘極電極層包含以下特徵： l 實質上線形閘極電極結構， l 在閘極電極層上的三個以上線形結構，其中至少二者係虛設結構， l 在閘極電極層上的虛設結構係具有相同尺寸， l 在閘極電極層上的結構係在x方向上實質均勻分隔開及/或相等節距化， l 虛設結構係與在左方及/或右方的相鄰元件共用， l 在電源軌下方切割虛設結構， l 控制二個以上p型和n型電晶體的單一閘極電極結構，在製造過程中之後被分開而形成二個以上不同的閘極電極，例如閘極電極結構2601及2603所描繪， l 在相同x位置的閘極電極係連接至兩個以上不同連線，連接至兩個以上不同的輸入連線，例如由連接至輸入連線2605的閘極電極結構2601、及由連接至輸入連線2607之閘極電極結構2603所描繪者， l 在相同x位置的二個以上虛設段。In accordance with several embodiments of the present invention, Figures 26A/B show an exemplary component layout that implements a diffusion fin. Figure 26B shows the same layout as Figure 26A, with the layout depicted in a merged format for clarity. In the illustrated layout of Figures 26A/B, the gate electrode layer comprises the following features: • a substantially linear gate electrode structure, l three or more linear structures on the gate electrode layer, at least two of which are dummy structures, l The dummy structures on the gate electrode layer have the same size, l the structures on the gate electrode layer are substantially evenly spaced and/or equally pitched in the x direction, l the dummy structure is on the left and / or adjacent components on the right side, l cutting the dummy structure under the power rail, l controlling the single gate electrode structure of two or more p-type and n-type transistors, which are separated after the manufacturing process to form more than two Different gate electrodes, such as gate electrode structures 2601 and 2603, are depicted, where the gate electrode at the same x position is connected to more than two different wires, connected to more than two different input wires, such as by a connection The gate electrode structure 2601 to the input wiring 2605 and the gate electrode structure 2603 connected to the input wiring 2607 are two or more dummy segments at the same x position.
在圖26A/B的例示佈局中，擴散鰭部包含以下特徵： l 依據實質上相等節距實質上均勻分隔開的擴散鰭部，擴散鰭部可在一格子上，擴散鰭部節距在若干實施例中小於90 nm， l p型和n型每一者的一個以上擴散鰭部， l 相同數量的p型和n型擴散鰭部， l 在電源軌下方刪除一個以上擴散鰭部， l 在p型和n型段之間無擴散鰭部被刪除， l 各擴散鰭部具實質上相等的寬度和長度，及 l 配置在n型擴散鰭部之間的p型擴散鰭部，反之亦然。In the illustrated arrangement of Figures 26A/B, the diffusing fins include the following features: • The diffusing fins may be on a lattice with a diffused fin pitch at a substantially uniform pitch with substantially equal pitches. In some embodiments less than 90 nm, more than one diffusing fin of each of the p-type and n-type, l the same number of p-type and n-type diffused fins, l removing more than one diffusing fin below the power rail, l No diffusing fins are removed between the p-type and n-type segments, l each diffusing fin has substantially equal width and length, and l a p-type diffusing fin disposed between the n-type diffusing fins, and vice versa Of course.
在圖26A/B的例示佈局中，局部內連線包含以下特徵： l 閘極電極和擴散鰭部源極/汲極接線係在不同的導體層；這些不同的導體層係彼此分隔開， l 用於源極汲極接線之平行於閘極的實質上線形導體層；在若干實施例中，具與閘極層相同的節距；且在若干實施例中，這個線形導體層可偏移半閘極節距，及 l 局部內連線與擴散鰭部的正重疊。In the illustrated layout of Figures 26A/B, the local interconnects include the following features: • The gate electrode and the diffuser fin source/drain wiring are in different conductor layers; these different conductor layers are separated from each other, a substantially linear conductor layer parallel to the gate for the source drain connection; in several embodiments, having the same pitch as the gate layer; and in several embodiments, the linear conductor layer is offset The half gate pitch, and the partial overlap of the local interconnect and the diffuser fin.
在圖26A/B的例示佈局中，較高階層的met1內連線層包含以下特徵： l 擴散鰭部之間的閘極電極結構接觸窗， l 接觸窗係在x和y方向其中之一或二者分格化， l 接觸窗將局部內連線和閘極導體連接至上方金屬層， l 在輸出節點上實質上線形的導體， l 在不同層之上的輸出節點和輸入節點接腳， l 在中間的電源軌，與在頂部和底部處電源軌相對；頂部和底部電源軌係共用；所有電源軌藉由毗鄰部連接至左方和右方，及 l 在最高金屬層上的輸出節點。In the illustrated layout of Figure 26A/B, the higher level of the met1 interconnect layer includes the following features: • a gate electrode structure contact window between the diffuser fins, l the contact window is in one of the x and y directions or The two are divided, l the contact window connects the local interconnect and the gate conductor to the upper metal layer, l the substantially linear conductor at the output node, and the output node and the input node pin on the different layers. l The power rail in the middle is opposite to the power rail at the top and bottom; the top and bottom power rails are shared; all power rails are connected to the left and right by adjacent parts, and the output node on the highest metal layer .
根據本發明若干實施例，圖27A/B顯示圖26A/B佈局的變形。圖27B顯示與圖27A相同的佈局，為了清楚緣故將佈局以合併型式描繪。圖27A/B的佈局包含以下特徵： l 將閘極電極繪製成具有一切割層，例如包含切割形狀部2701的切割層， l 在相同x位置處二個閘極導體段，其各自連接至一不同的連線，閘極導體段各自連接至一輸入連線，閘極導體段各自控制以多個鰭部建構之一p型和一n型電晶體，例如閘極導體2703及2705，及 l 在最高金屬層上的一個輸入接腳，在下方金屬層上的另一輸入接腳和輸出接腳。27A/B shows a variation of the layout of Fig. 26A/B, in accordance with several embodiments of the present invention. Figure 27B shows the same layout as Figure 27A, with the layout depicted in a merged format for clarity. The layout of Figures 27A/B includes the following features: • The gate electrode is drawn to have a cut layer, such as a cut layer comprising a cut shape portion 2701, l two gate conductor segments at the same x position, each connected to a Different wirings, the gate conductor segments are each connected to an input connection, and the gate conductor segments respectively control one p-type and one n-type transistor, such as gate conductors 2703 and 2705, and a plurality of fins. One input pin on the highest metal layer and another input pin and output pin on the lower metal layer.
根據本發明若干實施例，圖28A/B顯示實現擴散鰭部的例示元件佈局。圖28B顯示與圖28A相同的佈局，為了清楚緣故將佈局以合併型式描繪。在圖28A/B的例示佈局中，閘極電極層包含以下特徵： l 實質上線形的閘極電極結構， l 在閘極電極層上三個以上的線形結構，其中至少二者係虛設結構， l 三個以上閘極電極結構具有相同的尺寸， l 在閘極電極層上的結構在x方向上實質上均勻地分隔開及/或相等地節距化， l 虛設結構係與在左方及/或右方的相鄰元件共用， l 虛設結構在電源軌下方加以切割，In accordance with several embodiments of the present invention, FIG. 28A/B shows an exemplary component layout that implements a diffusion fin. Figure 28B shows the same layout as Figure 28A, with the layout depicted in a merged format for clarity. In the illustrated layout of FIG. 28A/B, the gate electrode layer includes the following features: • a substantially linear gate electrode structure, l three or more linear structures on the gate electrode layer, at least two of which are dummy structures, l Three or more gate electrode structures have the same size, l the structure on the gate electrode layer is substantially evenly spaced and/or equally pitched in the x direction, l the dummy structure is on the left And/or adjacent components on the right side, l the dummy structure is cut under the power rail,
應理解的是，任何此處所顯示的圖示，包含圖28A/B的例示佈局，取決於特定實行實施例，可具有定義成p型擴散鰭部的類型1擴散鰭部、及定義成n型擴散鰭部的類型2擴散鰭部，或者可具有定義成n型擴散鰭部的類型1擴散鰭部、及定義成p型擴散鰭部的類型2擴散鰭部。在圖28A/B的例示佈局中，擴散鰭部包含以下特徵： l 根據實質上相等的節距而實質上均勻分隔開的擴散鰭部，擴散鰭部可在一格子上，在若干實施例中擴散鰭部節距係小於90 nm， l p型和n型每一者的一個以上擴散鰭部， l 不同數量的p型和n型擴散鰭部， l 在電源軌下方將一個以上擴散鰭部刪除， l 在p型和n型段之間刪除一個以上擴散鰭部， l 各擴散鰭部具有實質上相等的寬度和長度。It should be understood that any of the illustrations shown herein, including the illustrated layout of FIG. 28A/B, may have a type 1 diffuser fin defined as a p-type diffuser fin and defined as an n-type, depending on the particular implementation embodiment. The type 2 diffusing fin of the diffusing fin may have a type 1 diffusing fin defined as an n-type diffusing fin and a type 2 diffusing fin defined as a p-type diffusing fin. In the illustrated layout of FIG. 28A/B, the diffusing fins include the following features: • substantially uniformly spaced apart diffusing fins according to substantially equal pitches, the diffusing fins can be on a grid, in several embodiments Medium diffuser fin pitch system is less than 90 nm, l p-type and n-type each of more than one diffuser fin, l different number of p-type and n-type diffuser fins, l more than one diffuser fin below the power rail Partial deletion, l Deleting more than one diffuser fin between the p-type and n-type segments, l each diffusing fin has substantially equal width and length.
在圖28A/B的例示佈局中，局部內連線包含以下特徵： l 閘極電極和擴散鰭部源極/汲極接線係直接自一傳導層， l 用於源極汲極接線之平行於閘極的實質上線形傳導層；在若干實施例中，具與閘極層相同的節距；且在若干實施例中，這個線形導體層可偏移半閘極節距， l 局部內連線與擴散鰭部及閘極電極結構之間的零或負重疊， l 局部內連線可以二個步驟建構，首先為垂直局部內連線結構，接著是水平局部內連線結構；各個步驟建立一組線形、單方向的局部內連線結構，及 l 或者是，二個獨立的局部內連線層，即一個垂直局部內連線層，和一水平局部內連線層。In the illustrated layout of Figure 28A/B, the local interconnects include the following features: • The gate electrode and the diffused fin source/drain wiring are directly from a conductive layer, and the source drain is parallel to the source. a substantially linear conductive layer of the gate; in some embodiments, having the same pitch as the gate layer; and in several embodiments, the linear conductor layer can be offset by a half gate pitch, l a local interconnect Zero or negative overlap with the diffuser fin and gate electrode structure, l The local interconnect can be constructed in two steps, first vertical vertical interconnect structure, then horizontal local interconnect structure; each step establishes a A linear, unidirectional local interconnect structure, and or two independent local interconnect layers, a vertical local interconnect layer, and a horizontal local interconnect layer.
在圖28A/B的例示佈局中，較高階層met1內連線層包含以下技術特徵： l 擴散鰭部可配置於電源軌下方 l 在x和y方向其中之一或二者上將接觸窗分格化（gridded）， l 接觸窗將所有局部內連線連接至上方金屬層，及 l 可在任何位置配置接觸窗。In the illustrated layout of FIG. 28A/B, the higher level met1 interconnect layer includes the following technical features: • The diffuser fin can be disposed under the power rail l to contact the window in one or both of the x and y directions Gridded, l The contact window connects all local interconnects to the upper metal layer, and l can be configured with contact windows at any location.
根據本發明若干實施例，圖29A/B顯示圖28A/B佈局的變形，其中在兩個n型電晶體的閘極電極結構之間沒有局部內連線結構。圖29B顯示與圖29A相同的佈局，為了清楚緣故將佈局以合併型式描繪。In accordance with several embodiments of the present invention, FIGS. 29A/B show a variation of the layout of FIG. 28A/B in which there is no local interconnect structure between the gate electrode structures of the two n-type transistors. Figure 29B shows the same layout as Figure 29A, with the layout depicted in a merged format for clarity.
根據本發明若干實施例，圖30A/B顯示實現擴散鰭部的例示元件佈局。圖30B顯示與圖30A相同的佈局，為了清楚緣故將佈局以合併型式描繪。在圖30A/B的例示佈局中，閘極電極層包含以下特徵： l 實質上線形閘極電極結構， l 在閘極電極層上的三個以上線形結構，其中至少二者係虛設結構， l 三個以上閘極電極結構具有相同尺寸， l 於閘極電極層上的結構在x方向上實質上均勻分隔開及/或相等節距化， l 虛設結構係與在左方及/或右方的相鄰元件共用， l 虛設結構在電源軌下方加以切割。30A/B shows an exemplary component layout that implements a diffusion fin, in accordance with several embodiments of the present invention. Figure 30B shows the same layout as Figure 30A, with the layout depicted in a merged format for clarity. In the illustrated layout of FIG. 30A/B, the gate electrode layer includes the following features: • substantially linear gate electrode structure, l three or more linear structures on the gate electrode layer, at least two of which are dummy structures, l More than three gate electrode structures have the same size, l the structure on the gate electrode layer is substantially evenly spaced and/or equally pitched in the x direction, l the dummy structure is on the left and/or right The adjacent components of the square are shared, and the dummy structure is cut under the power rail.
在圖30A/B的例示佈局中，擴散鰭部包含以下特徵： l 依據實質上相等節距實質上均勻分隔開的擴散鰭部，擴散鰭部可在一格子上，在若干實施例中擴散鰭部節距小於90 nm， l p型和n型各者之一個以上的擴散鰭部， l 相同數量的p型和n型擴散鰭部， l 在電源軌下方將一個以上擴散鰭部刪除， l 在p型和n型段之間將一個以上擴散鰭部刪除， l 擴散鰭部每一者具實質上相等的寬度和長度。In the illustrated arrangement of Figures 30A/B, the diffusing fins comprise the following features: • The diffusing fins may be spread over a grid, in several embodiments, according to substantially uniformly spaced diffusing fins of substantially equal pitch Fin pitch less than 90 nm, l more than one diffusing fin of p-type and n-type, l same number of p-type and n-type diffused fins, l remove more than one diffuser fin below the power rail, l Delete more than one diffuser fin between the p-type and n-type segments, and each of the diffused fins has substantially equal width and length.
在圖30A/B的例示佈局中，局部內連線包含以下特徵： l 閘極電極和擴散鰭部源極/汲極接線係直接來自一導體層， l 源極汲極接線用之平行於閘極的實質上線形導體層；在若干實施例中，具與閘極層相同的節距；且在若干實施例中，這個線形導體層可偏移半個閘極節距， l 局部內連線與擴散鰭部及閘極電極結構的零或負重疊， l 局部內連線可由二步驟建立，首先係垂直局部內連線結構，接著係水平局部內連線結構；各步驟建立一組線形、單方向局部內連線結構，及 l 在若干實施例中，垂直和水平局部內連線結構可形成為彼此交叉和連接，藉此形成一二維變化局部內連線結構，亦即是具有彎曲的局部內連線結構， l 或者是，二個獨立的局部內連線層――一個垂直局部內連線層、及一個水平局部內連線層。In the illustrated layout of FIG. 30A/B, the local interconnect includes the following features: • The gate electrode and the diffusion fin source/drain connection are directly from a conductor layer, and the source drain connection is parallel to the gate. a substantially substantially linear conductor layer; in some embodiments, having the same pitch as the gate layer; and in several embodiments, the linear conductor layer can be offset by a half gate pitch, l a local interconnect Zero or negative overlap with the diffuser fin and gate electrode structure, l the local interconnect can be established in two steps, firstly a vertical local interconnect structure, followed by a horizontal local interconnect structure; each step establishes a set of lines, Single-directional local interconnect structure, and in several embodiments, vertical and horizontal partial interconnect structures may be formed to intersect and join each other, thereby forming a two-dimensionally varying local interconnect structure, i.e., having a bend The local interconnect structure, l or two independent local interconnect layers - a vertical local interconnect layer and a horizontal local interconnect layer.
在圖30A/B的例示佈局中，較高階層met1內連線層包含以下特徵： l 擴散鰭部可配置於電源軌下方 l 在x和y方向其中之一或二者上將接觸窗分格化（gridded）， l 依據與閘極電極結構相同的節距配置met1內連線結構， l 接觸窗將所有局部內連線連接至上方金屬層，及 l 可在任何位置配置接觸窗。In the illustrated layout of FIG. 30A/B, the higher level met1 interconnect layer includes the following features: • The diffuser fin can be placed under the power rail l to separate the contact window in one or both of the x and y directions Gridded, l Configure the met1 interconnect structure according to the same pitch as the gate electrode structure. l The contact window connects all local interconnects to the upper metal layer, and l can be configured with contact windows at any position.
根據本發明若干實施例，圖31A顯示例示sdff元件佈局，其中閘極電極和局部內連線線端間隙位於擴散鰭部之間的實質上中心。在圖31A中，將閘極電極線端間隙圈出。圖31B顯示圖31A的例示sdff元件佈局，其中將位在擴散鰭部之間的實質上中心的局部內連線線端間隙圈出。基於圖31A至31B，應理解的是，可產生一元件庫結構，其中所有閘極電極和垂直內連線線端間隙實質上位於擴散鰭部之間的中心。根據本發明若干實施例，圖31C顯示具有兩個相鄰閘極電極結構之間的區域3105之標註的圖31A和31B的例示sdff元件佈局，其中擴散鰭部端部在x方向彼此重疊。31A shows an sdff component layout in which the gate electrode and the local interconnect line end gap are located substantially at the center between the diffuser fins, in accordance with several embodiments of the present invention. In Fig. 31A, the gate electrode line end gap is circled. Figure 31B shows the illustrated sdff element layout of Figure 31A in which a substantially central partial interconnect line end gap between the diffuser fins is circled. Based on Figures 31A through 31B, it will be appreciated that a component library structure can be created in which all gate electrodes and vertical interconnect line end gaps are substantially centered between the diffuser fins. 31C shows an exemplary sdff element layout of FIGS. 31A and 31B with an annotation of a region 3105 between two adjacent gate electrode structures, wherein the diffusion fin ends overlap each other in the x direction, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖32-34顯示標準元件電路佈局的一部分之三個範例。圖32顯示一例示佈局，其中所有將所有接觸層結構配置於擴散鰭部之間。圖33和34顯示例示佈局，其中將所有接觸層結構配置於擴散鰭部之上。在圖32的例子中，閘極電極線端間隙在若干實例中係實質上位於擴散鰭部上方的中心，如圓3201所標示，且在若干實例中，閘極電極線端間隙係實質上位於擴散鰭部之間的中心，如圓3203所標示。藉由利用將所有接觸層結構配置於擴散鰭部上方的一元件結構，所有閘極電極線端間隙可實質上位於擴散鰭部之間的中心，如在圖33和34之中的圓3301所標示。此處的一個優點係閘極電極線端間隙係皆具一固定的節距。從製造的觀點，閘極電極線端間隙是否在擴散鰭部上或擴散鰭部之間的中心處是不要緊的。然而，閘極電極線端間隙沒有混雜則是要緊的，如圖32的範例所示。使閘極電極線端間隙皆具相同節距會導致閘極電極製造過程較不昂貴、或更可靠、或滿足以上二者。Figures 32-34 show three examples of a portion of a standard component circuit layout, in accordance with several embodiments of the present invention. Figure 32 shows an exemplary layout in which all of the contact layer structures are disposed between the diffusion fins. Figures 33 and 34 show an exemplary layout in which all of the contact layer structures are disposed over the diffuser fins. In the example of FIG. 32, the gate electrode line end gap is substantially centered over the diffuser fin in several instances, as indicated by circle 3201, and in some examples, the gate electrode line end gap is substantially located The center between the diffusing fins is indicated by circle 3203. By utilizing an element structure in which all contact layer structures are disposed over the diffusion fins, all gate electrode line end gaps can be substantially centered between the diffusion fins, as in circle 3301 in Figures 33 and 34. Marked. One advantage here is that the gate electrode line gaps have a fixed pitch. From a manufacturing point of view, it does not matter whether the gate electrode line end gap is at the center of the diffusion fin or between the diffusion fins. However, it is important that the gate electrode end gaps are not mixed, as shown in the example of FIG. Having the same pitch at the gate end of the gate electrode results in a gate electrode fabrication process that is less expensive, more reliable, or both.
圖35A-69A顯示各種元件佈局，其展示可利用鰭式場效電晶體實施交叉連接電晶體配置之不同方式的範例。圖35A-69A的交叉連接佈局係以二輸入多工器電路（MUX2）的背景加以顯示。根據本發明若干實施例，圖35C顯示圖35A/B至47A/B及63A/B至67A/B的佈局的電路圖。根據本發明若干實施例，圖48C顯示圖48A/B至58A/B的佈局的電路圖。根據本發明若干實施例，圖59C顯示圖59A/B的佈局的電路圖。根據本發明若干實施例，圖60C顯示圖60A/B至62A/B及68A/B至69A/B的佈局的電路圖。根據本發明若干實施例，圖71C顯示圖71A/B及77A/B的佈局的電路圖。根據本發明若干實施例，圖72C顯示圖72A/B至76A/B的佈局的電路圖。在左方和右方邊緣上的電晶體被加入至該交叉連接以達成MUX2功能。對具有交叉連接電路的其他功能，這些可能係不同的。圖35B-69B分別顯示與圖35A-69A相同的佈局，為了清楚的緣故將佈局以合併型式描繪，且基於元件佈局的電路圖標示電路的節點。此外，在圖35A-69A中的交叉連接電晶體接線以線cc1和cc2加以標示。Figures 35A-69A show various component layouts showing examples of different ways in which cross-connect transistor configurations can be implemented using fin field effect transistors. The cross-connect layout of Figures 35A-69A is shown in the background of a two-input multiplexer circuit (MUX2). 35C shows a circuit diagram of the layout of FIGS. 35A/B to 47A/B and 63A/B to 67A/B, in accordance with several embodiments of the present invention. Figure 48C shows a circuit diagram of the layout of Figures 48A/B through 58A/B, in accordance with several embodiments of the present invention. Figure 59C shows a circuit diagram of the layout of Figure 59A/B, in accordance with several embodiments of the present invention. Figure 60C shows a circuit diagram of the layout of Figures 60A/B to 62A/B and 68A/B to 69A/B, in accordance with several embodiments of the present invention. Figure 71C shows a circuit diagram of the layout of Figures 71A/B and 77A/B, in accordance with several embodiments of the present invention. Figure 72C shows a circuit diagram of the layout of Figures 72A/B through 76A/B, in accordance with several embodiments of the present invention. A transistor on the left and right edges is added to the cross-connect to achieve the MUX2 function. These may be different for other functions with cross-connect circuits. Figures 35B-69B show the same layout as Figures 35A-69A, respectively, with the layout depicted in a merged format for clarity, and the circuit based on the component layout represents the nodes of the circuit. In addition, the cross-connect transistor wirings in Figures 35A-69A are labeled with lines cc1 and cc2.
圖35A/B至47A/B及63A/B至67A/B顯示在邏輯路徑二者上具有傳輸閘極的交叉連接電晶體配置，其需要所有內部節點具有p型和n型之間的連接。圖48A/B至57A/B顯示顯示交叉連接電晶體配置，其中具有使用較大電晶體之在邏輯路徑上的傳輸閘極，以及在其他路徑上的三態閘極。三態閘極不需要於內部節點上之p型擴散和n型擴散之間的接線。Figures 35A/B through 47A/B and 63A/B through 67A/B show a cross-connect transistor configuration with transmission gates on both logical paths that require all internal nodes to have a connection between p-type and n-type. Figures 48A/B through 57A/B show a cross-connect transistor configuration with a transmission gate on a logic path using a larger transistor and a three-state gate on other paths. The three-state gate does not require wiring between p-type diffusion and n-type diffusion on the internal node.
圖58A/B至59A/B顯示交叉連接電晶體配置，其中具有利用較小電晶體之在邏輯路徑上傳輸閘極，以及在其他路徑上的三態閘極。三態閘極不需要於內部節點上之p型擴散和n型擴散之間的接線。Figures 58A/B through 59A/B show a cross-connect transistor configuration with a gate that transmits on a logic path with a smaller transistor and a three-state gate on other paths. The three-state gate does not require wiring between p-type diffusion and n-type diffusion on the internal node.
圖60A/B至62A/B及68A/B至69A/B顯示在邏輯路徑二者上具有三態閘極的交叉連接電晶體配置。Figures 60A/B through 62A/B and 68A/B through 69A/B show cross-connect transistor configurations with three-state gates on both logic paths.
圖63A/B至69A/B顯示具有相等於n型擴散鰭部數量之p型擴散鰭部數量的元件佈局。其他圖35A/B至62A/B其中若干顯示具有不相等於n型擴散鰭部數量之p型擴散鰭部數量的元件佈局。Figures 63A/B through 69A/B show an element layout having the number of p-type diffusion fins equal to the number of n-type diffusion fins. The other FIGS. 35A/B to 62A/B show several of the element layouts having the number of p-type diffusion fins that are not equal to the number of n-type diffusion fins.
圖40A/B顯示使用水平/垂直局部內連線結構之間較緊密間距的元件佈局。圖37A/B、45A/B、及49A/B顯示使用擴散鰭部之間較大間距的元件佈局範例。圖63A/B至69A/B顯示使用擴散鰭部之間較緊密間距的元件佈局範例。圖43A/B及44A/B顯示利用一擴散鰭部作為一配線的元件佈局範例。Figure 40A/B shows a component layout using tighter spacing between horizontal/vertical local interconnect structures. Figures 37A/B, 45A/B, and 49A/B show examples of component layouts using larger spacing between diffusing fins. Figures 63A/B through 69A/B show an example of component placement using a tighter spacing between diffusing fins. 43A/B and 44A/B show an example of component layout using a diffusion fin as a wiring.
圖35A/B至41A/B、48A/B至65A/B、及68A/B至69A/B顯示利用沒有分離閘極之密集閘極電極結構實施方式的元件佈局範例。圖42A/B至47A/B及66A/B至67A/B顯示利用具較少配線及較大電晶體尺寸的使用分離閘極實施方式的元件佈局範例。Figures 35A/B through 41A/B, 48A/B through 65A/B, and 68A/B through 69A/B show examples of component layouts using dense gate electrode structure embodiments without split gates. Figures 42A/B through 47A/B and 66A/B through 67A/B show examples of component layouts using separate gate embodiments with less wiring and larger transistor sizes.
圖35A/B至69A/B顯示元件佈局範例，其展示用於各種元件佈局之數個不同的佈線範例。圖35A/B至69A/B顯示元件佈局範例，其展示使用全部填滿之閘極電極層，包含閘極電極端蓋的延伸部及使用可能在閘極電極層之內的虛設結構。在圖35A/B至69A/B所顯示的若干元件佈局，顯示在元件頂部和底部沒有切割之虛設閘極電極層結構，亦即是在製造過程期間切割遮罩操作之前。若干元件佈局，例如圖53A/B至55A/B及66A/B，顯示其中刪除電源匯流排的例示元件佈局。Figures 35A/B through 69A/B show an example of component layout showing several different wiring paradigms for various component layouts. Figures 35A/B through 69A/B show an example of component layout showing the use of a fully filled gate electrode layer, an extension including a gate electrode cap, and a dummy structure that may be used within the gate electrode layer. The number of component layouts shown in Figures 35A/B through 69A/B shows the dummy gate electrode layer structure without dicing at the top and bottom of the component, i.e., prior to the trim masking operation during the manufacturing process. Several component layouts, such as Figures 53A/B through 55A/B and 66A/B, show an exemplary component layout in which the power busbars are removed.
圖35A/B至69A/B的交叉連接電晶體構造，包含在各層上以及層的組合上所形成的結構，並且許多以上所提及的元件佈局特徵可互相獨立地應用。應理解的是，圖35A/B至69A/B的元件佈局顯示可利用基於鰭式場效電晶體交叉連接電晶體構造而實行的範例，且不代表可能元件佈局配置的所有包含集合。在圖35A/B至69A/B的各種元件佈局範例中所展示的任何特徵，可加以組合而產生額外的元件佈局。The cross-connected transistor configuration of Figures 35A/B to 69A/B includes structures formed on various layers and combinations of layers, and many of the above-mentioned component layout features can be applied independently of each other. It should be understood that the component layouts of Figures 35A/B through 69A/B show examples that may be implemented using a fin field effect transistor cross-connect transistor configuration and do not represent all of the included sets of possible component layout configurations. Any of the features shown in the various component layout examples of Figures 35A/B through 69A/B can be combined to create additional component layouts.
光學解析度不足以直接解析線圖案的技術，將會使用若干型式的節距分割（pitch division）。節距分割可在可達成的解析度上經由多個曝光步驟或利用間格部加以自對準。舉例來說，對於使用水浸最末透鏡的ArF準分子雷射掃描器及曝光之晶圓的一部分，光學解析度係限制至～40 nm。這相當於1.35有效數值孔徑與波長193 nm的k1值0.28。對於擴散鰭部層和閘極電極層和利用節距分割所形成的其他層（例如間隔物雙重圖案化、間隔物四重圖案化、多重曝光微影-蝕刻-微影-蝕刻等等），縱使佈局係以傳導結構用（即用於該等線）的均勻節距（縱向中心線至縱向中心線節距）加以進行，製造後傳導結構可能由於處理變異而輕微地偏離目標，使得最終晶圓上有多個（例如：二、四等等）節距。A technique in which the optical resolution is insufficient to directly resolve the line pattern will use several types of pitch division. The pitch segmentation can be self-aligned over a plurality of exposure steps or using a bay portion at an achievable resolution. For example, for an ArF excimer laser scanner using a water immersed lens and a portion of the exposed wafer, the optical resolution is limited to ~40 nm. This is equivalent to a 1.35 effective numerical aperture and a k1 value of 0.28 at a wavelength of 193 nm. For the diffusion fin layer and the gate electrode layer and other layers formed by the pitch division (for example, spacer double patterning, spacer quadruple patterning, multiple exposure lithography-etching-lithography-etching, etc.), Even though the layout is performed with a uniform pitch (longitudinal centerline to longitudinal centerline pitch) for the conductive structure (ie for the lines), the post-production conductive structure may slightly deviate from the target due to processing variations, resulting in a final crystal There are multiple (for example: two, four, etc.) pitches on the circle.
可與自對準間隔物方式或多重微影曝光法一起，應用節距分割多次，例如以二節距分割（pitch-division-by-2）、以四節距分割（pitch-division-by-4）。以四節距分割已被記載達成約11 nm的線/間格。節距分割的一個限制係結果的線圖案可在圖案之內具有些微不同的節距。對於以二節距分割，這意指二條線的群組將具有一個節距，其下一個二條線的群組可能具有些微不同的節距，下一個二線群組將會具有與第一群組相等的節距等等。在所完成晶圓上的結果將會是意欲達到具均勻的、固定的節距的線，但該等最終會具有二或四或其他多種的節距。對於自對準間隔部，將依一固定的、均勻的節距繪製原始核心線圖案。對於多重曝光，曝光每一者將會具有以均勻固定節距所繪製的線。由節距分割過程所引入的非均勻節距可能會在10%或更少最終節距的等級。舉例來說，對於最終目標節距50 nm，二條線群組每一者的節距可能有小於5 nm的差異。受限制的閘極階層佈局結構 The pitch can be divided multiple times together with the self-aligned spacer method or the multiple lithography exposure method, for example, pitch-division-by-2, split-division-by -4). Segmentation at four pitches has been documented to achieve a line/space of approximately 11 nm. One limitation of pitch segmentation is that the resulting line pattern can have slightly different pitches within the pattern. For splitting by two pitches, this means that the group of two lines will have a pitch, the group of the next two lines may have a slightly different pitch, and the next two-line group will have the same group Group equal pitch and so on. The result on the finished wafer will be to achieve a line with a uniform, fixed pitch, but these will eventually have two or four or many other pitches. For self-aligned spacers, the original core line pattern will be drawn at a fixed, uniform pitch. For multiple exposures, each of the exposures will have a line drawn at a uniform fixed pitch. The non-uniform pitch introduced by the pitch segmentation process may be at the level of 10% or less final pitch. For example, for a final target pitch of 50 nm, the pitch of each of the two line groups may have a difference of less than 5 nm. Restricted gate level layout structure
如以上所探討，包含鰭式場效電晶體的各種電路佈局，可在一限制的閘極階層佈局結構之內加以施行。對於閘極階層，數條平行虛擬線定義成延伸通過該佈局。這些平行虛擬線係稱作閘極電極軌道，因為它們係用以指示在佈局之內各種電晶體的閘極電極的配置。在若干實施例中，形成閘極電極軌道的平行虛擬線，係由與指定的閘極電極節距相等的其間垂直間距加以界定。因此，在閘極電極軌道上的閘極電極區段的配置係對應於該指定的閘極電極節距。在另一實施例中，閘極電極軌道可由大於或等於一指定閘極電極節距的可變節距加以分隔開。As discussed above, various circuit layouts including fin field effect transistors can be implemented within a limited gate level layout structure. For the gate level, a number of parallel virtual lines are defined to extend through the layout. These parallel virtual lines are referred to as gate electrode tracks because they are used to indicate the configuration of the gate electrodes of the various transistors within the layout. In several embodiments, the parallel imaginary lines forming the gate electrode tracks are defined by their vertical spacing equal to the specified gate electrode pitch. Thus, the configuration of the gate electrode segments on the gate electrode tracks corresponds to the specified gate electrode pitch. In another embodiment, the gate electrode tracks may be separated by a variable pitch greater than or equal to a specified gate electrode pitch.
根據本發明若干實施例，圖70A顯示在受限制的閘極階層佈局結構之內所定義的閘極電極軌道70-1A至70-1E的範例。閘極電極軌道70-1A至70-1E係由延伸通過晶片的閘極階層佈局的平行虛擬線所形成，其具有等於一指定閘極電極節距70-3的垂直間距於其間。Figure 70A shows an example of gate electrode tracks 70-1A through 70-1E defined within a restricted gate level layout structure, in accordance with several embodiments of the present invention. The gate electrode tracks 70-1A through 70-1E are formed by parallel imaginary lines extending through the gate level layout of the wafer with a vertical pitch equal to a specified gate electrode pitch 70-3 therebetween.
在受限制的閘極階層佈局結構之內，閘極階層特徵佈局通道係關於一特定閘極電極軌道而加以定義，以在與該特定閘極電極軌道相鄰的閘極電極軌道之間延伸。舉例來說，閘極階層特徵佈局通道70-5A至70-5E係分別關於閘極電極軌道70-1A至70-1E而加以定義。應理解的是，各閘極電極軌道具有對應的閘極階層特徵佈局通道。此外，對於配置成與一規定的佈局空間的邊緣相鄰（例如與元件邊界相鄰）之閘極電極軌道，對應的閘極階層特徵佈局通道延伸成就如在該規定佈局空間外側的虛擬閘極電極軌道，如閘極階層特徵佈局通道70-5A及70-5E所描述。更應理解的是，各閘極階層特徵佈局通道係定義成沿著其對應閘極電極軌道的全部長度延伸。因此，各閘極階層特徵佈局通道係定義成延伸通過在該閘極階層佈局所關聯之晶片的一部份之內的該閘極階層佈局。Within the restricted gate level layout structure, the gate level feature layout channel is defined with respect to a particular gate electrode track to extend between the gate electrode tracks adjacent to the particular gate electrode track. For example, the gate level feature layout channels 70-5A through 70-5E are defined with respect to the gate electrode tracks 70-1A through 70-1E, respectively. It should be understood that each gate electrode track has a corresponding gate level feature layout channel. In addition, for a gate electrode track that is disposed adjacent to an edge of a prescribed layout space (eg, adjacent to an element boundary), the corresponding gate level feature layout channel extends as a virtual gate outside the specified layout space Electrode tracks, as described in the gate level feature layout channels 70-5A and 70-5E. It should be further understood that each gate level feature layout channel is defined to extend along the entire length of its corresponding gate electrode track. Thus, each gate level feature layout channel is defined to extend through the gate level layout within a portion of the wafer associated with the gate level layout.
在受限制的閘極階層佈局結構中，與一特定閘極電極軌道相關聯的閘極階層特徵係定義在與該特定閘極電極軌道相關聯的閘極階層特徵佈局通道之內。一連續的閘極階層特徵可包含定義一電晶體的閘極電極的部分（如此處所揭露的鰭式場效電晶體）、及未定義一電晶體的閘極電極的部分二者。因此，一連續閘極階層特徵可延伸於一擴散區域（即擴散鰭部）及一下方晶片階層的介電區域二者上方。In a restricted gate level layout structure, a gate level feature associated with a particular gate electrode track is defined within a gate level feature layout channel associated with the particular gate electrode track. A continuous gate level feature can include both portions defining a gate electrode of a transistor (such as the fin field effect transistor disclosed herein), and portions of a gate electrode not defining a transistor. Thus, a continuous gate level feature can extend over both a diffusion region (ie, a diffusion fin) and a dielectric region of a lower wafer level.
在若干實施例中，將形成一電晶體的閘極電極的閘極階層特徵的各部分，配置成實質上位於一特定閘極電極軌道的中心。此外，在這個實施例中，不形成一電晶體的閘極電極的閘極階層特徵的部分，可配置於與該特定閘極軌道相關聯的閘極階層特徵佈局通道之內。因此，一特定閘極階層特徵可實質上定義在一特定閘極階層特徵佈局通道之內的任何位置，只要該特定閘極階層特徵的閘極電極部分在對應該特定閘極階層佈局特徵的閘極電極軌道的中心，且只要該特定閘極階層特徵相對於在相鄰閘極階層佈局通道中的其他閘極階層特徵符合設計法則間距規定。此外，定義於與相鄰閘極電極軌道相關聯的閘極階層特徵通道中的閘極階層特徵之間的物理性接觸係不允許的。In some embodiments, portions of the gate level features of the gate electrode forming a transistor are configured to be substantially centered on a particular gate electrode track. Moreover, in this embodiment, the portion of the gate level feature of the gate electrode that does not form a transistor can be disposed within the gate level feature layout channel associated with the particular gate track. Thus, a particular gate level feature can be defined substantially anywhere within a particular gate level feature layout channel as long as the gate electrode portion of the particular gate level feature is gated corresponding to a particular gate level layout feature The center of the pole electrode track, as long as the particular gate level feature meets the design rule spacing with respect to other gate level features in adjacent gate level layout channels. Furthermore, physical contact between gate level features defined in the gate level feature channels associated with adjacent gate electrode tracks is not permitted.
根據本發明若干實施例，圖70B顯示圖70A的例示受限制的閘極階層佈局結構，其具有數個例示閘極階層特徵7001-7008定義於其中。閘極階層特徵7001係定義在與閘極電極軌道70-1A相關聯的閘極階層特徵佈局通道70-5A之內。閘極階層特徵7001的閘極電極部分係實質上位於閘極電極軌道70-1A的中心。此外，閘極階層特徵7001的非閘極電極部分維持設計規則間距規定，其中閘極階層特徵7002及7003係定義在相鄰閘極階層特徵佈局通道70-5B之內。類似地，閘極階層特徵7002-7008係定義在其各自閘極階層特徵佈局通道之內，且其閘極電極部分位於對應其各自閘極階層特徵佈局通道的閘極電極軌道上的中心。此外，應瞭解的是，閘極階層特徵7002-7008每一者係維持設計規則間距規定，其中閘極階層特徵係定義在相鄰閘極階層特徵佈局通道之內，且避免與相鄰閘極階層特徵佈局通道之內所定義的任何另外的閘極階層特徵之物理性接觸。Figure 70B shows an exemplary restricted gate level layout structure of Figure 70A having a plurality of exemplary gate level features 7001-7008 defined therein, in accordance with several embodiments of the present invention. The gate level feature 7001 is defined within the gate level feature layout channel 70-5A associated with the gate electrode track 70-1A. The gate electrode portion of the gate level feature 7001 is substantially at the center of the gate electrode track 70-1A. In addition, the non-gate electrode portion of the gate level feature 7001 maintains a design regular spacing specification wherein the gate level features 7002 and 7003 are defined within adjacent gate level feature layout channels 70-5B. Similarly, gate level features 7002-7008 are defined within their respective gate level feature layout channels, and their gate electrode portions are centered on the gate electrode tracks corresponding to their respective gate level feature layout channels. In addition, it should be understood that the gate level features 7002-7008 each maintain a design rule spacing specification, wherein the gate level features are defined within adjacent gate level feature layout channels and avoid adjacent gates. The physical contact of any additional gate-level features defined within the hierarchical feature layout channel.
一閘極電極係對應在一擴散結構上方（亦即是擴散鰭部上方）延伸的一各自的閘極階層特徵的一部份，其中將各自的閘極階層特徵整體地定義於一閘極階層特徵佈局通道之內。在沒有物理性接觸在相鄰閘極階層特徵佈局通道之內所定義的另一閘極階層特徵的狀況下，各閘極階層特徵係定義在其閘極階層特徵佈局通道之內。如圖70B的例示閘極階層特徵佈局通道70-5A至70-5E所描述，各閘極階層特徵佈局通道係與一特定閘極電極軌道相關聯，且對應一佈局區域，該佈局區域沿著該特定閘極電極軌道延伸，且在自該特定閘極電極軌道至相鄰閘極電極軌道或佈局邊界外側的一虛擬閘極電極軌道任一者之其中最接近者的各個相反方向上垂直向外延伸。A gate electrode corresponds to a portion of a respective gate level feature extending above a diffusion structure (ie, above the diffusion fin), wherein the respective gate level features are integrally defined at a gate level Within the feature layout channel. In the absence of physical contact with another gate-level feature defined within adjacent gate-level feature layout channels, each gate-level feature is defined within its gate-level feature layout channel. As depicted in the illustrated gate level feature layout channels 70-5A through 70-5E of Figure 70B, each gate level feature layout channel is associated with a particular gate electrode track and corresponds to a layout area along which the layout area The particular gate electrode track extends vertically in each of the opposite directions of the closest one of the virtual gate electrode tracks from the particular gate electrode track to the adjacent gate electrode track or outside of the layout boundary Extend outside.
若干閘極階層特徵可具有一個以上接觸頭部（contact head）部分，其定義在沿其長度的任何數量的位置處。一特定閘極階層特徵的接觸頭部部分係定義成具有足夠尺寸的高度和寬度的閘極階層特徵區段，以容納閘極接觸窗結構。在這個實例中，「寬度」係在垂直於該特定閘極階層特徵的閘極電極軌道的方向上橫越基板而加以定義，且「高度」係在平行於該特定閘極階層特徵的閘極電極軌道的方向上橫越基板而定義。取決於在一元件之內閘極階層特徵的定向，閘極階層特徵寬度和高度可對應或可不對應元件寬度W及元件高度H。應瞭解的是，一閘極階層特徵的接觸頭部，當自上方觀察，可由實質上任何佈局形狀加以定義，該佈局形狀包含正方形或矩形。此外，取決於佈局需求和電路設計，一閘極階層特徵的一特定接觸頭部部分可具有或可不具有定義於其上方的一閘極接觸窗。A number of gate level features may have more than one contact head portion defined at any number of locations along its length. The contact head portion of a particular gate level feature is defined as a gate level feature segment having a height and width of sufficient size to accommodate the gate contact window structure. In this example, the "width" is defined across the substrate in a direction perpendicular to the gate electrode track of the particular gate level feature, and the "height" is at the gate parallel to the particular gate level feature. The direction of the electrode track is defined across the substrate. Depending on the orientation of the gate level features within a component, the gate level feature width and height may or may not correspond to component width W and component height H. It will be appreciated that the contact head of a gate level feature, as viewed from above, may be defined by substantially any layout shape comprising a square or a rectangle. Moreover, depending on the layout requirements and circuit design, a particular contact head portion of a gate level feature may or may not have a gate contact window defined above it.
揭露於此處的若干實施例的一閘極階層係定義成一受限制的閘極階層，如上所述。該等閘極階層特徵其中若干形成電晶體裝置的閘極電極。該等閘極階層特徵的其他者可形成延伸於該閘極階層之內二點之間的傳導區段。此外該等閘極階層特徵的其他者可相對於積體電路操作無功能。應理解的是，無論功能，在沒有物理性接觸由相鄰閘極階層特徵佈局通道所定義的其他閘極階層特徵的狀況下，各閘極階層特徵係定義成在其各自閘極階層特徵佈局通道之內延伸通過該閘極階層。A gate hierarchy of several embodiments disclosed herein is defined as a restricted gate level, as described above. Some of the gate level features form the gate electrode of the transistor device. Others of the gate level features may form a conductive section extending between two points within the gate level. In addition, the other of the gate level features may be non-functional with respect to the integrated circuit operation. It should be understood that regardless of function, in the absence of physical contact with other gate-level features defined by adjacent gate-level feature layout channels, each gate-level feature is defined as a feature layout at its respective gate level. The gate extends through the gate level.
在若干實施例中，閘極階層特徵係定義成提供有限數量的受控制的佈局形狀對形狀微影交互作用，其在製造和設計過程中可精確地加以預測和予以最佳化。在這個實施例中，閘極階層特徵係定義成用以避免會在佈局之內引入不利的微影交互作用的佈局形狀對形狀空間關係，該不利的微影交互作用無法準確地加以預測且不具高度可能性加以減輕。然而，應理解的是，當對應的微影交互作用係可預測的且可控制的，在閘極階層特徵的閘極階層佈局通道之內閘極階層特徵方向上的變化係可接受的。In several embodiments, the gate level feature is defined to provide a limited number of controlled layout shape-to-shape lithography interactions that can be accurately predicted and optimized during manufacturing and design. In this embodiment, the gate level feature is defined to avoid layout shape-to-shape spatial relationships that would introduce unfavorable lithographic interactions within the layout, which unpredictable lithographic interactions cannot be accurately predicted and High probability is alleviated. However, it should be understood that when the corresponding lithographic interaction is predictable and controllable, variations in the direction of the gate level feature within the gate level layout channel of the gate level feature are acceptable.
應理解的是，無論功能，閘極階層特徵每一者係定義成，沒有沿著一特定閘極電極軌道的閘極階層特徵係建構成自閘極階層之內直接連接至沿著的不同閘極電極軌道所定義的另一閘極階層特徵而沒有利用非閘極階層特徵。此外，配置於與不同閘極電極軌道相關聯的不同閘極階層佈局通道之內的閘極階層特徵之間的各接線，係製作成穿過可定義於較高內連線階層的一個以上非閘極階層特徵，亦即是穿過閘極階層上方一或多內連線階層，或藉由在閘極階層或於閘極階層下方的局部內連線特徵所製作。It should be understood that regardless of function, the gate level features are each defined such that the gate level features of a particular gate electrode track are not directly connected to each other along the gate from the gate level. Another gate-level feature defined by the pole electrode track does not utilize non-gate-level features. In addition, the wires between the gate-level features disposed within different gate-level layout channels associated with different gate electrode tracks are made to pass through more than one non-definitely defined at a higher interconnect level The characteristics of the gate level, that is, one or more interconnect levels above the gate level, or by local interconnect features at the gate level or below the gate level.
根據本發明若干實施例，圖71A/B至77A/B顯示數個例示SDFF電路佈局，其利用基於傳輸和三態閘極二者的交叉連接電路結構。根據本發明若干實施例，圖71C顯示圖71A/B和77A/B的電路圖。根據本發明若干實施例，圖72C顯示圖73A/B至76A/B的電路圖。圖71B-77B顯示分別與圖71A-77A相同的佈局，其中為了清楚的緣故將佈局以合併方式描繪，且電路的節點係基於元件佈局電路圖而加以標示。圖71A/B至77A/B的例示SDFF電路佈局包含以下特徵： 1. 閘極導體： a. 實質上均勻分隔開的閘極導體。 b. 利用切割遮罩所形成的相同的閘極導體線端間隙，其與大的閘極導體線端間隙結合以避免局部互連，或者若有足夠空間容許不須切割之較大閘極導體線端間隙。 c. 在若干實例中，若干閘極導體係用以作為佈線以減少金屬層利用率，亦即是降低較高階層內連線利用率。 2. 擴散鰭部： a. 實質上均勻分隔開的擴散鰭部。 b. 在p型和n型之間以及頂部和底部元件邊緣，將擴散鰭部刪除。 c. 擴散鰭部寬度對間距關係可變化，或可具有實質上相等的關係，如在圖71A/B至77A/B的範例中所描繪。 3. 局部內連線： a. 局部內連線結構可直接連接至擴散鰭部和閘極導體。 b. 局部內連線結構可經由一接觸層連接至金屬層1（met1或M1）。 c. 水平和垂直局部內連線結構，例如以例示為目的的圖76A/B所顯示者，可利用獨立的設計層加以製造，亦即是利用獨立的遮罩層加以製造。 d. 水平和垂直局部內連線結構可在相同的層，即在相同的遮罩層，如圖71A/B至圖75A/B及77A/B的範例中所顯示。此外，在製造期間，水平和垂直局部內連線結構可用二個不同的步驟或以一單一步驟加以製作。 e. 局部內連線結構可具有與擴散鰭部和閘極導體之正、零、或負重疊。 f. 垂直局部內連線可具有與閘極導體相似的節距，且具有自閘極導體半節距偏移。 4. 接觸窗： a. 接觸窗可定義成用以連接局部內連線結構至金屬層1（met1或M1）。 b. 局部內連線結構可具有在接觸窗上之正、零、或負重疊。 c. 金屬層1（met1或M1）可具有在接觸窗上之正、零、或負重疊。 5. 金屬層2（met2或M2） a. 在若干實施例中，金屬層2結構可為單方向的，即線形。 b. 金屬層2結構可在水平（x）及/或垂直（y）方向上延伸。In accordance with several embodiments of the present invention, FIGS. 71A/B through 77A/B show several exemplary SDFF circuit layouts that utilize a cross-connect circuit structure based on both transmission and tri-state gates. Figure 71C shows a circuit diagram of Figures 71A/B and 77A/B, in accordance with several embodiments of the present invention. Figure 72C shows the circuit diagram of Figures 73A/B through 76A/B, in accordance with several embodiments of the present invention. Figures 71B-77B show the same layout as Figures 71A-77A, respectively, with the layout depicted in a merged manner for clarity, and the nodes of the circuit are labeled based on the component layout circuit diagram. The illustrated SDFF circuit layout of Figures 71A/B through 77A/B includes the following features: 1. Gate conductor: a. Substantially evenly spaced gate conductors. b. Use the same gate conductor line end gap formed by the cut mask, which is combined with the large gate conductor line end gap to avoid local interconnection, or if there is enough space to allow larger gate conductors that do not need to be cut Line end clearance. c. In several instances, several gate conduction systems are used as wiring to reduce metal layer utilization, that is, to reduce wiring utilization in higher levels. 2. Diffusion fins: a. Diffusion fins that are substantially evenly spaced apart. b. Remove the diffusing fin between the p-type and n-type and the top and bottom component edges. c. The diffuser fin width may vary in pitch relationship or may have a substantially equal relationship, as depicted in the examples of Figures 71A/B through 77A/B. 3. Local interconnects: a. The local interconnect structure can be directly connected to the diffuser fins and gate conductors. b. The local interconnect structure may be connected to the metal layer 1 (met1 or M1) via a contact layer. c. Horizontal and vertical partial interconnect structures, such as those shown for ease of illustration in Figures 76A/B, may be fabricated using separate design layers, i.e., fabricated using separate mask layers. d. The horizontal and vertical local interconnect structures may be shown in the same layer, i.e., in the same mask layer, as in the examples of Figures 71A/B through 75A/B and 77A/B. In addition, the horizontal and vertical partial interconnect structures can be fabricated in two separate steps or in a single step during manufacture. e. The local interconnect structure may have a positive, zero, or negative overlap with the diffuser fin and the gate conductor. f. The vertical partial interconnect may have a pitch similar to that of the gate conductor and have a half pitch offset from the gate conductor. 4. Contact window: a. The contact window can be defined to connect the local interconnect structure to the metal layer 1 (met1 or M1). b. The local interconnect structure may have a positive, zero, or negative overlap on the contact window. c. Metal layer 1 (met1 or M1) may have a positive, zero, or negative overlap on the contact window. 5. Metal layer 2 (met2 or M2) a. In several embodiments, the metal layer 2 structure may be unidirectional, i.e., linear. b. The metal layer 2 structure may extend in a horizontal (x) and/or vertical (y) direction.
圖71A/B的例示SDFF電路佈局顯示以下其所包含的特徵： l 金屬層2係不用於內部佈線。 l 金屬層2係用於電源軌。 l 使用三態和傳輸閘極交叉連接電晶體結構。 l 局部內連線結構在水平（x）和垂直（y）方向上延伸。 l 若干閘極導體係用以作為佈線，且不形成一電晶體的閘極電極。 l 在各種位置和組合配置閘極導體切割。 l 閘極導體切割在尺寸上一致。 l 閘極導體層係全部被填滿的，亦即是至少一個閘極導體係配置於元件內各可使用的閘極導體節距位置。The exemplary SDFF circuit layout of Figures 71A/B shows the following features: • Metal layer 2 is not used for internal wiring. l Metal layer 2 is used for the power rail. l Use a tri-state and a transfer gate to cross-connect the transistor structure. l The local interconnect structure extends in the horizontal (x) and vertical (y) directions. l Several gate conduction systems are used as wiring and do not form a gate electrode of a transistor. l Configure gate conductor cuts in a variety of locations and combinations. l The gate conductor cuts are identical in size. l The gate conductor layer is completely filled, that is, at least one gate conduction system is disposed at each of the gate conductor pitch positions that can be used in the component.
圖72A/B的例示SDFF電路佈局顯示包含的以下特徵： l 金屬層2結構係用於在垂直（y）方向上的內部佈線。 l 較圖71A/B的範例密集的電路佈局。 l 使用三態和傳輸閘極二者的交叉連接電晶體結構。 l 閘極導體層係全部填滿的，亦即是至少一個閘極導體係配置於元件內各可使用的閘極導體節距位置。 l 顯示閘極導體切割。 l 在各種組合及/或位置使用實質上一致的閘極導體切割，以將佈局最佳化。The illustrated SDFF circuit layout of Figures 72A/B shows the following features: The metal layer 2 structure is used for internal routing in the vertical (y) direction. l Example dense circuit layout compared to Figure 71A/B. l Use a cross-connect transistor structure that uses both tristate and transfer gates. l The gate conductor layer is completely filled, that is, at least one gate conduction system is disposed at each of the gate conductor pitch positions that can be used in the component. l Display gate conductor cut. • Use substantially identical gate conductor cuts in various combinations and/or locations to optimize layout.
圖73A/B的例示SDFF電路佈局顯示SDFF電路的一版本，其將閘極導體和金屬層2二者使用於垂直（y方向）佈線。圖74A/B的例示SDFF電路佈局顯示SDFF電路一版本，其將水平定向（即在x方向）的金屬層2結構使用於內部佈線。圖75A/B的例示SDFF電路佈局顯示SDFF電路的一替代版本，其亦將水平定向（即在x方向）的金屬層2結構使用於內部佈線。圖76A/B的例示SDFF電路佈局顯示圖72A/B佈局的變形，其中將水平局部內連線和垂直局部內連線使用為獨立的導體，以容許內部金屬層2導體的移除。圖77A/B的例示SDFF電路佈局顯示部分的SDFF佈局，其描述用以定義電路結構之替代方式，以將金屬層2的使用最小化並將電晶體密度最大化。The illustrated SDFF circuit layout of Figures 73A/B shows a version of the SDFF circuit that uses both the gate conductor and the metal layer 2 for vertical (y-direction) routing. The illustrated SDFF circuit layout of Figures 74A/B shows a version of the SDFF circuit that uses a horizontally oriented (i.e., in the x-direction) metal layer 2 structure for internal routing. The exemplary SDFF circuit layout of Figures 75A/B shows an alternative version of the SDFF circuit that also uses a horizontally oriented (i.e., in the x-direction) metal layer 2 structure for internal routing. The illustrated SDFF circuit layout of Figures 76A/B shows a variation of the layout of Figure 72A/B in which horizontal partial interconnects and vertical local interconnects are used as separate conductors to allow removal of the inner metal layer 2 conductor. 77A/B illustrates an SDFF layout of the SDFF circuit layout display portion, which describes an alternative way to define the circuit structure to minimize the use of the metal layer 2 and maximize the transistor density.
應理解的是，基於電路佈局和此處所提供的說明，在若干實施例中可使用一個以上以下特徵： l 共同對準及相鄰配置的擴散鰭部端部之間的間隔距離（即擴散鰭部切割距離）可小於閘極電極節距的尺寸， l 垂直局部內連線結構可在擴散鰭部的一個邊緣（水平定向的邊緣）上與一擴散鰭部（其係水平定向的）重疊；在此情況下，用以分開垂直局部內連線結構的若干切割（在一切割遮罩中）可定義成與一擴散鰭部接觸或重疊， l 一水平局部內連線結構可在閘極電極結構的一邊緣（垂直定向的邊緣）上與一閘極電極結構（其為垂直定向的）重疊， l 閘極端蓋的尺寸（即閘極電極結構延伸超出下方擴散鰭部的距離）可小於一個以上擴散鰭部節距的尺寸，或小於平均擴散鰭部節距的尺寸， l 共同對準和相鄰配置的閘極電極結構端部之間的間隔距離（即閘極電極結構切割距離）可小於或等於一個以上擴散鰭部節距的尺寸，或小於平均擴散鰭部節距的尺寸， l 相鄰配置的n型和p型擴散鰭部之間的縱向中心線間隔距離（如在垂直於擴散鰭部的方向上所測得）可定義為一個以上擴散鰭部節距的整數倍數，或為平均擴散鰭部節距的整數倍數。It should be understood that based on the circuit layout and the description provided herein, more than one of the following features may be used in several embodiments: • The distance between the ends of the diffusion fins that are co-aligned and adjacently configured (ie, the diffusion fins) The cutting distance can be smaller than the size of the gate electrode pitch. l The vertical partial interconnect structure can overlap a diffusing fin (which is horizontally oriented) on one edge (horizontally oriented edge) of the diffusing fin; In this case, a plurality of cuts (in a cut mask) for separating the vertical partial interconnect structures may be defined to contact or overlap with a diffuser fin, l a horizontal partial interconnect structure may be at the gate electrode An edge of the structure (vertically oriented edge) overlaps with a gate electrode structure (which is vertically oriented), and the size of the gate pole cover (ie, the distance of the gate electrode structure extending beyond the lower diffuser fin) may be less than one The size of the above diffusing fin pitch, or smaller than the average diffusing fin pitch, l the distance between the common alignment and the adjacently disposed gate electrode structure ends (ie, The gate electrode structure cutting distance) may be less than or equal to the size of more than one diffusing fin pitch, or smaller than the average diffusing fin pitch, l the longitudinal center between adjacently configured n-type and p-type diffusing fins The line spacing distance (as measured in a direction perpendicular to the diffusing fin) may be defined as an integer multiple of more than one diffusing fin pitch, or an integer multiple of the average diffusing fin pitch.
在一例示實施例中，半導體裝置包含一基板、一第一電晶體、及一第二電晶體。該第一電晶體具有在一第一擴散鰭部之內的一源極區域及一汲極區域。該第一擴散鰭部係建構成自該基板的一表面突出。該第一擴散鰭部係建構成自該第一擴散鰭部的一第一端部至該第一擴散鰭部的一第二端部在一第一方向上縱向延伸。該第二電晶體具有在一第二擴散鰭部之內的一源極區域及一汲極區域。該第二擴散鰭部係建構成自該基板的該表面突出。該第二擴散鰭部係建構成自該第二擴散鰭部的一第一端部至該第二擴散鰭部的一第二端部在該第一方向上縱向延伸。該第二擴散鰭部係配置成緊鄰該第一擴散鰭部且與該第一擴散鰭部分隔開。此外該第二擴散鰭部的該第一端部或該第二端部任一者係配置在該第一方向上介於該第一擴散鰭部的該第一端部和該第二端部之間。In an exemplary embodiment, a semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor has a source region and a drain region within a first diffusion fin. The first diffusion fin is configured to protrude from a surface of the substrate. The first diffusion fin is configured to extend longitudinally from a first end of the first diffusion fin to a second end of the first diffusion fin in a first direction. The second transistor has a source region and a drain region within a second diffusion fin. The second diffusing fin is configured to protrude from the surface of the substrate. The second diffusion fin is configured to extend longitudinally from the first end of the second diffusion fin to a second end of the second diffusion fin in the first direction. The second diffusion fin is disposed adjacent to the first diffusion fin and spaced apart from the first diffusion fin portion. In addition, the first end portion or the second end portion of the second diffusion fin portion is disposed in the first direction between the first end portion and the second end portion of the first diffusion fin portion between.
上述第一和第二電晶體可位於第二方向上的不同位置。此外，該第一和第二電晶體每一者可為三維閘控（gated）電晶體。The first and second transistors described above may be located at different locations in the second direction. Additionally, the first and second transistors can each be a three-dimensional gated transistor.
上述第一電晶體包含一第一線形閘極電極結構，當自該基板上方觀察，該第一線形閘極電極結構係在垂直於該第一方向的一第二方向上縱向延伸。上述第二電晶體包含一第二線形閘極電極結構，當自該基板上方觀察，該第二線形閘極電極結構係在垂直於該第一方向的該第二方向上縱向延伸。該第一擴散鰭部的該第一端部和第二端部其中至少一者可配置在第一方向上介於該第一和第二線形閘極電極結構之間。此外，該第二擴散鰭部的該第一和第二端部其中至少一者可配置在該第一方向上介於該第一和第二線形閘極電極結構之間。該第一線形閘極電極結構係配置成緊鄰該第二線形閘極電極結構且與該第二線形閘極電極結構分隔開。The first transistor includes a first linear gate electrode structure, and the first linear gate electrode structure extends longitudinally in a second direction perpendicular to the first direction when viewed from above the substrate. The second transistor includes a second linear gate electrode structure extending longitudinally in the second direction perpendicular to the first direction when viewed from above the substrate. At least one of the first end and the second end of the first diffusion fin may be disposed between the first and second linear gate electrode structures in a first direction. Additionally, at least one of the first and second ends of the second diffusion fin may be disposed between the first and second linear gate electrode structures in the first direction. The first linear gate electrode structure is disposed in close proximity to the second linear gate electrode structure and spaced apart from the second linear gate electrode structure.
該半導體裝置亦可包含一線形局部內連線結構，其在該第二方向上延伸且配置於該第一和第二線形閘極電極結構之間。該線形局部內連線結構可在該第一方向上位於該第一和第二線形閘極電極結構之間的實質上中心。該線形局部內連線結構可連接至該第一和第二擴散鰭部其中一者以上。The semiconductor device can also include a linear local interconnect structure extending in the second direction and disposed between the first and second linear gate electrode structures. The linear partial interconnect structure can be substantially centered between the first and second linear gate electrode structures in the first direction. The linear partial interconnect structure can be coupled to one of the first and second diffuser fins.
該半導體裝置亦可包含一線形局部內連線結構，其在該第一方向上延伸且配置於該第一和第二擴散鰭部之間。該線形局部內連線結構可在該第二方向上位於該第一和第二擴散鰭部之間的實質上中心。此外，此線形局部內連線結構可連接至該第一和第二閘極電極結構其中一者以上。The semiconductor device can also include a linear local interconnect structure extending in the first direction and disposed between the first and second diffusion fins. The linear partial interconnect structure can be substantially centered between the first and second diffuser fins in the second direction. Additionally, the linear local interconnect structure can be connected to one or more of the first and second gate electrode structures.
延伸於該第一方向的上述線形局部內連線結構，可稱作第一線形局部內連線結構。該半導體裝置亦可包含一第二線形局部內連線結構，其在該第二方向上延伸且配置於該第一和第二線形閘極電極結構之間。該第二線形局部內連線結構可在第一方向上位於該第一和第二線形閘極電極結構之間的實質上中心。此外，該第二線形局部內連線結構可連接至該第一擴散鰭部、該第二擴散鰭部其中一者以上。此外，在若干實施例中，該第一線形局部內連線結構可為一二維變化非線形局部內連線結構的一第一線形區段，並且該第二線形局部內連線結構可為該二維變化非線形局部內連線結構的一第二線形區段。此外，在若干實例中，該第一和第二線形局部內連線結構可彼此連接。The above-mentioned linear partial interconnect structure extending in the first direction may be referred to as a first linear partial interconnect structure. The semiconductor device can also include a second linear partial interconnect structure extending in the second direction and disposed between the first and second linear gate electrode structures. The second linear partial interconnect structure can be substantially centered between the first and second linear gate electrode structures in a first direction. In addition, the second linear partial interconnect structure may be connected to one of the first diffusion fin and the second diffusion fin. In addition, in some embodiments, the first linear partial interconnect structure may be a first linear segment of a two-dimensional varying nonlinear local interconnect structure, and the second linear partial interconnect structure may be A second linear segment of the non-linear partial interconnect structure is changed in two dimensions. Moreover, in several examples, the first and second linear partial interconnect structures can be connected to each other.
該半導體裝置亦可包含配置於該第一和第二擴散鰭部之間的接觸結構。在若干實施例中，該接觸結構可位於該第一和第二擴散鰭部之間的實質上中心。在若干實施例中，該接觸結構可連接至該第一閘極電極結構或該第二閘極電極結構任一者。The semiconductor device can also include a contact structure disposed between the first and second diffusion fins. In several embodiments, the contact structure can be located substantially centrally between the first and second diffusion fins. In some embodiments, the contact structure can be connected to either the first gate electrode structure or the second gate electrode structure.
該半導體裝置亦可包含配置於該第一和第二閘極電極結構之間的接觸結構。在若干實施例中，該接觸結構可位於該第一和第二閘極電極結構之間的實質上中心。此外，在若干實施例中，該半導體裝置可包含配置於該第二方向上第一和第二擴散鰭部之間的一傳導內連線結構，其中該接觸結構連接至該傳導內連線結構。在若干實施例中，該傳導內連線結構係非擴散鰭部之延伸於該第一方向上的一最低階層內連線結構。The semiconductor device can also include a contact structure disposed between the first and second gate electrode structures. In several embodiments, the contact structure can be located substantially centrally between the first and second gate electrode structures. Moreover, in some embodiments, the semiconductor device can include a conductive interconnect structure disposed between the first and second diffusion fins in the second direction, wherein the contact structure is coupled to the conductive interconnect structure . In some embodiments, the conductive interconnect structure is a lowest level interconnect structure extending in the first direction of the non-diffusing fin.
該半導體裝置亦可包含配置於該第一方向上介於第一和第二擴散鰭部之間的一傳導內連線結構，其中該接觸結構連接至一傳導內連線結構。在若干實施例中，該傳導內連線結構係較高階層的內連線結構。The semiconductor device can also include a conductive interconnect structure disposed between the first and second diffusion fins in the first direction, wherein the contact structure is coupled to a conductive interconnect structure. In several embodiments, the conductive interconnect structure is a higher level interconnect structure.
該半導體裝置亦可包含一個以上內連線結構，其中該一個以上內連線結構其中若干包含在該第一方向上延伸的一個以上內連線區段。在若干實施例中，延伸於該第一方向上的該一個以上內連線區段其中若干，係配置於該第一和第二擴散鰭部之間。此外，在若干實施例中，延伸於該第一方向上的該一個以上內連線區段其中若干，係配置於該第一擴散鰭部或該第二擴散鰭部任一者的上方。在若干實施例中，在該第一方向上延伸的該一個以上內連線區段，係依據一第二方向內連線節距而加以配置，該節距係在第二方向上該一個以上內連線區段的各自第一方向定向之中心線之間所測得。The semiconductor device can also include more than one interconnect structure, wherein a plurality of the one or more interconnect structures comprise more than one interconnect segment extending in the first direction. In some embodiments, a plurality of the one or more interconnecting segments extending in the first direction are disposed between the first and second diffusing fins. In addition, in some embodiments, a plurality of the one or more interconnecting segments extending in the first direction are disposed above the first diffusing fin or the second diffusing fin. In some embodiments, the one or more interconnecting segments extending in the first direction are configured according to a second direction interconnecting pitch, the pitch being more than one in the second direction. Measured between the centerlines of the respective first direction orientations of the interconnect segments.
在若干實施例中，該第一和第二擴散鰭部可依據一擴散鰭部節距而加以配置，該節距係在該第二方向上該第一和第二擴散鰭部的各自第一方向定向的中心線之間所測得，其中該第二方向內連線節距係該擴散鰭部節距的一有理數倍數，該有理數倍數係定義成整數的比例。In some embodiments, the first and second diffusion fins can be configured according to a diffusion fin pitch, wherein the pitch is the first of the first and second diffusion fins in the second direction Measured between the directionally oriented centerlines, wherein the second direction inner wiring pitch is a rational multiple of the diffusion fin pitch, and the rational multiple is defined as an integer ratio.
在若干實施例中，該第一和第二擴散鰭部每一者，係依據一第一擴散鰭部節距或一第二擴散鰭部節距任一者而加以中心線配置，該第一擴散鰭部節距係在第二方向上所測得，該第二擴散鰭部節距係在該第二方向上所測得，其中該第一和第二擴散節距在該第二方向上相繼地交替，且其中一平均擴散鰭部節距係該第一和第二擴散鰭部節距的平均，並且In some embodiments, each of the first and second diffusion fins is centered according to any one of a first diffusion fin pitch or a second diffusion fin pitch, the first The diffusion fin pitch is measured in a second direction, the second diffusion fin pitch being measured in the second direction, wherein the first and second diffusion pitches are in the second direction Alternatingly alternately, and wherein an average diffusing fin pitch is an average of the pitches of the first and second diffusing fins, and
其中該第二方向內連線節距係該平均擴散鰭部節距的一有理數倍數，該有理數倍數係定義為整數值的比例。在若干實施例中，該第一擴散鰭部節距係與該第二擴散鰭部節距相等。在若干實施例中，該第一擴散鰭部節距係與該第二擴散鰭部節距不同。The second direction inner wiring pitch is a rational multiple of the average diffusion fin pitch, and the rational multiple is defined as a ratio of integer values. In some embodiments, the first diffusion fin pitch is equal to the second diffusion fin pitch. In some embodiments, the first diffusion fin pitch is different from the second diffusion fin pitch.
以上提及的一個以上內連線結構可包含一局部內連線結構、一較高階層內連線結構、或其組合任一者，其中該局部內連線結構係非擴散鰭部的一最低階層內連線結構，且其中較高階層內連線結構係在相對於該基板之該局部內連線結構上方的一階層處所形成的一內連線結構。One or more of the interconnect structures mentioned above may comprise a partial interconnect structure, a higher level interconnect structure, or a combination thereof, wherein the local interconnect structure is a minimum of non-diffusing fins An intra-level interconnect structure, and wherein the higher-level interconnect structure is an interconnect structure formed at a level above the local interconnect structure of the substrate.
在若干實施例中，該第一和第二擴散鰭部每一者，係依據在該第二方向上所測得的一第一擴散鰭部節距、或在該第二方向上所測得的一第二擴散鰭部節距之任一者而加以中心線配置，其中該第一和第二擴散節距係相繼地在該第二方向上交替，且其中一平均擴散鰭部節距係該第一和第二擴散鰭部節距的平均。此外，延伸於該第一方向上的該一個以上內連線區段，可依據在該第二方向所測得的一第一內連線節距或在該第二方向上所測得的一第二內連線節距之任一者而加以中心線配置，其中該第一和第二內連線節距係相繼地在該第二方向上交替，且其中一平均內連線節距係該第一和第二內連線節距的平均。此外，該平均內連線節距係該平均擴散鰭部節距的一有理數倍數，該有理數倍數係定義成整數值的比例。In some embodiments, the first and second diffusion fins are each measured according to a first diffusion fin pitch measured in the second direction or in the second direction a centerline configuration of any one of the second diffusion fin pitches, wherein the first and second diffusion pitches are alternately alternated in the second direction, and wherein an average diffusion fin pitch system The average of the first and second diffusion fin pitches. In addition, the one or more interconnecting segments extending in the first direction may be based on a first interconnect pitch measured in the second direction or a measured one in the second direction a centerline configuration of any of the second interconnect pitches, wherein the first and second interconnect fringes alternate sequentially in the second direction, and wherein an average interconnect fringe is The average of the first and second interconnecting pitches. Moreover, the average interconnect pitch is a rational multiple of the average diffused fin pitch, and the rational multiple is defined as a ratio of integer values.
在若干實施例中，該第一擴散鰭部節距係與該第二擴散鰭部節距相等，且該第一內連線節距係與該第二內連線節距相等。在若干實施例中，該第一擴散鰭部節距係不同於該第二擴散鰭部節距，且該第一內連線節距係不同於該第二內連線節距。在若干實施例中，該第一擴散鰭部節距係與該第一內連線節距相等，且該第二擴散鰭部節距係與該第二內連線節距相等。In some embodiments, the first diffusion fin pitch is equal to the second diffusion fin pitch, and the first interconnect pitch is equal to the second interconnect pitch. In some embodiments, the first diffusion fin pitch is different from the second diffusion fin pitch, and the first interconnect pitch is different from the second interconnect pitch. In some embodiments, the first diffusion fin pitch is equal to the first interconnect pitch and the second diffusion fin pitch is equal to the second interconnect pitch.
該半導體裝置亦可包含一個以上內連線結構，其中該一個以上內連線結構其中若干包含在該第二方向上延伸的一個以上內連線區段。在若干實施例中，在該第二方向上延伸的該一個以上內連線區段其中若干係配置於該第一和第二閘極電極結構之間。在若干實施例中，在該第二方向上延伸的該一個以上內連線區段其中若干係位於該第一閘極電極結構或該第二閘極電極結構任一者的上方。The semiconductor device can also include more than one interconnect structure, wherein a plurality of the one or more interconnect structures comprise more than one interconnect segment extending in the second direction. In several embodiments, a plurality of the one or more interconnecting segments extending in the second direction are disposed between the first and second gate electrode structures. In some embodiments, a plurality of the one or more interconnecting segments extending in the second direction are above the first gate electrode structure or the second gate electrode structure.
在若干實施例中，在該第二方向上延伸的該一個以上內連線區段係根據一第一方向內連線節距而加以配置，該節距係在該第一方向上該一個以上內連線區段的各自第二方向定向的中心線之間所測得。此外，該第一和第二閘極電極結構可依據一閘極電極節距加以配置，該節距係在該第一方向上該第一和第二閘極電極結構的各自第二方向定向的中心線之間所測得。該第一方向內連線節距可為該閘極電極節距的有理數倍數，該有理數倍數係定義為整數值的比例。In some embodiments, the one or more interconnecting segments extending in the second direction are configured according to a first direction interconnecting pitch, the pitch being more than one in the first direction Measured between the centerlines of the respective second direction orientations of the interconnect segments. Furthermore, the first and second gate electrode structures can be configured according to a gate electrode pitch, the pitch being oriented in a respective second direction of the first and second gate electrode structures in the first direction Measured between the centerlines. The first direction inner wiring pitch may be a rational multiple of the gate electrode pitch, and the rational multiple is defined as a ratio of integer values.
以上提及的一個以上內連線結構可包含局部內連線結構、較高階層內連線結構、或其組合之任一者，其中該局部內連線結構係非擴散鰭部的一最低階層內連線結構，且其中較高階層內連線結構係一內連線結構，其在相對於該基板之該局部內連線結構上方的一階層處所形成。One or more of the interconnect structures mentioned above may comprise a local interconnect structure, a higher level interconnect structure, or a combination thereof, wherein the local interconnect structure is a lowest level of non-diffusing fins An interconnect structure, and wherein the higher level interconnect structure is an interconnect structure formed at a level above the local interconnect structure of the substrate.
在若干實施例中，該半導體裝置亦可包含一第一複數電晶體，其每一者具有藉由各自擴散鰭部所形成的一各自的源極區域和一各自的汲極區域。該第一複數電晶體的擴散鰭部每一者建構成自該基板的該表面突出。該第一複數電晶體的各擴散鰭部，係建構成自各自擴散鰭部的一第一端部至一第二端部在該第一方向上縱向延伸。該第一複數電晶體的該等擴散鰭部的該等第一端部係在該第一方向上實質上彼此對齊。In some embodiments, the semiconductor device can also include a first plurality of transistors each having a respective source region and a respective drain region formed by respective diffusion fins. The diffusion fins of the first plurality of transistors are each formed to protrude from the surface of the substrate. Each of the diffusion fins of the first plurality of transistors is configured to extend longitudinally from the first end to the second end of the respective diffusion fins in the first direction. The first ends of the diffusing fins of the first plurality of transistors are substantially aligned with one another in the first direction.
此外，該半導體裝置亦可包含第二複數電晶體，其每一者具有由各自擴散鰭部所形成的一各自的源極區域及一各自的汲極區域。該第二複數電晶體的各擴散鰭部係建構成自該基板的該表面突出。該第二複數電晶體的各擴散鰭部係建構成自各自擴散鰭部的一第一端部至一第二端部在第一方向上縱向延伸。該第二複數電晶體的該等擴散鰭部的該等第一端部係在該第一方向上實質上彼此對齊。並且，該第二複數電晶體的該等擴散鰭部的該等第一端部其中一者以上係配置成在該第一方向上介於該第一複數電晶體的該等擴散鰭部其中一者以上的該等第一和第二端部之間。In addition, the semiconductor device can also include a second plurality of transistors each having a respective source region formed by a respective diffusion fin and a respective drain region. Each of the diffusion fins of the second plurality of transistors is configured to protrude from the surface of the substrate. Each of the diffusion fins of the second plurality of transistors is configured to extend longitudinally from the first end to the second end of the respective diffusion fins in the first direction. The first ends of the diffusing fins of the second plurality of transistors are substantially aligned with one another in the first direction. And one or more of the first ends of the diffusion fins of the second plurality of transistors are disposed in the first direction between the diffusion fins of the first plurality of transistors Between the first and second ends of the above.
在若干實施例中，該第二複數電晶體的擴散鰭部的第一端部每一者，係配置在該第一方向上介於該第一複數電晶體的擴散鰭部其中一者以上的第一和第二端部之間。在若干實施例中，該第二複數電晶體的擴散鰭部其中至少一者係配置成與該第一複數電晶體的至少一擴散鰭部緊鄰且分隔開。此外，在若干實施例中，該第一複數電晶體可包含n型電晶體、p型電晶體、或n型及p型電晶體組合之任一者，且該第二複數電晶體可包含n型電晶體、p型電晶體、或n型及p型電晶體組合之任一者。在若干實施例中，該第一複數電晶體係n型電晶體，且該第二複數電晶體係p型電晶體。In some embodiments, the first ends of the diffusion fins of the second plurality of transistors are each disposed in the first direction between one or more of the diffusion fins of the first plurality of transistors. Between the first and second ends. In some embodiments, at least one of the diffusion fins of the second plurality of transistors is disposed in close proximity to and spaced apart from at least one of the diffusion fins of the first plurality of transistors. Moreover, in some embodiments, the first plurality of transistors may comprise any one of an n-type transistor, a p-type transistor, or a combination of n-type and p-type transistors, and the second plurality of transistors may comprise n Any of a combination of a type of transistor, a p-type transistor, or an n-type and p-type transistor. In some embodiments, the first plurality of electromorphic system n-type transistors, and the second plurality of electro-crystalline system p-type transistors.
在若干實施例中，該第一和第二複數擴散鰭部係配置成，使其各自的第一方向定向的中心線係與一擴散鰭部對準格柵（alignment grating）實質上對準，該擴散鰭部對準格柵係由在該第二方向上所測得的一第一擴散鰭部節距及在該第二方向所測得的一第二擴散鰭部節距加以定義。該第一和第二擴散鰭部節距係以交替的順序在該第二方向上出現。此外，在若干實施例中，該第一和第二複數電晶體的擴散鰭部係共同地占用擴散鰭部對準格柵的至少八個連貫的對準位置其中部分。In some embodiments, the first and second plurality of diffusing fins are configured such that their respective first direction oriented centerlines are substantially aligned with a diffuser fin alignment grating, The diffusion fin alignment grid is defined by a first diffusion fin pitch measured in the second direction and a second diffusion fin pitch measured in the second direction. The first and second diffusion fin pitches appear in the second direction in an alternating sequence. Moreover, in several embodiments, the diffusing fins of the first and second plurality of transistors collectively occupy portions of at least eight consecutive aligned positions of the diffusing fin alignment grid.
在例示實施例中，揭示一種製造半導體裝置的方法。該方法包含提供一基板。該方法亦包含在該基板上形成一第一電晶體，使得該第一電晶體在一第一擴散鰭部之內具有一源極區域和一汲極區域，且使得該第一擴散鰭部形成為自該基板的一表面突出，且使得該第一擴散鰭部自該第一擴散鰭部的一第一端部至該第一擴散鰭部的一第二端部在一第一方向上縱向延伸。該方法亦包含在該基板上形成一第二電晶體，使得該第二電晶體在一第二擴散鰭部之內具有一源極區域及一汲極區域，且使得該第二擴散鰭部係形成為自該基板的該表面突出，且使得該第二擴散鰭部係形成為在該第一方向上自該第二擴散鰭部的一第一端部至該第二擴散鰭部的一第二端部而縱向延伸，且使得該第二擴散鰭部係在與該第一擴散鰭部緊鄰且分隔開的位置處加以形成。此外，將該第一和第二電晶體形成，俾使該第二擴散鰭部的該第一端部或該第二端部任一者，係於在該第一方向上介於該第一擴散鰭部的該第一端部和該第二端部之間的位置處加以形成。In an exemplary embodiment, a method of fabricating a semiconductor device is disclosed. The method includes providing a substrate. The method also includes forming a first transistor on the substrate such that the first transistor has a source region and a drain region within a first diffusion fin, and the first diffusion fin is formed Projecting from a surface of the substrate, and causing the first diffusion fin to be longitudinally in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin extend. The method also includes forming a second transistor on the substrate such that the second transistor has a source region and a drain region within a second diffusion fin, and the second diffusion fin portion Forming to protrude from the surface of the substrate, and forming the second diffusion fin portion to be formed from a first end portion of the second diffusion fin portion to the second diffusion fin portion in the first direction The two ends extend longitudinally, and the second diffusion fins are formed at a position adjacent to and spaced apart from the first diffusion fins. In addition, the first and second transistors are formed such that the first end or the second end of the second diffusion fin is in the first direction A position between the first end portion and the second end portion of the diffusion fin is formed.
應理解的是，如此處所揭露包含鰭式場效電晶體的任何電路佈局可以一實體型式儲存，例如在一電腦可讀媒體上的數位格式。舉例來說，一特定的電路佈局可儲存於一佈局資料檔案，且係可選擇自一個以上元件庫。該佈局資料檔案可格式化為GDS II（圖形資料系統）資料庫檔案、OASIS（開放式原圖系統交換標準）資料庫檔案、或適用於儲存和傳播半導體裝置佈局的任何其他類型資料檔案格式。此外，如此處所揭露的包含鰭式場效電晶體的元件的多階層佈局，可被包含於較大半導體裝置的多階層佈局之內。該較大半導體裝置的多階層佈局亦可用例如以上所述的佈局資料檔案的型式加以儲存。It should be understood that any circuit layout including a fin field effect transistor as disclosed herein may be stored in a physical form, such as a digital format on a computer readable medium. For example, a particular circuit layout can be stored in a layout data file and can be selected from more than one component library. The layout data file can be formatted as a GDS II (Graphics Data System) database file, an OASIS (Open Original System Exchange Standard) database file, or any other type of data file format suitable for storing and distributing semiconductor device layouts. Moreover, the multi-level layout of the elements comprising fin field effect transistors as disclosed herein can be included within a multi-level layout of larger semiconductor devices. The multi-level layout of the larger semiconductor device can also be stored in a pattern such as the layout data file described above.
此外，此處所述發明可在電腦可讀媒體上具體化為電腦可讀碼。舉例來說，該電腦可讀碼可包含佈局資料檔案，其中儲存有如此處所揭示之包含鰭式場效電晶體的元件的佈局。電腦可讀碼亦可包含用於選擇如此處所揭示之包含鰭式場效電晶體的一個以上佈局庫及/或元件之程式指令。該佈局庫及/或元件亦可在電腦可讀媒體上以數位格式加以儲存。Moreover, the invention described herein can be embodied as a computer readable code on a computer readable medium. For example, the computer readable code can include a layout data file in which the layout of the components comprising the fin field effect transistor as disclosed herein is stored. The computer readable code can also include program instructions for selecting one or more layout libraries and/or components comprising a fin field effect transistor as disclosed herein. The layout library and/or components can also be stored in a digital format on a computer readable medium.
此處所提及之電腦可讀媒體係可儲存可由電腦系統之後讀出的資料之任何資料儲存裝置。電腦可讀媒體的範例包含硬碟、網路附接儲存器（NAS）、唯讀記憶體、隨機存取記憶體、CD-ROM、CD-R、CD-RW、磁帶、及其他光學和非光學資料儲存裝置。分布於連接之電腦系統的網路之內的多個電腦可讀媒體亦可用以儲存電腦可讀碼的各個部份，俾使該電腦可讀碼係在該網路之內以分散型式加以儲存和執行。A computer readable medium as referred to herein is any data storage device that stores data that can be read by a computer system. Examples of computer readable media include hard disk, network attached storage (NAS), read only memory, random access memory, CD-ROM, CD-R, CD-RW, magnetic tape, and other optical and non- Optical data storage device. A plurality of computer readable media distributed within the network of the connected computer system can also be used to store portions of the computer readable code such that the computer readable code is stored in a distributed manner within the network And execution.
在一例示實施例中，一資料儲存裝置具有用於提供半導體裝置佈局之儲存於其上的電腦可執行程式指令。該資料儲存裝置包含用於定義形成於一基板之上的一第一電晶體的電腦程式指令，俾使該第一電晶體定義成在一第一擴散鰭部之內具有一源極區域及一汲極區域，且俾使該第一擴散鰭部定義成自該基板的一表面突出，且俾使該第一擴散鰭部定義成在一第一方向自該第一擴散鰭部的一第一端部至該第一擴散鰭部的一第二端部而縱向延伸。該資料儲存裝置亦包含用於定義在該基板上形成一第二電晶體的電腦程式指令，俾使該第二電晶體定義成在一第二擴散鰭部之內具有一源極區域及一汲極區域，且俾使該第二擴散鰭部定義成自該基板的該表面突出，且俾使該第二擴散鰭部定義成在該第一方向上自該第二擴散鰭部的第一端部至該第二擴散鰭部的第二端部而縱向延伸，且俾使該第二擴散鰭部定義成與該第一擴散鰭部緊鄰且分隔開而加以配置，且俾使該第二擴散鰭部定義成使其第一端部或其第二端部配置成在該第一方向上介於該第一擴散鰭部的該第一端部和該第二端部之間。In an exemplary embodiment, a data storage device has computer executable program instructions stored thereon for providing a semiconductor device layout. The data storage device includes computer program instructions for defining a first transistor formed on a substrate, the first transistor being defined as having a source region and a source within a first diffusion fin a drain region, wherein the first diffusion fin is defined to protrude from a surface of the substrate, and the first diffusion fin is defined as a first from the first diffusion fin in a first direction The end portion extends longitudinally to a second end of the first diffusion fin. The data storage device also includes computer program instructions for defining a second transistor formed on the substrate, the second transistor being defined as having a source region and a drain within a second diffusion fin a pole region, and wherein the second diffusion fin is defined to protrude from the surface of the substrate, and the second diffusion fin is defined to be from the first end of the second diffusion fin in the first direction Extending longitudinally to the second end of the second diffusion fin, and defining the second diffusion fin to be disposed adjacent to and spaced apart from the first diffusion fin, and arranging the second The diffusion fin is defined such that its first end or its second end is disposed between the first end and the second end of the first diffusion fin in the first direction.
更應理解的是，如此處所揭露之包含鰭式場效電晶體的任何電路佈局可製造成一半導體裝置或晶片的部分。在例如積體電路、記憶體元件等等之半導體裝置的製造中，執行一系列的製造操作以定義半導體晶圓上的特徵部。該晶圓包含呈定義於一矽基板之上的多階層結構之型式的積體電路裝置。在一基板階層，形成具有擴散區域及/或擴散鰭部的電晶體裝置。在後續的階層，將內連線金屬線加以圖案化且電連接至電晶體裝置，以定義一期望的積體電路裝置。此外，圖案化傳導層係藉由介電材料與其他傳導層絕緣。 雖然這個發明已就數個實施例加以描述，吾人可明瞭，熟習此技藝者在研讀前述說明書和圖式後將了解其各種變化、附加、置換、及均等物。因此，本發明應包含落入本發明真實精神和範圍之內的所有此等變化、附加、置換、及均等物。It should be further understood that any circuit layout including a fin field effect transistor as disclosed herein can be fabricated as part of a semiconductor device or wafer. In the fabrication of semiconductor devices such as integrated circuits, memory devices, and the like, a series of fabrication operations are performed to define features on a semiconductor wafer. The wafer includes an integrated circuit device of a multi-level structure defined on a single substrate. At a substrate level, a transistor device having a diffusion region and/or a diffusion fin is formed. At subsequent levels, the interconnect metal lines are patterned and electrically connected to the transistor device to define a desired integrated circuit device. In addition, the patterned conductive layer is insulated from other conductive layers by a dielectric material. Although the invention has been described in terms of several embodiments, it will be understood by those skilled in the Accordingly, the present invention is intended to embrace all such modifications, alternatives,
100‧‧‧鰭式場效電晶體
102‧‧‧擴散鰭部
104‧‧‧閘極電極層
105‧‧‧基板
106‧‧‧閘極氧化物層
107‧‧‧核心部
109‧‧‧側間隔部
201A/201B‧‧‧擴散鰭部
203‧‧‧節距
205‧‧‧節距
207‧‧‧閘極電極結構
209‧‧‧閘極節距
211‧‧‧水平內連線結構
213‧‧‧垂直內連線結構
215‧‧‧met1內連線結構
215A/215B‧‧‧內連線結構
217‧‧‧接觸窗
219‧‧‧met2內連線結構
221‧‧‧介層窗結構
250‧‧‧橢圓
251‧‧‧橢圓
260‧‧‧圓
261‧‧‧圓
270‧‧‧箭頭
2001‧‧‧區域
2601及2603‧‧‧閘極電極結構
2605‧‧‧輸入連線
2607‧‧‧輸入連線
2701‧‧‧切割形狀部
2703及2705‧‧‧閘極導體
3105‧‧‧區域
3201‧‧‧圓
3301‧‧‧圓
70-1A至70-1E‧‧‧閘極電極軌道
70-3 ‧‧‧閘極電極節距
70-5A至70-5E‧‧‧通道
7001-7008‧‧‧閘極階層特徵
8001‧‧‧區域
8003‧‧‧擴散鰭部100‧‧‧Fin field effect transistor
102‧‧‧Diffuse fins
104‧‧‧gate electrode layer
105‧‧‧Substrate
106‧‧‧ gate oxide layer
107‧‧‧ Core Department
109‧‧‧ side spacer
201A/201B‧‧‧Diffuse fins
203‧‧ ‧ pitch
205‧‧ ‧ pitch
207‧‧‧gate electrode structure
209‧‧‧gate pitch
211‧‧‧ horizontal interconnect structure
213‧‧‧Vertical interconnect structure
215‧‧‧met1 interconnect structure
215A/215B‧‧‧Interconnection structure
217‧‧‧Contact window
219‧‧‧met2 interconnect structure
221‧‧‧Meso window structure
250‧‧‧ ellipse
251‧‧‧ ellipse
260‧‧‧ round
261‧‧‧ round
270‧‧‧ arrow
2001‧‧‧Area
2601 and 2603‧‧ ‧ gate electrode structure
2605‧‧‧Input connection
2607‧‧‧Input connection
2701‧‧‧cut shape department
2703 and 2705‧‧‧ gate conductors
3105‧‧‧Area
3201‧‧‧ Round
3301‧‧‧ Round
70-1A to 70-1E‧‧‧ gate electrode track
70-3 ‧‧‧gate electrode pitch
70-5A to 70-5E‧‧‧ channel
7001-7008‧‧‧The characteristics of the gate class
8001‧‧‧Area
8003‧‧‧Diffuse fins
根據本發明若干實施例，圖1A和1B顯示鰭式場效電晶體的例示佈局圖。1A and 1B show an exemplary layout of a fin field effect transistor, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖1C顯示圖1A/1B的鰭式場效電晶體的變形，其中在垂直剖面視圖A-A中擴散鰭部102係更為角椎形的。1C shows a variation of the fin field effect transistor of FIGS. 1A/1B, wherein the diffuser fins 102 are more angular in the vertical cross-sectional view A-A, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖1D顯示具有數個鰭式場效電晶體形成於其上的基板的簡化垂直剖面圖。1D shows a simplified vertical cross-sectional view of a substrate having a plurality of fin field effect transistors formed thereon, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖1E顯示鰭部節距關係的示圖，其中內鰭部節距Ps1係實質上等於外鰭部節距Ps2。1E shows a diagram of a fin pitch relationship in which the inner fin pitch Ps1 is substantially equal to the outer fin pitch Ps2, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖1F顯示圖1E的鰭部節距關係示圖的變化，其中有理數的分母（y）係二。In accordance with several embodiments of the present invention, FIG. 1F shows a variation of the fin pitch relationship diagram of FIG. 1E, wherein the denominator (y) of the rational number is two.
根據本發明若干實施例，圖1G顯示圖1E的鰭部節距關係示圖的變化，其中有理數的分母（y）係三。In accordance with several embodiments of the present invention, FIG. 1G shows a variation of the fin pitch relationship diagram of FIG. 1E, wherein the denominator (y) of the rational number is three.
根據本發明若干實施例，圖1Ｈ顯示圖1E的鰭部節距關係示圖的更廣義版本，其中內鰭部節距Ps1和外鰭部節距Ps2係不同。1H shows a broader version of the fin pitch relationship diagram of FIG. 1E, wherein the inner fin pitch Ps1 and the outer fin pitch Ps2 are different, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖2A顯示包含鰭式場效電晶體的例示元件佈局。2A shows an exemplary component layout including a fin field effect transistor, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖2B顯示對應圖2D的2輸入NAND配置的電路圖。2B shows a circuit diagram corresponding to the 2-input NAND configuration of FIG. 2D, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖2Ｃ顯示對應圖2Ｅ的2輸入NOR配置的電路圖。2C shows a circuit diagram corresponding to the 2-input NOR configuration of FIG. 2E, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖2D顯示圖2A的佈局，其中擴散鰭部201A係由n型擴散材料所形成，而擴散鰭部201B係由p型擴散材料所形成。2D shows the layout of FIG. 2A in which the diffusion fins 201A are formed of an n-type diffusion material and the diffusion fins 201B are formed of a p-type diffusion material, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖2E顯示圖2A的佈局，其中擴散鰭部201A係由p型擴散材料所形成，而擴散鰭部201B係由n型擴散材料所形成。2E shows the layout of FIG. 2A in which the diffusion fins 201A are formed of a p-type diffusion material and the diffusion fins 201B are formed of an n-type diffusion material, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖2F顯示圖2A的佈局的變形，其中閘極電極結構端部係在元件的頂部和元件的底部實質上對齊。。2F shows a variation of the layout of FIG. 2A in which the gate electrode structure ends are substantially aligned at the top of the component and the bottom of the component, in accordance with several embodiments of the present invention. .
根據本發明若干實施例，圖2G顯示圖2A佈局的變形，其中接觸窗係形成為在元件頂部和元件底部處於電源軌下方自met1內連線結構至水平局部內連線結構延伸。2G shows a variation of the layout of FIG. 2A in which the contact window is formed to extend from the metro interconnect structure to the horizontal local interconnect structure below the power rail at the top of the component and the bottom of the component.
根據本發明若干實施例，圖2H顯示圖2A元件的變形，其中使用二個不同的擴散鰭部節距。2H shows a variation of the element of FIG. 2A in which two different diffusion fin pitches are used, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖2I顯示圖2A佈局的變形，其中在元件頂部和底部處電源軌下方的擴散鰭部和水平局部內連線結構係延伸作為電源軌之met1內連線結構的全寬度。In accordance with several embodiments of the present invention, FIG. 2I shows a variation of the layout of FIG. 2A in which the diffusing fins and horizontal local interconnect structures below the power rails at the top and bottom of the component extend as a full line of the me1 interconnect structure of the power rail. width.
根據本發明若干實施例，圖3顯示圖2A的佈局的變形，其中met1電源軌係連接至垂直局部內連線，使得met1電源軌作為局部電源。3 shows a variation of the layout of FIG. 2A in which the met1 power rail is connected to a vertical local interconnect such that the met1 power rail acts as a local power source, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖4顯示圖2A佈局的變形，其中在元件之內使用二維變化的met1內連線結構以進行元件內繞線。In accordance with several embodiments of the present invention, FIG. 4 shows a variation of the layout of FIG. 2A in which a two-dimensionally varying met1 interconnect structure is used within the component for in-component winding.
根據本發明若干實施例，圖5顯示圖2A佈局的變形，其中met1電源軌係連接至垂直局部內連線，且其中在元件內使用二維變化met1內連線結構以進行元件內繞線。In accordance with several embodiments of the present invention, FIG. 5 shows a variation of the layout of FIG. 2A in which a met1 power rail is coupled to a vertical local interconnect, and wherein a two-dimensional varying met1 interconnect structure is used within the component for in-component routing.
根據本發明若干實施例，圖6顯示圖2A佈局的變形，其中使用固定、最小寬度、共用的局部met1電源，以及在元件內用於元件內繞線之二維變化met1內連線結構。In accordance with several embodiments of the present invention, FIG. 6 shows a variation of the layout of FIG. 2A in which a fixed, minimum width, shared local met1 power supply, and a two-dimensional change met1 interconnect structure for in-component windings within the component are used.
根據本發明若干實施例，圖7顯示圖2A佈局的變形，其具有於元件中具硬接線的共用的局部和全域電源，以及在元件內用於元件內繞線之二維變化met1內連線結構。In accordance with several embodiments of the present invention, FIG. 7 shows a variation of the layout of FIG. 2A with a shared local and global power supply with hardwired components in the component, and a two-dimensional variation of the inner winding of the component within the component. structure.
根據本發明若干實施例，圖8A顯示例示標準元件的佈局，其中將輸入接腳配置於相同類型的擴散鰭部之間以減輕繞線擁塞，且其中使用若干擴散鰭部作為內連線導體。8A shows a layout of a standard component in which input pins are disposed between diffusion fins of the same type to mitigate winding congestion, and in which a plurality of diffusion fins are used as interconnect conductors, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖8B顯示圖8A的變形，其中使用二個不同的閘極電極節距。8B shows a variation of FIG. 8A in which two different gate electrode pitches are used, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖8C顯示圖8A佈局的電路圖。Figure 8C shows a circuit diagram of the layout of Figure 8A, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖9A顯示例示標準元件佈局，其中使用擴散鰭部作為內連線導體。In accordance with several embodiments of the present invention, FIG. 9A shows an exemplary standard component layout in which a diffusion fin is used as an interconnect conductor.
根據本發明若干實施例，圖9B顯示圖9A的佈局，其中標示三組交叉連接的電晶體。。In accordance with several embodiments of the present invention, FIG. 9B shows the layout of FIG. 9A in which three sets of cross-connected transistors are labeled. .
根據本發明若干實施例，圖9C顯示圖9A佈局的電路圖。Figure 9C shows a circuit diagram of the layout of Figure 9A, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖10顯示例示標準元件佈局，其中將閘極電極接觸窗實質上配置於擴散鰭部上方。In accordance with several embodiments of the present invention, FIG. 10 shows an exemplary standard component layout in which a gate electrode contact window is disposed substantially above a diffusion fin.
根據本發明若干實施例，圖11顯示實現擴散鰭部的例示元件佈局。Figure 11 shows an exemplary component layout for implementing a diffusion fin, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖12A/B顯示具有最小寬度met1電源軌的圖11佈局的變形。In accordance with several embodiments of the present invention, FIG. 12A/B shows a variation of the layout of FIG. 11 with a minimum width met1 power rail.
根據本發明若干實施例，圖13A/B顯示圖12A/B佈局的變形，其不具有自各個局部內連線和閘極電極結構至met1的接觸窗。In accordance with several embodiments of the present invention, FIGS. 13A/B show a variation of the layout of FIG. 12A/B that does not have contact windows from respective local interconnect and gate electrode structures to met1.
根據本發明若干實施例，圖14A/B顯示圖11佈局的變形，其具有最小寬度met1電源軌，且包含電源軌之所有met1結構具相同的寬度和相同的節距。In accordance with several embodiments of the present invention, FIGS. 14A/B show a variation of the layout of FIG. 11 with a minimum width met1 power rail and all of the met1 structures including the power rail have the same width and the same pitch.
根據本發明若干實施例，圖15A/B顯示圖14A/B佈局的變形，其具有met1繞線結構，該繞線結構配置成各（y）位置具有一met1結構。15A/B shows a variation of the layout of FIG. 14A/B having a met1 winding structure configured such that each (y) position has a met1 structure, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖16A/B顯示圖11佈局的變形，其具有配置於p型擴散鰭部之間的閘極電極結構接觸窗。16A/B shows a variation of the layout of FIG. 11 having a gate electrode structure contact window disposed between p-type diffusion fins, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖17A/B顯示實現擴散鰭部的例示元件佈局。In accordance with several embodiments of the present invention, Figures 17A/B show an exemplary component layout that implements a diffusion fin.
根據本發明若干實施例，圖18A/B顯示圖17A/B佈局的變形，其中接觸窗連接至水平局部內連線，且其中水平局部內連線直接連接至垂直局部內連線。18A/B shows a variation of the layout of FIG. 17A/B, wherein the contact window is connected to a horizontal partial interconnect, and wherein the horizontal partial interconnect is directly connected to the vertical partial interconnect.
根據本發明若干實施例，圖19A/B顯示圖17A/B佈局的變形，其中至局部內連線的電源軌接觸窗係不共用的，且其中在電源軌下方沒有共用的局部內連線。19A/B shows a variation of the layout of FIG. 17A/B in which the power rail contact window to the local interconnect is not shared, and wherein there is no common local interconnect below the power rail.
根據本發明若干實施例，圖20A/B顯示圖19A/Ｂ佈局的變形，其中擴散鰭部係相對於元件邊界偏移半個擴散鰭部節距。20A/B shows a variation of the layout of FIG. 19A/B in which the diffusing fins are offset by a half of the diffusing fin pitch relative to the element boundary, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖21A/B顯示圖20A/B佈局的變形，其具有最小寬度電源軌及擴散鰭部之負垂直局部內連線重疊。21A/B shows a variation of the layout of FIG. 20A/B with a negative width local interconnect and a negative vertical local interconnect overlap of the diffuser fins, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖22A/B顯示圖17A/B佈局的變形，其具有最小寬度電源軌、在電源軌下方不共用的局部內連線及擴散鰭部、及p鰭部和n鰭部之間較大的間距。22A/B shows a variation of the layout of FIG. 17A/B with a minimum width power rail, local interconnects and diffuser fins that are not shared under the power rail, and p-fin and n-fins, in accordance with several embodiments of the present invention. Large spacing between the sections.
根據本發明若干實施例，圖23A/B顯示圖17A/B佈局的變形。23A/B shows a variation of the layout of Fig. 17A/B, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖24A/B顯示圖23A/B佈局的變形。24A/B shows a variation of the layout of Fig. 23A/B, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖25A/B顯示圖23A/B佈局的變形，其中元件在高度上加倍。25A/B shows a variation of the layout of Fig. 23A/B in which the elements are doubled in height, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖26A/B顯示實現擴散鰭部的例示元件佈局。In accordance with several embodiments of the present invention, Figures 26A/B show an exemplary component layout that implements a diffusion fin.
根據本發明若干實施例，圖27A/B顯示圖26A/B佈局的變形。27A/B shows a variation of the layout of Fig. 26A/B, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖28A/B顯示實現擴散鰭部的例示元件佈局。In accordance with several embodiments of the present invention, FIG. 28A/B shows an exemplary component layout that implements a diffusion fin.
根據本發明若干實施例，圖29A/B顯示圖28A/B佈局的變形，其中在兩個n型電晶體的閘極電極結構之間沒有局部內連線結構。In accordance with several embodiments of the present invention, FIGS. 29A/B show a variation of the layout of FIG. 28A/B in which there is no local interconnect structure between the gate electrode structures of the two n-type transistors.
根據本發明若干實施例，圖30A/B顯示實現擴散鰭部的例示元件佈局。30A/B shows an exemplary component layout that implements a diffusion fin, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖31A顯示例示sdff元件佈局，其中閘極電極和局部內連線線端間隙位於擴散鰭部之間的實質上中心。31A shows an sdff component layout in which the gate electrode and the local interconnect line end gap are located substantially at the center between the diffuser fins, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖31B顯示圖31A的例示sdff元件佈局，其中將位在擴散鰭部之間的實質上中心的局部內連線線端間隙圈出。31B shows an exemplary sdff element layout of FIG. 31A in which a substantially central partial interconnect line end gap between the diffuser fins is circled, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖31C顯示具有兩個相鄰閘極電極結構之間的區域之標註的圖31A和31B的例示sdff元件佈局，其中擴散鰭部端部在x方向彼此重疊。31C shows an exemplary sdff element layout of FIGS. 31A and 31B with an annotation of a region between two adjacent gate electrode structures, wherein the diffusion fin ends overlap each other in the x direction, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖32顯示一例示佈局，其中所有將所有接觸層結構配置於擴散鰭部之間。In accordance with several embodiments of the present invention, FIG. 32 shows an exemplary layout in which all of the contact layer structures are disposed between the diffusion fins.
根據本發明若干實施例，圖33和34顯示例示佈局，其中將所有接觸層結構配置於擴散鰭部之上。33 and 34 show an exemplary layout in which all contact layer structures are disposed over the diffusion fins, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖35A/B至47A/B顯示在邏輯路徑二者上具有傳輸閘極的交叉連接電晶體配置，其需要所有內部節點具有p型和n型之間的連接。35A/B through 47A/B show a cross-connect transistor configuration with transmission gates on both logical paths that require all internal nodes to have a connection between p-type and n-type, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖35C顯示圖35A/B至47A/B及63A/B至67A/B的佈局的電路圖。35C shows a circuit diagram of the layout of FIGS. 35A/B to 47A/B and 63A/B to 67A/B, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖48A/B至57A/B顯示交叉連接電晶體配置，其中具有使用較大電晶體之在邏輯路徑上的傳輸閘極，以及在其他路徑上的三態閘極。48A/B through 57A/B show a cross-connect transistor configuration with a transmission gate on a logic path using a larger transistor and a three-state gate on other paths, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖48C顯示圖48A/B至58A/B的佈局的電路圖。Figure 48C shows a circuit diagram of the layout of Figures 48A/B through 58A/B, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖58A/B至59A/B顯示交叉連接電晶體配置，其中具有利用較小電晶體之在邏輯路徑上的傳輸閘極，以及在其他路徑上的三態閘極。In accordance with several embodiments of the present invention, FIGS. 58A/B through 59A/B illustrate a cross-connect transistor configuration with a transmission gate on a logic path utilizing a smaller transistor, and a three-state gate on other paths.
根據本發明若干實施例，圖59C顯示圖59A/B的佈局的電路圖。Figure 59C shows a circuit diagram of the layout of Figure 59A/B, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖60A/B至62A/B顯示具有在邏輯路徑二者上之三態閘極的交叉連接電晶體配置。60A/B through 62A/B show a cross-connect transistor configuration with three-state gates on both logical paths, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖60C顯示圖60A/B至62A/B及圖68A/B至69A/B的佈局的電路圖。Figure 60C shows a circuit diagram of the layout of Figures 60A/B to 62A/B and Figures 68A/B to 69A/B, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖63A/B至67A/B顯示在邏輯路徑二者上具有傳輸閘極的交叉連接電晶體配置，其需要所有內部節點具有p型和n型之間的連接。。In accordance with several embodiments of the present invention, Figures 63A/B through 67A/B show a cross-connect transistor configuration with transmission gates on both logical paths that require all internal nodes to have a connection between p-type and n-type. .
根據本發明若干實施例，圖68A/B至69A/B顯示在邏輯路徑二者上具有三態閘極的交叉連接電晶體配置。In accordance with several embodiments of the present invention, FIGS. 68A/B through 69A/B show cross-connect transistor configurations having tri-state gates on both logical paths.
根據本發明若干實施例，圖70A顯示在受限制的閘極階層佈局結構之內所定義的閘極電極軌道70-1A至70-1E的範例。Figure 70A shows an example of gate electrode tracks 70-1A through 70-1E defined within a restricted gate level layout structure, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖70B顯示圖70A的例示受限制的閘極階層佈局結構，其具有數個例示閘極階層特徵7001-7008定義於其中。Figure 70B shows an exemplary restricted gate level layout structure of Figure 70A having a plurality of exemplary gate level features 7001-7008 defined therein, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖71A/B至77A/B顯示數個例示SDFF電路佈局，其利用基於傳輸和三態閘極二者的交叉連接電路結構。In accordance with several embodiments of the present invention, FIGS. 71A/B through 77A/B show several exemplary SDFF circuit layouts that utilize a cross-connect circuit structure based on both transmission and tri-state gates.
根據本發明若干實施例，圖71C顯示圖71A/B及77A/B的佈局的電路圖。Figure 71C shows a circuit diagram of the layout of Figures 71A/B and 77A/B, in accordance with several embodiments of the present invention.
根據本發明若干實施例，圖72C顯示圖72A/B至76A/B的佈局的電路圖。Figure 72C shows a circuit diagram of the layout of Figures 72A/B through 76A/B, in accordance with several embodiments of the present invention.
201A/201B‧‧‧擴散鰭部 201A/201B‧‧‧Diffuse fins
203‧‧‧節距 203‧‧ ‧ pitch
207‧‧‧閘極電極結構 207‧‧‧gate electrode structure
209‧‧‧閘極節距 209‧‧‧gate pitch
211‧‧‧水平內連線結構 211‧‧‧ horizontal interconnect structure
213‧‧‧垂直內連線結構 213‧‧‧Vertical interconnect structure
215‧‧‧met1內連線結構 215‧‧‧met1 interconnect structure
217‧‧‧接觸窗 217‧‧‧Contact window
221‧‧‧介層窗結構 221‧‧‧Meso window structure
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- 2013-01-13 SG SG11201404024YA patent/SG11201404024YA/en unknown
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| TW201717355A (en) | 2017-05-16 |
| SG10201605564WA (en) | 2016-09-29 |
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| EP2803077A4 (en) | 2015-11-04 |
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| SG11201404024YA (en) | 2014-08-28 |
| JP2015506589A (en) | 2015-03-02 |
| AU2018200549A1 (en) | 2018-02-15 |
| CN104303263B (en) | 2016-12-14 |
| TW201349451A (en) | 2013-12-01 |
| JP2019054297A (en) | 2019-04-04 |
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