TWI565037B - 含絕緣體上覆矽基材之嵌入式記憶體裝置,及其製作方法 - Google Patents
含絕緣體上覆矽基材之嵌入式記憶體裝置,及其製作方法 Download PDFInfo
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Description
本發明係關於嵌入式非揮發性記憶體裝置。
在塊體矽半導體基材上形成非揮發性記憶體裝置已為人所熟知。例如,美國專利第6,747310號、第7,868,375號及第7,927,994號揭示在塊體半導體基材上形成記憶體單元,記憶體單元含有四個閘(浮動閘、控制閘、選擇閘及抹除閘)。源極區及汲極區作為擴散植入區而形成至基材中,從而在基材中在其等之間界定一通道區。浮動閘係設置在通道區之一第一部分上方且控制通道區之第一部分,選擇閘係設置在通道區之一第二部分上方且控制通道區之第二部分,控制閘係設置在浮動閘上方,且抹除閘係設置在源極區上方。塊體基材對於這些類型記憶體裝置而言為理想的,此係因為深擴散至基材中可用於形成源極區及汲極區接面。為了所有目的,這三個專利以引用之方式併入本文中。
絕緣體上覆矽(SOI)裝置在微電子領域中已為人所熟知。SOI裝置與塊體矽基材裝置差異在於,基材經分
層,其中在矽表面下方為一嵌入式絕緣層(即,矽-絕緣體-矽),而非純粹為矽。運用SOI裝置,在經設置在嵌入於矽基材中之電絕緣體上方之薄矽層中形成矽接面。該絕緣體典型為二氧化矽(氧化物)。此基材組態減少寄生裝置電容,藉此改良效能。可藉由SIMOX(藉由使用氧離子束植入來植入氧進行分離,請參閱美國專利第5,888,297號及第5,061,642號)、晶圓接合(接合經氧化之矽與一第二基材,且移除大部分第二基材,請參閱美國專利第4,771,016號),或加晶種(直接在絕緣體上方生長最上層矽層,請參閱美國專利第5,417,180號),來製造SOI基材。為了所有目的,這四個專利以引用之方式併入本文中。
已知核心邏輯裝置(諸如高電壓裝置、輸入/輸出裝置及/或類比裝置)係形成在與非揮發性記憶體裝置(即,一般稱為嵌入式記憶體裝置)相同之基材上。隨著裝置幾何形狀持續縮減,這些核心邏輯裝置可大幅受益於SOI基材之優點。然而,非揮發性記憶體裝置並不利於SOI基材。有需要結合在SOI基材上形成之核心邏輯裝置與在塊體基材上形成之記憶體裝置之優點。
一種半導體裝置包含一矽基材,該矽基材具有一第一區域及一第二區域,該基材在該第一區域中包含一埋入式絕緣層且在該絕緣層上方及下方含有矽,該基材在該第二區域中不具有設置在任何矽下方之埋入式絕緣體。邏輯裝置係形成在該第一區域中,其中該等邏輯裝置之各者
包含:間隔分離之源極區及汲極區,其等形成在該絕緣層上方之該矽中;及一傳導閘,其形成在位於該絕緣層上方且介於該等源極區與汲極區之間之該矽之一部分上方且與其絕緣。記憶體單元係形成在該第二區域中,其中該等記憶體單元之各者包含:間隔分離之第二源極區及第二汲極區,其等形成在該基材中且在其等之間界定一通道區;一浮動閘,其經設置於該通道區之一第一部分上方且與其絕緣;及一選擇閘,其經設置於該通道區之一第二部分上方且與其絕緣。
一種形成一半導體裝置之方法包含:提供一矽基材,其包含一埋入式絕緣層且在該絕緣層上方及下方含有矽;自該基材之一第二區域移除該埋入式絕緣層,同時保持該基材之一第一區域中之該埋入式絕緣層;在該基材之該第一區域中形成邏輯裝置,其中該等邏輯裝置之各者包含間隔分離之源極區及汲極區以及一傳導閘,該等源極區及汲極區係形成在該絕緣層上方之該矽中,該傳導閘係形成在位於該絕緣層上方且介於該等源極區與汲極區之間之該矽之一部分上方且與其絕緣;及在該基材之該第二區域中形成記憶體單元,其中該等記憶體單元之各者包含間隔分離之第二源極區及第二汲極區、一浮動閘以及一選擇閘,該等第二源極區及汲極區係形成在該基材中且在其等之間界定一通道區,該浮動閘係形成於該通道區之一第一部分上方且與其絕緣,該選擇閘係形成於該通道區之一第二部分上方且與其絕緣。
【0001】本發明的其他目的與特徵將藉由檢視說明書、申請專利範圍與隨附圖式而變得顯而易見。
10‧‧‧SOI基材
10a‧‧‧矽;基材
10b‧‧‧絕緣材料層;絕緣體層;氧化物
10c‧‧‧矽;矽層
12‧‧‧第一絕緣材料層;氧化物
14‧‧‧第二絕緣材料層;氮化物
16‧‧‧渠溝
18‧‧‧絕緣材料
20‧‧‧核心邏輯區域
22‧‧‧記憶體區域
24‧‧‧渠溝
26‧‧‧氧化物層;氧化物
28‧‧‧絕緣層
30‧‧‧光阻
32‧‧‧氧化物層
34‧‧‧多晶矽層;多晶矽;浮動閘
36‧‧‧絕緣層;氧化物
38‧‧‧控制閘
40‧‧‧硬遮罩材料
42‧‧‧源極擴散;源極區;源極
44‧‧‧選擇閘
46‧‧‧抹除閘
47‧‧‧通道區
48‧‧‧汲極擴散;汲極區;汲極
49‧‧‧記憶體單元
50‧‧‧絕緣層
52‧‧‧光阻
56‧‧‧多晶矽層
56a‧‧‧多晶矽區塊
58‧‧‧源極擴散區;源極區
60‧‧‧汲極擴散區;汲極區
62‧‧‧邏輯裝置
圖1至圖9為依序繪示用以製造本發明之嵌入式記憶體裝置所執行之處理步驟之橫剖面側視圖。
圖10A為繪示用以製造本發明之嵌入式記憶體裝置所執行之下一處理步驟之橫剖面側視圖。
圖10B為對於結構之記憶體區域而言正交於圖10A之橫剖面側視圖的橫剖面側視圖。
圖11至圖14為依序繪示用以製造本發明之嵌入式記憶體裝置所執行之下一處理步驟之橫剖面側視圖。
圖15為對於結構之核心邏輯區域及記憶體區域而言正交於圖14之橫剖面側視圖的橫剖面側視圖。
本發明係一種嵌入式記憶體裝置,其具有在SOI基材上形成在核心邏輯裝置旁之非揮發性記憶體單元。自其中形成非揮發性記憶體的SOI基材之記憶體區域,移除嵌入式絕緣體。在SOI基材上形成嵌入式記憶體裝置之程序係開始於提供一SOI基材10,如圖1中所繪示。該SOI基材包含三個部分:矽10a;一絕緣材料層10b(例如,氧化物),其位在矽10a上方;及一矽薄層10c,其位在絕緣體層10b上方。SOI基材之形成在此項技術中已為人所熟知,如上文所描述且在上文美國專利中指出,且因此本文中未進一步描述。
在矽10c上形成一第一絕緣材料層12,諸如二氧化矽(氧化物)。可例如藉由氧化或藉由沉積(例如,化學氣相沉積(CVD))來形成層12。在層12上形成一第二絕緣材料層14,諸如氮化矽(氮化物)。執行微影程序,其包含:在氮化物14上形成一光阻材料,後續接著使用一光學遮罩選擇性地使該光阻材料曝光,後續接著選擇性地移除該光阻材料之部分以曝露氮化物層14之部分。微影術在此項技術中已為人所熟知。接著在彼等曝露區域中執行一連串蝕刻以移除氮化物14、氧化物12、矽10c、氧化物10b及矽10a(即,氮化物蝕刻以曝露氧化物12,氧化物蝕刻以曝露矽10c,矽蝕刻以曝露氧化物10b,氧化物蝕刻以曝露矽10a,及一矽蝕刻)而形成渠溝16,渠溝16向下延伸穿過層14、12、10c、10b且至矽10a中。移除光阻材料後,藉由氧化物沉積及氧化物蝕刻(例如,化學機械拋光(CMP),其使用氮化物14作為蝕刻停止),用一絕緣材料18(例如,氧化物)填充渠溝16,從而導致圖2中所示之結構。絕緣材料18充當基材10之核心邏輯區域20及記憶體區域22兩者之隔離區。
接下來執行氮化物蝕刻以移除氮化物14。執行微影程序以在結構上方形成光阻,後續接著遮罩步驟,在遮罩步驟中自記憶體區域22移除光阻,但不自結構之核心邏輯區域20移除光阻。執行一連串蝕刻以移除經曝露之記憶體區域22中的氧化物12、矽10c及氧化物10b(即,在氧化物18之間形成向下延伸至矽10a的渠溝24)。接著移除光阻,導致圖3之結構。接著執行選擇性磊晶矽生長程序(即,
在矽10a上),以在記憶體區域22中之渠溝24中形成矽最多至核心邏輯區域20中之矽層10c之位準,如圖4中所繪示。基本上,此矽生長程序使矽10a延伸最多至矽層10c之位準。因此,自記憶體區域22有效移除SOI基材10之嵌入式氧化物10b,同時使嵌入式氧化物10b保持在核心邏輯區域20中。
從現在開始,核心邏輯裝置可形成在核心邏輯區域20中之矽層10c上,且記憶體裝置可形成在記憶體區域22中之矽10a上。接下來描述從圖4中之結構開始,形成例示性核心邏輯裝置及記憶體裝置之步驟。使用氧化物沉積或氧化步驟以在基材10a上形成氧化物層26。在結構上方(即,在氧化物12、18及26上)形成一絕緣層28(諸如氮化物),如圖5中所繪示。接著在整個結構上方沉積光阻30,後續接著微影程序,微影程序移除記憶體區域22中的光阻30,並且使光阻30保留在核心邏輯區域20中。接著使用氮化物蝕刻(例如,各向同性氮化物蝕刻)移除記憶體區域22中的經曝露之氮化物28。所得結構係如圖6所示。
移除光阻30後,使用氧化物蝕刻以自記憶體區域22移除氧化物26,如圖7中所示。氧化物蝕刻亦減小記憶體區域22中之氧化物18之高度。接著使用氧化物形成步驟(例如,氧化)在記憶體區域22中之基材10a上形成氧化物層32(此將係在其上形成浮動閘之氧化物),如圖8中所示。在結構上方形成多晶矽,後續接著多晶矽移除(例如,CMP),而在核心邏輯區域20及記憶體區域22兩者中留下多晶矽層
34。較佳地,但非必要,記憶體區域22中之多晶矽34及氧化物18之頂部表面為共面(即,使用氧化物18作為多晶矽移除之蝕刻停止)。所得結構係如圖9所示。
接下來執行一連串處理步驟以完成在記憶體區域22中形成記憶體單元,這在此項技術中已為人所熟知。具體而言,多晶矽34形成浮動閘。在多晶矽34上方形成一絕緣層36(例如,氧化物)。在氧化物36上形成一傳導控制閘38,及在控制閘38上方形成一硬遮罩材料40(例如,氮化物、氧化物及氮化物之一複合層)。在基材10a中形成一源極擴散42至浮動閘之一側。在浮動閘34之另一側上方形成一選擇閘44且選擇閘44與基材10a絕緣。在源極區42上方形成一抹除閘46。在相鄰於選擇閘44之基材10a中形成一汲極擴散48。源極區42及汲極區48在其等之間界定一通道區47,其中浮動閘34經設置在通道區47之一第一部分上方且控制通道區47之第一部分,且選擇閘44經設置在通道區47之一第二部分上方且控制通道區47之第二部分。形成這些記憶體單元在此項技術中已為人所熟知(請參閱美國專利第6,747310號、第7,868,375號及第7,927,994號,該等案以引用之方式併入本文中)且本文中未進一步描述。所得結構係如圖10A及圖10B所示(圖10B之視圖正交於一記憶體單元49形成在記憶體區域22中之圖10A之視圖)。記憶體單元49具有一浮動閘34、控制閘38、源極區42、選擇閘44、抹除閘46及汲極區48。記憶體單元處理步驟結束於自核心邏輯區域20移除多晶矽34,及在氮化物層28上方加上一絕
緣層50(例如,高溫氧化物層(HTO)),如圖10A中所繪示。
在結構上方形成光阻52,及使用微影程序僅自核心邏輯區域20移除光阻52。執行氧化物蝕刻及氮化物蝕刻以自核心邏輯區域20移除氧化物層50及氮化物層28,如圖11中所繪示。執行氧化物蝕刻(例如,乾式及濕式)以自核心邏輯區域20移除氧化物層12(此亦移除至氧化物18之頂部)。接著移除光阻52,導致圖12中繪示之結構。在經曝露之矽層10c上形成一薄絕緣層(例如,經由氧化之氧化物),其將為核心邏輯裝置之閘極氧化物。接著在結構上形成一多晶矽層56,如圖13中所繪示。使用微影程序以在多晶矽層56上形成光阻區塊(該等光阻區塊設置在氧化物18上方),後續接著多晶矽蝕刻程序,此程序在核心邏輯區域20中留下多晶矽區塊56a,如圖14中所繪示。多晶矽區塊56a在區域20中形成核心邏輯裝置之邏輯閘。在薄矽層10c中形成適合之源極及汲極擴散區58及60以完成邏輯裝置62,如圖15中所繪示(圖15之視圖正交於圖14之視圖)。
上文描述之製造程序在同一SOI基材上形成記憶體單元49及核心邏輯裝置,其中自記憶體區域22有效移除SOI基材10之嵌入式絕緣體層10b。此組態允許記憶體單元之源極區42及汲極區48延伸入基材中之深度更深於核心邏輯區域20中的源極區58及汲極區60(即,源極42/汲極48可延伸之深度可更深於矽層10c之厚度,且因此更深於核心邏輯區域中之絕緣層10b之頂部表面,並且甚至可能更深於核心邏輯區域中之絕緣層10b之底部表面)。
應了解,本發明不受限於本文上述提及與描述的實施例,而是其涵蓋屬於隨附申請專利範圍之範疇內的任何及所有變化例。例如,本文中對本發明的引述並非意欲用以限制任何申請專利範圍或申請專利範圍術語之範疇,而僅是用以對可由申請專利範圍中一或多項所涵蓋的一或多種技術特徵作出引述。上述之材料、製程及數值之實例僅為例示之用,且不應視為對申請專利範圍之限制。再者,如從申請專利範圍及說明書可明白,並非所有方法步驟皆須完全依照所說明或主張的順序執行,而是可以任意的順序來執行,只要是可適當地形成本發明之記憶體單元區域及核心邏輯區域即可。除上文描述及圖式中繪示之閘外,記憶體單元49可包含額外或較少閘。最後,單層的材料可被形成為多層的此種或相似材料,且反之亦然。
應注意的是,如本文中所使用,「在...上方(over)」及「在...之上(on)」之用語皆含括性地包括了「直接在...之上」(無居中的材料、元件或間隔設置於其間)及「間接在...之上」(有居中的材料、元件或間隔設置於其間)的含意。同樣地,用語「相鄰」包括「直接相鄰」(二者之間無設置任何中間材料、元件或間隔)和「間接相鄰」(二者之間設置有中間材料、元件或間隔)。例如,「在一基材上方」形成一元件可包括直接在基材上形成元件而其間無居中的材料/元件存在,以及間接在基材上形成元件而其間有一或多個居中的材料/元件存在。
10‧‧‧SOI基材
10a‧‧‧矽;基材
10b‧‧‧絕緣材料層;絕緣體層;氧化物
10c‧‧‧矽;矽層
18‧‧‧絕緣材料
20‧‧‧核心邏輯區域
22‧‧‧記憶體區域
34‧‧‧多晶矽層;多晶矽;浮動閘
38‧‧‧控制閘
40‧‧‧硬遮罩材料
42‧‧‧源極擴散;源極區;源極
44‧‧‧選擇閘
46‧‧‧抹除閘
47‧‧‧通道區
48‧‧‧汲極擴散;汲極區;汲極
49‧‧‧記憶體單元
56a‧‧‧多晶矽區塊
58‧‧‧源極擴散區;源極區
60‧‧‧汲極擴散區;汲極區
62‧‧‧邏輯裝置
Claims (20)
- 一種半導體裝置,其包括:一矽基材,其具有一第一區域及一第二區域,該基材在該第一區域中包含一埋入式絕緣層且在該絕緣層上方及下方含有矽,該基材在該第二區域中不具有設置在任何矽下方之埋入式絕緣體;邏輯裝置,其等形成在該第一區域中,其中該等邏輯裝置之各者包括:間隔分離之源極區及汲極區,其等形成位在該絕緣層上方之該矽中,以及一傳導閘,其形成在位於該絕緣層上方且介於該等源極區與汲極區之間之該矽之一部分上方且與其絕緣;記憶體單元,其等形成在該第二區域中,其中該等記憶體單元之各者包括:間隔分離之第二源極區及第二汲極區,其等形成在該基材中且在其等之間界定一通道區,一浮動閘,其經設置於該通道區之一第一部分上方且與其絕緣,以及一選擇閘,其經設置於該通道區之一第二部分上方且與其絕緣。
- 如請求項1之半導體裝置,其中經形成在該第二區域中之該等第二源極區及汲極區所延伸至該基材中之深度 更深於經形成在該第一區域中之該等源極區及汲極區所延伸至該基材中之深度。
- 如請求項2之半導體裝置,其中經形成在該第二區域中之該等第二源極區及汲極區所延伸至該基材中之深度更深於經設置在該第一區域中之該埋入式絕緣層上方之該矽之一厚度。
- 如請求項2之半導體裝置,其中經形成在該第二區域中之該等第二源極區及汲極區所延伸至該基材中之深度更深於在該第一區域中之該埋入式絕緣層之一頂部表面的一深度。
- 如請求項2之半導體裝置,其中經形成在該第二區域中之該等第二源極區及汲極區所延伸至該基材中之深度更深於在該第一區域中之該埋入式絕緣層之一底部表面的一深度。
- 如請求項1之半導體裝置,其中該等記憶體單元之各者進一步包含:一控制閘,其經設置於該浮動閘上方且與其絕緣;以及一抹除閘,其經設置於該源極區上方且與其絕緣。
- 如請求項1之半導體裝置,其中該基材之該第一區域進一步包含:隔離區,各隔離區係由絕緣材料所形成,該絕緣材料延伸穿過位在該埋入式絕緣層上方之該矽、穿過該埋入式絕緣層、且至位在該埋入式絕緣層下方之該矽中。
- 如請求項7之半導體裝置,其中該基材之該第二區域進一步包含:第二隔離區,各第二隔離區係由延伸至該矽基材中之絕緣材料所形成。
- 一種形成一半導體裝置之方法,其包含:提供一矽基材,其包含一埋入式絕緣層且在該絕緣層上方及下方含有矽;自該基材之一第二區域移除該埋入式絕緣層,同時保持在該基材之一第一區域中之該埋入式絕緣層;在該基材之該第一區域中形成邏輯裝置,其中該等邏輯裝置之各者包含:間隔分離之源極區及汲極區,其等形成在位在該絕緣層上方之該矽中,以及一傳導閘,其形成在位於該絕緣層上方且介於該等源極區與汲極區之間之該矽之一部分上方且與其絕緣;在該基材之該第二區域中形成記憶體單元,其中該等記憶體單元之各者包括:間隔分離之第二源極區及第二汲極區,其等形成在該基材中且在其等之間界定一通道區,一浮動閘,其形成於該通道區之一第一部分上方且與其絕緣,以及一選擇閘,其形成於該通道區之一第二部分上方且與其絕緣。
- 如請求項9之方法,其中該移除在該基材之該第二區域中之該埋入式絕緣層包括:移除在該第二區域中之該埋入式絕緣層上方之該矽;移除在該第二區域中之該埋入式絕緣層;以及在該基材上在該埋入式絕緣層及矽被移除之處生長矽。
- 如請求項9之方法,其中經形成在該第二區域中之該等第二源極區及汲極區所延伸至該基材中之深度更深於經形成在該第一區域中之該等源極區及汲極區所延伸至該基材中之深度。
- 如請求項11之方法,其中經形成在該第二區域中之該等第二源極區及汲極區所延伸至該基材中之深度更深於經設置在該第一區域中之該埋入式絕緣層上方之該矽之一厚度。
- 如請求項11之方法,其中經形成在該第二區域中之該等第二源極區及汲極區所延伸至該基材中之深度更深於在該第一區域中之該埋入式絕緣層之一頂部表面的一深度。
- 如請求項11之方法,其中經形成在該第二區域中之該等第二源極區及汲極區所延伸至該基材中之深度更深於在該第一區域中之該埋入式絕緣層之一底部表面的一深度。
- 如請求項9之方法,其中該等記憶體單元之各者進一步包含:一控制閘,其形成於該浮動閘上方且與其絕緣;以及一抹除閘,其形成於該源極區上方且與其絕緣。
- 如請求項9之方法,其進一步包含:在該第一區域中形成隔離區,各隔離區包括絕緣材料,該絕緣材料延伸穿過位在該埋入式絕緣層上方之該矽、穿過該埋入式絕緣層、且至位在該埋入式絕緣層下方之該矽中。
- 如請求項16之方法,其進一步包含:在該第二區域中形成第二隔離區,各第二隔離區包括延伸至該矽基材中之第二絕緣材料。
- 如請求項17之方法,其中在該自該基材之該第二區域移除該埋入式絕緣層前,執行該形成該等隔離區及該形成該等第二隔離區。
- 如請求項18之方法,其中該在該第一區域中形成該等隔離區包含:形成渠溝,其等延伸穿過位在該埋入式絕緣層上方之該矽、穿過該埋入式絕緣層、且至位在該埋入式絕緣層下方之該矽中;以及用該絕緣材料填充該等渠溝。
- 如請求項19之方法,其中該在該第二區域中形成該等第二隔離區包含: 形成第二渠溝,其等延伸至該矽基材中;以及用該第二絕緣材料填充該等第二渠溝。
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PCT/US2015/015503 WO2015142440A1 (en) | 2014-03-17 | 2015-02-11 | Embedded memory device on bulk/soi hybrid substrate, and method of making same |
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US20160211250A1 (en) * | 2015-01-15 | 2016-07-21 | Infineon Technologies Ag | Semiconductor substrate arrangement, a semiconductor device, and a method for processing a semiconductor substrate |
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US9673208B2 (en) * | 2015-10-12 | 2017-06-06 | Silicon Storage Technology, Inc. | Method of forming memory array and logic devices |
US9754951B2 (en) * | 2015-10-30 | 2017-09-05 | Globalfoundries Inc. | Semiconductor device with a memory device and a high-K metal gate transistor |
CN107305892B (zh) * | 2016-04-20 | 2020-10-02 | 硅存储技术公司 | 使用两个多晶硅沉积步骤来形成三栅极非易失性闪存单元对的方法 |
CN107425003B (zh) | 2016-05-18 | 2020-07-14 | 硅存储技术公司 | 制造***栅非易失性闪存单元的方法 |
US10541205B1 (en) * | 2017-02-14 | 2020-01-21 | Intel Corporation | Manufacture of interconnects for integration of multiple integrated circuits |
US10879256B2 (en) * | 2017-11-22 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Embedded memory using SOI structures and methods |
CN108461514A (zh) * | 2018-03-28 | 2018-08-28 | 德淮半导体有限公司 | Cmos图形传感器的隔离结构及其形成方法 |
US10790292B2 (en) * | 2018-05-14 | 2020-09-29 | Silicon Storage Technology, Inc. | Method of making embedded memory device with silicon-on-insulator substrate |
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