TWI503928B - 半導體封裝件及其製法與中介板結構 - Google Patents

半導體封裝件及其製法與中介板結構 Download PDF

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TWI503928B
TWI503928B TW101132953A TW101132953A TWI503928B TW I503928 B TWI503928 B TW I503928B TW 101132953 A TW101132953 A TW 101132953A TW 101132953 A TW101132953 A TW 101132953A TW I503928 B TWI503928 B TW I503928B
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interposer
encapsulant
conductive
semiconductor package
semiconductor
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TW101132953A
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TW201411782A (zh
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莊冠緯
林畯棠
廖怡茜
賴顗喆
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矽品精密工業股份有限公司
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Priority to TW101132953A priority Critical patent/TWI503928B/zh
Priority to CN201210356327.3A priority patent/CN103681528B/zh
Priority to US13/722,017 priority patent/US9257381B2/en
Publication of TW201411782A publication Critical patent/TW201411782A/zh
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Publication of TWI503928B publication Critical patent/TWI503928B/zh
Priority to US14/986,903 priority patent/US9548220B2/en

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Description

半導體封裝件及其製法與中介板結構
本發明係有關一種半導體封裝件，尤指一種具矽穿孔之半導體封裝件及其製法與中介板結構。
在現行之覆晶技術因具有縮小晶片封裝面積及縮短訊號傳輸路徑等優點，目前已經廣泛應用於晶片封裝領域，例如，晶片尺寸構裝(Chip Scale Package,CSP)、晶片直接貼附封裝(Direct Chip Attached,DCA)以及多晶片模組封裝(Multi-Chip Module,MCM)等型態的封裝模組，均可利用覆晶技術而達到封裝的目的。
於覆晶封裝製程中，因晶片與封裝基板之熱膨脹係數的差異甚大，故晶片外圍的凸塊無法與封裝基板上對應的接點形成良好的接合，使得凸塊易自封裝基板上剝離。另一方面，隨著積體電路之積集度的增加，因晶片與封裝基板之間的熱膨脹係數不匹配(mismatch)，其所產生的熱應力(thermal stress)與翹曲(warpage)的現象也日漸嚴重，其結果將導致晶片與封裝基板之間的可靠度(reliability)下降，並造成信賴性測試失敗。
為了解決上述問題，遂發展出以半導體基材作為中介結構的製程，係於一封裝基板與一半導體晶片之間增設一矽中介板(Silicon interposer)。因該矽中介板與該半導體晶片的材質接近，故可有效避免熱膨脹係數不匹配所產生的問題。
第1A至1C圖係為習知半導體封裝件1之製法。
如第1A圖所示，係於一整片矽中介板10中形成複數導電矽穿孔(Through-silicon via,TSV)100，再於該矽中介板10之上側形成線路重佈結構(圖略)，以將半導體晶片11接置於該矽中介板10之上側，且藉由導電凸塊110電性連接該導電矽穿孔100。
如第1B圖所示，形成封裝膠體12於該矽中介板10上以包覆該半導體晶片11，俾形成複數封裝體1a。
如第1C圖所示，於該矽中介板10之下側依需求形成線路重佈結構(Redistribution layer,RDL)13，再進行切單製程，以將單一封裝體1a藉由複數導電凸塊14接置且電性連接於該封裝基板15。
惟，習知半導體封裝件1之製法中，該矽中介板10形成該導電矽穿孔100之製作成本極高，且該矽中介板10之每一矽中介板單元10’因製程良率之故，往往存在有良好者與不良者。故當半導體晶圓切割成半導體晶片11(該半導體晶片11之製造成本亦高)後，再經電性量測後，可選擇好的半導體晶片11接置於該矽中介板10上所對應之矽中介板單元10’上。因此，好的半導體晶片11可能會接置於不良之矽中介板單元10’上，導致於後續測試封裝體1a後，需將好的半導體晶片11與供其接置之不良矽中介板單元10’一併報廢，而令製造該矽中介板10模組之成本無法降低。
再者，若於形成該封裝膠體12之前即已發現不良之 矽中介板單元10’，而不放置好的半導體晶片11於不良之矽中介板單元10’上，則該矽中介板10上將出現空位，致將無法控制該封裝膠體12之膠量，且因空位之位置並非可預期，將無法藉由程式控制該封裝膠體12之流動路徑，亦即該封裝膠體12之流動路徑不一致，遂令無法均勻覆蓋該半導體晶片11。
又，將半導體晶片11置放於未經切割之一整片矽中介板10上，該半導體晶片11之尺寸面積會受到限制，亦即該半導體晶片11之尺寸面積需小於該矽中介板單元10’之尺寸面積，故該半導體晶片11之電極(即結合導電凸塊110處)之數量無法增加，導致該矽中介板單元10’之模組功能及效率等受到限制。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件，係包括：第一封裝膠體；中介板，係嵌埋於該第一封裝膠體中，且該中介板具有相對之第一表面與第二表面及連接該第一與第二表面之側面，並具有連通該第一與第二表面之複數導電穿孔，該導電穿孔具有相對之第一端面與第二端面，令該導電穿孔之第一端面對應該第一表面，且令該中介板之側面上覆蓋有該第一封裝膠體；以及至少一半導體元件，係設於該中介板之第一表面之上並電性連接該中介板。
本發明復提供一種半導體封裝件之製法，係包括：提供一具有相對之第一表面與第二表面之基材，該基材中具有連通該第一表面之複數導電穿孔，該導電穿孔具有相對之第一端面與第二端面，令該導電穿孔之第一端面對應該第一表面；切割該基材以形成複數中介板，各該中介板具有連接該第一與第二表面之側面；將各該中介板以其第一表面置於一承載件上，且該承載件具有複數開口，以令各該中介板分別對應置於各該開口中，又任二該開口之間具有間隔；形成第一封裝膠體於該承載件上，以令該第一封裝膠體形成於該中介板之側面上並包覆該些中介板；移除該承載件；以及結合至少一半導體元件於該中介板之第一表面之上，且電性連接該中介板。
前述之製法中，該中介板之第一表面上具有複數導電元件，以令該導電元件位於該開口中，且該些導電元件電性連接該導電穿孔之第一端面。於移除該承載件後，該半導體元件係結合於該些導電元件上，且電性連接該些導電元件。
前述之製法中，復包括形成黏著材料於該承載件之開口中，以將該中介板結合至該承載件。
前述之製法中，復包括於接置該半導體元件於該中介板之製程後，進行切割製程，以形成複數半導體封裝件。
前述之半導體封裝件及其製法中，該中介板之第一表面上具有線路重佈結構，以電性連接該導電穿孔之第一端面，且該半導體元件係結合至該線路重佈結構並電性連接 該線路重佈結構。
前述之半導體封裝件及其製法中，復包括當移除該承載件之前或之後，形成線路重佈結構於該中介板之第二表面上，且該線路重佈結構係電性連接該導電穿孔之第二端面。
前述之半導體封裝件及其製法中，該半導體元件與該中介板之導電穿孔之第一端面係藉由複數導電元件作電性連接。
前述之半導體封裝件及其製法中，於移除該承載件後，該些導電元件係凸出該第一封裝膠體之表面。
前述之半導體封裝件及其製法中，復包括形成第二封裝膠體於該第一封裝膠體上，以包覆該半導體元件。
前述之半導體封裝件及其製法中，復包括移除該第二封裝膠體之部分材質，以外露該半導體元件未接置該中介板之一側。
另外，前述之半導體封裝件及其製法中，復包括移除該中介板之第二表面之部分材質，以外露該導電穿孔之第二端面。
本發明又提供一種中介板結構，係包括：封裝膠體；以及中介板，係嵌埋於該封裝膠體中，且該中介板具有相對之第一表面與第二表面及連接該第一與第二表面之側面，並具有連通該第一與第二表面之複數導電穿孔，該導電穿孔具有相對之第一端面與第二端面，令該導電穿孔之第一端面對應該第一表面，且令該中介板之側面上覆蓋有 該封裝膠體。
前述之中介板結構中，該中介板之第一表面與該封裝膠體之表面齊平。
前述之中介板結構中，該封裝膠體係覆蓋該中介板之第二表面與該導電穿孔之第二端面。
前述之中介板結構中，該中介板之第二表面與該導電穿孔之第二端面係外露於該封裝膠體。
前述之中介板結構中，該中介板之第二表面、該導電穿孔之第二端面與該封裝膠體之表面齊平。
前述之中介板結構中，復包括線路重佈結構，係形成於該中介板之第一表面上，且電性連接該導電穿孔之第一端面。亦包括導電元件，係形成於該線路重佈結構上並凸出該封裝膠體之表面。再者，該線路重佈結構之位置係與該封裝膠體之表面位置齊高。
前述之中介板結構中，復包括導電元件，係形成於該中介板之第一表面上並凸出該封裝膠體之表面。
另外，前述之中介板結構中，復包括線路重佈結構，係形成於該中介板之第二表面上，且電性連接該導電穿孔之第二端面。
由上可知，本發明之半導體封裝件及其製法與中介板結構，係藉由先切割該基材，以選擇良好之中介板重新排設於該承載件之開口上，再將好的半導體元件接置於良好之中介板，以避免習知技術之一併報廢之問題，故可降低該中介板之生產成本。
再者，於該承載件之各該開口上重新排設該些中介板，可令該些中介板之間的間隔大於該基材上之中介板的間隔，故可接置尺寸面積大於中介板之半導體元件於重新排設之該些中介板上，亦即半導體元件之尺寸面積不致受限。因此，該半導體元件之電極之數量能依需求增加，以提升該中介板之模組功能及效率。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2H圖係為本發明之半導體封裝件2之製法之第一實施例的剖面示意圖。
如第2A及2A’圖所示，提供一具有相對之第一表面20a 與第二表面20b之基材20，該基材20中具有連通該第一表面20a之複數導電穿孔200，該導電穿孔200具有相對之第一端面200a與第二端面200b，令該導電穿孔200之第一端面200a外露於該基材20之第一表面20a。
於本實施例中，該基材20係為晶圓或其它含矽之板材，且於該基材20之第一表面20a上可依需求形成線路重佈結構(RDL)201，以電性連接該導電穿孔200之第一端面200a。
再者，該線路重佈結構201上具有複數導電元件202，且該些導電元件202可直接或藉由該線路重佈結構201電性連接該導電穿孔200之第一端面200a。
又，該導電元件202係為表面具有銲錫材料之金屬凸塊，如銅凸塊。
如第2B圖所示，沿切割路徑S(如第2A及2A’圖所示)切割該基材20，以形成複數中介板20’，使各該中介板20’具有連接該第一與第二表面20a,20b之側面20c。
接著，將各該中介板20’以其該第一表面20a朝向一承載件3之開口30而置放於該開口30上，該承載件3具有複數開口30，且任二該開口30之間具有間隔D。
於本實施例中，該間隔D之寬度係大於該切割路徑S之寬度t。
再者，該些導電元件202係位於該開口30中，且藉由形成於該承載件3之開口30中的黏著材料31，使該些導電元件202嵌入該黏著材料31中並結合該黏著材料31 中，以固定該中介板20’。
又，有關中介板與承載件之結合方式繁多，並不限於上述。
另外，該導電元件202係為凸塊或柱體，但並無特別限制。
如第2C圖所示，形成第一封裝膠體22於該承載件3上，以形成封裝體2a，該第一封裝膠體22係覆蓋該中介板20’之側面20c並包覆該些中介板20’。
如第2D圖所示，移除該承載件3，以令該些導電元件202凸出該第一封裝膠體22之表面。
如第2E圖所示，結合一個或多個半導體元件21於各該中介板20’之第一表面20a上方。
於本實施例中，該半導體元件21係為晶片，且具有相對之主動面21a與非主動面21b，而該半導體元件21以其主動面21a接置於該些導電元件202上，使該半導體元件21藉由該些導電元件202電性連接該中介板20’之線路重佈結構201(或導電穿孔200之第一端面200a)。
於另一實施例中，所述之導電元件202亦可設於該半導體元件21上，而不先設於該線路重佈結構201上，當移除該承載件3之後，再將該半導體元件21藉由導電元件202設於該中介板20’之第一表面20a上方。
另外，該半導體元件21亦可以其主動面21a直接接置於該中介板20’之第一表面20a上或該線路重佈結構201上，而不需形成該導電元件202。
如第2F圖所示，形成第二封裝膠體23於該第一封裝膠體22上，以包覆該半導體元件21與該些導電元件202上。
於本實施例中，係藉由研磨方式，移除該第二封裝膠體23上側之部分材質，使該半導體元件21之非主動面21b與該第二封裝膠體23上側表面齊平，以外露該半導體元件21之非主動面21b。
再者，移除該第二封裝膠體23上側之部分材質可視需求而進行，並無特別限制。
又，該半導體元件21之非主動面21b外露於該第二封裝膠體23上側，可供散熱之用。
如第2G圖所示，移除該中介板20’之第二表面20b與該第一封裝膠體22下側之部分材質，使該中介板20’之第二表面20b’、該第一封裝膠體22下側表面與該導電穿孔200之第二端面200b齊平，以外露該導電穿孔200之第二端面200b。
再者，移除該中介板20’之第二表面20b與該第一封裝膠體22下側之部分材質，均可視需求而進行，並無特別限制。
如第2H圖所示，形成線路重佈結構(RDL)24於該第一封裝膠體22下側與該中介板20’之第二表面20b’上，且該線路重佈結構24電性連接該導電穿孔200之第二端面200b。
接著，可形成如銲球之導電元件25於該線路重佈結 構24上，以於切割製程後，接置如封裝基板(圖略)或電路板(圖略)之電子裝置(圖略)。
之後，沿切割路徑L(如第2H圖所示)，即對應該間隔D處，進行切割製程，以形成複數半導體封裝件2。
於本實施例中，該線路重佈結構24之態樣繁多，可依需求製作，故不詳述。
再者，切割路徑亦可依需求而定，並不限於上述。
第3A及3C圖係為本發明之半導體封裝件2’之製法之第二實施例中。本實施例與第一實施例之差異在於未形成該第二封裝膠體23，其它製程大致相同，故不再贅述。
如第3A圖所示，係接續第2D圖所示之製程，可依需求以保護膜(圖略)覆蓋該些導電元件202，且藉由研磨方式移除該中介板20’之第二表面20b與該第一封裝膠體22之部分材質，以外露該導電穿孔200之第二端面200b，使該中介板20’之第二表面20b’、該第一封裝膠體22下側表面與該導電穿孔200之第二端面200b齊平。
如第3B圖所示，形成該線路重佈結構(RDL)24，再移除該保護膜，以結合該半導體元件21。
如第3C圖所示，形成該導電元件25，且進行切割製程。
於另一方式中，係為接續第2C圖所示之製程。如第3A’圖所示，先移除該中介板20’之第二表面20b與該第一封裝膠體22之部分材質，再形成該線路重佈結構(RDL)24與該些導電元件25。接著，如第3B’圖所示，移除該該 承載件3，再結合該半導體元件21。之後，進行切割製程，以形成如第3C圖所示之結構。
本發明之製法乃藉由先切割該基材20，選擇良好之中介板20’重新排設，再將好的半導體元件21接置於良好之中介板20’，以避免習知技術之一併報廢之問題，並能降低半導體封裝件2之製造成本。
再者，藉由該承載件3之開口30重新排設該些中介板20’，不僅利於對位，且因該些中介板20’之間的間隔D大於該基材20上之中介板20’的間隔(即該切割路徑S之寬度t，且該寬度t極小)，而使該半導體元件21之尺寸面積較不受限，亦即該半導體元件21之尺寸面積可大於該中介板20’之尺寸面積。因此，該半導體元件21之電極(即結合導電元件202處)之數量能依需求增加，以提升該中介板20’之模組功能及效率。
本發明復提供一種半導體封裝件2,2’，其包括：第一封裝膠體22、嵌埋於該第一封裝膠體22中之一中介板20’、以及設於該第一封裝膠體22上之一半導體元件21。
所述之中介板20’係具有相對之第一表面20a與第二表面20b’及連接該第一與第二表面20a,20b’之側面20c，該中介板20’中並具有連通該第一與第二表面20a,20b’之複數導電穿孔200，該導電穿孔200具有相對之第一端面200a與第二端面200b，令該導電穿孔200之第一端面200a外露於該第一表面20a，且令該中介板20’之側面20c上覆蓋有該第一封裝膠體22。
所述之半導體元件21係具有相對之主動面21a與非主動面21b，並以其主動面21a設置並電性連接於該中介板20’之第一表面20a。
所述之半導體封裝件2復包括第二封裝膠體23，係形成於該第一封裝膠體22上，以包覆該半導體元件21，且該半導體元件21之非主動面21b係外露於該第二封裝膠體23。
所述之半導體封裝件2,2’復包括線路重佈結構24，係形成於該第一封裝膠體22與中介板20’之第二表面20b’上，且該線路重佈結構24電性連接該導電穿孔200之第二端面200b。
所述之半導體封裝件2,2’復包括線路重佈結構201，係形成於該半導體元件21與中介板20’之第一表面20a之間，且該線路重佈結構201電性連接該導電穿孔200之第一端面200a。
於一實施例中，該中介板20’之第一表面20a藉由複數導電元件202電性連接該導電穿孔200之第一端面200a與該半導體元件21之主動面21a，且該些導電元件202凸出該第一封裝膠體22之表面。
於一實施例中，該中介板20’之第二表面20b’與該導電穿孔200之第二端面200b係外露於該第一封裝膠體22。
第4A至4C圖係為本發明之中介板結構4,4’,4”，其包括封裝膠體42,42’、以及嵌埋於該封裝膠體42,42’中之一中介板40。
所述之中介板40係具有相對之第一表面40a與第二表面40b及連接該第一與第二表面40a,40b之側面40c，該中介板40中並具有連通該第一與第二表面40a,40b之複數導電穿孔400，該導電穿孔400具有相對之第一端面400a與第二端面400b，令該導電穿孔400之第一端面400a外露於該第一表面40a。
所述之封裝膠體42,42’係覆蓋該中介板40之側面40c。
所述之中介板結構4,4’,4”復包括一線路重佈結構401，係形成於該中介板40之第一表面40a上，且電性連接該導電穿孔400之第一端面400a。
所述之中介板結構4,4’,4”復包括導電元件402，係形成於該中介板40之第一表面40a上並凸出該封裝膠體42,42’之表面。於本實施例中，該些導電元件402係形成於該線路重佈結構401上。
於本實施例中，該線路重佈結構401之位置係與該封裝膠體42之表面位置齊高，如第4A圖所示。於另一實施例中，若該中介板40之第一表面40a上未形成有該線路重佈結構401，則該中介板40之第一表面40a係與該封裝膠體42之表面齊平。另外，如第4B及4C圖所示，該封裝膠體42’亦可覆蓋該線路重佈結構401(或該中介板40之第一表面40a與該導電穿孔400之第一端面400a)。
於一實施例中，如第4A圖所示，該封裝膠體42係覆蓋該中介板40之第二表面40b與該導電穿孔400之第二端 面400b。
於一實施例中，如第4B圖所示，該中介板40之第二表面40b與該導電穿孔400之第二端面400b係外露於該封裝膠體42’，例如，該中介板40之第二表面40b、該導電穿孔400之第二端面400b與該封裝膠體42’之下表面齊平。因此，如第4C圖所示，該中介板結構4”復包括另一線路重佈結構44，係形成於該中介板40之第二表面40b與該封裝膠體42’上，且電性連接該導電穿孔400之第二端面400b。
另外，有關該中介板結構4,4’,4”之材質或構成可參考上述第2A至2H圖之說明，於此不再贅述。
綜上所述，本發明之半導體封裝件及其製法與中介板結構，主要藉由先切割該基材，以選擇良好之中介板重新排設於該承載件之開口上，再將好的半導體元件接置於良好之中介板，以避免好的半導體元件接置於不良的中介板上，故能避免於封裝後好的半導體元件需報廢之問題。
再者，於該承載件之開口上重新排設該些中介板，使該些中介板之間的間隔大於未切割前該基材上之中介板的間隔，故能使用尺寸面積大於該中介板之半導體元件。因此，該半導體元件之電極之數量能依需求增加，以提升該中介板之模組功能及效率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2,2’‧‧‧半導體封裝件
1a,2a‧‧‧封裝體
10‧‧‧矽中介板
10’‧‧‧矽中介板單元
100‧‧‧導電矽穿孔
11‧‧‧半導體晶片
110,14‧‧‧導電凸塊
12,42,42’‧‧‧封裝膠體
13,201,24,401,44‧‧‧線路重佈結構
15‧‧‧封裝基板
20‧‧‧基材
20’,40‧‧‧中介板
20a,40a‧‧‧第一表面
20b,20b’,40b‧‧‧第二表面
20c,40c‧‧‧側面
200,400‧‧‧導電穿孔
200a,400a‧‧‧第一端面
200b,400b‧‧‧第二端面
202,25,402‧‧‧導電元件
21‧‧‧半導體元件
21a‧‧‧主動面
21b‧‧‧非主動面
22‧‧‧第一封裝膠體
23‧‧‧第二封裝膠體
3‧‧‧承載件
30‧‧‧開口
31‧‧‧黏著材料
4,4’,4”‧‧‧中介板結構
D‧‧‧間隔
S,L‧‧‧切割路徑
t‧‧‧寬度
第1A至1C圖係為習知半導體封裝件之製法之剖視示意圖；第2A至2H圖係為本發明之半導體封裝件之製法之第一實施例的剖視示意圖；其中，第2A’圖係為第2A圖之上視圖；第3A至3C圖係為本發明之半導體封裝件之製法之第二實施例的剖視示意圖；其中，第3A’至3B’圖係為第3A至3B圖之另一方式；以及第4A至4C圖係為本發明之中介板結構之不同實施例的剖視示意圖。
2‧‧‧半導體封裝件
20’‧‧‧中介板
20a‧‧‧第一表面
20b’‧‧‧第二表面
20c‧‧‧側面
200‧‧‧導電穿孔
200a‧‧‧第一端面
200b‧‧‧第二端面
201‧‧‧線路重佈結構
202‧‧‧導電元件
21‧‧‧半導體元件
22‧‧‧第一封裝膠體
23‧‧‧第二封裝膠體
24‧‧‧線路重佈結構
25‧‧‧導電元件

Claims (19)

  1. 一種半導體封裝件，係包括：第一封裝膠體；中介板，係嵌埋於該第一封裝膠體中，且該中介板具有相對之第一表面與第二表面及連接該第一與第二表面之側面，並具有連通該第一與第二表面之複數導電穿孔，該導電穿孔具有相對之第一端面與第二端面，令該導電穿孔之第一端面對應該第一表面，且令該中介板之側面上覆蓋有該第一封裝膠體；以及至少一半導體元件，係設於該中介板之第一表面之上並電性連接該中介板，且該半導體元件之各表面上均未形成有封裝膠體。
  2. 一種半導體封裝件，係包括：第一封裝膠體；中介板，係嵌埋於該第一封裝膠體中，且該中介板具有相對之第一表面與第二表面及連接該第一與第二表面之側面，並具有連通該第一與第二表面之複數導電穿孔，該導電穿孔具有相對之第一端面與第二端面，令該導電穿孔之第一端面對應該第一表面，且令該中介板之側面上覆蓋有該第一封裝膠體；至少一半導體元件，係設於該中介板之第一表面之上並電性連接該中介板；以及第二封裝膠體，係形成於該第一封裝膠體上，以包覆該半導體元件，且該第一封裝膠體之側面齊平該 第二封裝膠體之側面。
  3. 如申請專利範圍第1或2項所述之半導體封裝件，其中，該中介板之第一表面與該半導體元件之間係由複數導電元件作電性連接。
  4. 如申請專利範圍第3項所述之半導體封裝件，其中，該些導電元件係凸出該第一封裝膠體之表面。
  5. 如申請專利範圍第2項所述之半導體封裝件，其中，該半導體元件未接置該中介板之一側係外露於該第二封裝膠體。
  6. 如申請專利範圍第1或2項所述之半導體封裝件，其中，該中介板之第二表面與導電穿孔之第二端面係外露於該第一封裝膠體。
  7. 如申請專利範圍第1或2項所述之半導體封裝件，復包括線路重佈結構，係形成於該中介板之第二表面上，且該線路重佈結構係電性連接該導電穿孔之第二端面。
  8. 如申請專利範圍第1或2項所述之半導體封裝件，復包括線路重佈結構，係形成於該半導體元件與中介板之第一表面之間，且該線路重佈結構係電性連接該半導體元件與該導電穿孔之第一端面。
  9. 一種半導體封裝件之製法，係包括：提供一具有相對之第一表面與第二表面之基材，該基材中具有連通該第一表面之複數導電穿孔，該導電穿孔具有相對之第一端面與第二端面，令該導電穿 孔之第一端面對應該第一表面；切割該基材以形成複數中介板，各該中介板具有連接該第一與第二表面之側面；將各該中介板以其第一表面置於一承載件上，且該承載件具有複數開口，以令各該中介板分別對應置於各該開口中，又任二該開口之間具有間隔；形成第一封裝膠體於該承載件上，以令該第一封裝膠體形成於該中介板之側面上並包覆該些中介板；移除該承載件，且於移除該承載件之前或之後，移除該中介板之第二表面之部分材質，以外露該導電穿孔之第二端面；以及結合至少一半導體元件於該中介板之第一表面之上，且電性連接該中介板。
  10. 如申請專利範圍第9項所述之半導體封裝件之製法，復包括形成黏著材料於該承載件之開口中，以將該中介板結合至該承載件。
  11. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該中介板之第一表面上具有線路重佈結構，以電性連接該導電穿孔之第一端面，且該半導體元件係結合至該線路重佈結構並電性連接該線路重佈結構。
  12. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該中介板之第一表面上具有複數導電元件，以令該導電元件位於該開口中，且該些導電元件電性連接該導電穿孔之第一端面。
  13. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，於移除該承載件後，該些導電元件係凸出該第一封裝膠體之表面。
  14. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，於移除該承載件後，該半導體元件係結合於該些導電元件上，且電性連接該些導電元件。
  15. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該半導體元件與該中介板之導電穿孔之第一端面係藉由複數導電元件作電性連接。
  16. 如申請專利範圍第9項所述之半導體封裝件之製法，復包括形成第二封裝膠體於該第一封裝膠體上，以包覆該半導體元件。
  17. 如申請專利範圍第16項所述之半導體封裝件之製法，復包括移除該第二封裝膠體之部分材質，以外露該半導體元件未接置該中介板之一側。
  18. 如申請專利範圍第9或16項所述之半導體封裝件之製法，復包括於移除該承載件之前或之後，形成線路重佈結構於該中介板之第二表面上，且該線路重佈結構係電性連接該導電穿孔之第二端面。
  19. 如申請專利範圍第9項所述之半導體封裝件之製法，復包括於接置該半導體元件於該中介板之製程後，進行切割製程，以形成複數半導體封裝件。
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US20140070424A1 (en) 2014-03-13
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US20160118271A1 (en) 2016-04-28
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