TWI555145B - 基板結構 - Google Patents

基板結構 Download PDF

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TWI555145B
TWI555145B TW103146515A TW103146515A TWI555145B TW I555145 B TWI555145 B TW I555145B TW 103146515 A TW103146515 A TW 103146515A TW 103146515 A TW103146515 A TW 103146515A TW I555145 B TWI555145 B TW I555145B
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layer
metal layer
substrate
substrate structure
wiring region
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TW103146515A
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TW201624646A (zh
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張辰安
孫崧桓
吳建宏
陳以婕
廖文楷
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矽品精密工業股份有限公司
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Priority to TW103146515A priority Critical patent/TWI555145B/zh
Priority to CN201510025409.3A priority patent/CN105870087B/zh
Priority to US14/879,254 priority patent/US9515007B2/en
Publication of TW201624646A publication Critical patent/TW201624646A/zh
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Publication of TWI555145B publication Critical patent/TWI555145B/zh

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Description

基板結構
本發明係有關一種半導體結構，尤指一種提升可靠度之基板結構。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1圖係為習知半導體基板之剖面示意圖，且第1’圖係為對應第1圖之上視示意圖。
如第1及1’圖所示，習知半導體基板1係為晶圓，其包括：一基板本體10、一線路層11以及一絕緣層12。
所述之基板本體10定義有複數佈線區100、鄰接該佈線區100之密封體101、及鄰接該密封體101之切割區102。於沿該切割區102進行切單製程時，該基板本體10表面有時會產生裂縫，此裂縫會沿著該基板本體10表面朝該佈線 區100的方向裂開，故藉由該密封體101之阻擋效果，以避免該裂縫延伸至該佈線區100。
所述之線路層11係形成於部分該佈線區100上，且該線路層11具有複數電性連接墊110。
所述之絕緣層12係形成於部分該佈線區100與該線路層11上，且令該些電性連接墊110外露於該絕緣層12。後續可於該些電性連接墊110上形成一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)14，以於後續製程形成如銲錫材料或金屬凸塊等之導電元件(圖略)於該凸塊底下金屬層14上。
惟，習知半導體基板1中，該基板本體10與該絕緣層12兩者之接觸面積極大，且兩者之熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)具有差異，故於進行熱處理製程期間(thermal cycle)，該半導體基板1難以均勻釋放熱應力(thermal stress)，故當該絕緣層12受應力時，該絕緣層12容易與該基板本體10發生分層(delamination)，導致該半導體基板1容易發生翹曲(warpage)之問題。
再者，於切單製程之過程中時，雖然該密封體101具有阻擋的效果，但有時裂縫仍會破壞該密封體101而延伸至該佈線區100，導致該線路層11損壞。
因此，如何克服習知技術之種種缺失，實為一重要課題。
為克服習知技術之種種缺失，本發明係提供一種基板 結構，係包括：一基板本體，其定義有至少一佈線區、鄰接該佈線區之密封體、及鄰接該密封體之切割區；一線路層，係形成於該基板本體之佈線區之部分表面上；一絕緣層，係形成於該基板本體之佈線區之部分表面與該線路層上；以及一金屬層，係形成於該絕緣層與該基板本體之佈線區之部分表面上。
前述之基板結構中，該密封體係環繞該佈線區。
前述之基板結構中，該密封體係為柵欄狀或環圈狀。
前述之基板結構中，該線路層具有複數電性連接墊，令該些電性連接墊外露於該絕緣層。復包括一形成於該些電性連接墊上之凸塊底下金屬層。例如，該凸塊底下金屬層與該金屬層的材質係為相同或不相同、該凸塊底下金屬層與該金屬層的厚度係為相同或不相同。
前述之基板結構中，該金屬層未接觸該線路層。
前述之基板結構中，該金屬層係接觸該密封體、或未接觸該密封體。
另外，前述之基板結構中，復包括一介電層，係形成於該絕緣層與該基板本體之間。例如，該絕緣層之材質與該介電層之材質可相同或不相同。
由上可知，本發明之基板結構，係藉由在該基板本體表面與該絕緣層上形成一金屬層，以增加該基板本體與該絕緣層之間的結合力，避免該絕緣層發生分層之情況。
再者，於切單製程之過程中時，該金屬層能避免該基板本體之切割區之裂縫延伸至該佈線區，因而能避免該線 路層損壞，進而提高產品良率。
1‧‧‧半導體基板
10,20‧‧‧基板本體
100,200‧‧‧佈線區
101,201,301‧‧‧密封體
102,202‧‧‧切割區
11,21‧‧‧線路層
110,210‧‧‧電性連接墊
12,22‧‧‧絕緣層
14,24‧‧‧凸塊底下金屬層
2,3‧‧‧基板結構
220‧‧‧開孔
23,33‧‧‧金屬層
35‧‧‧介電層
350‧‧‧開口
D‧‧‧間距
t1,t2‧‧‧厚度
第1圖係為習知半導體基板之剖面示意圖；第1’圖係為對應第1圖之上視示意圖；第2圖係為本發明基板結構之剖面示意圖；第2’圖係為對應第2圖之上視示意圖；以及第3圖係為本發明基板結構之另一實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2圖係為本發明基板結構之剖面示意圖，且第2’ 圖係為對應第2圖之上視示意圖。
如第2及2’圖所示，所述之基板結構2係包括：一基板本體20、一線路層21、一絕緣層22以及一金屬層23。
所述之基板本體20定義有複數佈線區200、鄰接該佈線區200之密封體201、及鄰接該密封體201之切割區202。
於本實施例中，該基板本體20之種類繁多，例如，具矽穿孔(Through-silicon via，簡稱TSV)之中介板、矽中介板(Through Silicon interposer，簡稱TSI)或半導體晶圓等半導體板材。於其它實施例中，該基板本體之內部可包含介電層(圖略)與內部線路(圖略)，且該內部線路可選擇性地電性連接該電性連接墊。因此，該基板本體之構造並無特別限制。
再者，該密封體201係為柵欄狀並環繞該佈線區200。
所述之線路層21係形成於該基板本體20之佈線區200之部分表面上及基板本體20內，且該線路層21具有複數電性連接墊210。
所述之絕緣層22係形成於該基板本體20之佈線區200之部分表面與該線路層21上，且該絕緣層22具有複數開孔220，以令該些電性連接墊210外露於該絕緣層22之開孔220。
於本實施例中，形成該絕緣層22之材質係為氮化矽(SiNX)、氧化矽(SiO2)、光阻介電材(photosensitive dielectric material，簡稱PDM)、聚醯亞胺(polyimide，簡稱PI)、苯並環丁烯(Bis-Benzo-Cyclo-Butene，簡稱BCB)、 聚對二唑苯(Polybenzoxazole，簡稱PBO)、環氧樹脂(epoxy)或矽膠等。
再者，可於該些開孔220之電性連接墊210上形成一凸塊底下金屬層(UBM)24，以於後續製程形成如銲錫材料或金屬凸塊等之導電元件(圖略)於該凸塊底下金屬層24上。
又，形成該凸塊底下金屬層24之材質不限，例如Ti/Cu、Ti/Cu/Ni、Cu/Ni、Cu/Ni/Au或Al/NiV/Cu。
另外，該絕緣層22與該密封體201之間保持間距D，使該佈線區200之邊緣沒有該絕緣層22。
所述之金屬層23係形成於該絕緣層22與該基板本體20之佈線區200之部分表面上，且該金屬層23未接觸該線路層21。
於本實施例中，該凸塊底下金屬層24與該金屬層23可同時或非同時形成。例如，先形成該凸塊底下金屬層24，再形成該金屬層23；或先形成該金屬層23，再形成該凸塊底下金屬層24。較佳為同時形成該凸塊底下金屬層24與該金屬層23，因而無需增加製程及成本。
再者，該凸塊底下金屬層24與該金屬層23的材質或厚度t1,t2可相同或不同。例如，該凸塊底下金屬層24之材質為Al/NiV/Cu，該金屬層23之材質為Cu。
又，該金屬層23的一側覆蓋部分該絕緣層22，而另一側係接觸該密封體201，藉此強化該絕緣層22與該基板本體20間的結合力，且使該金屬層23具有延續該密封體 201阻擋裂縫的效果，以避免於沿該切割區202切單時該基板本體20表面的裂痕延伸至該佈線區200。
另外，該金屬層23係環繞該絕緣層22而成為金屬框，且佈滿該間距D。
第3圖係為本發明基板結構之另一實施例之剖面示意圖。本實施例與上述實施例之差異在於新增介電層及密封體之態樣。
如第3圖所示，該金屬層33未接觸該密封體301但仍環繞該絕緣層22而成為金屬框，且該密封體301係為環圈狀，又該基板結構3復包括形成於該絕緣層22與該基板本體20之間的一介電層35。
於本實施例中，先形成該介電層35於部分該佈線區200與該線路層21上，且該介電層35具有複數開口350，以令該些電性連接墊210外露於該些開口350。之後形成該絕緣層22於部分該佈線區200與該介電層35上，且令該些電性連接墊210外露於該絕緣層22之開孔220。
再者，形成該介電層35之材質係為氮化矽(SiNX)、氧化矽(SiO2)、光阻介電材(photosensitive dielectric material，簡稱PDM)、聚醯亞胺(polyimide，簡稱PI)、苯並環丁烯(Bis-Benzo-Cyclo-Butene，簡稱BCB)、聚對二唑苯(Polybenzoxazole，簡稱PBO)、環氧樹脂(epoxy)或矽膠等。
又，該絕緣層22之材質與該介電層35之材質可相同或不相同。
綜上所述，本發明之基板結構2,3藉由在該基板本體20表面與該絕緣層22上形成一金屬層23，以增加該基板本體20與該絕緣層22之間的結合力，避免該絕緣層22發生分層(delamination)之情況。
再者，於切單製程之過程中時，該金屬層23能避免該基板本體20之切割區202之裂縫延伸至該佈線區200，因而能避免該線路層21損壞，進而提高產品良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧基板結構
20‧‧‧基板本體
200‧‧‧佈線區
201‧‧‧密封體
202‧‧‧切割區
21‧‧‧線路層
210‧‧‧電性連接墊
22‧‧‧絕緣層
220‧‧‧開孔
23‧‧‧金屬層
24‧‧‧凸塊底下金屬層
D‧‧‧間距
t1,t2‧‧‧厚度

Claims (15)

  1. 一種基板結構，係包括：一基板本體，其定義有至少一佈線區、鄰接該佈線區之密封體、及鄰接該密封體之切割區；一線路層，係形成於該基板本體之佈線區之部分表面上；一絕緣層，係形成於該基板本體之佈線區之部分表面與該線路層上；以及一金屬層，係形成於該絕緣層與該基板本體之佈線區之部分表面上，其中，該金屬層係接觸該密封體。
  2. 一種基板結構，係包括：一基板本體，其定義有至少一佈線區、鄰接該佈線區之密封體、及鄰接該密封體之切割區；一線路層，係形成於該基板本體之佈線區之部分表面上；一絕緣層，係形成於該基板本體之佈線區之部分表面與該線路層上；以及一金屬層，係形成於該絕緣層與該基板本體之佈線區之部分表面上，其中，該金屬層未接觸該密封體。
  3. 如申請專利範圍第1或2項所述之基板結構，其中，該密封體係環繞該佈線區。
  4. 如申請專利範圍第1或2項所述之基板結構，其中，該密封體係為柵欄狀。
  5. 如申請專利範圍第1或2項所述之基板結構，其中，該 密封體係為環圈狀。
  6. 如申請專利範圍第1或2項所述之基板結構，其中，該線路層具有複數電性連接墊，且該些電性連接墊外露於該絕緣層。
  7. 如申請專利範圍第6項所述之基板結構，復包括一形成於該些電性連接墊上之凸塊底下金屬層。
  8. 如申請專利範圍第7項所述之基板結構，其中，該凸塊底下金屬層與該金屬層的材質係為相同。
  9. 如申請專利範圍第7項所述之基板結構，其中，該凸塊底下金屬層與該金屬層的材質係為不相同。
  10. 如申請專利範圍第7項所述之基板結構，其中，該凸塊底下金屬層與該金屬層的厚度係為相同。
  11. 如申請專利範圍第7項所述之基板結構，其中，該凸塊底下金屬層與該金屬層的厚度係為不相同。
  12. 如申請專利範圍第1或2項所述之基板結構，其中，該金屬層未接觸該線路層。
  13. 如申請專利範圍第1或2項所述之基板結構，復包括一介電層，係形成於該絕緣層與該基板本體之間。
  14. 如申請專利範圍第13項所述之基板結構，其中，該絕緣層之材質與該介電層之材質係相同。
  15. 如申請專利範圍第13項所述之基板結構，其中，該絕緣層之材質與該介電層之材質係不相同。
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