TWI552138B - Display and gate driver thereof - Google Patents

Display and gate driver thereof Download PDF

Info

Publication number
TWI552138B
TWI552138B TW103127526A TW103127526A TWI552138B TW I552138 B TWI552138 B TW I552138B TW 103127526 A TW103127526 A TW 103127526A TW 103127526 A TW103127526 A TW 103127526A TW I552138 B TWI552138 B TW I552138B
Authority
TW
Taiwan
Prior art keywords
voltage level
circuit
coupled
switch
logic control
Prior art date
Application number
TW103127526A
Other languages
Chinese (zh)
Other versions
TW201606742A (en
Inventor
廖偉見
莊銘宏
Original Assignee
友達光電股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 友達光電股份有限公司 filed Critical 友達光電股份有限公司
Priority to TW103127526A priority Critical patent/TWI552138B/en
Priority to CN201410493298.4A priority patent/CN104299581B/en
Publication of TW201606742A publication Critical patent/TW201606742A/en
Application granted granted Critical
Publication of TWI552138B publication Critical patent/TWI552138B/en

Links

Landscapes

  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Description

顯示器及其閘極驅動電路 Display and its gate drive circuit

本發明係有關於一種顯示器及其閘極驅動電路，尤指一種具有多個閂鎖電路的顯示器及其閘極驅動電路。 The present invention relates to a display and a gate drive circuit thereof, and more particularly to a display having a plurality of latch circuits and a gate drive circuit therefor.

液晶顯示器(liquid crystal display,LCD)發展至今已多年，早期液晶電視發展著力於重量輕、體積小，並且成功取代笨重且大體積的陰極映像管顯示器(cathode ray tube display)。近年來，隨著記憶畫素(memory in pixel；MIP)技術的發展，僅更改任意部分畫面資料的功能越來越受重視。此外，傳統閘極驅動器(gate driver)中的移位暫存器(shift register)由於受到必須從第一級開始傳輸訊號的限制，因此已不適用於記憶畫素(MIP)技術的產品。因此一般會以解碼電路(decoder circuit)來取代，如此才可達到僅更改任意部分畫面資料並降低功耗。 Liquid crystal displays (LCDs) have been in development for many years. Early developments in LCD TVs focused on light weight and small size, and successfully replaced the bulky and bulky cathode ray tube display. In recent years, with the development of memory in pixel (MIP) technology, the function of changing only part of the picture data has been paid more and more attention. In addition, the shift register in a conventional gate driver is not suitable for products of memory pixel (MIP) technology because of the limitation of having to transmit signals from the first stage. Therefore, it is generally replaced by a decoder circuit, so that only a part of the picture data can be changed and the power consumption can be reduced.

請參考第1圖，第1圖習知用於閘極驅動器的解碼電路10的電路圖。解碼電路10具有多個輸出端O1至O7，而輸出端O1至O7中的每個輸出端耦接於顯示器中一條對應的掃描線。解碼電路10會依據包含了三個位元A0、A1及A2的數位訊號，使輸出端O1至O7的其中一個輸出端輸出閘極高電位，並使其餘的輸出端為閘極低電位。解碼電路10包含多個反相器12，分別用以將三個位元A0、A1及A2反相後輸出。解碼電路10另包含多個及邏輯閘14，耦接於解碼電路10的輸入端及反相器12，用以對位元A0、A1及A2及位元A0、A1及A2的反相位元進行運算，以輸出閘極高電位至所要驅動的 掃描線。 Please refer to FIG. 1, which is a circuit diagram of a decoding circuit 10 for a gate driver. The decoding circuit 10 has a plurality of output terminals O 1 to O 7 , and each of the output terminals O 1 to O 7 is coupled to a corresponding one of the scan lines in the display. The decoding circuit 10 causes the output terminals of the output terminals O 1 to O 7 to output a gate high potential according to the digital signal including the three bits A 0 , A 1 and A 2 , and the remaining output terminals are gated. Very low potential. The decoding circuit 10 includes a plurality of inverters 12 for respectively inverting and outputting three bits A 0 , A 1 , and A 2 . The decoding circuit 10 further includes a plurality of logic gates 14 coupled to the input end of the decoding circuit 10 and the inverter 12 for pairing the bits A 0 , A 1 and A 2 and the bits A 0 , A 1 and A The inverse phase element of 2 performs an operation to output a gate high potential to the scan line to be driven.

然而，傳統的解碼電路使用大量邏輯閘電路，且其所需的電晶體數目會隨著顯示器解析度的增加而大幅增加。更進一步地說，顯示器的解析度每增加二倍，顯示器之閘極驅動器的每一個用以控制掃描線之電壓準位的電路就需要再增加一個及(AND)邏輯閘，而每個及邏輯閘會用到六顆電晶體。以第1圖的解碼電路10為例，當其解析度倍增時，亦即由八個輸出端提升至十六個輸出端時，除了原本的輸出端O1至O7每個都須再另為其多設置一個及邏輯閘之外，所另外新增的八個輸出端其每個輸出端也須設置三個及邏輯閘。換言之，當解碼電路10由八個輸出端提升至十六個輸出端時，至少需增加192(即(8x1+8x3)x6)個電晶體。因此，就習知的解碼電路來說，其所需的電晶體數目相當龐大。 However, conventional decoding circuits use a large number of logic gate circuits, and the number of transistors required thereof greatly increases as the resolution of the display increases. Furthermore, each time the resolution of the display is doubled, each circuit of the gate driver of the display used to control the voltage level of the scan line needs to add an AND logic gate, and each logic The gate will use six transistors. Taking the decoding circuit 10 of FIG. 1 as an example, when the resolution is multiplied, that is, from eight output terminals to sixteen output terminals, each of the original output terminals O 1 to O 7 must be additionally used. In addition to setting one and logic gates, the other eight additional outputs must also have three and logic gates for each output. In other words, when the decoding circuit 10 is boosted from eight outputs to sixteen outputs, at least 192 (i.e., (8x1 + 8x3) x 6) transistors are added. Therefore, in the case of conventional decoding circuits, the number of transistors required is quite large.

本發明之一實施例提供一種閘極驅動電路。閘極驅動電路包含邏輯控制電路以及M個閂鎖電路。邏輯控制電路耦接於M條掃描線，用以依據數位訊號及時脈訊號，使上述M條掃描線中的其中一條掃描線的電壓準位由第一電壓準位轉為第二電壓準位，並使上述M條掃描線中的其他條掃描線的電壓準位為第一電壓準位。其中M為大於1的整數。每一閂鎖電路耦接於該邏輯控制電路及上述M條掃描線中的一條對應的掃描線，用以於此對應的掃描線的電壓準位處於第一電壓準位時，閂鎖此對應的掃描線的電壓準位。 One embodiment of the present invention provides a gate drive circuit. The gate drive circuit includes a logic control circuit and M latch circuits. The logic control circuit is coupled to the M scan lines for changing the voltage level of one of the M scan lines from the first voltage level to the second voltage level according to the digital signal and the pulse signal. And making the voltage level of the other one of the M scan lines the first voltage level. Where M is an integer greater than one. Each of the latching circuits is coupled to the logic control circuit and a corresponding one of the M scan lines for latching the corresponding voltage level of the corresponding scan line when the voltage level is at the first voltage level. The voltage level of the scan line.

本發明之一實施例提供一種顯示器。顯示器包含多條資料線、多條掃描線、複數個畫素、至少一源極驅動電路以及前述的閘極驅動電路。其中，每一畫素耦接於一條對應的資料線以及一條對應的掃描線。所述的至少一源極驅動電路耦接於所述的多條資料線，用以藉由所述的多條資料線傳送資料訊號至畫素。 An embodiment of the invention provides a display. The display comprises a plurality of data lines, a plurality of scan lines, a plurality of pixels, at least one source driving circuit, and the aforementioned gate driving circuit. Each pixel is coupled to a corresponding data line and a corresponding scan line. The at least one source driving circuit is coupled to the plurality of data lines for transmitting the data signal to the pixels by the plurality of data lines.

10‧‧‧解碼電路 10‧‧‧Decoding circuit

12、142、162‧‧‧反相器 12, 142, 162‧‧ ‧ inverter

14‧‧‧及邏輯閘 14‧‧‧ and logic gate

16‧‧‧畫素 16‧‧‧ pixels

18‧‧‧記憶單元 18‧‧‧ memory unit

100‧‧‧顯示器 100‧‧‧ display

110‧‧‧畫素陣列 110‧‧‧ pixel array

120‧‧‧源極驅動電路 120‧‧‧Source drive circuit

130‧‧‧閘極驅動電路 130‧‧ ‧ gate drive circuit

130A、130B‧‧‧閘極驅動電路 130A, 130B‧‧‧ gate drive circuit

140A、140B‧‧‧邏輯控制電路 140A, 140B‧‧‧ logic control circuit

144‧‧‧輸入端 144‧‧‧ input

150‧‧‧開關模組 150‧‧‧Switch Module

152‧‧‧第一級電路 152‧‧‧First stage circuit

154‧‧‧第二級電路 154‧‧‧Second stage circuit

156‧‧‧第三級電路 156‧‧‧ third-level circuit

160、160A、160B、160C、160D‧‧‧閂鎖電路 160, 160A, 160B, 160C, 160D‧‧‧ latch circuit

C1‧‧‧電容 C1‧‧‧ capacitor

CK‧‧‧時脈訊號 CK‧‧‧ clock signal

/CK‧‧‧時脈訊號CK的反相訊號 /CK‧‧‧Inverted signal of clock signal CK

CP‧‧‧畫素電容 C P ‧‧‧pixel capacitor

A0、A1、A2、D0、D1、D2‧‧‧位元 A 0 , A 1 , A 2 , D0, D1, D2‧‧‧ bits

/D0、/D1、/D2‧‧‧反相位元 /D0, /D1, /D2‧‧‧ anti-phase elements

DP‧‧‧畫素資料 D P ‧‧‧ pixel data

G1至GM、Gy‧‧‧掃描線 G 1 to G M , G y ‧‧‧ scan lines

IN‧‧‧輸入端 IN‧‧‧ input

N1‧‧‧第二開關 N1‧‧‧ second switch

N2、N3、N4、N5、N6‧‧‧開關 N2, N3, N4, N5, N6‧‧‧ switch

O1至O7‧‧‧輸出端 O 1 to O 7 ‧‧‧ output

P1‧‧‧第一開關 P1‧‧‧ first switch

P2、P3、P4、P5、P6‧‧‧開關 P2, P3, P4, P5, P6‧‧‧ switch

Q‧‧‧畫素開關 Q‧‧‧ pixel switch

R‧‧‧電阻 R‧‧‧resistance

S1至SP、Sx‧‧‧資料線 S 1 to S P , S x ‧‧‧ data line

T‧‧‧時脈週期 T‧‧‧ clock cycle

t1、t2、t3、t4、t5、t6‧‧‧時段 T1, t2, t3, t4, t5, t6‧‧

VCOM‧‧‧共通電極 V COM ‧‧‧ common electrode

VGL‧‧‧第一電壓準位；閘極低電位 VGL‧‧‧first voltage level; gate low potential

VGH‧‧‧第二電壓準位；閘極高電位 VGH‧‧‧second voltage level; gate high potential

第1圖習知用於閘極驅動器的解碼電路的電路圖。 Fig. 1 is a circuit diagram of a decoding circuit for a gate driver.

第2圖為本發明一實施例之顯示器的示意圖。 2 is a schematic view of a display according to an embodiment of the present invention.

第3圖為第2圖之顯示器的畫素之示意圖。 Figure 3 is a schematic diagram of the pixels of the display of Figure 2.

第4圖為本發明之一實施例之閘極驅動電路的電路圖。 Fig. 4 is a circuit diagram of a gate driving circuit according to an embodiment of the present invention.

第5圖為第4圖閘極驅動電路的時序圖。 Fig. 5 is a timing chart of the gate driving circuit of Fig. 4.

第6圖為本發明之一實施例之閘極驅動電路的電路圖。 Fig. 6 is a circuit diagram of a gate driving circuit according to an embodiment of the present invention.

第7圖為第6圖閘極驅動電路的時序圖。 Fig. 7 is a timing chart of the gate driving circuit of Fig. 6.

第8圖至第11圖分別為本發明之不同實施例的閂鎖電路之電路圖。 8 through 11 are circuit diagrams of latch circuits of different embodiments of the present invention, respectively.

首先，須瞭解地，本發明所揭露的閘極驅動電路，除了適用於一般的液晶顯示器之外，亦適用於採用了記憶畫素(memory in pixel；MIP)技術的顯示器。請參考第2圖及第3圖。第2圖為本發明一實施例之顯示器100的示意圖，而第3圖為第2圖之顯示器100的畫素16之示意圖。顯示器100包含多條資料線S1至SP、多條掃描線G1至GM、畫素陣列110、至少一源極驅動電路120以及閘極驅動電路130，而畫素陣列110包含複數個畫素16。其中，P和M皆為大於1的整數。在本實施例中，顯示器100採用了記憶畫素(MIP)的技術，其每一個畫素16具有記憶單元18以及畫素電容CP。記憶單元18耦接於畫素電容CP，用以從上述多條資料線S1至SP的其中一條資料線Sx接收畫素資料DP並儲存所接收的畫素資料DP。如此，畫素16即可依據記憶單元18所儲存的畫素資料DP對畫素電容CP進行極性轉換。因此，當畫素16所要顯示的灰階不變時，畫素16即不需從源極驅動電路120接收新的畫素資料DP，而可依據記憶單元18所儲存的畫素資料DP對畫素電容CP進行極性轉換。 First of all, it should be understood that the gate driving circuit disclosed in the present invention is applicable to a display using memory in pixel (MIP) technology, in addition to a general liquid crystal display. Please refer to Figure 2 and Figure 3. 2 is a schematic diagram of a display 100 according to an embodiment of the present invention, and FIG. 3 is a schematic diagram of a pixel 16 of the display 100 of FIG. 2. The display 100 includes a plurality of data lines S 1 to S P , a plurality of scanning lines G 1 to G M , a pixel array 110 , at least one source driving circuit 120 , and a gate driving circuit 130 , and the pixel array 110 includes a plurality of pixels Picture 16. Wherein, both P and M are integers greater than one. In the present embodiment, the display 100 employs a technique of memory pixels (MIP), each of which has a memory unit 18 and a pixel capacitance C P . The memory unit 18 is coupled to the pixel capacitor C P, D P to the pixel data from said plurality of data lines S 1 to S P of a data line S x wherein receiving and storing pixel data D P received. In this way, the pixel 16 can perform polarity conversion on the pixel capacitor C P according to the pixel data D P stored in the memory unit 18. Therefore, when the gray scale to be displayed by the pixel 16 is unchanged, the pixel 16 does not need to receive the new pixel data D P from the source driving circuit 120, but can be based on the pixel data D P stored in the memory unit 18. The polarity of the pixel capacitor C P is converted.

請參考第4圖及第5圖，第4圖為本發明之一實施例之閘極驅動 電路130A的電路圖，而第5圖為第4圖閘極驅動電路130A的時序圖。閘極驅動電路130A包含邏輯控制電路140A以及M個閂鎖電路160。其中，M為大於1的整數，而在本實施例中M=8。須瞭解地，在本發明其他實施例中，M可以為其他大於1的正整數，其大小係取決於所要驅動的顯示器之掃描線的數目。另外，邏輯控制電路140A耦接於掃描線G1至G8，用以依據時脈訊號CK以及依據包含三個位元D0、D1及D2的數位訊號，使掃描線G1至G8中的其中一條掃描線的電壓準位由第一電壓準位VGL轉為第二電壓準位VGH，並使掃描線G1至G8中的其他條掃描線的電壓準位為第一電壓準位VGL。舉例來說，當位元D0、D1及D2分別為“0”、“0”、“0”時，掃描線G1的電壓準位會由第一電壓準位VGL轉為第二電壓準位VGH，而其他條掃描線G2至G8的電壓準位會為第一電壓準位VGL；又例如，當位元D0、D1及D2分別為“1”、“0”、“0”時，掃描線G1的電壓準位會由第一電壓準位VGL轉為第二電壓準位VGH，而其他條掃描線G1、G3至G8的電壓準位會為第一電壓準位VGL；又例如，當位元D0、D1及D2分別為“0”、“1”、“0”時，掃描線G3的電壓準位會由第一電壓準位VGL轉為第二電壓準位VGH，而其他條掃描線G1、G2、G4至G8的電壓準位會為第一電壓準位VGL；其餘可依此類推。位元D0、D1及D2的值的不同組合及其所對應被驅動的掃描線可參照下列的表1。 Please refer to FIG. 4 and FIG. 5, FIG. 4 is a circuit diagram of the gate driving circuit 130A according to an embodiment of the present invention, and FIG. 5 is a timing chart of the gate driving circuit 130A of FIG. The gate drive circuit 130A includes a logic control circuit 140A and M latch circuits 160. Where M is an integer greater than 1, and in the present embodiment M = 8. It will be appreciated that in other embodiments of the invention, M may be other positive integers greater than one, the size of which depends on the number of scan lines of the display to be driven. Further, the control logic circuit 140A is coupled to the scan lines G 1 to G. 8, according to the time and the clock signal CK based contain three bits D0, D1 and D2 of the digital signal, the scan lines G 1 to G's. 8 wherein a voltage level of the scanning line by the first voltage into a second voltage level VGL level VGH, and the voltage level of the scanning lines in the other of 8 scan lines G 1 to G as the first voltage level VGL . For example, when the bits D0, D1 and D2 are "0", "0", "0", the voltage level of the scanning line G 1 will be the second voltage level into a first voltage level by the VGL VGH, and the voltage levels of the other scanning lines G 2 to G 8 will be the first voltage level VGL; for example, when the bits D0, D1, and D2 are "1", "0", and "0", respectively. , the voltage level of the scanning line G 1 will be converted by the first voltage level VGL second voltage level VGH, and the other scan lines G 1, G G voltage level. 3 to 8 will be the first voltage level VGL; as another example, when the bits D0, D1 and D2 are "0", "1", "0", the voltage level of the scanning lines G 3 will be converted into a second voltage level of a first voltage level by the VGL Bit VGH, and the voltage levels of the other scan lines G 1 , G 2 , G 4 to G 8 will be the first voltage level VGL; the rest can be deduced by analogy. The different combinations of the values of the bits D0, D1, and D2 and the corresponding scan lines to be driven can be referred to Table 1 below.

在本實施例中，第一電壓準位VGL為閘極低電位，而第二電壓準 位VGH為閘極高電位，但本發明並不以此為限。此外，閘極驅動電路130A的每一閂鎖電路160耦接於邏輯控制電路140A及掃描線G1至G8中的一條對應的掃描線，用以於對應的掃描線的電壓準位處於第一電壓準位VGL時，閂鎖(latch)此對應的掃描線的電壓準位，以避免因掃描線G1至G8的電壓準位產生非預期的變動，而對畫素16進行非預期的驅動。關於閂鎖電路160的操作方式，以下將會有更進一步的說明。 In this embodiment, the first voltage level VGL is a gate low potential, and the second voltage level VGH is a gate high potential, but the invention is not limited thereto. In addition, each latch circuit 130A of the gate driving circuit 160 is coupled to the control logic circuit 140A and the scanning lines G 1 to G. 8 corresponding to a scanning line to the voltage level corresponding to the scanning line is in the first when a voltage level VGL, the voltage level of the latch (lATCH) scanning lines corresponding thereto, in order to avoid unintended changes due to a voltage level of the scanning lines G 1 to G 8, and 16 of the pixel unintended Drive. Regarding the manner of operation of the latch circuit 160, further explanation will be given below.

在本實施例中，時脈訊號CK在每個時脈週期T內會由第一電壓 準位VGL提升至第二電壓準位VGH，再由第二電壓準位VGH降至第一電壓準位VGL。此外，位元D0的值每隔一個時脈週期T會切換一次(由“0”切換至“1”，或由“1”切換至“0”)，位元D1的值每隔兩個時脈週期T(即2T)會切換一次，而位元D2的值每隔四個時脈週期T(即4T)會切換一次。以第5圖的波形來看，位元D0的電壓準位每隔一個時脈週期T，會由第一電壓準位VGL切換至第二電壓準位VGH，或由第二電壓準位VGH切換至第一電壓準位VGL；位元D1的電壓準位每隔兩個時脈週期T(即2T)，會由第一電壓準位VGL切換至第二電壓準位VGH，或由第二電壓準位VGH切換至第一電壓準位VGL；而位元D2的電壓準位每隔四個時脈週期T(即4T)，會由第一電壓準位VGL切換至第二電壓準位VGH，或由第二電壓準位VGH切換至第一電壓準位VGL。如此一來，掃描線G1至G8的電壓準位即可依序地被提升至第 二電壓準位VGH。因此，閘極驅動電路130A可產生與習知具有移位暫存器(shift register)的閘極驅動器(gate driver)相同時序的掃描線訊號，故閘極驅動電路130A適用於驅動一般的液晶顯示器。此外，亦可藉由控制三個位元D0、D1及D2的值，使掃描線G1至G8中某條特定的掃描線的電壓準位為第二電壓準位VGH，以對耦接於此特定的掃描線的畫素16被驅動，故閘極驅動電路130A亦適用於驅動採用了記憶畫素(MIP)技術的顯示器。 In this embodiment, the clock signal CK is raised from the first voltage level VGL to the second voltage level VGH in each clock cycle T, and then decreased to the first voltage level by the second voltage level VGH. VGL. In addition, the value of the bit D0 is switched every other clock cycle T (switching from "0" to "1" or "1" to "0"), and the value of the bit D1 is every two o'clock. The pulse period T (i.e., 2T) is switched once, and the value of the bit D2 is switched every four clock cycles T (i.e., 4T). According to the waveform of FIG. 5, the voltage level of the bit D0 is switched from the first voltage level VGL to the second voltage level VGH every other clock period T, or is switched by the second voltage level VGH. Up to the first voltage level VGL; the voltage level of the bit D1 is switched to the second voltage level VGH by the first voltage level VGL every two clock cycles T (ie, 2T), or by the second voltage The level VGH is switched to the first voltage level VGL; and the voltage level of the bit D2 is switched to the second voltage level VGH from the first voltage level VGL every four clock cycles T (ie, 4T). Or switching from the second voltage level VGH to the first voltage level VGL. In this way, the voltage levels of the scan lines G 1 to G 8 can be sequentially increased to the second voltage level VGH. Therefore, the gate driving circuit 130A can generate the scanning line signal at the same timing as the gate driver having the shift register, so that the gate driving circuit 130A is suitable for driving a general liquid crystal display. . In addition, also by controlling the three bits D0, D1 and D2, the value of the scanning lines G 1 to G 8 in a voltage level of some specific scanning line is the second voltage level VGH, to be coupled to ground The pixel 16 of this particular scan line is driven, so the gate drive circuit 130A is also suitable for driving a display using memory pixel (MIP) technology.

請再參考第4圖，在此實施例中，邏輯控制電路140A受控於包 含三個位元D0、D1及D2的數位訊號，而邏輯控制電路140A包含第一級電路152、第二級電路154和第三級電路156共三級的電路。其中，第一級電路152、第二級電路154和第三級電路156各包含多個開關模組150，而每一級電路的開關模組150受控於三個位元D0、D1、D2中一個對應位元。詳言之，第一級電路152所包含的兩個開關模組150受控於位元D2，第二級電路154所包含的四個開關模組150受控於位元D1，而第三級電路154所包含的八個開關模組150受控於位元D2。其中，第二級電路154耦接於第一級電路152與第三級電路156之間。此外，時脈訊號CK係由邏輯控制電路140A的輸入端144輸入至邏輯控制電路140A，第一級電路152的每一開關模組150耦接於輸入端144以及第二級電路154的四個開關模組150中的兩個開關模組150。第二級電路154的每一開關模組150耦接於第一級電路152的兩個開關模組150中的一個開關模組150以及第三級電路156的八個開關模組150中的四個開關模組150。 Referring again to FIG. 4, in this embodiment, the logic control circuit 140A is controlled by the package. The digital signal includes three bits D0, D1, and D2, and the logic control circuit 140A includes three stages of circuits of the first stage circuit 152, the second stage circuit 154, and the third stage circuit 156. The first stage circuit 152, the second stage circuit 154 and the third stage circuit 156 each comprise a plurality of switch modules 150, and the switch module 150 of each stage circuit is controlled by three bits D0, D1, D2. A corresponding bit. In detail, the two switch modules 150 included in the first stage circuit 152 are controlled by the bit D2, and the four switch modules 150 included in the second stage circuit 154 are controlled by the bit D1, and the third stage The eight switch modules 150 included in circuit 154 are controlled by bit D2. The second stage circuit 154 is coupled between the first stage circuit 152 and the third stage circuit 156. In addition, the clock signal CK is input to the logic control circuit 140A by the input terminal 144 of the logic control circuit 140A. Each switch module 150 of the first stage circuit 152 is coupled to the input terminal 144 and the fourth stage circuit 154. Two switch modules 150 in the switch module 150. Each switch module 150 of the second stage circuit 154 is coupled to one of the two switch modules 150 of the first stage circuit 152 and four of the eight switch modules 150 of the third stage circuit 156. Switch module 150.

在本發明一實施例中，第一級電路152、第二級電路154和第三 級電路156可各包含一個反相器142，用以將各級電路所接收的對應位元反相，以輸出對應位元的反相位元。詳言之，第一級電路152的反相器142用以將位元D2反相，以輸出位元D2的反相位元；第二級電路154的反相器142 用以將位元D1反相，以輸出位元D1的反相位元；而第三級電路156的反相器142用以將位元D0反相，以輸出位元D0的反相位元。此外，每一開關模組150可包含第一開關P1及第二開關N1，而第一開關P1及第二開關N1受控於上述數位訊號中一個對應位元及此對應位元的反相位元。詳言之，第一級電路152的每一開關模組150其第一開關P1及第二開關N1分別受控於位元D2及位元D2的反相位元；第二級電路154的每一開關模組150其第一開關P1及第二開關N1分別受控於位元D1及位元D1的反相位元；第三級電路156的每一開關模組150其第一開關P1及第二開關N1分別受控於位元D0及位元D0的反相位元。在本實施例中，第一開關P1為P型電晶體(例如：P型薄膜電晶體)，而第二開關N1為N型電晶體(例如：N型薄膜電晶體)。 In an embodiment of the invention, the first stage circuit 152, the second stage circuit 154, and the third The stage circuits 156 can each include an inverter 142 for inverting corresponding bits received by the stages of the circuit to output the inverse phase elements of the corresponding bits. In particular, the inverter 142 of the first stage circuit 152 is used to invert the bit D2 to output the inverse phase element of the bit D2; the inverter 142 of the second stage circuit 154 The pixel D1 is inverted to output the inverse phase element of the bit D1; and the inverter 142 of the third stage circuit 156 is used to invert the bit D0 to output the inverse phase element of the bit D0. . In addition, each switch module 150 can include a first switch P1 and a second switch N1, and the first switch P1 and the second switch N1 are controlled by a corresponding bit of the digital signal and an inverse phase of the corresponding bit. yuan. In detail, each of the switch modules 150 of the first stage circuit 152 has its first switch P1 and the second switch N1 controlled by the inverse phase elements of the bit D2 and the bit D2, respectively; each of the second stage circuits 154 The first switch P1 and the second switch N1 of a switch module 150 are respectively controlled by the reverse phase elements of the bit D1 and the bit D1; the first switch P1 of each switch module 150 of the third stage circuit 156 is The second switch N1 is controlled by the bit phase D0 and the inverse phase element of the bit D0, respectively. In the present embodiment, the first switch P1 is a P-type transistor (for example, a P-type thin film transistor), and the second switch N1 is an N-type transistor (for example, an N-type thin film transistor).

依據上述邏輯控制電路140A的電路架構及控制方式，顯示器的 解析度每增加二倍，邏輯控制電路140A的每一個用以控制掃描線之電壓準位的電路僅需再增加一個開關模組150。因此，相較於習知的解碼電路10的每個及邏輯閘14需使用六個電晶體，邏輯控制電路140A的每個開關模組150僅需使用兩個電晶體即可，故邏輯控制電路140A的佈線方式更為簡單，且所需的佈線面積也會更小。 According to the circuit structure and control mode of the logic control circuit 140A, the display For each doubling of the resolution, each circuit of the logic control circuit 140A for controlling the voltage level of the scan line only needs to add another switch module 150. Therefore, compared with the conventional decoder circuit 10 and the logic gate 14 need to use six transistors, each switch module 150 of the logic control circuit 140A only needs to use two transistors, so the logic control circuit The 140A's wiring is simpler and the required wiring area is smaller.

請參考第6圖及第7圖，第6圖為本發明另一實施例之閘極驅動 電路130B的電路圖，而第7圖為第6圖閘極驅動電路130B的時序圖。閘極驅動電路130B包含邏輯控制電路140B以及M個閂鎖電路160。其中，M為大於1的整數，而在本實施例中M=8。須瞭解地，M可以為其他大於1的正整數，而其大小係取決於所要驅動的顯示器之掃描線的數目。與邏輯控制電路140A相似地，邏輯控制電路140B亦耦接於掃描線G1至G8，用以依據時脈訊號CK以及依據包含三個位元D0、D1及D2的數位訊號，使掃描線G1至G8中的其中一條掃描線的電壓準位由第一電壓準位VGL轉為第二電壓準 位VGH，並使掃描線G1至G8中的其他條掃描線的電壓準位為第一電壓準位VGL。舉例來說，當位元D0、D1及D2分別為“0”、“0”、“0”時，掃描線G1的電壓準位會由第一電壓準位VGL轉為第二電壓準位VGH，而其他條掃描線G2至G8的電壓準位會為第一電壓準位VGL。請同時參考第7圖和第5圖。 在本實施中，閘極驅動電路130B的時序圖與閘極驅動電路130A的時序圖完全一致。換言之，依據時脈訊號CK以及依據包含三個位元D0、D1及D2的數位訊號，閘極驅動電路130B可將掃描線G1至G8的電壓準位依序地提升至第二電壓準位VGH。此外，亦可藉由控制三個位元D0、D1及D2的值，使閘極驅動電路130B將掃描線G1至G8中某條特定的掃描線的電壓準位為第二電壓準位VGH，以對耦接於此特定的掃描線的畫素16被驅動，故閘極驅動電路130B亦適用於驅動採用了記憶畫素(MIP)技術的顯示器。因此，閘極驅動電路130B所驅動的掃描線與對應的位元D0、D1及D2的值亦可參照上述的表1。此外，閂鎖電路160在閘極驅動電路130B的功用與在閘極驅動電路130A的功用相同，而關於閂鎖電路160的操作方式，將在以下的說明中敘明。 Please refer to FIG. 6 and FIG. 7. FIG. 6 is a circuit diagram of a gate driving circuit 130B according to another embodiment of the present invention, and FIG. 7 is a timing chart of the gate driving circuit 130B of FIG. The gate drive circuit 130B includes a logic control circuit 140B and M latch circuits 160. Where M is an integer greater than 1, and in the present embodiment M = 8. It should be understood that M can be other positive integers greater than one, and the size depends on the number of scan lines of the display to be driven. Similarly to the logic control circuit 140A, the logic control circuit 140B is also coupled to the scan lines G 1 to G 8 for making the scan line according to the clock signal CK and the digital signal including the three bits D0, D1 and D2. voltage level. 8 G 1 to one of the scan lines G from the first into the second voltage level VGL voltage level VGH, and the voltage level of the scanning lines G 1 to G other scanning lines. 8 It is the first voltage level VGL. For example, when the bits D0, D1 and D2 are "0", "0", "0", the voltage level of the scanning line G 1 will be the second voltage level into a first voltage level by the VGL VGH, and the voltage levels of the other scanning lines G 2 to G 8 will be the first voltage level VGL. Please also refer to Figures 7 and 5. In the present embodiment, the timing chart of the gate driving circuit 130B is completely identical to the timing chart of the gate driving circuit 130A. In other words, when the clock signal CK based and contains three bits basis D0, D1 and D2 of the digital signal, the gate driving circuit 130B can scan lines G 1 to G 8 voltage levels sequentially lifted to a second voltage level Bit VGH. In addition, also by controlling the three bits D0, D1 and D2, the value of the gate driving circuit 130B scan lines G 1 to G 8 in a voltage level of some specific scanning line is the second voltage level VGH is driven by a pixel 16 coupled to the particular scan line, so the gate drive circuit 130B is also suitable for driving a display using memory pixel (MIP) technology. Therefore, the values of the scanning lines and the corresponding bit elements D0, D1, and D2 driven by the gate driving circuit 130B can also be referred to Table 1 above. Further, the function of the latch circuit 160 in the gate driving circuit 130B is the same as that in the gate driving circuit 130A, and the operation of the latch circuit 160 will be described in the following description.

請再參考第6圖，在此實施例中，邏輯控制電路140B受控於包 含三個位元D0、D1及D2的數位訊號，而掃描線G1至G8中的每一條掃描線耦接於邏輯控制電路140B的三個開關模組150，且此三個開關模組150中的每一個開關模組150分別受控於上述數位訊號的不同位元。當有任何一條掃描線的電壓準位由第一電壓準位VGL轉為第二電壓準位VGH時，此掃描線所耦接的三個開關模組150皆被開啟，以使時脈訊號CK經由此掃描線所耦接的三個開關模組150傳送至此掃描線。舉例來說，掃描線G1所耦接的三個開關模組150分別受控於位元D0、D1和D2。當位元D0、D1和D2皆為“0”時，掃描線G1所耦接的三個開關模組150都會被開啟，而使脈訊號CK經由掃描線G1所耦接的三個開關模組150傳送至掃描線G1。此外，在本發明其他實施例中，三個位元D0、D1及D2會先經過反相處理，而產生位元D0、 D1及D2的反相位元/D0、/D1及/D2。每一開關模組150則可包含第一開關P1及第二開關N1，而第一開關P1及第二開關N1受控於上述數位訊號中一個對應位元及此對應位元的反相位元。 Please refer to FIG. 6, in this embodiment, it is controlled by the logic control circuit 140B comprises three bits D0, D1 and D2 of the digital signal, and the scan lines G 1 to G. 8 is coupled to each scan line The three switch modules 150 of the logic control circuit 140B, and each of the three switch modules 150 are controlled by different bits of the digital signal. When the voltage level of any one of the scan lines is changed from the first voltage level VGL to the second voltage level VGH, the three switch modules 150 coupled to the scan line are turned on to enable the clock signal CK. The three switch modules 150 coupled to the scan line are transferred to the scan line. For example, the three switch modules 150 to which the scan line G 1 is coupled are controlled by the bits D0, D1, and D2, respectively. When the bits D0, D1 and D2 are "0", the scanning line G 1 is coupled to three switch module 150 will be turned on, the clock signal CK via the scan lines G 1 is coupled to the three switches module 150 transmits to the scan line G 1. In addition, in other embodiments of the present invention, the three bits D0, D1, and D2 are first subjected to inversion processing to generate inverse phase elements /D0, /D1, and /D2 of the bits D0, D1, and D2. Each of the switch modules 150 may include a first switch P1 and a second switch N1, and the first switch P1 and the second switch N1 are controlled by a corresponding bit of the digital signal and an inverse phase element of the corresponding bit .

依據第6圖中的邏輯控制電路140B的電路架構及控制方式，顯 示器的解析度每增加二倍，邏輯控制電路140B的每一個用以控制掃描線之電壓準位的電路僅需再增加一個開關模組150。因此，相較於習知的解碼電路10的每個及邏輯閘14需使用六個電晶體，邏輯控制電路140B的每個開關模組150僅需使用兩個電晶體即可，故邏輯控制電路140B的佈線方式更為簡單，且所需的佈線面積也會更小。 According to the circuit structure and control mode of the logic control circuit 140B in FIG. Each time the resolution of the display is doubled, each circuit of the logic control circuit 140B for controlling the voltage level of the scan line only needs to add another switch module 150. Therefore, compared with the conventional decoder circuit 10 and the logic gate 14 need to use six transistors, each switch module 150 of the logic control circuit 140B only needs to use two transistors, so the logic control circuit The 140B's wiring is simpler and the required wiring area is smaller.

以下將以多個實施例，來說明上述閂鎖電路160的操作方式。請 參考第8圖，第8圖為本發明一實施例之閂鎖電路160A的電路圖。閂鎖電路160A的輸入端IN耦接於邏輯控制電路140A或140B，而閂鎖電路160A的輸出端耦接於顯示器100多條掃描線G1至GM中的一條掃描線Gy，其中y為整數，且1≦y≦M。閂鎖電路160A包含電容C1以及兩開關P2及N2。在本實施例中，開關P2及N2可分別為P型電晶體(例如：P型薄膜電晶體)及N型電晶體(例如：N型薄膜電晶體)。為方便說明的緣故，在此假設掃描線Gy為第一條的掃描線G1，亦即y=1。請參考第8圖，並同時參照表1及第5圖或第7圖。在時段t1期間，因位元D0、D1和D2皆為“0”，故時脈訊號CK會由輸入端IN輸入至閂鎖電路160A。此時，因時脈訊號CK的電壓準位為第一電壓準位VGL，故開關P2及N2會開啟，而使得電容C1的兩端都受到第一電壓準位VGL的偏壓。 The mode of operation of the latch circuit 160 described above will be described below in terms of various embodiments. Please refer to FIG. 8. FIG. 8 is a circuit diagram of a latch circuit 160A according to an embodiment of the present invention. Input terminal of the latch circuit 160A is IN is coupled to the logic control circuit 140A or 140B, and the output terminal of the latch circuit 160A is coupled to the display 100 a plurality of scan lines G 1 to G M of the scan line G y, where y Is an integer and 1≦y≦M. The latch circuit 160A includes a capacitor C1 and two switches P2 and N2. In the present embodiment, the switches P2 and N2 may be a P-type transistor (for example, a P-type thin film transistor) and an N-type transistor (for example, an N-type thin film transistor). For the sake of convenience of explanation, it is assumed here that the scanning line G y is the scanning line G 1 of the first strip, that is, y=1. Please refer to Figure 8 and refer to Table 1 and Figure 5 or Figure 7 at the same time. During the period t1, since the bits D0, D1, and D2 are all "0", the clock signal CK is input to the latch circuit 160A from the input terminal IN. At this time, since the voltage level of the clock signal CK is the first voltage level VGL, the switches P2 and N2 are turned on, so that both ends of the capacitor C1 are biased by the first voltage level VGL.

在時段t2期間，因位元D0、D1和D2皆為“0”，故時脈訊號CK 會由輸入端IN輸入至閂鎖電路160A。此外，因時脈訊號CK的電壓準位為 第二電壓準位VGH，故開關P2及N2會被關閉。此時，掃描線G1的電壓準位為第二電壓準位VGH，而電容C1因其兩端分別受到第一電壓準位VGL及第二電壓準位VGH的偏壓而進行充電。 During the period t2, since the bits D0, D1, and D2 are all "0", the clock signal CK is input to the latch circuit 160A from the input terminal IN. In addition, since the voltage level of the clock signal CK is the second voltage level VGH, the switches P2 and N2 are turned off. At this time, the voltage level of the scanning line G 1 is the second voltage level VGH, and the capacitor C1 is charged by the bias of the first voltage level VGL and the second voltage level VGH.

在時段t3期間，因位元D0、D1和D2皆為“0”，故時脈訊號CK 會由輸入端IN輸入至閂鎖電路160A。此時，因時脈訊號CK的電壓準位為第一電壓準位VGL，故開關P2及N2會開啟，而使得電容C1因其兩端都受到第一電壓準位VGL的偏壓而進行放電。 During the period t3, since the bits D0, D1, and D2 are all "0", the clock signal CK It will be input to the latch circuit 160A by the input terminal IN. At this time, since the voltage level of the clock signal CK is the first voltage level VGL, the switches P2 and N2 are turned on, so that the capacitor C1 is discharged due to the bias of the first voltage level VGL at both ends thereof. .

在時段t4期間，因位元D0為“1”，故輸入端IN與邏輯控制電路 140A或140B之間的電性連結被切斷，而使時脈訊號CK無法經由輸入端IN輸入至閂鎖電路160A。此時，因時脈訊號CK的電壓準位為第一電壓準位VGL，故開關P2及N2會開啟，而使得掃描線G1受到第一電壓準位VGL的偏壓，而使掃描線G1的電壓準位被閂鎖在第一電壓準位VGL。 During the period t4, since the bit D0 is "1", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot be input to the latch via the input terminal IN. Circuit 160A. At this time, because the voltage level of the clock signal CK of a first voltage level VGL, it switches P2 and N2 will be turned on, so that the scanning lines G 1 is biased to a first voltage level VGL is, the scanning line G The voltage level of 1 is latched at the first voltage level VGL.

在時段t5期間，因位元D0為“1”，故輸入端IN與邏輯控制電路 140A或140B之間的電性連結被切斷，而使時脈訊號CK無法經由輸入端IN輸入至閂鎖電路160A。此時，因時脈訊號CK的電壓準位為第二電壓準位VGH，故開關P2及N2會關閉，掃描線G1處於浮接的狀態。 During the period t5, since the bit D0 is "1", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot be input to the latch via the input terminal IN. Circuit 160A. At this time, due to voltage levels of the clock signal CK to the second level voltage VGH, it will close switches P2 and N2, the scanning lines G 1 in a floating state.

在時段t6期間，因位元D0為“1”，故輸入端IN與邏輯控制電路 140A或140B之間的電性連結被切斷，而使時脈訊號CK無法經由輸入端IN輸入至閂鎖電路160A。此時，因時脈訊號CK的電壓準位為第一電壓準位VGL，故開關P2及N2會開啟，而使得掃描線G1受到第一電壓準位VGL的偏壓，而使掃描線G1的電壓準位被閂鎖在第一電壓準位VGL。 During the period t6, since the bit D0 is "1", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot be input to the latch via the input terminal IN. Circuit 160A. At this time, because the voltage level of the clock signal CK of a first voltage level VGL, it switches P2 and N2 will be turned on, so that the scanning lines G 1 is biased to a first voltage level VGL is, the scanning line G The voltage level of 1 is latched at the first voltage level VGL.

請參考第9圖，第9圖為本發明另一實施例之閂鎖電路160B的 電路圖。閂鎖電路160B的輸入端IN耦接於邏輯控制電路140A或140B，而閂鎖電路160B的輸出端耦接於顯示器100多條掃描線G1至GM中的一條掃描線Gy。閂鎖電路160B包含電阻R，電阻R的一端偶接於掃描線Gy，而電阻R的另一端則受到第一電壓準位VGL的偏壓。電阻R具有極大的電阻值(一般在400KΩ~600KΩ之間)，故當時脈訊號CK經由輸入端IN輸入至閂鎖電路160B，且時脈訊號CK的電壓準位為第二電壓準位VGH時，掃描線Gy的電壓準位會被轉為第二電壓準位VGH，且同時流經電阻R的電流不會過大。此外，當輸入端IN與邏輯控制電路140A或140B之間的電性連結被切斷時，掃描線Gy透過電阻R而受到第一電壓準位VGL的偏壓，而使此時的掃描線Gy的電壓準位被閂鎖在第一電壓準位VGL。 Please refer to FIG. 9. FIG. 9 is a circuit diagram of a latch circuit 160B according to another embodiment of the present invention. A latch circuit 160B is coupled to the input terminal IN logic control circuit 140A or 140B, 160B of the latch circuit and an output terminal coupled to the display 100 a plurality of scan lines G 1 to G M of the scan line G y. The latch circuit 160B includes a resistor R. One end of the resistor R is coupled to the scan line G y , and the other end of the resistor R is biased by the first voltage level VGL . The resistor R has a very large resistance value (generally between 400KΩ and 600KΩ), so when the pulse signal CK is input to the latch circuit 160B via the input terminal IN, and the voltage level of the clock signal CK is the second voltage level VGH. The voltage level of the scan line G y is converted to the second voltage level VGH, and the current flowing through the resistor R is not excessive. In addition, when the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, the scan line G y is biased by the resistor R and subjected to the bias of the first voltage level VGL, thereby making the scan line at this time. The voltage level of G y is latched at the first voltage level VGL.

請參考第10圖，第10圖為本發明再一實施例之閂鎖電路160C 的電路圖。閂鎖電路160C的輸入端IN耦接於邏輯控制電路140A或140B，而閂鎖電路160C的輸出端耦接於顯示器100多條掃描線G1至GM中的一條掃描線Gy。閂鎖電路160C包含電容C1、反相器162、開關P2、P3、N2及N3。在本實施例中，開關P2及P3為P型電晶體(例如：P型薄膜電晶體)，而開關N2及N3為N型電晶體(例如：N型薄膜電晶體)。當時脈訊號CK經由輸入端IN輸入至閂鎖電路160B，且時脈訊號CK的電壓準位為第二電壓準位VGH時，掃描線Gy的電壓準位會被轉為第二電壓準位VGH。當輸入端IN與邏輯控制電路140A或140B之間的電性連結被切斷時，因電容C1進行放電，而使得掃描線Gy的電壓準位降為第一電壓準位VGL，而使得開關P3被開啟，進而使掃描線Gy受到第一電壓準位VGL的偏壓。此時，反相器162會輸出高電位，而使開關N3也被開啟。另外，當時脈訊號CK的電壓準位為第一電壓準位VGL時，開關P2及N2會被開啟。因此，當輸入端IN與邏輯控制電路140A或140B之間的電性連結被切斷時，掃描線Gy的電壓準位會 被閂鎖在第一電壓準位VGL。 Please refer to FIG. 10, which is a circuit diagram of a latch circuit 160C according to still another embodiment of the present invention. The latch circuit 160C is coupled to the input terminal IN logic control circuit 140A or 140B, and the output terminal of the latch circuit 160C, the display 100 is coupled to a plurality of scan lines G 1 to G M of the scan line G y. The latch circuit 160C includes a capacitor C1, an inverter 162, and switches P2, P3, N2, and N3. In the present embodiment, the switches P2 and P3 are P-type transistors (for example, P-type thin film transistors), and the switches N2 and N3 are N-type transistors (for example, N-type thin film transistors). When the pulse signal CK is input to the latch circuit 160B via the input terminal IN, and the voltage level of the clock signal CK is the second voltage level VGH, the voltage level of the scan line G y is converted to the second voltage level. VGH. When the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, the capacitor C1 discharges, and the voltage level of the scan line G y is lowered to the first voltage level VGL, so that the switch P3 is turned on, thereby enabling the scanning line G y is biased to a first voltage level VGL. At this time, the inverter 162 outputs a high potential, and the switch N3 is also turned on. In addition, when the voltage level of the pulse signal CK is the first voltage level VGL, the switches P2 and N2 are turned on. Therefore, when the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, the voltage level of the scan line G y is latched at the first voltage level VGL.

請參考第11圖，第11圖為本發明一實施例之閂鎖電路160D的 電路圖。閂鎖電路160D的輸入端IN耦接於邏輯控制電路140A或140B，而閂鎖電路160D的輸出端耦接於顯示器100多條掃描線G1至GM中的一條掃描線Gy，其中y為整數，且1≦y≦M。閂鎖電路160D包含電容C1、三個反相器162、164與166以及多個開關P2至P6與N2至N6。在本實施例中，開關P2至P6為P型電晶體(例如：P型薄膜電晶體)，而開關N2至N6為N型電晶體(例如：N型薄膜電晶體)。為方便說明的緣故，在此假設掃描線Gy為第一條的掃描線G1，亦即y=1。請參考第11圖，並同時參照表1及第5圖或第7圖。在時段t1期間，因位元D0、D1和D2皆為“0”，而/D0為“1”，故時脈訊號CK會由輸入端IN輸入至閂鎖電路160A，且開關P3及N4會開啟，而開關P5及N6關閉。此時，因時脈訊號CK的電壓準位為第一電壓準位VGL，故開關P2、N2及P4會開啟，而開關N3關閉，而使得電容C1的兩端都受到第一電壓準位VGL的偏壓，且反相器164的輸入端的電壓準位因開關P3及P4的開啟而為第二電壓準位VGH，並導致開關P6開啟及開關N5關閉。由於開關P2及N2開啟，反相器164的輸入端的電壓準位為第二電壓準位VGH，且因時脈訊號CK的電壓準位為第一電壓準位VGL，故掃描線Gy的輸入端的電壓準位為第一電壓準位VGL。 Please refer to FIG. 11. FIG. 11 is a circuit diagram of a latch circuit 160D according to an embodiment of the present invention. Input terminal of the latch circuit 160D of IN is coupled to the logic control circuit 140A or 140B, and the output terminal of the latch circuit 160D is coupled to the display 100 a plurality of scan lines G 1 to G M of the scan line G y, where y Is an integer and 1≦y≦M. The latch circuit 160D includes a capacitor C1, three inverters 162, 164, and 166, and a plurality of switches P2 to P6 and N2 to N6. In the present embodiment, the switches P2 to P6 are P-type transistors (for example, P-type thin film transistors), and the switches N2 to N6 are N-type transistors (for example, N-type thin film transistors). For the sake of convenience of explanation, it is assumed here that the scanning line G y is the scanning line G 1 of the first strip, that is, y=1. Please refer to Figure 11 and refer to Table 1 and Figure 5 or Figure 7 at the same time. During the period t1, since the bits D0, D1, and D2 are all "0" and /D0 is "1", the clock signal CK is input from the input terminal IN to the latch circuit 160A, and the switches P3 and N4 are Turn on, and switches P5 and N6 are off. At this time, since the voltage level of the clock signal CK is the first voltage level VGL, the switches P2, N2, and P4 are turned on, and the switch N3 is turned off, so that both ends of the capacitor C1 are subjected to the first voltage level VGL. The bias voltage, and the voltage level at the input of the inverter 164 is the second voltage level VGH due to the opening of the switches P3 and P4, and causes the switch P6 to be turned on and the switch N5 to be turned off. Since the switches P2 and N2 are turned on, the voltage level of the input terminal of the inverter 164 is the second voltage level VGH, and the input of the scan line G y is because the voltage level of the clock signal CK is the first voltage level VGL. The voltage level of the terminal is the first voltage level VGL.

在時段t2期間，因位元D0、D1和D2皆為“0”，而/D0為“1”，故 時脈訊號CK會由輸入端IN輸入至閂鎖電路160A，且開關P3及N4會開啟，而開關P5及N6關閉。此時，因時脈訊號CK的電壓準位為第二電壓準位VGH，故開關P2、N2及P4會關閉，而開關N3開啟，而使得電容C1因其兩端分別受到第二電壓準位VGH與第一電壓準位VGL的偏壓而充電，且反相器164的輸入端的電壓準位因開關N3及N4的開啟而為第一電壓準位 VGL，並導致開關N5開啟及開關P6關閉。由於反相器164的輸入端的電壓準位為第一電壓準位VGL，故掃描線Gy的輸入端的電壓準位為第二電壓準位VGH。 During the period t2, since the bits D0, D1, and D2 are all "0" and /D0 is "1", the clock signal CK is input from the input terminal IN to the latch circuit 160A, and the switches P3 and N4 are Turn on, and switches P5 and N6 are off. At this time, since the voltage level of the clock signal CK is the second voltage level VGH, the switches P2, N2, and P4 are turned off, and the switch N3 is turned on, so that the capacitor C1 is respectively subjected to the second voltage level due to its two ends. VGH is charged with the bias of the first voltage level VGL, and the voltage level of the input terminal of the inverter 164 is the first voltage level VGL due to the opening of the switches N3 and N4, and the switch N5 is turned on and the switch P6 is turned off. . Since the voltage level of the input terminal of the inverter 164 is the first voltage level VGL, the voltage level of the input end of the scan line G y is the second voltage level VGH.

在時段t3期間，因位元D0、D1和D2皆為“0”，而/D0為“1”，故 時脈訊號CK會由輸入端IN輸入至閂鎖電路160A，且開關P3及N4會開啟，而開關P5及N6關閉。此時，因時脈訊號CK的電壓準位為第一電壓準位VGL，故開關P2、N2及P4會開啟，而開關N3關閉，而使得電容C1因其兩端都受到第一電壓準位VGL的偏壓而放電，且反相器164的輸入端的電壓準位因開關P3及P4的開啟而為第二電壓準位VGH，並導致開關P6開啟及開關N5關閉。由於開關P2及N2開啟，反相器164的輸入端的電壓準位為第二電壓準位VGH，且因時脈訊號CK的電壓準位為第一電壓準位VGL，故掃描線Gy的輸入端的電壓準位為第一電壓準位VGL。 During the period t3, since the bits D0, D1 and D2 are both "0" and /D0 is "1", the clock signal CK is input from the input terminal IN to the latch circuit 160A, and the switches P3 and N4 will Turn on, and switches P5 and N6 are off. At this time, since the voltage level of the clock signal CK is the first voltage level VGL, the switches P2, N2, and P4 are turned on, and the switch N3 is turned off, so that the capacitor C1 is subjected to the first voltage level because both ends thereof. The bias voltage of the VGL is discharged, and the voltage level at the input of the inverter 164 is the second voltage level VGH due to the opening of the switches P3 and P4, and causes the switch P6 to be turned on and the switch N5 to be turned off. Since the switches P2 and N2 are turned on, the voltage level of the input terminal of the inverter 164 is the second voltage level VGH, and the input of the scan line G y is because the voltage level of the clock signal CK is the first voltage level VGL. The voltage level of the terminal is the first voltage level VGL.

在時段t4期間，因位元D0為“1”，/D0為“0”，故輸入端IN與邏 輯控制電路140A或140B之間的電性連結被切斷，而使時脈訊號CK無法經由輸入端IN輸入至閂鎖電路160D。此外，因/D0為“0”，故開關P5及N6會被開啟，而開關P3及N4會被關閉。此外，因電容C1的作用，輸入端IN的電壓準位維持在第一電壓準位VGL，而使得開關P4被開啟而開關N3關閉。 此時，因時脈訊號CK的電壓準位為第一電壓準位VGL，故開關P2及N2會開啟，而使得掃描線G1受到第一電壓準位VGL的偏壓，並導致開關P6開啟而開關N5關閉。因開關P5及P6開啟，故反相器164的輸入端會受到第二電壓準位VGH的偏壓，而使反相器164的輸出第一電壓準位VGL，故掃描線G1的電壓準位被閂鎖在第一電壓準位VGL。 During the period t4, since the bit D0 is "1" and /D0 is "0", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot be passed. The input terminal IN is input to the latch circuit 160D. In addition, since /D0 is "0", switches P5 and N6 are turned on, and switches P3 and N4 are turned off. In addition, due to the action of the capacitor C1, the voltage level of the input terminal IN is maintained at the first voltage level VGL, so that the switch P4 is turned on and the switch N3 is turned off. At this time, because the voltage level of the clock signal CK of a first voltage level VGL, it switches P2 and N2 will be turned on, so that the scanning lines G 1 is biased to a first voltage level VGL is turned on and causes the switch P6 The switch N5 is turned off. P5 and P6 is turned on by the switch, so the input terminal of the inverter 164 will be biased to a second voltage level VGH, the output of the inverter 164 is a first voltage level VGL, so the voltage of the scan line G 1 Quasi The bit is latched at the first voltage level VGL.

在時段t5期間，因位元D0為“1”，/D0為“0”，故輸入端IN與邏 輯控制電路140A或140B之間的電性連結被切斷，而使時脈訊號CK無法經由輸入端IN輸入至閂鎖電路160D。此外，因/D0為“0”，故開關P5及N6會被開啟，而開關P3及N4會被關閉。此外，因電容C1的作用，輸入端IN的電壓準位維持在第一電壓準位VGL，而使得開關P4被開啟而開關N3關閉。 此時，因時脈訊號CK的電壓準位為第一電壓準位VGL，故開關P2及N2會關閉，並導致開關P6開啟而開關N5關閉。因開關P5及P6開啟，故反相器164的輸入端會受到第二電壓準位VGH的偏壓，而使反相器164的輸出第一電壓準位VGL，故掃描線G1的電壓準位被閂鎖在第一電壓準位VGL。 During the period t5, since the bit D0 is "1" and /D0 is "0", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot be passed. The input terminal IN is input to the latch circuit 160D. In addition, since /D0 is "0", switches P5 and N6 are turned on, and switches P3 and N4 are turned off. In addition, due to the action of the capacitor C1, the voltage level of the input terminal IN is maintained at the first voltage level VGL, so that the switch P4 is turned on and the switch N3 is turned off. At this time, since the voltage level of the clock signal CK is the first voltage level VGL, the switches P2 and N2 are turned off, and the switch P6 is turned on and the switch N5 is turned off. P5 and P6 is turned on by the switch, so the input terminal of the inverter 164 will be biased to a second voltage level VGH, the output of the inverter 164 is a first voltage level VGL, so the voltage of the scan line G 1 Quasi The bit is latched at the first voltage level VGL.

在時段t6期間，因位元D0為“1”，/D0為“0”，且時脈訊號CK的電壓準位為第一電壓準位VGL，故此時閂鎖電路160D的操作方式與時段t6期間內的操作方式一樣，掃描線G1的電壓準位被閂鎖在第一電壓準位VGL。 During the period t6, since the bit D0 is "1", /D0 is "0", and the voltage level of the clock signal CK is the first voltage level VGL, the operation mode of the latch circuit 160D and the time period t6 at this time. as the operation mode in a period, the voltage level of the scanning line G 1 is latched in the first level voltage VGL.

由於閂鎖電路160A至160B在掃描線掃描線Gy的電壓準位處於第一電壓準位VGL時，會對掃描線Gy的電壓準位進行閂鎖(latch)，故可避免因掃描線Gy的電壓準位產生非預期的變動，而對畫素16進行非預期的驅動。因此，可進一步地確保顯示器100的畫質。 Since the latch circuits 160A to 160B are at the first voltage level VGL when the voltage level of the scan line scan line G y is at the first voltage level VGL, the voltage level of the scan line G y is latched, so that the scan line can be avoided. The voltage level of G y produces an unexpected change, while the pixel 16 is driven unintended. Therefore, the image quality of the display 100 can be further ensured.

綜上所述，由於本發明之顯示器及其閘極驅動電路採用了新的電路架構，當顯示器的解析度每增加二倍，閘極驅動電路的每一個用以控制掃描線之電壓準位的電路僅需再增加兩個電晶體。因此，相較於習知的解碼電路的每個及(AND)邏輯閘需使用六個電晶體，本發明之閘極驅動電路的邏輯控制電路的佈線方式更為簡單，且所需的佈線面積也會更小。此外，由於本發明之閘極驅動電路的閂鎖電路在掃描線的電壓準位處於第一電壓準位時，會對掃描線的電壓準位進行閂鎖，故可避免因掃描線的電壓準位產生非預期的變動，而使顯示器的畫質獲得確保。 In summary, since the display of the present invention and its gate driving circuit adopt a new circuit structure, each time the resolution of the display is doubled, each of the gate driving circuits is used to control the voltage level of the scanning line. The circuit only needs to add two more transistors. Therefore, the logic control circuit of the gate driving circuit of the present invention has a simpler wiring pattern and a required wiring area than the use of six transistors for each AND gate logic gate of the conventional decoding circuit. It will be smaller. In addition, since the latch circuit of the gate driving circuit of the present invention latches the voltage level of the scan line when the voltage level of the scan line is at the first voltage level, the voltage level of the scan line can be avoided. The bit produces unintended changes that ensure the image quality of the display.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

130A‧‧‧閘極驅動電路 130A‧‧‧Gate drive circuit

140A‧‧‧邏輯控制電路 140A‧‧‧Logic Control Circuit

142‧‧‧反相器 142‧‧‧Inverter

144‧‧‧輸入端 144‧‧‧ input

150‧‧‧開關模組 150‧‧‧Switch Module

152‧‧‧第一級電路 152‧‧‧First stage circuit

154‧‧‧第二級電路 154‧‧‧Second stage circuit

156‧‧‧第三級電路 156‧‧‧ third-level circuit

160‧‧‧閂鎖電路 160‧‧‧Latch circuit

D0、D1、D2‧‧‧位元 D0, D1, D2‧‧‧ bits

CK‧‧‧時脈訊號 CK‧‧‧ clock signal

G1至G8‧‧‧掃描線 G 1 to G 8 ‧‧‧ scan line

P1‧‧‧第一開關 P1‧‧‧ first switch

N1‧‧‧第二開關 N1‧‧‧ second switch

Claims (8)

一種閘極驅動電路，包含：一邏輯控制電路，耦接於M條掃描線，用以依據一數位訊號及一時脈訊號，使該些掃描線中的其中一條掃描線的電壓準位由一第一電壓準位轉為一第二電壓準位，並使該些掃描線中的其他條掃描線的電壓準位為該第一電壓準位，其中M為大於1的整數；以及M個閂鎖電路，每一閂鎖電路耦接於該邏輯控制電路及該些掃描線中的一條對應的掃描線，用以於該條對應的掃描線的電壓準位處於該第一電壓準位時，閂鎖該條對應的掃描線的電壓準位；其中：該數位訊號為N位元的數位訊號，N為大於1的整數，而每一條掃描線耦接於該邏輯控制電路的N個開關模組，而該N個開關模組受控於該數位訊號的不同位元；及該時脈訊號係由該邏輯控制電路的一輸入端輸入至該邏輯控制電路，而當有任何一條掃描線的電壓準位由該第一電壓準位轉為該第二電壓準位時，該任何一條掃描線所耦接的N個開關模組皆被開啟，以使該時脈訊號經由該任何一條掃描線所耦接的N個開關模組傳送至該任何一條掃描線。 A gate driving circuit includes: a logic control circuit coupled to the M scan lines for causing a voltage level of one of the scan lines to be based on a digital signal and a clock signal a voltage level is converted to a second voltage level, and the voltage levels of the other scan lines in the scan lines are the first voltage level, where M is an integer greater than 1; and M latches a latch circuit coupled to the logic control circuit and a corresponding one of the scan lines for latching when a voltage level of the corresponding scan line is at the first voltage level Locking the voltage level of the scan line corresponding to the strip; wherein: the digit signal is a N-bit digital signal, N is an integer greater than 1, and each scan line is coupled to the N switch modules of the logic control circuit And the N switch modules are controlled by different bits of the digital signal; and the clock signal is input to the logic control circuit by an input of the logic control circuit, and when there is any scan line voltage The level is changed from the first voltage level to the When the voltage level is two, the N switch modules coupled to any one of the scan lines are turned on, so that the clock signal is transmitted to the any one of the N switch modules coupled by any one of the scan lines. Scan line. 一種閘極驅動電路，包含：一邏輯控制電路，耦接於M條掃描線，用以依據一數位訊號及一時脈訊號，使該些掃描線中的其中一條掃描線的電壓準位由一第一電壓準位轉為一第二電壓準位，並使該些掃描線中的其他條掃描線的電壓準位為該第一電壓準位，其中M為大於1的整數；以及M個閂鎖電路，每一閂鎖電路耦接於該邏輯控制電路及該些掃描線中的 一條對應的掃描線，用以於該條對應的掃描線的電壓準位處於該第一電壓準位時，閂鎖該條對應的掃描線的電壓準位；其中該數位訊號為N位元的數位訊號，N為大於1的整數，該邏輯控制電路包含N級電路，其中所述的N級電路中的每一級電路都包含多個開關模組，而每一級電路的該些開關模組受控於該數位訊號中對應的一個位元。 A gate driving circuit includes: a logic control circuit coupled to the M scan lines for causing a voltage level of one of the scan lines to be based on a digital signal and a clock signal a voltage level is converted to a second voltage level, and the voltage levels of the other scan lines in the scan lines are the first voltage level, where M is an integer greater than 1; and M latches a circuit, each latch circuit is coupled to the logic control circuit and the scan lines a corresponding scan line for latching the voltage level of the corresponding scan line when the voltage level of the corresponding scan line is at the first voltage level; wherein the digital signal is N bits The digital signal, N is an integer greater than 1, the logic control circuit comprises an N-level circuit, wherein each of the N-level circuits comprises a plurality of switch modules, and the switch modules of each stage circuit are subjected to Controls a corresponding bit in the digital signal. 如請求項2所述之閘極驅動電路，其中該時脈訊號係由該邏輯控制電路的一輸入端輸入至該邏輯控制電路；其中該N級電路中的第一級電路包含兩個開關模組，該N級電路中的第二級電路包含四個開關模組，該N級電路中的第三級電路包含八個開關模組，而該第二級電路耦接於該第一級電路與該第三級電路之間；其中該第一級電路的每一開關模組耦接於該邏輯控制電路的該輸入端以及該第二級電路的四個開關模組中的兩個開關模組；其中該第二級電路的每一開關模組耦接於該第一級電路的兩個開關模組中的一個開關模組以及該第三級電路的八個開關模組中的四個開關模組。 The gate driving circuit of claim 2, wherein the clock signal is input to the logic control circuit by an input terminal of the logic control circuit; wherein the first stage circuit of the N-stage circuit comprises two switching modes The second-stage circuit of the N-stage circuit includes four switch modules, and the third-stage circuit of the N-stage circuit includes eight switch modules, and the second-stage circuit is coupled to the first-stage circuit And the third stage circuit; wherein each switch module of the first stage circuit is coupled to the input end of the logic control circuit and two switch modes of the four switch modules of the second stage circuit Each of the switch modules of the second-stage circuit is coupled to one of the two switch modules of the first-stage circuit and four of the eight switch modules of the third-stage circuit Switch module. 如請求項1、2或3所述之閘極驅動電路，其中每一開關模組包含一第一開關及一第二開關，每一個開關模組的該第一開關及該第二開關受控於該數位訊號中一個對應位元及該對應位元的反相位元。 The gate driving circuit of claim 1, 2 or 3, wherein each of the switch modules includes a first switch and a second switch, and the first switch and the second switch of each switch module are controlled A corresponding bit in the digital signal and an inverse phase element of the corresponding bit. 如請求項1、2或3所述之閘極驅動電路，其中每一閂鎖電路包含：一開關元件，耦接於一對應的掃描線及一系統電壓，並受控於該時脈訊號；以及 一電容，耦接於該對應的掃描線及一偏壓之間。 The gate driving circuit of claim 1, 2 or 3, wherein each latch circuit comprises: a switching element coupled to a corresponding scan line and a system voltage, and controlled by the clock signal; as well as A capacitor is coupled between the corresponding scan line and a bias voltage. 如請求項1、2或3所述之閘極驅動電路，其中每一閂鎖電路包含一電阻，耦接於一對應的掃描線及一偏壓之間。 The gate driving circuit of claim 1, 2 or 3, wherein each of the latch circuits includes a resistor coupled between a corresponding scan line and a bias voltage. 一種顯示器，包含：多條資料線；多條掃描線；複數個畫素，每一該些畫素耦接於一條對應的資料線以及一條對應的掃描線；至少一源極驅動電路，耦接於該些資料線，用以藉由該些資料線傳送資料訊號至該些畫素；以及如請求項1、2或3所述之閘極驅動電路。 A display comprising: a plurality of data lines; a plurality of scan lines; a plurality of pixels, each of the pixels being coupled to a corresponding data line and a corresponding scan line; at least one source driving circuit coupled And the data lines for transmitting the data signals to the pixels by the data lines; and the gate driving circuit of claim 1, 2 or 3. 如請求項7所述之顯示器，其中每一該些畫素具有一記憶單元以及一畫素電容，該記憶單元耦接於該畫素電容，用以從該些資料線的其中一條資料線接收一畫素資料並儲存該畫素資料，以依據該記憶單元所儲存的該畫素資料對該畫素電容進行極性轉換。 The display device of claim 7, wherein each of the pixels has a memory unit and a pixel capacitor, and the memory unit is coupled to the pixel capacitor for receiving from one of the data lines of the data lines. a pixel data and storing the pixel data to perform polarity conversion on the pixel capacitor according to the pixel data stored in the memory unit.
TW103127526A 2014-08-11 2014-08-11 Display and gate driver thereof TWI552138B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW103127526A TWI552138B (en) 2014-08-11 2014-08-11 Display and gate driver thereof
CN201410493298.4A CN104299581B (en) 2014-08-11 2014-09-24 Display and grid drive circuit thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW103127526A TWI552138B (en) 2014-08-11 2014-08-11 Display and gate driver thereof

Publications (2)

Publication Number Publication Date
TW201606742A TW201606742A (en) 2016-02-16
TWI552138B true TWI552138B (en) 2016-10-01

Family

ID=52319282

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103127526A TWI552138B (en) 2014-08-11 2014-08-11 Display and gate driver thereof

Country Status (2)

Country Link
CN (1) CN104299581B (en)
TW (1) TWI552138B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI788578B (en) * 2018-06-25 2023-01-01 矽創電子股份有限公司 Driving method and circuit using the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW410503B (en) * 1998-12-10 2000-11-01 Via Tech Inc A voltage level converter with single input via gate voltage
TW201248585A (en) * 2011-05-24 2012-12-01 Novatek Microelectronics Corp Apparatus and method for driving display
TWI378438B (en) * 2007-12-21 2012-12-01 Ili Technology Corp Driving circuit of display apparatus and driving method thereof
US20130106826A1 (en) * 2011-09-14 2013-05-02 Shenzhen China Star Optoelectronics Technology Co Ltd. Liquid crystal display panel and gate driver circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998048318A1 (en) * 1997-04-22 1998-10-29 Matsushita Electric Industrial Co., Ltd. Drive circuit for active matrix liquid crystal display
JP3812340B2 (en) * 2001-01-15 2006-08-23 株式会社日立製作所 Image display device
JP2006184718A (en) * 2004-12-28 2006-07-13 Casio Comput Co Ltd Display driving device, driving control method therefor, and display device
WO2012144171A1 (en) * 2011-04-22 2012-10-26 パナソニック株式会社 Solid-state imaging device, drive method for same and camera system
TWI529691B (en) * 2014-04-08 2016-04-11 友達光電股份有限公司 Data driver and display device driving method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW410503B (en) * 1998-12-10 2000-11-01 Via Tech Inc A voltage level converter with single input via gate voltage
TWI378438B (en) * 2007-12-21 2012-12-01 Ili Technology Corp Driving circuit of display apparatus and driving method thereof
TW201248585A (en) * 2011-05-24 2012-12-01 Novatek Microelectronics Corp Apparatus and method for driving display
TWI441128B (en) * 2011-05-24 2014-06-11 Novatek Microelectronics Corp Apparatus and method for driving display
US20130106826A1 (en) * 2011-09-14 2013-05-02 Shenzhen China Star Optoelectronics Technology Co Ltd. Liquid crystal display panel and gate driver circuit

Also Published As

Publication number Publication date
TW201606742A (en) 2016-02-16
CN104299581B (en) 2017-01-18
CN104299581A (en) 2015-01-21

Similar Documents

Publication Publication Date Title
US10204582B2 (en) Shift register and driving method thereof, gate electrode driving circuit, and display device
TWI433459B (en) Bi-directional shift register
US7710373B2 (en) Liquid crystal display device for improved inversion drive
US20050162371A1 (en) Liquid crystal display and data latch circuit
WO2013084813A1 (en) Display device and electrical apparatus
US7663586B2 (en) Reference voltage generation circuit, display driver, electro-optical device, and electronic instrument
WO2010050543A1 (en) Level shifter circuit, load-driving device, and liquid crystal display device
JP4158658B2 (en) Display driver and electro-optical device
JP2009186911A (en) Source driver
WO2016150103A1 (en) Shift register unit, gate drive circuit and display device
WO2019019612A1 (en) Latch and driving method therefor, source drive circuit and display apparatus
JP2006227272A (en) Reference voltage generation circuit, display driver, electrooptical apparatus and electronic equipment
US20050270263A1 (en) Source driver and a source line driving method using a gamma driving scheme for a liquid crystal display (LCD)
CN106128378B (en) Shift register unit, shift register and display panel
US20060198009A1 (en) Reference voltage generation circuit, display driver, electro-optical device, and electronic instrument
TWI386903B (en) Scan driver
US7499517B2 (en) Shift register and shift register set using the same
JP2009003101A (en) Method for driving electro-optical device, source driver, electro-optical device, projection type display device, and electronic equipment
US11049469B2 (en) Data signal line drive circuit and liquid crystal display device provided with same
TWI402808B (en) Liquid crystal display driving circuit
KR101452645B1 (en) Decoding and scan driver
TWI745757B (en) Source driver and composite level shifter
TWI552138B (en) Display and gate driver thereof
JP2006243233A (en) Reference voltage generation circuit, display driver, electro-optic device and electronic device
JP2008225494A (en) Display driver and electro-optical device