CN104299581A - Display and grid drive circuit thereof - Google Patents
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- CN104299581A CN104299581A CN201410493298.4A CN201410493298A CN104299581A CN 104299581 A CN104299581 A CN 104299581A CN 201410493298 A CN201410493298 A CN 201410493298A CN 104299581 A CN104299581 A CN 104299581A
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Abstract
The invention discloses a display and a grid drive circuit thereof. The gate driving circuit comprises a logic control circuit and M latch circuits. Wherein M is an integer greater than 1. The logic control circuit is coupled to the M scan lines of the display, and is configured to convert a voltage level of one of the M scan lines from a first voltage level to a second voltage level according to the digital signal and the clock signal, and to set voltage levels of other scan lines of the M scan lines to the first voltage level. Each latch circuit is coupled to the logic control circuit and a corresponding scan line of the M scan lines, and is configured to latch a voltage level of the corresponding scan line when the voltage level of the corresponding scan line is at a first voltage level.
Description
Technical field
The present invention has about a kind of display and gate driver circuit thereof, espespecially a kind of display and gate driver circuit thereof with multiple latch circuit.
Background technology
Liquid crystal display (liquid crystal display, LCD) be developed so far for many years, early stage LCD TVs put forth effort on lightweight, volume is little, and successfully replaces the heavy and negative electrode crt display of large volume (cathode ray tube display).In recent years, along with memory pixel (memory in pixel; MIP) development of technology, the function only changing arbitrary portion picture data is more and more paid attention to.In addition, shift register (shift register) in traditional gate drivers (gate driver) is owing to being subject to from the restriction of first order proceed to transmit signal, therefore must not being suitable for the product of memory pixel (MIP) technology.Therefore generally can replace with decoding circuit (decoder circuit), so just can reach and only change arbitrary portion picture data and reduce power consumption.
Please refer to Fig. 1, the circuit diagram of the existing decoding circuit 10 for gate drivers of Fig. 1.Decoding circuit 10 has multiple output terminal O
1to O
7, and output terminal O
1to O
7in each output terminal to be coupled in display a corresponding sweep trace.Decoding circuit 10 can according to containing three bit A
0, A
1and A
2digital signal, make output terminal O
1to O
7one of them output terminal export grid noble potential, and make remaining output terminal be grid electronegative potential.Decoding circuit 10 comprises multiple phase inverter 12, respectively in order to by three bit A
0, A
1and A
2anti-phase rear output.Decoding circuit 10 separately comprises multiple with door 14, is coupled to input end and the phase inverter 12 of decoding circuit 10, in order to bit A
0, A
1and A
2and bit A
0, A
1and A
2anti-phase bit carry out computing, to export grid noble potential to the sweep trace that will drive.
But traditional decoding circuit uses a large amount of logic gates, and the transistor size needed for it significantly can increase along with the increase of resolution of display.Furthermore, the resolution of display often increases by two times, each circuit in order to the voltage quasi position of gated sweep line of the gate drivers of display just need to increase again one with door (AND), and eachly can use six transistors with door.For the decoding circuit 10 of Fig. 1, when its resolution doubles, that is when being promoted to 16 output terminals by eight output terminals, except output terminal O originally
1to O
7each must be separately that it arranges outside one and door more again, and its each output terminal of eight output terminals increased newly in addition also must arrange three and door.In other words, when decoding circuit 10 is promoted to 16 output terminals by eight output terminals, at least need increase by 192 (i.e. (8x1+8x3) x6) individual transistor.Therefore, with regard to existing decoding circuit, the transistor size needed for it is quite huge.
Summary of the invention
One embodiment of the invention provide a kind of gate driver circuit.Gate driver circuit comprises logic control circuit and M latch circuit.Logic control circuit is coupled to M bar sweep trace, in order to foundation digital signal and clock signal, make the voltage quasi position of the wherein sweep trace in above-mentioned M bar sweep trace transfer the second voltage quasi position to by the first voltage quasi position, and the voltage quasi position making other sweep traces in above-mentioned M bar sweep trace is the first voltage quasi position.Wherein M be greater than 1 integer.Each latch circuit is coupled to sweep trace corresponding in this logic control circuit and above-mentioned M bar sweep trace one, when the voltage quasi position being used to the sweep trace of this correspondence is in the first voltage quasi position, and the voltage quasi position of the sweep trace of this correspondence of breech lock.
One embodiment of the invention provide a kind of display.Display comprises a plurality of data lines, multi-strip scanning line, multiple pixel, at least one source electrode drive circuit and aforesaid gate driver circuit.Wherein, each pixel is coupled to a corresponding data line and a corresponding sweep trace.Described at least one source electrode drive circuit is coupled to described a plurality of data lines, in order to by described a plurality of data lines data signal to pixel.
Accompanying drawing explanation
The circuit diagram of the existing decoding circuit for gate drivers of Fig. 1.
Fig. 2 is the schematic diagram of the display of one embodiment of the invention.
Fig. 3 is the schematic diagram of the pixel of the display of Fig. 2.
Fig. 4 is the circuit diagram of the gate driver circuit of one embodiment of the invention.
Fig. 5 is the sequential chart of Fig. 4 gate driver circuit.
Fig. 6 is the circuit diagram of the gate driver circuit of one embodiment of the invention.
Fig. 7 is the sequential chart of Fig. 6 gate driver circuit.
Fig. 8 to Figure 11 is respectively the circuit diagram of the latch circuit of different embodiments of the invention.
Wherein, Reference numeral:
10 decoding circuits
12,142,162 phase inverters
14 and door
16 pixels
18 mnemons
100 displays
110 pel arrays
120 source electrode drive circuits
130 gate driver circuits
130A, 130B gate driver circuit
140A, 140B logic control circuit
144 input ends
150 switch modules
152 first order circuit
154 second level circuit
156 tertiary circuits
160,160A, 160B, 160C, 160D latch circuit
C1 electric capacity
CK clock signal
The inversion signal of/CK clock signal CK
C
ppixel capacitance
A
0, A
1, A
2, D0, D1, D2 bit
/ D0 ,/D1, the anti-phase bit of/D2
D
ppixel data
G
1to G
m, G
ysweep trace
IN input end
N1 second switch
N2, N3, N4, N5, N6 switch
O
1to O
7output terminal
P1 first switch
P2, P3, P4, P5, P6 switch
Q pixel switch
R resistance
S
1to S
p, S
xdata line
T clock cycle
T1, t2, t3, t4, t5, t6 period
V
cOMcommon electrode
VGL first voltage quasi position; Grid electronegative potential
VGH second voltage quasi position; Grid noble potential
Embodiment
First, must ground be understood, gate driver circuit disclosed in this invention, except being applicable to general liquid crystal display, also be applicable to have employed memory pixel (memory in pixel; MIP) display of technology.Please refer to Fig. 2 and Fig. 3.Fig. 2 is the schematic diagram of the display 100 of one embodiment of the invention, and Fig. 3 is the schematic diagram of the pixel 16 of the display 100 of Fig. 2.Display 100 comprises a plurality of data lines S
1to S
p, multi-strip scanning line G
1to G
m, pel array 110, at least one source electrode drive circuit 120 and gate driver circuit 130, and pel array 110 comprises multiple pixel 16.Wherein, P and M is all the integer being greater than 1.In the present embodiment, display 100 have employed the technology of memory pixel (MIP), and its each pixel 16 has mnemon 18 and pixel capacitance C
p.Mnemon 18 is coupled to pixel capacitance C
p, in order to from above-mentioned a plurality of data lines S
1to S
pa wherein data line S
xreceive pixel data D
pand store the pixel data D received
p.So, pixel 16 can according to the pixel data D stored by mnemon 18
pto pixel capacitance C
pcarry out dipole inversion.Therefore, when pixel 16 GTG to display is constant, namely pixel 16 need not receive new pixel data D from source electrode drive circuit 120
p, and can according to the pixel data D stored by mnemon 18
pto pixel capacitance C
pcarry out dipole inversion.
Please refer to Fig. 4 and Fig. 5, Fig. 4 is the circuit diagram of the gate driver circuit 130A of one embodiment of the invention, and Fig. 5 is the sequential chart of Fig. 4 gate driver circuit 130A.Gate driver circuit 130A comprises a logic control circuit 140A and M latch circuit 160.Wherein, M be greater than 1 integer, and M=8 in the present embodiment.Must understand ground, in other embodiments of the present invention, the positive integer that M can be greater than 1 for other, its size depends on the number of the sweep trace of the display that will drive.In addition, logic control circuit 140A is coupled to sweep trace G
1to G
8, in order to according to clock signal CK and according to the digital signal comprising three bits D0, D1 and D2, make sweep trace G
1to G
8in the voltage quasi position of a wherein sweep trace transfer the second voltage quasi position VGH to by the first voltage quasi position VGL, and make sweep trace G
1to G
8in the voltage quasi position of other sweep traces be the first voltage quasi position VGL.For example, when bit D0, D1 and D2 are respectively " 0 ", " 0 ", " 0 ", sweep trace G
1voltage quasi position can transfer the second voltage quasi position VGH to by the first voltage quasi position VGL, and other sweep traces G
2to G
8voltage quasi position can be the first voltage quasi position VGL; Again such as, when bit D0, D1 and D2 are respectively " 1 ", " 0 ", " 0 ", sweep trace G
1voltage quasi position can transfer the second voltage quasi position VGH to by the first voltage quasi position VGL, and other sweep traces G
1, G
3to G
8voltage quasi position can be the first voltage quasi position VGL; Again such as, when bit D0, D1 and D2 are respectively " 0 ", " 1 ", " 0 ", sweep trace G
3voltage quasi position can transfer the second voltage quasi position VGH to by the first voltage quasi position VGL, and other sweep traces G
1, G
2, G
4to G
8voltage quasi position can be the first voltage quasi position VGL; All the other can the rest may be inferred.Various combination and corresponding driven sweep trace thereof of the value of bit D0, D1 and D2 can refer to following table 1.
| D0 | D1 | D2 | Voltage quasi position transfers the sweep trace of VGH to |
| 0 | 0 | 0 | G 1 |
| 0 | 0 | 1 | G 2 |
| 0 | 1 | 0 | G 3 |
| 0 | 1 | 1 | G 4 |
| 1 | 0 | 0 | G 5 |
| 1 | 0 | 1 | G 6 |
| 1 | 1 | 0 | G 7 |
| 1 | 1 | 1 | G 8 |
Table 1
In the present embodiment, the first voltage quasi position VGL is grid electronegative potential, and the second voltage quasi position VGH is grid noble potential, but the present invention is not as limit.In addition, each latch circuit 160 of gate driver circuit 130A is coupled to logic control circuit 140A and sweep trace G
1to G
8in a corresponding sweep trace, when the voltage quasi position being used to corresponding sweep trace is in the first voltage quasi position VGL, the voltage quasi position of the sweep trace of breech lock (latch) this correspondence, to avoid because of sweep trace G
1to G
8voltage quasi position produce unexpected variation, and unexpected driving is carried out to pixel 16.About the mode of operation of latch circuit 160, below further description will be had.
In the present embodiment, clock signal CK can be promoted to the second voltage quasi position VGH by the first voltage quasi position VGL in each clock cycle T, then is down to the first voltage quasi position VGL by the second voltage quasi position VGH.In addition, the value of bit D0 can switch once every a clock cycle T and (switched to " 1 " by " 0 ", or switched to " 0 " by " 1 "), the value of bit D1 can switch once every two clock cycle T (i.e. 2T), and the value of bit D2 can switch once every four clock cycle T (i.e. 4T).With the waveform of Fig. 5, the voltage quasi position of bit D0, every a clock cycle T, can switch to the second voltage quasi position VGH by the first voltage quasi position VGL, or switch to the first voltage quasi position VGL by the second voltage quasi position VGH; The voltage quasi position of bit D1, every two clock cycle T (i.e. 2T), can switch to the second voltage quasi position VGH by the first voltage quasi position VGL, or switch to the first voltage quasi position VGL by the second voltage quasi position VGH; And the voltage quasi position of bit D2 is every four clock cycle T (i.e. 4T), the second voltage quasi position VGH can be switched to by the first voltage quasi position VGL, or switch to the first voltage quasi position VGL by the second voltage quasi position VGH.Thus, sweep trace G
1to G
8voltage quasi position can be promoted to the second voltage quasi position VGH in order.Therefore, gate driver circuit 130A can produce and the existing scanning-line signal with gate drivers (gate driver) the identical sequential of shift register (shift register), therefore gate driver circuit 130A is applicable to drive general liquid crystal display.In addition, also by the value of control three bits D0, D1 and D2, sweep trace G can be made
1to G
8in the voltage quasi position of certain specific sweep trace be the second voltage quasi position VGH, to be driven the pixel 16 being coupled to this specific sweep trace, therefore gate driver circuit 130A is also applicable to the display that driving have employed memory pixel (MIP) technology.
Refer again to Fig. 4, in this embodiment, logic control circuit 140A is controlled by the digital signal comprising three bits D0, D1 and D2, and logic control circuit 140A comprises first order circuit 152, second level circuit 154 and tertiary circuit 156 circuit of totally three grades.Wherein, first order circuit 152, second level circuit 154 and tertiary circuit 156 respectively comprise multiple switch module 150, and the switch module 150 of every stage circuit is controlled by a corresponding bit in three bits D0, D1, D2.In detail, two switch modules 150 that first order circuit 152 comprises are controlled by bit D2, and four switch modules 150 that second level circuit 154 comprises are controlled by bit D1, and eight switch modules 150 that tertiary circuit 154 comprises are controlled by bit D2.Wherein, second level circuit 154 is coupled between first order circuit 152 and tertiary circuit 156.In addition, clock signal CK inputs to logic control circuit 140A by the input end 144 of logic control circuit 140A, and each switch module 150 of first order circuit 152 is coupled to two switch modules 150 in four switch modules 150 of input end 144 and second level circuit 154.Each switch module 150 of second level circuit 154 is coupled to four switch modules 150 in eight switch modules 150 of a switch module 150 in two switch modules 150 of first order circuit 152 and tertiary circuit 156.
In an embodiment of the present invention, first order circuit 152, second level circuit 154 and tertiary circuit 156 respectively can comprise a phase inverter 142, anti-phase in order to the corresponding bit received by circuit at different levels, to export the anti-phase bit of corresponding bit.In detail, the phase inverter 142 of first order circuit 152 in order to by anti-phase for bit D2, to export the anti-phase bit of bit D2; The phase inverter 142 of second level circuit 154 in order to by anti-phase for bit D1, to export the anti-phase bit of bit D1; And the phase inverter 142 of tertiary circuit 156 is in order to by anti-phase for bit D0, to export the anti-phase bit of bit D0.In addition, each switch module 150 can comprise the first switch P 1 and second switch N1, and the first switch P 1 and second switch N1 are controlled by the anti-phase bit of a corresponding bit and this corresponding bit in above-mentioned digital signal.In detail, its first switch P 1 of each switch module 150 of first order circuit 152 and second switch N1 are controlled by the anti-phase bit of bit D2 and bit D2 respectively; Its first switch P 1 of each switch module 150 of second level circuit 154 and second switch N1 are controlled by the anti-phase bit of bit D1 and bit D1 respectively; Its first switch P 1 of each switch module 150 of tertiary circuit 156 and second switch N1 are controlled by the anti-phase bit of bit D0 and bit D0 respectively.In the present embodiment, the first switch P 1 is P-type crystal pipe (such as: P-type TFT), and second switch N1 is N-type transistor (such as: N-type TFT).
According to circuit framework and the control mode of above-mentioned logic control circuit 140A, the resolution of display often increases by two times, and each circuit in order to the voltage quasi position of gated sweep line of logic control circuit 140A only needs to increase a switch module 150 again.Therefore, each and door 14 compared to existing decoding circuit 10 need use six transistors, each switch module 150 of logic control circuit 140A only needs use two transistors, therefore the wire laying mode of logic control circuit 140A is more simple, and required wiring area also can be less.
Please refer to Fig. 6 and Fig. 7, Fig. 6 is the circuit diagram of the gate driver circuit 130B of another embodiment of the present invention, and Fig. 7 is the sequential chart of Fig. 6 gate driver circuit 130B.Gate driver circuit 130B comprises a logic control circuit 140B and M latch circuit 160.Wherein, M be greater than 1 integer, and M=8 in the present embodiment.Must understand ground, the positive integer that M can be greater than 1 for other, and its size depends on the number of the sweep trace of the display that will drive.Similarly, logic control circuit 140B is also coupled to sweep trace G to andlogic control circuit 140A
1to G
8, in order to according to clock signal CK and according to the digital signal comprising three bits D0, D1 and D2, make sweep trace G
1to G
8in the voltage quasi position of a wherein sweep trace transfer the second voltage quasi position VGH to by the first voltage quasi position VGL, and make sweep trace G
1to G
8in the voltage quasi position of other sweep traces be the first voltage quasi position VGL.For example, when bit D0, D1 and D2 are respectively " 0 ", " 0 ", " 0 ", sweep trace G
1voltage quasi position can transfer the second voltage quasi position VGH to by the first voltage quasi position VGL, and other sweep traces G
2to G
8voltage quasi position can be the first voltage quasi position VGL.Please also refer to Fig. 7 and Fig. 5.In this enforcement, the sequential chart of gate driver circuit 130B and the sequential chart of gate driver circuit 130A completely the same.In other words, according to clock signal CK and according to the digital signal comprising three bits D0, D1 and D2, gate driver circuit 130B can by sweep trace G
1to G
8voltage quasi position be promoted to the second voltage quasi position VGH in order.In addition, also can, by the value of control three bits D0, D1 and D2, make gate driver circuit 130B by sweep trace G
1to G
8in the voltage quasi position of certain specific sweep trace be the second voltage quasi position VGH, to be driven the pixel 16 being coupled to this specific sweep trace, therefore gate driver circuit 130B is also applicable to the display that driving have employed memory pixel (MIP) technology.Therefore, the sweep trace that gate driver circuit 130B drives also can refer to above-mentioned table 1 with the value of corresponding bit D0, D1 and D2.In addition, latch circuit 160 is identical with in the function of gate driver circuit 130A in the function of gate driver circuit 130B, and about the mode of operation of latch circuit 160, will chat bright in the following description.
Refer again to Fig. 6, in this embodiment, logic control circuit 140B is controlled by the digital signal comprising three bits D0, D1 and D2, and sweep trace G
1to G
8in each sweep trace be coupled to three switch modules 150 of logic control circuit 140B, and each switch module 150 in these three switch modules 150 is controlled by the different bits of above-mentioned digital signal respectively.When there being the voltage quasi position of any sweep trace to transfer the second voltage quasi position VGH to by the first voltage quasi position VGL, three switch modules 150 that this sweep trace couples all are unlocked, and transmit so far sweep trace to make clock signal CK through three switch modules 150 that sweep trace couples thus.For example, sweep trace G
1three switch modules 150 coupled are controlled by bit D0, D1 and D2 respectively.When bit D0, D1 and D2 are all " 0 ", sweep trace G
1three switch modules 150 coupled all can be unlocked, and make arteries and veins signal CK via sweep trace G
1three switch modules 150 coupled are sent to sweep trace G
1.In addition, in other embodiments of the present invention, three bits D0, D1 and D2 first through anti-phase process, and can produce anti-phase bit/D0 ,/D1 and the/D2 of bit D0, D1 and D2.Each switch module 150 can comprise the first switch P 1 and second switch N1, and the first switch P 1 and second switch N1 are controlled by the anti-phase bit of a corresponding bit and this corresponding bit in above-mentioned digital signal.
According to circuit framework and the control mode of the logic control circuit 140B in Fig. 6, the resolution of display often increases by two times, and each circuit in order to the voltage quasi position of gated sweep line of logic control circuit 140B only needs to increase a switch module 150 again.Therefore, each and door 14 compared to existing decoding circuit 10 need use six transistors, each switch module 150 of logic control circuit 140B only needs use two transistors, therefore the wire laying mode of logic control circuit 140B is more simple, and required wiring area also can be less.
Below with multiple embodiment, the mode of operation of above-mentioned latch circuit 160 will be described.Please refer to Fig. 8, Fig. 8 is the circuit diagram of the latch circuit 160A of one embodiment of the invention.The input end IN of latch circuit 160A is coupled to logic control circuit 140A or 140B, and the output terminal of latch circuit 160A is coupled to display 100 multi-strip scanning line G
1to G
min a sweep trace G
y, wherein y is integer, and 1≤y≤M.Latch circuit 160A comprises electric capacity C1 and two switch P 2 and N2.In the present embodiment, switch P 2 and N2 can be respectively P-type crystal pipe (such as: P-type TFT) and N-type transistor (such as: N-type TFT).Cause for convenience of description, at this hypothesis sweep trace G
yfor the sweep trace G of Article 1
1, that is y=1.Please refer to Fig. 8, and simultaneously with reference to table 1 and Fig. 5 or Fig. 7.During period t1, because bit D0, D1 and D2 are all " 0 ", therefore clock signal CK can input to latch circuit 160A by input end IN.Now, the voltage quasi position because of clock signal CK is the first voltage quasi position VGL, therefore switch P 2 and N2 can open, and makes the two ends of electric capacity C1 all be subject to the bias voltage of the first voltage quasi position VGL.
During period t2, because bit D0, D1 and D2 are all " 0 ", therefore clock signal CK can input to latch circuit 160A by input end IN.In addition, the voltage quasi position because of clock signal CK is the second voltage quasi position VGH, therefore switch P 2 and N2 can be closed.Now, sweep trace G
1voltage quasi position be the second voltage quasi position VGH, and electric capacity C1 charges because its two ends are subject to the bias voltage of the first voltage quasi position VGL and the second voltage quasi position VGH respectively.
During period t3, because bit D0, D1 and D2 are all " 0 ", therefore clock signal CK can input to latch circuit 160A by input end IN.Now, the voltage quasi position because of clock signal CK is the first voltage quasi position VGL, therefore switch P 2 and N2 can open, and electric capacity C1 is discharged because its two ends are all subject to the bias voltage of the first voltage quasi position VGL.
During period t4, because bit D0 is " 1 ", therefore the electrically connect between input end IN andlogic control circuit 140A or 140B is cut off, and makes clock signal CK cannot input to latch circuit 160A via input end IN.Now, the voltage quasi position because of clock signal CK is the first voltage quasi position VGL, therefore switch P 2 and N2 can open, and makes sweep trace G
1be subject to the bias voltage of the first voltage quasi position VGL, and make sweep trace G
1voltage quasi position be latched in the first voltage quasi position VGL.
During period t5, because bit D0 is " 1 ", therefore the electrically connect between input end IN andlogic control circuit 140A or 140B is cut off, and makes clock signal CK cannot input to latch circuit 160A via input end IN.Now, the voltage quasi position because of clock signal CK is the second voltage quasi position VGH, therefore switch P 2 and N2 can close, sweep trace G
1be in the state of suspension joint.
During period t6, because bit D0 is " 1 ", therefore the electrically connect between input end IN andlogic control circuit 140A or 140B is cut off, and makes clock signal CK cannot input to latch circuit 160A via input end IN.Now, the voltage quasi position because of clock signal CK is the first voltage quasi position VGL, therefore switch P 2 and N2 can open, and makes sweep trace G
1be subject to the bias voltage of the first voltage quasi position VGL, and make sweep trace G
1voltage quasi position be latched in the first voltage quasi position VGL.
Please refer to Fig. 9, Fig. 9 is the circuit diagram of the latch circuit 160B of another embodiment of the present invention.The input end IN of latch circuit 160B is coupled to logic control circuit 140A or 140B, and the output terminal of latch circuit 160B is coupled to display 100 multi-strip scanning line G
1to G
min a sweep trace G
y.Latch circuit 160B comprises resistance R, and one end of resistance R is even is connected to sweep trace G
y, the other end of resistance R is then subject to the bias voltage of the first voltage quasi position VGL.Resistance R has great resistance value (generally between 400K Ω ~ 600K Ω), therefore when clock signal CK inputs to latch circuit 160B via input end IN, and when the voltage quasi position of clock signal CK is the second voltage quasi position VGH, sweep trace G
yvoltage quasi position can be converted to the second voltage quasi position VGH, and the electric current simultaneously flowing through resistance R can not be excessive.In addition, when the electrically connect between input end IN andlogic control circuit 140A or 140B is cut off, sweep trace G
ybe subject to the bias voltage of the first voltage quasi position VGL through resistance R, and make sweep trace G now
yvoltage quasi position be latched in the first voltage quasi position VGL.
Please refer to Figure 10, Figure 10 is the circuit diagram of the latch circuit 160C of yet another embodiment of the invention.The input end IN of latch circuit 160C is coupled to logic control circuit 140A or 140B, and the output terminal of latch circuit 160C is coupled to display 100 multi-strip scanning line G
1to G
min a sweep trace G
y.Latch circuit 160C comprises electric capacity C1, phase inverter 162, switch P 2, P3, N2 and N3.In the present embodiment, switch P 2 and P3 are P-type crystal pipe (such as: P-type TFT), and switch N2 and N3 is N-type transistor (such as: N-type TFT).When clock signal CK inputs to latch circuit 160B via input end IN, and when the voltage quasi position of clock signal CK is the second voltage quasi position VGH, sweep trace G
yvoltage quasi position can be converted to the second voltage quasi position VGH.When electrically connect between input end IN andlogic control circuit 140A or 140B is cut off, because electric capacity C1 discharges, and make sweep trace G
yvoltage quasi position reduce to the first voltage quasi position VGL, and switch P 3 is unlocked, and then makes sweep trace G
ybe subject to the bias voltage of the first voltage quasi position VGL.Now, phase inverter 162 can export noble potential, and switch N3 is also unlocked.In addition, when the voltage quasi position of clock signal CK is the first voltage quasi position VGL, switch P 2 and N2 can be unlocked.Therefore, when the electrically connect between input end IN andlogic control circuit 140A or 140B is cut off, sweep trace G
yvoltage quasi position can be latched in the first voltage quasi position VGL.
Please refer to Figure 11, Figure 11 is the circuit diagram of the latch circuit 160D of one embodiment of the invention.The input end IN of latch circuit 160D is coupled to logic control circuit 140A or 140B, and the output terminal of latch circuit 160D is coupled to display 100 multi-strip scanning line G
1to G
min a sweep trace G
y, wherein y is integer, and 1≤y≤M.Latch circuit 160D comprises electric capacity C1, three phase inverters 162,164 and 166 and multiple switch P 2 to P6 and N2 to N6.In the present embodiment, switch P 2 to P6 is P-type crystal pipe (such as: P-type TFT), and switch N2 to N6 is N-type transistor (such as: N-type TFT).Cause for convenience of description, at this hypothesis sweep trace G
yfor the sweep trace G of Article 1
1, that is y=1.Please refer to Figure 11, and simultaneously with reference to table 1 and Fig. 5 or Fig. 7.During period t1, because bit D0, D1 and D2 are all " 0 ", and/D0 is " 1 ", therefore clock signal CK can input to latch circuit 160A by input end IN, and switch P 3 and N4 can open, and switch P 5 and N6 close.Now, voltage quasi position because of clock signal CK is the first voltage quasi position VGL, therefore switch P 2, N2 and P4 can open, and switch N3 closes, and make the two ends of electric capacity C1 all be subject to the bias voltage of the first voltage quasi position VGL, and the voltage quasi position of the input end of phase inverter 164 because of switch P 3 and P4 unlatching and be the second voltage quasi position VGH, and cause switch P 6 to be opened and switch N5 closes.Because switch P 2 and N2 open, the voltage quasi position of the input end of phase inverter 164 is the second voltage quasi position VGH, and because of the voltage quasi position of clock signal CK be the first voltage quasi position VGL, therefore sweep trace G
ythe voltage quasi position of input end be the first voltage quasi position VGL.
During period t2, because bit D0, D1 and D2 are all " 0 ", and/D0 is " 1 ", therefore clock signal CK can input to latch circuit 160A by input end IN, and switch P 3 and N4 can open, and switch P 5 and N6 close.Now, voltage quasi position because of clock signal CK is the second voltage quasi position VGH, therefore switch P 2, N2 and P4 can close, and switch N3 opens, and electric capacity C1 is charged because its two ends are subject to the bias voltage of the second voltage quasi position VGH and the first voltage quasi position VGL respectively, and the voltage quasi position of the input end of phase inverter 164 is the first voltage quasi position VGL because of the unlatching of switch N3 and N4, and switch N5 unlatching and switch P 6 is caused to be closed.Voltage quasi position due to the input end of phase inverter 164 is the first voltage quasi position VGL, therefore sweep trace G
ythe voltage quasi position of input end be the second voltage quasi position VGH.
During period t3, because bit D0, D1 and D2 are all " 0 ", and/D0 is " 1 ", therefore clock signal CK can input to latch circuit 160A by input end IN, and switch P 3 and N4 can open, and switch P 5 and N6 close.Now, voltage quasi position because of clock signal CK is the first voltage quasi position VGL, therefore switch P 2, N2 and P4 can open, and switch N3 closes, and electric capacity C1 is discharged because its two ends are all subject to the bias voltage of the first voltage quasi position VGL, and the voltage quasi position of the input end of phase inverter 164 because of switch P 3 and P4 unlatching and be the second voltage quasi position VGH, and cause switch P 6 to be opened and switch N5 closes.Because switch P 2 and N2 open, the voltage quasi position of the input end of phase inverter 164 is the second voltage quasi position VGH, and because of the voltage quasi position of clock signal CK be the first voltage quasi position VGL, therefore sweep trace G
ythe voltage quasi position of input end be the first voltage quasi position VGL.
During period t4, because bit D0 is " 1 " ,/D0 is " 0 ", therefore the electrically connect between input end IN andlogic control circuit 140A or 140B is cut off, and makes clock signal CK cannot input to latch circuit 160D via input end IN.In addition, because of/D0 is " 0 ", therefore switch P 5 and N6 can be unlocked, and switch P 3 and N4 can be closed.In addition, because of the effect of electric capacity C1, the voltage quasi position of input end IN maintains the first voltage quasi position VGL, and makes that switch P 4 is unlocked and switch N3 closes.Now, the voltage quasi position because of clock signal CK is the first voltage quasi position VGL, therefore switch P 2 and N2 can open, and makes sweep trace G
1be subject to the bias voltage of the first voltage quasi position VGL, and cause that switch P 6 is opened and switch N5 closes.Because switch P 5 and P6 open, therefore the input end of phase inverter 164 can be subject to the bias voltage of the second voltage quasi position VGH, and makes the output first voltage quasi position VGL of phase inverter 164, therefore sweep trace G
1voltage quasi position be latched in the first voltage quasi position VGL.
During period t5, because bit D0 is " 1 " ,/D0 is " 0 ", therefore the electrically connect between input end IN andlogic control circuit 140A or 140B is cut off, and makes clock signal CK cannot input to latch circuit 160D via input end IN.In addition, because of/D0 is " 0 ", therefore switch P 5 and N6 can be unlocked, and switch P 3 and N4 can be closed.In addition, because of the effect of electric capacity C1, the voltage quasi position of input end IN maintains the first voltage quasi position VGL, and makes that switch P 4 is unlocked and switch N3 closes.Now, the voltage quasi position because of clock signal CK is the first voltage quasi position VGL, therefore switch P 2 and N2 can close, and causes that switch P 6 is opened and switch N5 closes.Because switch P 5 and P6 open, therefore the input end of phase inverter 164 can be subject to the bias voltage of the second voltage quasi position VGH, and makes the output first voltage quasi position VGL of phase inverter 164, therefore sweep trace G
1voltage quasi position be latched in the first voltage quasi position VGL.
During period t6, because bit D0 is " 1 " ,/D0 is " 0 ", and the voltage quasi position of clock signal CK is the first voltage quasi position VGL, so time latch circuit 160D mode of operation the same with the mode of operation in during period t6, sweep trace G
1voltage quasi position be latched in the first voltage quasi position VGL.
Because latch circuit 160A to 160B is at sweep trace G
yvoltage quasi position when being in the first voltage quasi position VGL, can to sweep trace G
yvoltage quasi position carry out breech lock (latch), therefore can to avoid because of sweep trace G
yvoltage quasi position produce unexpected variation, and unexpected driving is carried out to pixel 16.Therefore, the image quality of display 100 can be guaranteed further.
In sum, because display of the present invention and gate driver circuit thereof have employed new circuit framework, when the resolution of display often increases by two times, each circuit in order to the voltage quasi position of gated sweep line of gate driver circuit only needs to increase by two transistors again.Therefore, need use six transistors compared to each of existing decoding circuit and door (AND), the wire laying mode of the logic control circuit of gate driver circuit of the present invention is more simple, and required wiring area also can be less.In addition, because the latch circuit of gate driver circuit of the present invention is when the voltage quasi position of sweep trace is in the first voltage quasi position, breech lock can be carried out to the voltage quasi position of sweep trace, therefore the voltage quasi position because of sweep trace can be avoided to produce unexpected variation, and the acquisition of the image quality of display is guaranteed.
The foregoing is only preferred embodiment of the present invention, all equalizations made according to the claims in the present invention protection domain change and amendment, all should belong to covering scope of the present invention.
Claims (10)
1. a gate driver circuit, is characterized in that, comprises:
One logic control circuit, be coupled to M bar sweep trace, in order to foundation one digital signal and a clock signal, the voltage quasi position of the wherein sweep trace in those sweep traces is made to transfer one second voltage quasi position to by one first voltage quasi position, and make the voltage quasi position of other sweep traces in those sweep traces be this first voltage quasi position, wherein M be greater than 1 integer; And
M latch circuit, each latch circuit is coupled to sweep trace corresponding in this logic control circuit and those sweep traces one, when the voltage quasi position being used to this corresponding sweep trace is in this first voltage quasi position, the voltage quasi position of this corresponding sweep trace of breech lock.
2. gate driver circuit as claimed in claim 1, it is characterized in that, this digital signal is the digital signal of N bit, N be greater than 1 integer, and each sweep trace is coupled to N number of switch module of this logic control circuit, and this N number of switch module is controlled by the different bits of this digital signal.
3. gate driver circuit as claimed in claim 2, it is characterized in that, this clock signal inputs to this logic control circuit by an input end of this logic control circuit, and when there being the voltage quasi position of any sweep trace to transfer this second voltage quasi position to by this first voltage quasi position, N number of switch module that this any sweep trace couples all is unlocked, and is sent to this any sweep trace to make this clock signal via N number of switch module that this any sweep trace couples.
4. gate driver circuit as claimed in claim 1, it is characterized in that, this digital signal is the digital signal of N bit, N be greater than 1 integer, this logic control circuit comprises N level circuit, every stage circuit in wherein said N level circuit all comprises multiple switch module, and those switch modules of every stage circuit are controlled by a bit corresponding in this digital signal.
5. gate driver circuit as claimed in claim 4, it is characterized in that, this clock signal inputs to this logic control circuit by an input end of this logic control circuit;
First order circuit wherein in this N level circuit comprises two switch modules, second level circuit in this N level circuit comprises four switch modules, tertiary circuit in this N level circuit comprises eight switch modules, and this second level circuit is coupled between this first order circuit and this tertiary circuit;
Wherein each switch module of this first order circuit is coupled to two switch modules in this input end of this logic control circuit and four switch modules of this second level circuit;
Wherein each switch module of this second level circuit is coupled to four switch modules in eight switch modules of a switch module in two switch modules of this first order circuit and this tertiary circuit.
6. the gate driver circuit as described in claim 2,3,4 or 5, it is characterized in that, each switch module comprises one first switch and a second switch, and this first switch of each switch module and this second switch are controlled by the anti-phase bit of a corresponding bit and this corresponding bit in this digital signal.
7. the gate driver circuit as described in claim 2,3,4 or 5, is characterized in that, each latch circuit comprises:
One on-off element, is coupled to sweep trace and a system voltage of a correspondence, and is controlled by this clock signal; And
One electric capacity, between the sweep trace being coupled to this correspondence and a bias voltage.
8. the gate driver circuit as described in claim 2,3,4 or 5, is characterized in that, each latch circuit comprises a resistance, between the sweep trace being coupled to a correspondence and a bias voltage.
9. a display, is characterized in that, comprises:
A plurality of data lines;
Multi-strip scanning line;
Multiple pixel, each those pixel is coupled to a corresponding data line and a corresponding sweep trace;
At least one source electrode drive circuit, is coupled to those data lines, in order to by those data line data signal to those pixels; And
Gate driver circuit as described in claim 1,2,3,4 or 5.
10. display as claimed in claim 9, it is characterized in that, each those pixel has a mnemon and a pixel capacitance, this mnemon is coupled to this pixel capacitance, receive a pixel data and store this pixel data in order to the wherein data line from those data lines, to carry out dipole inversion according to this pixel data stored by this mnemon to this pixel capacitance.
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| TW103127526A TWI552138B (en) | 2014-08-11 | 2014-08-11 | Display and gate driver thereof |
| TW103127526 | 2014-08-11 |
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| CN104299581B CN104299581B (en) | 2017-01-18 |
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| TW (1) | TWI552138B (en) |
Cited By (1)
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| CN110634451A (en) * | 2018-06-25 | 2019-12-31 | 矽创电子股份有限公司 | Driving method and driving circuit thereof |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW201606742A (en) | 2016-02-16 |
| TWI552138B (en) | 2016-10-01 |
| CN104299581B (en) | 2017-01-18 |
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