TWI548006B - 形成半導體裝置之方法 - Google Patents

形成半導體裝置之方法 Download PDF

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TWI548006B
TWI548006B TW103144587A TW103144587A TWI548006B TW I548006 B TWI548006 B TW I548006B TW 103144587 A TW103144587 A TW 103144587A TW 103144587 A TW103144587 A TW 103144587A TW I548006 B TWI548006 B TW I548006B
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Taiwan
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layer
conductive
die
forming
passivation layer
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TW103144587A
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TW201539589A (zh
Inventor
何明哲
吳逸文
黃見翎
郭宏瑞
劉重希
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台灣積體電路製造股份有限公司
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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Description

形成半導體裝置之方法
本發明是關於一種半導體裝置及其形成方法，特別是有關於一種使用形成薄柱體或通孔或凸塊將導電墊互連至封裝體之半導體裝置及其形成方法。
典型的積體電路結構是由晶粒構成，而晶粒包含主動裝置例如電晶體和電容器。這些裝置最初相互隔離，之後於這些主動裝置上形成互連結構來產生功能電路。在互連結構的頂部之上，金屬焊墊形成並暴露在各別的晶粒表面上。通過金屬焊墊製造電連接以將晶粒連接到封裝基板或另一個晶粒。
在傳統的封裝技術的技術中，像是扇出型(fan-out)封裝，重分佈層(RDLs)可形成在一晶粒上並電連接到金屬焊墊。然後輸入/輸出(I/O)焊墊諸如焊球可形成以通過RDLs電連接到金屬焊墊。這種封裝技術的一個優點是形成扇出型封裝的可能性，這表示晶粒上之I/O焊墊可被重分佈到一個比晶粒更大的面積，而因此能夠增加封裝至晶粒的表面上之I/O焊墊的數量。
在一實施方式中，一種形成半導體裝置之方法包括提供一晶粒，此晶粒具有一鈍化層形成在其上並且在此鈍化層上具有一聚合物層，此晶粒尚具有一導電層位於此聚合物層上，此導電層延伸通過在此鈍化層中和此聚合物層之開口，使得此導電層電性接觸底層之諸導電墊；安裝此晶粒於一載體上；形成一模塑化合物於此導電層上方並沿著此晶粒的側壁；以及平坦化此模塑化合物和此導電層，以除去此聚合物層上之此導電層並形成從此導電層延伸通過此聚合物層的諸柱體。
在一實施方式中，一種形成裝置之方法，包括：提供一晶粒，其具有一鈍化層形成於其上，此鈍化層具有諸開口位於諸導電墊上，此晶粒尚具有諸導電柱延伸通過各別之此等開口以及具有一聚合物層覆蓋此等導電柱；安裝此晶粒於一載體上；形成一模塑化合物於此聚合物層上並沿著此晶粒的側壁；以及平坦化此模塑化合物的一上表面和此聚合物層以暴露此等導電柱。
在一實施方式中，一種形成半導體裝置之方法，包括提供一晶粒，此晶粒具有一鈍化層形成於其上，此鈍化層具有諸開口位於諸導電墊上，此晶粒尚具有諸導電元件延伸通過各別之此等開口，此等導電元件延伸至此鈍化層之一上表面；安裝此晶粒於一載體上；在此晶粒的鈍化層上並沿著此晶粒的側壁形成模塑化合物；以及平坦化此模塑化 合物的一上表面以暴露此等導電元件。
100‧‧‧基板
102‧‧‧導電墊
104‧‧‧鈍化層
106‧‧‧聚合物層
108‧‧‧開口
214‧‧‧內襯層
218‧‧‧導電層
320‧‧‧載體
322‧‧‧模塑材料
430‧‧‧柱體
532‧‧‧重分佈層RDL
534‧‧‧外部連接器
640‧‧‧柱體
H1‧‧‧高度
W1‧‧‧寬度
1450‧‧‧橢圓體凸塊
a‧‧‧高度
b‧‧‧重疊
a’‧‧‧高度
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為了對於實施例和它們的的優點有更完整的理解，現在參考以下描述結合附圖，其中：第1-5圖繪示出根據實施例形成之半導體裝置的中間階段。
第6-10圖根據實施例形成之半導體裝置的中間階段。
第11-13圖繪示出根據實施例形成之半導體裝置的中間階段。
第14-17圖繪示出根據實施例形成之半導體裝置的中間階段。
第18圖係一流程圖繪示出根據實施例形成半導體裝置的方法。
第19圖係一流程圖繪示出根據實施例形成半導體裝置的方法。
第20圖係一流程圖繪示出根據實施例形成半導體裝置的方法。
第21圖係一流程圖繪示出根據實施例形成半導體裝置的方法。
下面詳細討論實施方式的製造與使用。然而，應當理解的是，本案內容提供了能以廣泛差異之特定內文實 現之多種可適用發明構思。本文所討論的具體實施方式僅僅是以說明性的具體方式來製造和使用各式實施例，而非限制本案的範圍。
本案的實施方式涉及使用形成薄柱體或通孔或凸塊來將晶粒之導電墊互連至封裝體中之焊球或凸塊。雖然揭露的實施方式是以扇出型設計之內容揭露，但其它實施方式可以使用於其它應用中。例如，其他實施方式可以在其他配置中，如使用於三維(3D)積體電路(IC)或晶片堆疊的配置中。本案全部之各視圖與說明性的實施方式中，同類的符號數字用於表示同類的元件。
第1-5圖繪示根據實施例製造具有柱體薄形成於其中之半導體裝置的各個中間階段。首先參照第1圖，基板100的一部分係根據實施例繪示。基板100可包括例如摻雜或未摻雜的矽塊材(bulk silicon)、或絕緣層上覆半導體(SOI)基板的主動層。一般而言，SOI基板包括一層半導體材料(像是矽)形成於絕緣層上。此絕緣體層可為像是掩埋氧化物(BOX)層或氧化矽層。此絕緣層提供於基板(典型地為矽或玻璃基板)上。其它基板(如多層或漸層(gradient)基板)也可以使用。在另一實施方式中，基板100可包括基板其上可接附積體電路晶粒。例如，基板100可以包括***件(interposer)、封裝基板、高密度互連、印刷電路板、另一積體電路晶粒等等。
應該注意的是，在一些實施方式中，特別是在基板100包括積體電路晶粒的實施方式中，基板100可包括 電路(未繪示出)。在一個實施方式中，電路包括電氣裝置(electrical device)形成於基板100上，此電氣裝置上覆蓋有一或多個介電質層。金屬層可形成於介電質層之間以傳遞電氣裝置間電氣信號。電氣裝置也可形成在一或多個介電層中。
舉例來說，電路可包括各種N型金屬氧化物半導體(NMOS)及/或P型金屬氧化物半導體(PMOS)裝置，如電晶體、電容器、電阻器、二極體、光電二極體、保險絲之類的，相互連接以執行一或多個功能。這些功能可包括記憶結構、處理結構、感測器、放大器、功率分配、輸入/輸出電路等等。本領域的通常技術人士將理解，所提供的上述實例僅用於說明目的，以進一步解釋一些說明性實施方式的應用，而不意味著以任何方式限制本案內容。其他電路適合時也可用於給定的應用。在此實例中，基板100是一***件，此***件可包括被動元件、主動元件、主動元件和被動元件，或兩者都不是。
此外，基板100可為晶圓，其上可形成複數個晶粒然後分離，藉以形成各別的積體電路晶粒。因為如此，為了便於說明，圖式係繪示一個單一晶粒，而可以理解此晶粒可製造成部分的晶圓。
導電墊102處於基板100的上表面上，以提供外部電連接。應當注意的是，導電墊102可代表連接至形成於基板100上之電路的電連接、連接至基板通孔之電連接等等。導電墊102可包括導電材料如銅，儘管其它的導電材料 (例如鎢，鋁或銅合金)也可以使用。導電墊102可通過任何合適的方法(如沉積和蝕刻，鑲嵌或雙鑲嵌等)，以任何合適的導電材料(像是鋁)形成。
鈍化層104可以介電質材料製成，例如聚醯亞胺、聚合物、氧化物、氮化物等等，並圖形化於基板100的表面上，以在導電墊102上提供一個開口並保護其下所覆蓋層不受各種環境污染物的影響。在一實施方式中，第一鈍化層104包括氮化矽層和氧化層的複合層。氮化矽層可使用化學氣相沉積(CVD)技術，利用矽烷和氨作為前驅氣體形成至約2000埃的厚度。氧化物層可通過任何氧化程序來形成，例如在一包括氧化物、H2O、NO或其組合之環境中的濕式或乾式熱氧化，或者通過使用四乙基正矽酸鹽(TEOS)和氧作為前驅物之CVD技術。在一實施方式中，鈍化層的厚度為約2.5微米至約3.1微米。
任何適合的方法均可用於形成上述所討論的結構而將不更詳細地討論。如本領域中的通常技術人士將意識到，上面的描述提供的實施方式特徵的一般性描述而許多其他的特徵可以存在。舉例而言，其他電路、內襯、阻擋層、凸塊下金屬化(UBM)配置、附加鈍化層及類似物均可存在。繪示出單層導電/接合墊和一鈍化層僅用於說明的目的。其它實施方式可包括任何數量的導電層和/或鈍化層。此外，應該理解的是一或多個導電層可作為RDL以提供所需的接腳或焊球佈局。上面所描述的僅是為了提供此處所討論之實施方式的內文，而非意味著限制本案或請求項的範圍 至這些具體的實施方式。
根據一實施方式，聚合物層106形成在鈍化層104上並圖案化以形成開口108。聚合物層106將在後續的處理步驟作為一個塑模用於形成導電柱或通孔。在一實施方式中，聚合物層106是一種聚合物，如環氧樹脂、聚醯亞胺，苯并環丁烯(BCB)、聚苯并噁唑(PBO)等等。在一實施方式中，其中聚合物層為例如PBO，而聚合物層可以旋塗形成一厚度例如約2微米至約5微米，並且使用光微影技術進行圖案化。PBO是感光材料，並且可以通過對PBO層按照所期望的圖案曝光、顯影，以及固化來形成圖案。由於這些步驟，包括固化，聚合物層106的側壁呈錐形。這些錐形側壁有助於實現後來形成之內襯的良好台階覆蓋。在一實施方式中，聚合物層的側壁具有相對於第二鈍化層106主表面法線約5°至約35°的角度，如第1圖中所繪示。錐形側壁的角度可以通過調整圖案化步驟的曝光條件來控制，像是通過調節曝光能量、照射時間、和固化條件。
現在參照第2圖，內襯層214形成在聚合物層106的表面上和導電墊102暴露的部分上。襯墊層214是一個導電性材料薄層充當擴散阻擋層及/或黏合層。襯墊層214進一步有助於在後續的處理步驟中形成一更厚的導電層，如導電層218。在一實施方式中，內襯層214可使用CVD或PVD技術沉積形成一薄導電層，例如一薄層鈦、鉭、銅、錫、鉭、及/或類似物。例如，在一實施例中，共形襯墊層214包括一層以PVD程序沉積的鈦，其厚度為約200埃至約 1000埃。
此後，形成導電層218，使其厚度足以填充聚合物層106的開口108，如第2圖所繪。在一實施方式中，導電層218可為導電材料，諸如銅、鎢，或其它導電材料，通過例如電鍍、化學鍍或之類的方式形成。
圖3繪示出根據一實施例之晶粒安裝於載體320上。在實施方式中，晶粒形成為晶圓的一部分，各別晶粒可以通過鋸切、雷射或其組合，或類似方法沿著相鄰晶粒之間的劃線將其單片化。在一實施方式中，使用黏合劑將基板100安裝到載體320上。例如，載體320可包括晶粒附著膜(DAF)，而載體320可包括載體基板其具有DAF附接到其上。
第3圖繪示之單個晶粒置於載體320上僅係用於說明的目的。在其他實施方式中，可放置多個晶粒到載體320上，從而形成具有多個晶粒的單一封裝。在其他實施方式中，多個晶粒可安裝在載體320上後處理。處理之後，複數個晶粒可分成多個封裝體，其中每個封裝體包括一或多個單獨的晶粒。
之後，模塑材料322形成在基板100(例如一晶粒)上。模塑材料322包括一模塑化合物且可包括像是環氧樹脂、有機聚合物、或加入氧化矽基填料之聚合物。在一些實施方式中，模塑材料322包括液態模塑化合物(LMC)其係一種施用時凝膠型液體。或者，模塑材料322可包括其它絕緣材料。在一實施方式中，模塑材料322形成在導電層218 的頂表面上至一厚度為約40微米到約60微米。
在第4圖中，平面化程序，如研磨處理(例如，CMP或機械研磨)也可施作於模塑材料322和導電層218以形成柱體430。如第4圖所繪示，柱體430可具有一高度H1其高於導電墊102約2微米至約5微米之間。H1之低高度係部分可由形成模塑材料322於導電層218和聚合物層106上達成。模塑材料322和導電層218/聚合物層106之間的研磨速率差相對較大，所以導電層218/聚合物層106可作為研磨程序的停止層。因此，以前的系統由於控制研磨程序上困難，其柱體高度為約10微米(μm)；而如上面所述之方法則允許低得多的柱體高度，且因此允許一更小的封裝體。在一實施例中，柱體430具有一暴露表面寬度W1約5微米至約40微米。
第5圖繪示根據一實施方式形成RDL 532和外部連接器534電耦接到柱體430。第5圖繪示一實施方式，其中RDL 532係形成於兩個基板(例如，晶片)上並互連兩個基板，雖然可使用任意數量的晶片，例如一個晶片或三個或更多晶片。一般而言，RDL 532可包括一或多個導電層，其由金屬(例如鋁、銅、鎢、鈦，及其組合)製成，且其間層於介電層之間。RDL 532可藉由化學氣相沉積、電鍍、或無電鍍沉積金屬層，然後蝕刻掉不需要部分而留下RDL 532。RDL 532中金屬層的厚度可介於約1微米到約12微米之間。但是，其它的材料和製程，如眾所周知的鑲嵌程序(damascene process)亦可替代地用於形成RDL 532。
具選擇性地，在一實施方式中，RDL 532不僅可形成於晶片上，也可形成在模塑材料322上。藉由形成RDL 532於模塑材料322上，晶片之扇出區可延伸至晶片邊界之外，這還能夠增加I/O計數。
外部連接器534可接觸凸塊(像是微凸塊或受控塌陷晶片連接(C4)凸塊)，且可包括材料(如錫)或其它合適的材料(如銀或銅)。在實施方式中，外部連接器534係錫焊料凸塊，第二外部連接器534可通過任何合適的方法(像是蒸鍍、電鍍、印刷、焊料轉移(solder transfer)、焊球置放等等)先形成一種層錫形成。一旦錫層已形成於結構上，進行回流是為了塑形材料成所需的凸塊形狀。
因此，第5圖繪示一半導體裝置的實施方式，其具有一或多個基板100，例如積體電路晶粒、內插器或類似物，具於其上具有聚合物層106。導電柱430及/或內襯214延伸通過聚合物層106，以提供電接觸至基片100各別的導電墊102，其中導電柱430具有隨著導電柱430延伸遠離基板100，傾斜遠離導電柱430中央的錐形側壁。模塑材料322位於相鄰的基板100之間並沿著外週邊。RDL 532覆蓋在基板100及/或模塑材料322上，且外部連接器534電耦合至RDL 532以提供電連接給基板100。
第6-10圖繪示根據另一實施方式的製造半導體裝置且其中形成薄柱體的各個中間階段。第6-10圖使用類似的層和材料，其中類似的圖式符號表示類似的元件。首先參照第6圖，其繪示具有導電墊102的基板100，並在其上 形成鈍化層104。基板100、導電墊102及鈍化層104可使用如上討論之類似方法和材料形成。
其中，參照上面第1-5圖繪示之實施方式柱體430在形成聚合物層106之後形成，而在第6圖中所繪示的實施方式係在形成聚合物層106之前形成柱體640。在一實施方式中，柱體640的形成係藉由沉積一種晶層，沉積一個罩幕層，圖案化罩幕層來定義對應各個柱體640的開口，形成柱體，並除去罩幕層和過量的種子層材料。
例如，在形成鈍化層104之後，共形種子層沉積在鈍化層104的表面上及導電墊102暴露的部分。種子層是薄層導電性材料，其有助於在在後續的處理步驟中形成較厚的層。在一實施方式中，種晶層可使用CVD或PVD技術通過沉積形成一薄導電層，例如一薄層銅、鈦、鉭、氮化鈦、氮化鉭及/或類似物。舉例而言，在一實施方式中，種晶層包括以PVD程序沉積一層鈦和以PVD程序沉積一層銅。
其後，圖案化罩幕形成於種晶層且圖案化以形成對應於期望的形狀和放置柱體640的開口，使得圖案化罩幕作為一塑模用於在後續處理步驟形成柱體。圖案化罩幕可為圖案化的光阻罩幕、硬罩幕或類似物。如柱體640的形狀所顯示，圖案化罩幕具有之圖案，其中，開孔的寬度隨著開口延伸遠離導電墊102減少。在一實施例中，圖案化罩幕包括光阻(PR)材料，而處理的條件，例如曝光和顯影，可以控制其中的PR的交聯在頂部較強而在底部較弱。因此，隨著開口延伸入圖案化罩幕中，顯影後開口的尺寸增大。在一 實施方式中，開口的側壁是垂直或傾斜的，以提供相對於基板100的主表面上具有約0°至約10°側壁角度的柱體，如第6圖繪示。
然後以電鍍、無電鍍等或使用導電材料，如銅、鎢、或其它導電材料，形成導電柱體640於圖案化罩幕掩模的開口中。
在形成柱體640之後，移除圖案化罩幕和過量的種子層材料。在一實施方式中，該圖案化罩幕是一光阻，O2電漿灰化處理或濕式剝除處理可用於去除此圖案化罩幕。種晶層的暴露部分可通過例如濕蝕刻處理除去，如濕浸在磷酸(H3PO4)和過氧化氫(H2O2)的化學溶液(稱DPP)中，用2%的氫氟酸酸(HF)，或其他清洗處理也可使用。選擇性地，濕浸在硫酸(H2SO4)溶液中可用於清洗晶圓並除去剩餘的光阻材料。
現在參考第7圖，聚合物層106形成在鈍化層104和柱體640上。在一實施方式中，形成聚合物層106至其厚度足以覆蓋柱體640。如下面將進行之更詳細地說明，聚合物層106在平坦化或研磨處理中將被用來作為一停止層中。將藉由控制過蝕刻處理，柱體640上的聚合物層106將被除去而不除去柱體640的主要部分。這樣的技術因此允許較薄的柱體。
聚合物層106可使用如上述類似的工藝和材料來形成。
第8圖繪示根據一實施方式安裝晶粒到載體 320。在實施方式中，晶粒形成為晶圓的一部分，各個晶粒可沿著相鄰晶粒之間的劃線，以鋸切、雷射或其組合等成為單片。在一實施方式中，基板100安裝到載體320上。
類似於第3圖，第8圖繪示單一晶粒置放於載體320上僅係用於說明之目的。在其他實施方式中，多個晶粒可放置到載體320上，藉以形成具有多個晶粒的單一封裝體。在其他實施方式中，多個晶粒可安裝在載體320並經處理。處理之後，複數個晶粒可分成多個封裝體，其中每個封裝體包括一或多個單獨的晶粒。
然後，模塑材料322形成於基板100(如晶粒)上。可使用如上面討論的類似方法和材料來形成模塑材料322。在一實施方式中，模塑材料322形成於聚合物層106的頂表面上，其厚度為約40微米至約60微米。
第9圖繪示之裝置係已對模塑材料322和聚合物層106進行平坦化處理如研磨處理(例如CMP或機械研磨)以暴露柱體640。聚合物層106作為平坦化或研磨處理之停止層，以去除模塑材料322。過蝕刻處理經控制，以致柱體640上的聚合物層106被除去而不除去柱體640的主要部分，從而允許使用更薄的柱體。
舉例來說，如第9圖所繪示，柱體640可具有高度H1，其較導電墊102高出介於約2微米和約5微米之間，而上表面寬度W1約5微米至約40微米。低的高度H1部分可由形成模塑材料322於聚合物層106上達成。模塑材料322和聚合物層106間的研磨速率差相對較大，使得聚合物層 106作為研磨處理之停止層。因此，以前的系統由於在控制研磨處理的困難其具有約10微米的柱體高度，而如上面討論的方法則允許低得多的柱體高度，且因此允許更小的封裝體。
第10圖繪示根據一實施方式形成RDL 532和外部連接器534電耦連到柱體640。RDL 532和外部連接器534可使用類似於上面所討論的方法和材料來形成。
因此，第10圖繪示半導體裝置的一實施方式，其具有一或多個基板100，例如積體電路晶粒、內插器等等，具有聚合物層106在基板上。導電柱640延伸穿過聚合物層106，以提供電接觸至各個基板100上的導電墊102，其中，導電柱430具有錐形的側壁隨著導電柱430延伸遠離基板100朝向導電柱430的中心傾斜。模塑材料322位於相鄰的基板100之間且沿外週邊。RDL 532覆蓋基板100及/或模塑材料322，而外部連接器534電耦接到RDL 532以提供電連接給基板100。
第11-13圖繪示根據另一實施方式形成半導體裝置的另一方法的各中間階段，半導體裝置具有薄柱體形成於其中。第11-13圖使用類似的層和材料，其中，類似的圖式符號表示類似的元件，並假定類似於上面參照第6圖的討論之處理已執行。因此，第11圖繪示參照上面所討論之第6圖的結構，除了柱體的高度可大於下面所討論的，其具有模塑材料322形成於鈍化層104和導電柱640上。模塑材料322可使用如上述參照第8圖所討論之相似材料和方法形成。
第12圖繪示平坦化處理，像是研磨處理(例如化學機械拋光(CMP)或機械研磨)之後的裝置，已施作於模塑材料322以暴露柱體640。相較於上面參照第6-10圖討論的實施方式，此實施方式不利用聚合物層106，而是將模塑材料322形成在鈍化層104上。據此，在研磨過程中不能使用鈍化層104作為停止層。在一些實施方式中，可能需要增加柱體640的高度H1，像是高度H1為約2微米至約10微米以確保研磨過處理中有足夠的高度。應當指出的是，在此實施方式中柱體640的高度在研磨處理中，可能比利用聚合物層106的實施方式降低更多。在一實施方式中，柱體640具有的上表面寬度W1為約5微米至約40微米。
第13圖繪示根據一實施方式形成RDL 532和外部連接器534電耦接到柱體640。RDL 532和外部連接器534可使用如上所討論之類似方法和材料來形成。
因此，第13圖繪示具有一或多個基板100，例如積體電路晶粒、內插器等的半導體裝置之實施方式，而在基板100的連接側上具有模塑材料322。導電柱640延伸通過模塑材料322並沿著基板100的側壁，以提供電接觸至基板100的各別導電墊102，其中導電柱640具有錐形的側壁隨著導電柱640延伸遠離基板100朝向導電柱640的中心傾斜。RDL 532覆蓋基板100及/或模塑材料322，而外部連接器534電耦合到RDL 532以提供電連接給基板100。
第14-17圖繪示根據另一實施例的製造半導體裝置之各種中間階段，其具有形成於其中的的薄通孔。第 14-17圖使用類似的層和材料，其中相似之圖式符號代表相似的元件。首先參照第14圖，其中繪示基板100有橢圓體凸塊1450形成於其上。在一實施方式中，橢圓體凸塊1450以例如化學鍍技術(electroless plating techniques)形成，以選擇性地形成橢圓體凸塊1450於導電墊102上並延伸於鈍化層104之相鄰表面上。由於鈍化層104是由成非導電材料形成，橢圓凸塊1450僅形成於導電墊102暴露出的部分。在一實施方式中中，橢圓凸塊1450係由導電材料如鎳、鈀、金、和銅形成，其厚度約3微米至約15微米。如第14圖中所繪示，在一實施方式中，橢圓凸塊1450較鈍化層104之上表面高出的高度a與橢圓體凸塊1450於鈍化層104上的重疊b量值的比值為約1：0.7至約1：1。
第15圖繪示模塑材料322形成於鈍化層104和橢圓體凸塊1450上。模塑材料322可使用如上面參照第8圖討論之相似材料和處理方法形成。
第16圖繪示平坦化處理，像是研磨處理(例如，CMP或機械研磨)之後的裝置，已施作模塑材料322以暴露部分的橢圓體凸塊1450。在一些實施方式中，橢圓體凸塊1450的上部平坦化成為研磨處理過程的一部分，如第16圖所繪示。
在實施方式中，研磨處理後橢圓體凸塊1450高過鈍化層104上表面的高度a`與於鈍化層104上橢圓體凸塊1450的重疊量b之比值為約1：1至約1：1.4。在一實施方式中，橢圓體凸塊1450高過導電墊102的高度H1為約2微米 至約5微米，上表面的寬度W1為約5微米至約40微米。
第17圖繪示根據一實施方式形成RDL 532和外部連接器534的電耦接至橢圓體凸塊1450。RDL 532和外部連接器534可使用如上所討論類似的方法和材料來形成。
因此，第17圖繪示半導體裝置的實施方式，其具有一或多個基板100，例如積體電路晶粒、內插器等等，且在基板100的連接側上具有模塑材料322並沿著基板100的側壁。橢圓體凸塊1450延伸通過模塑材料322，以提供電接觸給基板100之各別的導電墊102。RDL 532覆蓋基板100及/或模塑材料322，而外部連接器534電耦接到RDL 532以提供電連接給基板100。
第18圖繪示根據一實施方式形成半導體裝置的方法之流程圖。方法於步驟1802開始，其中提供一個工件具有開口暴露出下層的導電墊，像是上面參照第1圖討論的。接下來，在步驟1804中內襯層和導電層形成於聚合物層上且形成於聚合物層的開口中，如上面參照第2圖所討論的。在步驟1806中，各個晶粒放置於載體上並模塑材料形成於晶粒上，如上面參照第3圖的討論。此後，在步驟1808中，進行平坦化處理以移除多餘部分的模塑材料和導電層，以形成柱體，如上面參照第4圖的討論。在步驟1810形成一或多重分佈層和外部連接，如上面參照第5圖的討論。
第19圖繪示根據一實施方式形成半導體裝置的方法的流程圖。方法開始於步驟1902，其中提供一工件 具有柱體形成於其上，如上面參照第6圖的討論。接著，在步驟1904，聚合物層形成於柱體上，如上面參考第7圖的討論。在步驟1906中，各個晶粒放置於載體上並形成模塑材料於晶粒上，如上面參照第8圖的討論。
之後，在步驟1908中，進行平坦化處理以除去模塑材料和聚合物層的多餘部分以暴露柱體，如上面參照第9圖的討論。在步驟1910中形成一或多個重分佈層和外部連接，如上面參照第10圖所討論的。
第20圖繪示根據一實施方式形成半導體裝置的方法之流程圖。方法開始於步驟2002，其中提供一個工件具有柱體於其上形成，如上面參照第6圖的討論。接著，在步驟2004中，各個晶粒放置於載體上且模塑型材料形成於晶粒上，如上面參照第11圖的討論。之後，在步驟2006中，執行平坦化處理來去除多餘部分的模塑材料，以暴露柱體，如上面參照第12圖的討論。在步驟2008中，形成一或多個重分佈層和外部連接，如上面參照第13圖的討論。
第21圖繪示根據一實施方式形成半導體裝置的方法之流程圖。此方法起始於步驟2102，其中提供一個工件具有鈍化層，鈍化層具有開口暴露出下層的導電墊，如上面參照第14圖的討論。接著，在步驟2104中，導電性凸塊形成於導電墊的暴露部分，如上面參照第14圖的討論。在步驟2106中，各個晶粒放置於載體上且模塑材料形成在晶粒上，如上面參照第15圖的討論。之後，在步驟2108中，執行平坦化處理以去除模塑材料的多餘部分，並暴露導電凸 塊，如上面參照第16圖的討論。在步驟2110中，形成一或多個重分佈層和外部連接，如上面參照第17圖的討論。
在一實施方式中，提供了一種形成裝置的方法。此方法包括提供晶粒，具有鈍化層形成在其上，並聚合物層在鈍化層上。晶粒還包括導電層於聚合物層上，導電層延伸通過鈍化層的和聚合物層的開口，使得導電層與之下導電墊電接觸。此晶粒安裝於載體上，而模塑化合物形成於晶粒的導電層上並沿著晶粒的側壁。在模塑化合物和晶粒的上表面進行平坦化處理，如研磨，以除去導電層上的聚合物層，並形成柱體從聚合物層延伸通過導電層。
在另一實施方式中，提供一種形成裝置的另一種方法。此方法包括提供晶粒，其上形成鈍化層，其中該鈍化層於其下的導電墊上具有開口。晶粒還具有導電柱延伸通過各別的開口且覆蓋導電柱之聚合物層。晶粒安裝於載體上，而模塑化合物形成於聚合物層上且沿著晶粒的側壁。對模塑化合物和聚合物層進行平坦化處理，以暴露導電柱。
在又一實施方式中，提供一種形成裝置的另一種方法。此方法包括提供晶粒，於其上形成鈍化層，鈍化層具有開口於導電墊上。晶粒進一步包括導電元件延伸穿過各別開口，並且延伸至鈍化層最上表面之上。晶粒安裝於載體上，而模塑化合物形成於晶粒的鈍化層上，並沿著晶粒的側壁。對模塑化合物的上表面進行平坦化處理，以暴露導電元件。
儘管本案內容及其優點已經詳細描述，但應該 理解的是，這裡可以作各種改變、替換和變更，而不脫離由所附請求項定義之本案的精神和範圍。此外，本案的範圍並非是要限定於說明書中描述的特定處理、機器、製造、和物質組成、手段，方法和步驟之具體實施方式。如本領域的通常技術人士將容易從本案的公開內容理解，處理、機器、製造、物質組成、手段、方法或步驟，當前存在或以後待開發，執行基本上相同的功能或實現基本相同的結果，以作為本文中所描述的對應實施方式而可根據本案加以利用。因此，所附請求項旨在包括它們的範圍於其中，像是處理、機器、製造、物質組成、手段、方法或步驟。
100‧‧‧基板
102‧‧‧導電墊
214‧‧‧內襯
320‧‧‧載體
322‧‧‧模塑材料
430‧‧‧導電柱
532‧‧‧重分佈層RDL
534‧‧‧外部連接器

Claims (10)

  1. 一種形成半導體裝置之方法，包含：提供一晶粒，具有一鈍化層形成在其上並且在該鈍化層上具有一聚合物層，該晶粒尚具有一導電層位於該聚合物層上，該導電層延伸通過在該鈍化層中和該聚合物層之開口，使得該導電層電性接觸底層之諸導電墊；安裝該晶粒於一載體上；形成一模塑化合物於該導電層上方並沿著該晶粒的側壁；以及平坦化該模塑化合物和該導電層，以除去該聚合物層上之該導電層並形成從該導電層延伸通過該聚合物層的諸柱體。
  2. 如請求項1所述之方法，其中該提供步驟包含：形成該鈍化層於該晶粒上，該鈍化層具有諸開口位於各別之該等導電墊之上；形成該聚合物層於該鈍化層上，該聚合物層具有諸開口位於各別之該等導電墊之上；形成一內襯於該聚合物層上且在該等開口中；以及形成該導電層於該內襯上，該導電層係與該等導電墊電性接觸。
  3. 如請求項1所述之方法，其中該提供步驟包含： 形成一層聚合物材料，以及圖案化該層聚合物材料以形成諸開口於各別的該等導電墊上，藉以形成該聚合物層，該等開口具有錐形側壁，其角度約5°至約30°。
  4. 如請求項1所述之方法，其中該平坦化步驟包括薄化該導電層至一高度較該導電墊高出約2微米至約5微米。
  5. 如請求項1所述之方法，其中該等柱體的寬度隨該柱體延伸遠離該導電墊而增加。
  6. 一種形成半導體裝置之方法，包含：提供一晶粒，其具有一鈍化層形成於其上，該鈍化層具有諸開口位於諸導電墊上，該晶粒尚具有諸導電柱延伸通過各別之該等開口以及具有一聚合物層覆蓋該等導電柱；安裝該晶粒於一載體上；形成一模塑化合物於該聚合物層上並沿著該晶粒的側壁；以及平坦化該模塑化合物的一上表面和該聚合物層以暴露該等導電柱。
  7. 如請求項6所述之方法，其中該等導電柱的寬度隨著該等導電柱延伸遠離該等導電墊而減小。
  8. 一種形成半導體裝置之方法，包含：提供一晶粒具有一鈍化層形成於其上，該鈍化層具有諸開口位於諸導電墊上，該晶粒尚具有諸導電元件延伸通過各別之該等開口，該等導電元件延伸至該鈍化層之一上表面；安裝該晶粒於一載體上；形成在該鈍化層並沿著該晶粒的側壁的模塑化合物；以及平坦化該模塑化合物的一上表面以暴露該等導電元件。
  9. 如請求項8所述之方法，其中該鈍化層上該等導電性凸塊的高度小於或等於該導電性凸塊與該鈍化層的一上表面重疊的距離。
  10. 如請求項8所述之方法，其中該等導電元件是柱體，具有傾斜側壁。
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