TWI546912B - 具有散熱結構之半導體封裝結構及其製造方法 - Google Patents

具有散熱結構之半導體封裝結構及其製造方法 Download PDF

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TWI546912B
TWI546912B TW102111040A TW102111040A TWI546912B TW I546912 B TWI546912 B TW I546912B TW 102111040 A TW102111040 A TW 102111040A TW 102111040 A TW102111040 A TW 102111040A TW I546912 B TWI546912 B TW I546912B
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wafer
package structure
semiconductor package
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connecting rod
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蔡甫擁
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日月光半導體製造股份有限公司
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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Description

具有散熱結構之半導體封裝結構及其製造方法
本發明係關於一種半導體封裝結構及其製造方法，詳言之，係關於具有散熱片之半導體封裝結構及其製造方法
扁平無接腳封裝結構(Flat No leads packages)，例如四邊扁平無接腳(Quad Flat No leads,QFN)封裝結構，操作上係耦合積體電路至印刷電路板。傳統四邊扁平無接腳(QFN)封裝結構包含一半導體晶片(Semiconductor Chip)、該晶片所在之一晶片承座(Die Pad)、複數條接合導線(Bonding Wires)、複數個引腳(Leads)及一封裝體(Package Body)。該等接合導線電性連接該晶片至該等引腳之上表面。該等引腳之下表面顯露於該封裝體之外且作為該四邊扁平無接腳(QFN)封裝結構之外部接點。該等引腳大致上排列成一周圍陣列(Perimeter Array)而圍繞該晶片，以增加引腳密度。然而，該晶片係被該封裝體所包覆，該封裝體通常為不易導熱之材料。但是，該晶片在運作時會產生熱，且這些熱必須被排除掉，以避免降低該晶片之效能。因此，對傳統四邊扁平無接腳(QFN)封裝結構而言，散熱是一項重要的課題。
本發明之一實施例包括一種半導體封裝結構，其包含一晶片承座及至少一連接桿，該連接桿從該晶片承座向外延伸。至少一支撐部從該至少一連接桿延伸至一與該晶片承 座間隔之位置，且包含一上表面，其係高於該晶片承座之一上表面。複數個引腳圍繞該晶片承座，彼此電性絕緣，且與該晶片承座電性絕緣。一半導體晶片係位於該晶片承座上，且電性連接至該等引腳。一散熱片附著至該至少一支撐部之上表面。一封膠材料封裝該半導體晶片、該散熱片之至少一部份、該晶片承座之至少一部份、該連接桿之至少一部份、該支撐部之至少一部份及每一該等引腳之至少一部份。
本發明之另一實施例包括一種半導體封裝結構，其包含一晶片承座及至少一連接桿，該連接桿從該晶片承座向外延伸。至少一支撐部從該至少一連接桿延伸，且位於與該晶片承座間隔之一末梢端。複數個引腳圍繞該晶片承座，彼此電性絕緣，且與該晶片承座電性絕緣。一半導體晶片位於該晶片承座上，且電性連接至該等引腳。一散熱片附著至該至少一支撐部之上表面。該散熱片包含一主體及至少一支腳。一封膠材料封裝該半導體晶片、該散熱片之至少一部份、該晶片承座之至少一部份、該連接桿之至少一部份、該支撐部之至少一部份及每一該等引腳之至少一部份。該半導體晶片之散熱路徑包括從該晶片承座經由該至少一連接桿，經由該至少一支撐部，經由該至少一支腳，及經由該主體。
本發明之另一實施例包括一種半導體封裝結構之製造方法。該方法包括提供一金屬板，其包含一基材、一中心突部、複數個周圍突部、複數個支撐突部、一第一金屬層及 一第二金屬層。該基材具有複數個連接部，連接該中心突部及該等支撐突部。該中心突部具有一上表面且從該基材向上延伸以定義出一空腔。每一該等周圍突部具有一上表面且從該基材向上延伸，且圍繞該中心突部。每一該等支撐突部具有一上表面且從該基材向上延伸，且圍繞該中心突部。該第一金屬層係位於該中心突部之上表面、該等周圍突部之上表面及該等支撐突部之上表面。該第二金屬層係形成於該金屬板之下表面，且位於該空腔、該中心突部、該等連接部、該等支撐突部及該等周圍突部之下方。該方法更包括固設一半導體晶片於該空腔中。該方法更包括電性連接該半導體晶片至該等周圍突部。該方法更包括固設一散熱片至該金屬板。該散熱片包含一主體及複數個支腳。該主體係位於該半導體晶片上方，且該等支腳從該主體延伸且被該等支撐突部所支撐。該方法更包括形成一封膠材料於該金屬板上，以包覆該半導體晶片、該散熱片、該中心突部、該等周圍突部、該等支撐突部及該第一金屬層。該方法更包括蝕刻該金屬板之下表面，以形成一晶片承座、複數個連接桿、複數個支撐部及複數個引腳。該等連接桿連接該晶片承座及該等支撐部，且該等引腳圍繞該晶片承座，彼此電性絕緣，且與該晶片承座電性絕緣。
參考圖1-3，分別顯示本發明半導體封裝結構1之一實施例之俯視、剖視及仰視示意圖。圖2所示之半導體封裝結 構1之剖視示意圖係沿著圖1之線2-2。該半導體封裝結構1包括一晶片承座12(Die Pad)、至少一連接桿(Connecting Bar)14、至少一支撐部(Supporting Portion)16、複數個引腳(Leads)18、一半導體晶片(Semiconductor Chip)20、一封膠材料(Molding Compound)22、複數條接合導線(Bonding Wires)28及一散熱片(Heat Sink)3。為了便於說明，圖1省略了圖2之該等接合導線28及該封膠材料22。
參考圖1，該晶片承座12包括一外緣區域121，其定義出該半導體晶片20所在之一空腔126。該等引腳18圍繞該晶片承座12，且彼此電性絕緣，且與該晶片承座12電性絕緣。該支撐部16位於該半導體封裝結構1之角落。該連接桿14從該晶片承座12向外延伸，因此，該連接桿14連接該晶片承座12及該支撐部16。
該散熱片3包含一主體31及至少一支腳32。該主體31係位於該半導體晶片20上方。該支腳32從該主體31延伸，且位於該半導體封裝結構1之角落，且被該等支撐部16所支撐。
參考圖2，該晶片承座12包括一外緣區域121，其定義出該半導體晶片20所在之一空腔126。該外緣區域121可以完全圍繞該空腔126，或者，在其他實施例中，可以僅部分圍繞該空腔126。該晶片承座12更包含一外上側壁122、一下側壁123、一位於該等側壁122,123之接合處之尖端(Peak)127、一下表面128、一上表面124及一內上側壁125。該內上側壁125係鄰接該上表面124，且面朝向(Face Toward)該空腔126。該外上側壁122係鄰接該上表面124，且面反向(Face Away)該空腔126。該下側壁123係鄰接該外上側壁122，且面反向(Face Away)該空腔126。該等側壁122,123,125可以是直線狀或弧狀，且通常不垂直於該外緣區域121之上表面124。該外上側壁122及該下側壁123相交於該尖端127。
如上所述，該連接桿14連接該晶片承座12及該支撐部16。該連接桿14包含一上表面142及一下表面141，該上表面142及該下表面141係彼此相對。該上表面142之水平位置係低於該外緣區域121之上表面124，且和該晶片承座12之空腔126之底部共平面。該下表面141和該晶片承座12之下表面128共平面。
該支撐部16從該連接桿14延伸至一與該晶片承座12間隔之位置，且包含一上表面161、一上側壁162、一下側壁163、一位於該等側壁162,163之接合處之尖端164及一下表面165。較佳地，該支撐部16從該連接桿14延伸，且位於與該晶片承座12間隔之一末梢端。該上表面161係高於該晶片承座12之一上表面。該上側壁162係鄰接該上表面161，且面反向該晶片承座12。該下側壁163係鄰接該該上側壁162，且面反向該晶片承座12。該等側壁162,163可以是直線狀或弧狀，且通常不垂直於該上表面161。該上側壁162及該下側壁163相交於該尖端164。該下表面165和該晶片承座12之下表面128及該連接桿14之下表面141共平面。在本實施例中，該晶片承座12、該連接桿14及該支撐 部16係一體成型，然而，在其他實施例中，它們可以分別形成。該連接桿14之寬度和該支撐部16之寬度相同。或者，該連接桿14之寬度小於該支撐部16之寬度。
每一該等引腳18更包括一上表面181、一上側壁182、一下側壁183、一位於該等側壁182,183之接合處之尖端184及一下表面185。該上側壁182鄰接於該上表面181，且可以是直線狀或弧狀，且通常不垂直於該上表面181。該下側壁183鄰接於該下表面185，且可以是直線狀或弧狀，且通常不垂直於該下表面185。該上側壁182及該下側壁183相交於該尖端184。在本實施例中，該支撐部16之表面積係大於每一該等引腳18之表面積。然而，在其他實施例中，該支撐部16之表面積係等於或小於每一該等引腳18之表面積。
一第一金屬層24係分別位於該支撐部16、該等引腳18及該外緣區域121之上表面161,181,124。該第一金屬層24可以利用任何技術施加，例如電解電鍍(Electrolytic Plating)或無電電鍍(Electroless Plating)。該第一金屬層24可以包括，例如：一接觸該等上表面161,181,124之鎳層，及一覆蓋該鎳層之金層或鈀層。或者，該第一金屬層24可以包括一合金層，該合金層係為鎳及金與鈀二者或二者其中之一。理想的情況是，該第一金屬層24黏緊且可以供該等接合導線28有效地打線接合。
一第二金屬層26係分別位於該晶片承座12、該連接桿14、該支撐部16及該等引腳18之下表面128,141,165, 185。在本實施例中，該等下表面128,141,165係為共平面，且形成一整體下表面以供該第二金屬層26形成於其上。該第二金屬層26可以包括和上述該第一金屬層24相同之材料，且可以利用相同之技術施加。該第二金屬層26黏緊且保護該等下表面128,141,165,185以避免氧化及其他環境條件。
一黏膠層201固設該半導體晶片20於該晶片承座12之空腔126之底部。該黏膠層201可以是一導電或不導電黏性材料，例如銀膏或不導電環氧樹脂。該半導體晶片20之主動面係利用該等接合導線28電性連接至該等引腳18，且可以利用該等接合導線28電性連接至該外緣區域121用以接地。
該散熱片3包含該主體31及該等支腳32。該主體31及該等支腳32定義出一空間以容納該半導體晶片20，且該等支腳32係被該等支撐部16所支撐。在本實施例中，該等支腳32包含一彎曲部320以形成一第一部份321及一第二部份322。該第一部份321從該主體31延伸，且該第二部份322被該支撐部16所支撐而在該彎曲部320形成一夾角。
該封膠材料22封裝該半導體晶片20、該散熱片3、該晶片承座12之至少一部份、該連接桿14之至少一部份、該支撐部16之至少一部份及每一該等引腳18之至少一部份。該引腳18之下側壁183、該晶片承座12之下側壁123、該支撐部16之下側壁163及該連接桿14從該封膠材料22之下表面221向外延伸。在本實施例中，該散熱片3之主體31之上表 面311未被該封膠材料22所覆蓋，而顯露至空氣中。
參考圖3，在本實施例中，該半導體封裝結構1包含四根連接桿14及四個支撐部16，且該晶片承座12大致為矩形。圖3之剖面線表示該金屬層26顯露於該封膠材料22之外。
在該半導體封裝結構1，從該半導體晶片20散熱之路徑包括：從該晶片承座12經由該連接桿14，經由該支撐部16，經由該散熱片3之支腳32，且經由該散熱片3之主體31，上述元件之材料皆為熱的良導體，例如金屬。因此，該半導體晶片20之熱可以有效地向外發散。再者，每一該等支撐部16之垂直厚度大於該等連接桿14之垂直厚度，使得每一支撐部16之上表面161係高於該等連接桿14。這樣的高度可減少該等支腳32從該主體31向下延伸之長度，使得該散熱片3在該等支腳32之區域不需要彎折出銳角，藉此可減少製造成本。
在本實施例中，該等支撐部16其中之一可以和其他支撐部16具有不同的形狀及/或尺寸。此一支撐部16可以做為最終封裝結構之辨別標誌以便於在表面黏著(Surface Mounting)時正確的定位。
參考圖4至17，顯示本發明半導體封裝結構之製造方法之一實施例之步驟示意圖。參考圖4，該製程由一板體40開始，該板體40具有一上表面401及一下表面402。該板體40之材質可以是金屬，例如銅、銅合金、或其他任何材質。
參考圖5，施加一第一光阻層42於該板體40之上表面401 上，且施加一第二光阻層44於該板體40之下表面402上。該等光阻層42,44可以利用塗佈、印刷或其他適當技術以形成。該等光阻層42,44被圖案化，使得該第一光阻層42具有複數個第一開口421以顯露該板體40之上表面401之部分，且該第二光阻層44具有複數個第二開口441以顯露該板體40之下表面402之部分。該圖案化可以利用例如微影(Photolithography)或其他適當技術來達成。
參考圖6，該第一金屬層24係形成於該等第一開口421，且該第二金屬層26係形成於該等第二開口441。參考圖7，移除該第一光阻層42。參考圖8及圖9，圖9顯示圖8中沿著線9-9之剖視圖。利用該金屬層24作為遮罩，於該板體40之上表面401進行半蝕刻(Half Etching)製程，以形成一基材46、一中心突部48、複數個周圍突部50及複數個支撐突部52。圖8之剖面線表示該板體40已被半蝕刻。
參考圖9，該基材46具有複數個連接部14，用以連接該中心突部48及該等支撐突部52。每一該等連接部14包含一上表面142及一下表面141，該上表面142及該下表面141係彼此相對。該中心突部48具有一上表面481及一下表面482，且從該基材46向上延伸以定義出一空腔126。該連接部14之上表面142係低於該中心突部48之上表面481，且和該空腔126之底部共平面。該連接部14之下表面141係與該中心突部48之下表面482共平面。該中心突部48更具有一上側壁125，鄰接該上表面481，且面朝向該空腔126。每一該等周圍突部50具有一上表面501及一下表面502，從該 基材46向上延伸，且圍繞該中心突部48。每一該等支撐突部52具有一上表面521及一下表面522，從該基材46向上延伸，且圍繞該中心突部48。該第一金屬層24保留在該中心突部48之上表面481、該等周圍突部50之上表面501及該等支撐突部52之上表面521。該第二金屬層26保留在該金屬板40之下表面402，且位於該空腔126、該中心突部48之下表面482、該等連接部14下表面141、該等支撐突部52之下表面522及該等周圍突部50之下表面502之下方。接著，移除該第二光阻層44。
參考圖10，利用該黏膠層201附著該半導體晶片20於該空腔126之底部。參考圖11，該半導體晶片20之主動面202係利用該等接合導線28電性連接至該等周圍突部50及該中心突部48。
參考圖12至圖15，圖13顯示圖12中沿著線13-13之剖視圖，且圖15顯示圖14中沿著線15-15之剖視圖。該散熱片3係被置放於該板體40上，使得該主體31係位於該半導體晶片20上方，且該等支腳32之第二部份322被該等支撐突部52所支撐。該半導體晶片20係容置於該主體31及該支腳32所定義出之空間。該等支腳32之第二部份322係黏附至該等支撐突部52。
參考圖16，形成一封膠材料22於該板體40上，以包覆該半導體晶片20、該散熱片3、該中心突部48、該等周圍突部50、該等支撐突部52及該第一金屬層24。在本實施例中，在本實施例中，該散熱片3之主體31之上表面311未被 該封膠材料22所覆蓋，而顯露至空氣中。
參考圖17，利用該第二金屬層26作為遮罩，蝕刻該板體40之下表面402，以形成該晶片承座12、該等連接桿14、該等支撐部16及該等引腳18。在該蝕刻製程後，該等連接桿14連接該晶片承座12及該等支撐部16，且該等引腳18圍繞該晶片承座12，彼此電性絕緣，且與該晶片承座12電性絕緣。接著，進行單體化製程(Singulation Process)，例如切割(Sawing)，以製得如圖1所示之半導體封裝結構1。
惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
1‧‧‧本發明半導體封裝結構之一實施例
3‧‧‧散熱片
12‧‧‧晶片承座
14‧‧‧連接桿/連接部
16‧‧‧支撐部
18‧‧‧引腳
20‧‧‧半導體晶片
22‧‧‧封膠材料
24‧‧‧第一金屬層
26‧‧‧第二金屬層
28‧‧‧接合導線
31‧‧‧主體
32‧‧‧支腳
40‧‧‧板體
42‧‧‧第一光阻層
44‧‧‧第二光阻層
46‧‧‧基材
48‧‧‧中心突部
50‧‧‧周圍突部
52‧‧‧支撐突部
121‧‧‧外緣區域
122‧‧‧外上側壁
123‧‧‧下側壁
124‧‧‧上表面
125‧‧‧上側壁
125‧‧‧內上側壁
126‧‧‧空腔
127‧‧‧尖端
128‧‧‧下表面
141‧‧‧下表面
142‧‧‧上表面
161‧‧‧上表面
162‧‧‧上側壁
163‧‧‧下側壁
164‧‧‧尖端
165‧‧‧下表面
181‧‧‧上表面
182‧‧‧上側壁
183‧‧‧下側壁
184‧‧‧尖端
185‧‧‧下表面
201‧‧‧黏膠層
311‧‧‧上表面
320‧‧‧彎曲部
321‧‧‧第一部份
322‧‧‧第二部份
401‧‧‧上表面
402‧‧‧下表面
421‧‧‧第一開口
441‧‧‧第二開口
481‧‧‧上表面
482‧‧‧下表面
501‧‧‧上表面
502‧‧‧下表面
521‧‧‧上表面
522‧‧‧下表面
圖1顯示本發明半導體封裝結構之一實施例之俯視示意圖；圖2顯示圖1中沿著線2-2之剖視示意圖；圖3顯示圖1之半導體封裝結構之仰視示意圖；及圖4至17顯示本發明半導體封裝結構之製造方法之一實施例之步驟示意圖。
1‧‧‧本發明半導體封裝結構之一實施例
3‧‧‧散熱片
12‧‧‧晶片承座
14‧‧‧連接桿/連接部
16‧‧‧支撐部
18‧‧‧引腳
20‧‧‧半導體晶片
31‧‧‧主體
32‧‧‧支腳
121‧‧‧外緣區域
126‧‧‧空腔
320‧‧‧彎曲部
321‧‧‧第一部份
322‧‧‧第二部份

Claims (20)

  1. 一種半導體封裝結構，包括：晶片承座；至少一連接桿，從該晶片承座向外延伸；至少一支撐部，從該至少一連接桿延伸至與該晶片承座間隔之位置，且包含上表面，其係高於該晶片承座之上表面；複數個引腳，圍繞該晶片承座，彼此電性絕緣，且與該晶片承座電性絕緣；半導體晶片，位於該晶片承座上，且電性連接至該等引腳；散熱片，附著至該至少一支撐部之上表面；及封膠材料，封裝該半導體晶片、該散熱片之至少一部份、該晶片承座之至少一部份、該連接桿之至少一部份、該支撐部之至少一部份及每一該等引腳之至少一部份，其中該晶片承座、該連接桿及該支撐部係由金屬組成。
  2. 如請求項1之半導體封裝結構，其中該晶片承座包括外緣區域，定義出該半導體晶片所在之空腔。
  3. 如請求項1之半導體封裝結構，其中每一該等引腳包括：上表面；下表面； 上側壁，鄰接於該上表面：及下側壁，鄰接於該下表面；其中該封膠材料封裝該上側壁，且顯露該下側壁。
  4. 如請求項1之半導體封裝結構，其中該至少一連接桿之下表面係與該至少一支撐部之下表面共平面。
  5. 如請求項1之半導體封裝結構，其中該至少一連接桿從該封膠材料之下表面向外延伸。
  6. 如請求項1之半導體封裝結構，其中該至少一支撐部之表面積係大於每一該等引腳之表面積。
  7. 如請求項1之半導體封裝結構，其中該散熱片之上表面係顯露於該封膠材料之外。
  8. 如請求項1之半導體封裝結構，其中該至少一支撐部包括複數個支撐部，位於該半導體封裝結構之角落。
  9. 如請求項8之半導體封裝結構，其中該散熱片包含主體及複數個支腳，且該等支腳係附著至該等支撐部之上表面。
  10. 一種半導體封裝結構，包括：晶片承座；至少一連接桿，從該晶片承座向外延伸；至少一支撐部，從該至少一連接桿延伸，且位於與該晶片承座間隔之末梢端；複數個引腳，圍繞該晶片承座，彼此電性絕緣，且與該晶片承座電性絕緣；半導體晶片，位於該晶片承座上，且電性連接至該等 引腳；散熱片，附著至該至少一支撐部之上表面，該散熱片包含主體及至少一支腳；及封膠材料，封裝該半導體晶片、該散熱片之至少一部份、該晶片承座之至少一部份、該連接桿之至少一部份、該支撐部之至少一部份及每一該等引腳之至少一部份；其中該半導體晶片之散熱路徑包括從該晶片承座經由該至少一連接桿，經由該至少一支撐部，經由該至少一支腳，及經由該主體；及其中該晶片承座、該連接桿及該支撐部係由金屬組成。
  11. 如請求項10之半導體封裝結構，其中該晶片承座包括外緣區域，定義出該半導體晶片所在之空腔。
  12. 如請求項10之半導體封裝結構，其中每一該等引腳更包括上表面及下表面，鄰接於該上表面之上側壁，及鄰接於該下表面之下側壁，其中該封膠材料封裝該上側壁，且顯露該下側壁。
  13. 如請求項10之半導體封裝結構，其中該至少一連接桿之下表面係與該至少一支撐部之下表面共平面。
  14. 如請求項10之半導體封裝結構，其中該至少一連接桿從該封膠材料之下表面向外延伸。
  15. 如請求項10之半導體封裝結構，其中該至少一支撐部之表面積係大於每一該等引腳之表面積。
  16. 如請求項10之半導體封裝結構，其中該散熱片之主體之上表面係顯露於該封膠材料之外。
  17. 如請求項10之半導體封裝結構，其中該至少一支撐部包含上表面，其係高於該晶片承座之上表面。
  18. 一種半導體封裝結構之製造方法，包括以下步驟：(a)提供金屬板，其包含基材、中心突部、複數個周圍突部、複數個支撐突部、第一金屬層及第二金屬層，其中該基材具有複數個連接部，連接該中心突部及該等支撐突部，該中心突部具有上表面且從該基材向上延伸以定義出空腔，每一該等周圍突部具有上表面且從該基材向上延伸，且圍繞該中心突部，每一該等支撐突部具有上表面且從該基材向上延伸，且圍繞該中心突部，該第一金屬層係位於該中心突部之上表面、該等周圍突部之上表面及該等支撐突部之上表面，且該第二金屬層係形成於該金屬板之下表面，且位於該空腔、該中心突部、該等連接部、該等支撐突部及該等周圍突部之下方；(b)固設半導體晶片於該空腔中；(c)電性連接該半導體晶片至該等周圍突部；(d)固設散熱片至該金屬板，其中該散熱片包含主體及複數個支腳，該主體係位於該半導體晶片上方，且該等支腳從該主體延伸且被該等支撐突部所支撐；(e)形成封膠材料於該金屬板上，以包覆該半導體晶片、該散熱片、該中心突部、該等周圍突部、該等支撐突 部及該第一金屬層；及(f)蝕刻該金屬板之下表面，以形成晶片承座、複數個連接桿、複數個支撐部及複數個引腳，其中該等連接桿連接該晶片承座及該等支撐部，且該等引腳圍繞該晶片承座，彼此電性絕緣，且與該晶片承座電性絕緣。
  19. 如請求項18之方法，其中該步驟(b)中，該半導體晶片係黏附於該空腔中，且該步驟(c)中，該半導體晶片係利用複數條接合導線電性連接至該等周圍突部。
  20. 如請求項18之方法，其中該步驟(e)中，該散熱片之主體之上表面係顯露。
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