TWI530241B - A multi - layer circuit board manufacturing method for embedded electronic components - Google Patents
A multi - layer circuit board manufacturing method for embedded electronic components Download PDFInfo
- Publication number
- TWI530241B TWI530241B TW099107672A TW99107672A TWI530241B TW I530241 B TWI530241 B TW I530241B TW 099107672 A TW099107672 A TW 099107672A TW 99107672 A TW99107672 A TW 99107672A TW I530241 B TWI530241 B TW I530241B
- Authority
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- Taiwan
- Prior art keywords
- layer
- copper foil
- electronic component
- circuit board
- dielectric
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- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 239000010410 layer Substances 0.000 claims description 266
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 124
- 239000011889 copper foil Substances 0.000 claims description 107
- 239000000758 substrate Substances 0.000 claims description 88
- 238000000034 method Methods 0.000 claims description 44
- 229910052802 copper Inorganic materials 0.000 claims description 17
- 239000010949 copper Substances 0.000 claims description 17
- 230000001681 protective effect Effects 0.000 claims description 13
- 239000012790 adhesive layer Substances 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- 238000011161 development Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 6
- 229920006267 polyester film Polymers 0.000 claims description 6
- 239000003365 glass fiber Substances 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 239000010408 film Substances 0.000 description 14
- 239000000853 adhesive Substances 0.000 description 11
- 230000001070 adhesive effect Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 239000003292 glue Substances 0.000 description 9
- 239000004033 plastic Substances 0.000 description 9
- 238000012545 processing Methods 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 5
- 239000011888 foil Substances 0.000 description 5
- 239000007788 liquid Substances 0.000 description 5
- 238000003825 pressing Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000003139 buffering effect Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229920000768 polyamine Polymers 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- SUKJFIGYRHOWBL-UHFFFAOYSA-N sodium hypochlorite Chemical compound [Na+].Cl[O-] SUKJFIGYRHOWBL-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10106—Light emitting diode [LED]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/063—Lamination of preperforated insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明係一種多層電路板之製造方法,尤指關於一種內埋有電子元件之多層電路板製造方法。
按,快速及高密度兩項要求一直是高科技發展之驅動力,目的是除了可以降低生產成本外,最重要的還是要滿足消費者需求,因而電子產品與行動通訊產品朝著輕薄短小、多功能、高可靠度與低價化,正以每三、五年一個世代的速度進行著;順應這個趨勢,在電子產品的電路設計中,面積佔據最大的被動元件也正在進行一整合化的革命。
在印刷電路板上,電子元件的體積所占用的面積是產品小型化最大的限制,再加上過多的焊接點除了降低系統的可靠度,也增加了產品製造成本,在強調高功能、小體積、重量輕的需求下,進一步希望能在有限的印刷電路板基板面積中,創造出更大的空間並提升模組的多功能性,因此,被動電子元件的整合及內埋化成重要發展趨勢。
為解決上述課題,如中華民國專利公告:第518616號「製作內嵌被動元件之多層電路板方法」,係以整合製成多種膜狀電子元件於一多層電路板中;其關鍵除了是將電路板內埋此類厚膜或薄膜電子元件的製程能力,該電子元件在整合於多層電路板中後,如何保持其良好的電性精確度,及如何將與原先設計值之間的差異降到最小,因此整體之製程會較複雜。
上述不利條件是市場上目前所熟知共見。
又,如中華民國專利公告:第I246383號「內埋被動元件之多層電路板之製造方法」,係提供一導電箔,該導電箔具有至少一對金屬凸點;將一被動元件接合於對應之金屬凸點;疊合一有機絕緣層於一核心板上;將該導電箔疊合於該有機絕緣層上;以及在該導電箔形成與被動元件連接之電路圖案;惟當已接合有該被動元件之該導電箔疊合於該有機絕緣層上時,由於該被動元件具有一定高度,於熱壓過程中,該有機絕緣層會直接對元件受壓而有損壞的風險,進而影響產品可靠度。
發明人有鑑上述製法於實施時之缺失,爰精心研究,再進一步發展出本案一種內埋電子元件之多層電路板製造方法。
本發明之一目的,在提供一種內埋電子元件之多層電路板製造方法,其係於有限銅箔層基材空間中,得以容納更多電子元件以提高功能、減少體積及重量;其電子元件係為主、被動元件或發光元件等。
本發明之又一目的,在提供一種於進行後續增層電路時,可因介電層而增加受壓時之緩衝力道,以避免於製作過程中將內埋之電子元件因受壓而損壞。
本發明為達上述目的所採用之一技術手段:提供一載板,該載板至少包括有一銅箔層基材及第一介電層;該第一介電層係疊設於該銅箔層基材上,且已預先開設有貫通之透孔,該透孔之位置恰可容置電子元件;續疊設一第二介電層於該第一介電層及電子元件上,以完成一內埋有電子元件之基礎電路板,其第一、二介電層係以具可塑性之材料所構成;續於該基礎電路板上進行增層電路;該電子元件係與該增層電路呈電導通。
本發明為達上述目的所採用另一技術手段:提供一載板,該載板至少包括有一銅箔層基材及第一介電層;該第一介電層疊設於該銅箔層基材上,且該銅箔層基材上設有藉壓膜、曝光、顯影、蝕刻方式製作之電氣線路;該第一介電層係疊設於該銅箔層基材上,且已預先開設有貫通之透孔,該透孔之位置恰可容置電子元件;續疊設一第二介電層於該第一介電層及電子元件上,以完成一內埋有電子元件之基礎電路板;其第一、二介電層係以具可塑性之材料所構成;續於該基礎電路板上進行增層電路,再使該電子元件與該銅箔層基材之電氣線路或該電子元件與增層電路呈電導通。
本發明為達上述目的所採用之再一技術手段:提供一載板,該載板至少包括有一銅箔層基材及第一介電層;該第一介電層疊設於該銅箔層基材上,且該銅箔層基材上設有藉壓膜、曝光、顯影、蝕刻方式製作之電氣線路;且該電氣線路之特定位置上置入電子元件,並呈電導通;該第一介電層係疊設於該銅箔層基材上,且已預先開設有貫通之透孔,該透孔中係可容置該電子元件;續疊設一第二介電層於該第一介電層及電子元件上,以完成一內埋有電子元件之基礎電路板;其第一、二介電層係以具可塑性之材料所構成;續於該基礎電路板上進行增層電路,並使該電子元件與該銅箔層基材之電氣線路或後續增層電路呈電導通。
本發明為達上述目的所採用之又一技術手段:亦可於該銅箔層基材上先塗佈一保護膠層,並於該保護膠層上開設有開窗,該開窗為容置電子元件之用。
請參照第1a~1c圖所示,其係本發明一種內埋電子元件之多層電路板製造方法之主要實施方式,其製造方法包括有:如第1a圖所示,提供一載板1,其至少包括有一銅箔層基材10、第一介電層20;其中,該銅箔層基材10上置放有電子元件30;及其中,該第一介電層20疊設於該銅箔層基材10上,且已預先開設有貫通之透孔21,該透孔21之位置內恰可容置該電子元件30,於本實施例該第一介電層係呈一片狀體(該第一介電層亦可為單層或複數層片體相疊合而成);如第1b圖所示,續於該載板1上疊設第二介電層40,於本實施例該第二介電層呈一片狀體(該第二介電層亦可以單層或複數層片體相疊合而成),如此即完成一內埋有電子元件之基礎電路板100;如第1c圖所示,續,於該基礎電路板100外層(上/下層)進行增層電路層200之增層程序,並使該電子元件30與該基礎電路板100或該電子元件30與該增層電路層200呈電導通,以電連導通該基礎電路板100與該增層電路層200,如此即完成一內埋有電子元件之多層電路板。
上述之內埋電子元件之多層電路板製造方法:其中,
該銅箔層基材10為一銅箔層;或,該銅箔層基材10為一銅箔層貼覆於聚亞醯胺(Polyimide,簡稱PI)或玻璃纖維膠片(Prepreg,簡稱PP)等材質上所構成;或,該銅箔層基材10為將一銅箔層貼覆於一金屬板材上(如銅板或鋁板等金屬板材上);其中,該銅箔層基材10上設有電氣線路,其電氣線路於該銅箔層上藉由壓膜、曝光、顯影、蝕刻方式製作完成;其中,該電子元件30可為主、被動電子元件(如電阻、電容、電感、晶片);或為發光元件(如發光二極體等);其中,該第一、第二介電層20、40為具有可塑性之材質所構成,如高樹脂含量之聚酯膠片(Prepreg)、介電薄膜(Dielectric Film)以及聚酯膠片與介電薄膜組合之其中之一;如此,藉由該第一、二介電層20、40之可塑性質以緊密填塞與該電子元件30與該透孔21間之空隙,增加該電子元件30之固定強度;同樣地,於進行增層電路層200時,可增加受壓時之緩衝力道,並避免於製作過程中內埋之電子元件30因重力壓合而損壞。
再請參照第2a~2d圖示,其係基於上述主要實施方法之第一種變化,其製造方法包括有:其提供一載板1,該載板1至少包括有一銅箔層基材10及第一介電層20;如第2a圖所示,其中,該銅箔層基材10上設有藉由壓膜、曝光、顯影、蝕刻方式製作之電氣線路11(於本實施方式之銅箔層基材係將銅箔層貼覆於聚亞醯胺或玻璃纖維膠片等材質上);續於該銅箔層基材10上塗佈一層保護膠層50(於本實施例之保護膠層可為純膠、液態樹脂(如AD膠(adhesive gel)或IR-6油墨));且該保護膠層50經熟化後,再透過加工技術(如雷射加工)於特定位置開設至少一個開窗51,以使該開窗51處之該電氣線路11顯露出來;如第2b圖所示,續,將該電子元件30置入於該透孔21中,並使該電子元件30(該電子元件可為主、被動電子元件,如電阻、電容、電感、晶
片等)與該電氣線路11呈電導通;續,於該保護膠層50上疊合一第一介電層20,該第一介電層20上預先設有與該電子元件30相配合且貫通之透孔21,以使該透孔21穿套於該電子元件30;續,於該載板1上以壓合方式疊設一第二介電層40;如此即完成一內埋有電子元件之基礎電路板100;如第2c圖所示,續,於完成該基礎電路板100後,續於外層進行增層電路層200程序;其中,該增層電路層200可為預先已完成電氣線路後再疊合於該第二介電層40上;如此,再透過機械鑽孔鑽出貫通之導通孔201,並對該導通孔201進行化銅、通孔電鍍之程序,以電連導通該基礎電路板100與該增層電路層200,即完成一內埋有電子元件之多層電路板;或,如第2d圖所示,該增層電路層200可為一銅箔層,再以雷射方式將電子元件30上方之第二介電層40去除以形成一盲孔202,並對該盲孔202內部進行化銅及電鍍之程序,以形成該電子元件30與該增層電路層200電導通(於本實施中之基礎電路板100係以對稱方式實施);如此再透過機械鑽孔鑽出貫通之導通孔201,並對該導通孔201進行化銅、通孔電鍍之程序,以電連導通該基礎電路板100與該增層電路層200,即完成另一型態之內埋有電子元件之多層電路板;於上述實施方式中,該銅箔層基材10之表面可於塗佈該保護膠層50前先進行粗化程序(Conditioning),以增加表面之附著力;其中,該電子元件30置入於該開窗51前,係於該電氣線路11上與該電子元件30呈電導通之位置處可預先塗佈導電膠12,如此,使該電子元件30與電氣線路11之間具有結合力及導電性。
其中,該第一、二介電層20、40可由單層或複數層片體相疊合而成;其中,該第一、第二介電層20、40具有可塑性,為具有高樹脂含量之聚酯膠片(Prepreg)、介電薄膜(Dielectric Film)以及聚酯膠片與介電薄膜組
合之其中之一;如此,藉由該第一、二介電層20、40之可塑性質,可緊密填塞與該電子元件30間之空隙,以增加該電子元件30之固定強度;同樣地,該第二介電層40於進行該增層電路層200增層時,可增加受壓時之緩衝力道,並避免於製作過程中內埋之電子元件30因熱壓合而損壞。
如第2e圖所示,其中,該電子元件亦可為發光元件30a(如發光二極體),惟其與主、被動元件製造方法之不同:係於該第二介電層40上進行增層電路層200之增層時,該增層電路層200相對於該發光元件30a位置設有一開口203,以使該發光元件30a露出,而不被遮住;其中,該第二介電層40貼設於該發光元件30a上時,具有防止於壓合該增層電路層200時該第一介電層20之溢流;其中,於該發光元件30a與該電氣線路11之粘著可藉由導電膠12(銲錫)固定,並呈電導通。
再請參照第3a~3f圖所示,其係基於上述主要實施方法之第二種變化,其製造方法包括有:係提供一載板1,其至少包括有一銅箔層基材10及第一介電層20;如第3a圖所示,其中,該銅箔層基材10係將一銅箔層貼覆於一金屬板材上(如銅板或鋁板金屬板材上);續於該銅箔層基材10上塗佈一層保護膠層50(於本實施例之保護膠層可為純膠、液態樹脂(如AD膠或IR-6油墨));如第3b圖所示,續,於該保護膠層50上之特定位置塗佈黏著劑16(於本實施例為紅膠);續,將電子元件30(該電子元件可為主、被動電子元件,如電阻、電容、電感、晶片等)置放於該黏著劑16上,藉由該黏著劑16使該電子元件30緊密固定於該銅箔層基材10上之該保護膠層50;如第3c圖所示,續,於該保護膠層50上疊合一第一介電層20,且該第一介電層20上預先設有與該電子元件30相配合且貫通之透孔21,以使該透孔21穿套該電子元件30;其中該第一介電層20亦可由複數層片體相疊合而成;續,於該載板1上疊設一第二介電層40,如此即完成一內埋有
電子元件之基礎電路板100;續,於該第二介電層40上疊設一第二銅箔層基材10a(於本實施該第二銅箔層基材係與銅箔層基材之構成相同,且該第二銅箔層基材上具有銅箔層之一面係面向並貼設於該第二介電層上);續,將該基礎電路板100及第二銅箔層基材10a進行壓合程序;如第3d圖所示,續,於壓合程序後,將該基礎電路板100及第二銅箔層基材10a中之金屬板材部分移除;續,再以加工技術(如雷射加工)將相對於該電子元件30位置處之該第二介電層40及該保護膠層50分別開設盲孔41、開窗51,以使該電子元件30之電極端31顯露出來;續,對該銅箔層基材10及第二銅箔層基材10a銅箔層之該盲孔41及開窗51內部進行化銅及電鍍之程序,及進行電氣線路製作,以形成該電子元件30與該銅箔層基材10及第二銅箔層基材10a之電氣線路呈電導通;如第3e圖所示,同樣地,續,於該基礎電路板100上亦可同時疊設增層電路層200,並於該增層電路層200開設盲孔202及其內部進行化銅及電鍍之程序,以使該銅箔層基材10及第二銅箔層基材10a與該增層電路層200呈電氣線路導通,如此再透過機械鑽孔鑽出貫通之導通孔201,並對該導通孔201進行化銅、通孔電鍍之程序,以電連導通該基礎電路板100與該增層電路層200,即完成一內埋有電子元件之多層電路板;於上述實施方式中,該銅箔層基材10及第二銅箔層基材10a之表面可於塗佈該保護膠層50前進行粗化程序(Conditioning),以增加表面之附著力;其中,該保護膠層50經熟化後,可開設出一貫穿之固定孔14,且該第二銅箔層基材10a相對於該銅箔層基材10之固定孔14處亦開設有相對應之固定孔14a;該等固定孔14、14a係透過一固定件15(於本實施例係為铆釘)穿設固定;該固定件15並於移除該銅箔層基材10及第二銅箔層基材10a中之金屬板材部分時一併移除;其中,該第一、第二介電層20、40具有可塑性,係為具有高樹脂含量
之聚酯膠片(Prepreg)、介電薄膜(Dielectric Film)以及聚酯膠片與介電薄膜組合之其中之一;如此,藉由該第一、二介電層20、40之可塑性質,可緊密填塞與該電子元件30間之空隙,以增加該電子元件30之固定強度;同樣地,該第二介電層40於進行該增層電路層200時,可增加受壓時之緩衝力道,並避免於製作過程中內埋之電子元件30因熱壓合而損壞。
如第3f圖所示,其中,該電子元件亦可為發光元件30a,如發光二極體等,惟其與主、被動元件製造方法之不同:係於該第二介電層40上進行增層電路層200時,該增層電路層200相對於該發光元件30a位置設有一開口203,以使該發光元件30a露出,而不被遮住;再請參照第4a~4c圖所示,其係基於上述第二種變化之另一種實施方式,其最大之不同係在於:係提供一載板1,其至少包括有一銅箔層基材10及第一介電層20;其中,如第4a圖所示,其中,該銅箔層基材10亦係將一銅箔層貼覆於一金屬板材上(如銅板或鋁板等金屬板材上);續於該銅箔層基材10上塗佈一層保護膠層50(於本實施例之保護膠層可為純膠、液態樹脂(如AD膠或IR-6油墨));續,於該銅箔層基材10上塗佈有一層保護膠層50,且該保護膠層50經熟化後,再透過加工技術(如雷射加工)於特定位置開設至少一個開窗51,以使特定位置處之該電氣線路11顯露出來,再將該電子元件30之金屬端置入於該開窗51上,並使該電子元件30與該電氣線路11呈電導通;如第4b圖所示,續,於該保護膠層50上疊合一第一介電層20,且該第一介電層20上預先設有與該電子元件30相配合且貫通之透孔21,以使該透孔21穿套該電子元件30;於該載板1上疊設一第二介電層40,如此即完成一內埋有電子元件之基礎電路板100;續,於該第二介電層40上疊設一第二銅箔層基材10a(於本實施該第二銅箔層基材係與銅箔層基材之構成相同,且該第二銅箔層基材上具有銅箔層之一面係面向並貼設於該第二介電層上);
續,將該基礎電路板100及第二銅箔層基材10a進行壓合程序;如第4c圖所示,續,於壓合程序後,將該基礎電路板100及第二銅箔層基材10a中之金屬板材部分移除;續,對該銅箔層基材10及第二銅箔層基材10a之銅箔層進行增層電路層200之製作,並於該第二銅箔層基材10a與該增層電路層200開設盲孔202及其內部進行化銅及電鍍之程序,以使該第二銅箔層基材10a與該增層電路層200呈電氣線路導通;續,再透過機械鑽孔鑽出貫通之導通孔201,並對該導通孔201進行化銅、通孔電鍍之程序,以電連導通該基礎電路板100與該增層電路層200,即完成一內埋有電子元件之多層電路板;其中,該第二介電層40之貼設於該電子元件30上,具有防止進行增層電路層200增層壓合時該第一介電層20之溢流;其中,於該電子元件30與該電氣線路11之粘著可藉由導電膠12(銲錫)固定及呈電導通。
再請參照第5a~5c圖所示,其係基於上述第二種變化之再一種實施方式,其最大之不同係在於:係提供一載板1,其至少包括有一銅箔層基材10及第一介電層20;其中,如第5a圖所示,其中,該銅箔層基材10亦係將一銅箔層貼覆於一金屬板材上(如銅板或鋁板等金屬板材上);續於該銅箔層基材10上塗佈一層保護膠層50(於本實施例之保護膠層可為純膠、液態樹脂(如AD膠或IR-6油墨));續,於該銅箔層基材10上塗佈有一層保護膠層50,且該保護膠層50經熟化後,再透過加工技術(如雷射加工)於特定位置開設至少一個開窗51,以使特定位置處之該電氣線路11顯露出來,再將該發光元件30a置入於該開窗51中,並使該發光元件30a與該電氣線路11呈電導通;如第5b圖所示,續,於該保護膠層50上疊合一第一介電層20,且該第一介電層20上預先設有與該發光元件30a相配合且貫通之透孔21,以使
該透孔21穿套該發光元件30a;於該載板1上疊設一第二介電層40,如此即完成一內埋有電子元件之基礎電路板100;續,於該第二介電層40上疊設一第二銅箔層基材10a(於本實施該第二銅箔層基材係與銅箔層基材之構成相同,且該第二銅箔層基材上具有銅箔層之一面係面向並貼設於該第二介電層上);續,將該基礎電路板100及第二銅箔層基材10a進行壓合程序;如第5c圖所示,續,於壓合程序後,將該基礎電路板100及第二銅箔層基材10a中之金屬板材部分移除;續,對該銅箔層基材10及第二銅箔層基材10a之銅箔層進行增層電路層200之製作;續,再透過機械鑽孔鑽出貫通之導通孔201,並對該導通孔201進行化銅、通孔電鍍之程序,以電連導通該基礎電路板100與該增層電路層200,即完成一內埋有發光元件之多層電路板;同樣地,於該第二介電層40上進行增層電路層200時,該增層電路層200相對於該發光元件30a位置設有一開口203,以使該發光元件30a露出而不被遮住;其中,該第二介電層40之貼設於該發光元件30a上,具有防止進行增層電路層200增層壓合時該第一介電層20之溢流;其中,於該發光元件30a與該電氣線路11之粘著可藉由導電膠12(銲錫)固定及呈電導通。
再請參照第6a~6d圖所示,其係基於上述之主要實施方法之第三種變化,於本實施係以對稱方式實施,其製造方法包括有:提供一載板1,其至少包括有一銅箔層基材10及第一介電層20;其中如第6a圖所示,該銅箔層基材10上設有藉由壓膜、曝光、顯影、蝕刻方式製作之電氣線路11(於本實施方式之銅箔層基材係將銅箔層貼覆於聚亞醯胺或玻璃纖維膠片等材質上);續,於該銅箔層基材10上塗佈一層保護膠層50(於本實施例之保護膠層可為純膠、液態樹脂(如AD膠或IR-6油墨));且該保護膠層50經熟化
後,再於特定位置處塗佈黏著劑16(於本實施例係為紅膠);續,將電子元件30(該電子元件可為主、被動電子元件,如電阻、電容、電感、晶片等)置於該黏著劑16上,藉由該黏著劑16以使該電子元件30緊密固定於該銅箔層基材10上;如第6b圖所示,續,於該保護膠層50上疊合一第一介電層20,該第一介電層20上預先設有與該電子元件30相配合且貫通之透孔21,以使該透孔21穿套該電子元件30;其中該第一介電層20亦可由複數層片體相疊合而成;如第6c圖所示,續,於該載板1上疊設一第二介電層40,如此即完成一內埋有電子元件之基礎電路板100;其中該第二介電層40亦可由複數層片體相疊合而成;如第6d圖所示,續,於完成該基礎電路板100後於該第二介電層40上疊設一增層電路層200(於本實施例係為一銅箔層),再以雷射方式將電子元件30上方之第二介電層40去除以形成一盲孔202,並對該盲孔202內部進行化銅及電鍍之程序,以形成該電子元件30與該增層電路層200之電導通;如此再透過機械鑽孔鑽出貫通之導通孔201,並對該導通孔201進行化銅、通孔電鍍之程序,以電連導通該基礎電路板100與該增層電路層200,即完成一內埋有電子元件之多層電路板;於上述實施方式中,該銅箔層基材10之表面可於進行後續塗佈該保護膠層50前進行粗化程序(Conditioning),以增加表面之附著力;其中,該第一、第二介電層20、40具有可塑性,係為具有高樹脂含量之聚酯膠片(Prepreg)、介電薄膜(Dielectric Film)以及聚酯膠片與介電薄膜組合之其中之一;如此,藉由該第一、二介電層20、40之可塑性質,可緊密填塞與該電子元件30間之空隙,以增加該電子元件30之固定強度;同樣地,該第二介電層40於進行增層電路層製作時,可增加受壓時之緩衝力道,並可避免於製作過程中內埋之電子元件30因熱壓合而損壞。
綜上所述,本發明係一種內埋電子元件之多層電路板製造方法,在產
業上具有很大之利用價值,可改良習用技術之缺點,在使用上能增進效益及效率,充份符合發明專利之要件,為一合於實用之理想創作,故申請人爰依專利法之規定,向 鈞局提出發明專利申請,並懇請早日賜准本案專利,至感德便。
1‧‧‧載板
10‧‧‧銅箔層基材
10a‧‧‧第二銅箔層基材
11‧‧‧電氣線路
12‧‧‧導電膠
14、14a‧‧‧固定孔
15‧‧‧固定件
16‧‧‧黏著劑
20‧‧‧第一介電層
21‧‧‧透孔
30‧‧‧電子元件
30a‧‧‧發光元件
31‧‧‧電極端
40‧‧‧第二介電層
50‧‧‧保護膠層
51‧‧‧開窗
100‧‧‧基礎電路板
200‧‧‧增層電路層
201‧‧‧導通孔
202‧‧‧盲孔
203‧‧‧開口
第1a~1c圖為本發明之主要實施方式之流程示意圖。
第2a~2e圖為本發明之第一實施方式之流程示意圖。
第3a~3f圖為本發明之第二實施方式之流程示意圖。
第4a~4c圖為本發明之第二實施方式另一變化流程示意圖。
第5a~5c圖為本發明之第二實施方式再一變化流程示意圖。
第6a~6d圖為本發明之第三實施方式之流程示意圖。
1...載板
10...銅箔層基材
20...第一介電層
21...透孔
30...電子元件
40...第二介電層
100...基礎電路板
200...增層電路層
201...導通孔
Claims (9)
- 一種內埋電子元件之多層電路板製造方法,其係提供:一載板,其包括有:一銅箔層基材,該銅箔層基材包括有銅箔層;及疊設一第一介電層於該銅箔層基材上,該第一介電層具有可塑性,且該第一介電層上預設有貫通之透孔;置放電子元件於該第一介電層貫通之透孔中;續壓合一第二介電層於該載板及該電子元件上,且該第二介電層係具有可塑性,如此即完成一基礎電路板;及續於該基礎電路板上增設增層電路層。
- 如申請專利範圍第1項所述之一種內埋電子元件之多層電路板製造方法,其銅箔層基材上設有電氣線路。
- 如申請專利範圍第1項所述之一種內埋電子元件之多層電路板製造方法,其銅箔層基材進一步包括有聚亞醯胺或玻璃纖維膠片所構成之基板,且該銅箔層係貼覆於該基板上。
- 如申請專利範圍第2項所述之一種內埋電子元件之多層電路板製造方法,其電氣線路係於該銅箔層基材上藉由壓膜、曝光、顯影、蝕刻方式製作完成。
- 如申請專利範圍第1項所述之一種內埋電子元件之多層電路板製造方法,其銅箔層基材上進一步塗佈有保護膠層。
- 如申請專利範圍第1項所述之一種內埋電子元件之多層電路板製造方法,其第一、第二介電層係為具有高樹脂含量之聚酯膠片(Prepreg)、介電薄膜(Dielectric Film)以及聚酯膠片與介電薄膜組合之其中之一。
- 如申請專利範圍第1項所述之一種內埋電子元件之多層電路板製造方法,其第一介電層或第二介電層係由複數層相疊合而成。
- 如申請專利範圍第1項所述之一種內埋電子元件之多層電路板製造方法,其增層電路層係以機械鑽孔鑽出貫通之導通孔,並對該導通孔進行 化銅、通孔電鍍之程序,以電連導通該基礎電路板與該增層電路層。
- 如申請專利範圍第1項所述之一種內埋電子元件之多層電路板製造方法,其電子元件為主、被動電子元件或發光元件。
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