TWI528423B - Methods for fabricating semiconductor device and semiconductor device - Google Patents
Methods for fabricating semiconductor device and semiconductor device Download PDFInfo
- Publication number
- TWI528423B TWI528423B TW100117201A TW100117201A TWI528423B TW I528423 B TWI528423 B TW I528423B TW 100117201 A TW100117201 A TW 100117201A TW 100117201 A TW100117201 A TW 100117201A TW I528423 B TWI528423 B TW I528423B
- Authority
- TW
- Taiwan
- Prior art keywords
- trench
- gate
- layer
- preparing
- runner
- Prior art date
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Description
本發明主要關於溝槽金屬氧化物半導體場效應管(MOSFET),更確切地說,是關於用於製備半導體元件的方法及半導體元件。 The present invention relates generally to trench metal oxide semiconductor field effect transistors (MOSFETs), and more particularly to methods and semiconductor components for fabricating semiconductor devices.
DMOS(雙擴散MOS)電晶體是一種利用兩個連續擴散技術,校準到同一邊緣上,以製備電晶體的通道區的電晶體。DMOS電晶體通常是用於低壓和高壓的高電流元件,用作獨立的電晶體或功率積體電路的組件。DMOS電晶體在很低的正向電壓降下,就能提供單位面積上很高的電流。 A DMOS (Double Diffusion MOS) transistor is a transistor that is calibrated to the same edge using two continuous diffusion techniques to produce the channel region of the transistor. DMOS transistors are typically high current components for low voltage and high voltage, used as components of separate transistors or power integrated circuits. DMOS transistors provide very high current per unit area at very low forward voltage drops.
典型的DMOS電晶體是一種稱為溝槽DMOS電晶體的電晶體,其中通道位於溝槽的側壁上,柵極形成在溝槽中,從源極開始,朝著漏極延伸。溝槽柵極佈滿薄氧化層,並用多晶矽填充,限制電流的能力次於平面柵極DMOS電晶體結構,因此其比導通電阻值較低。 A typical DMOS transistor is a transistor called a trench DMOS transistor in which the channel is on the sidewall of the trench and the gate is formed in the trench, starting from the source and extending toward the drain. The trench gate is covered with a thin oxide layer and filled with polysilicon, and the ability to limit current is inferior to the planar gate DMOS transistor structure, so its specific on-resistance is lower.
然而,製備這種溝槽DMOS場效應管的傳統方法需要五至六個掩膜技術,不僅昂貴,而且費時。第一個掩膜為深勢阱掩膜,也用於高壓截止。根據所製備的元件是否是高壓元件,來選擇是否使用該掩膜。第二個掩膜為溝槽掩膜,用於製備柵極和其他元件結構的溝槽。第三個掩膜為本體掩膜,也用於製備截止區,保護柵極 滑道中的柵極氧化物不會因為裸露在柵極電勢中而被破壞,並且遮罩柵極墊/柵極滑道遠離漏極電壓。第四個掩膜為源極掩膜,將源極區移出柵極滑道和截止區,從而將擊穿電流移出這些區域,提高非嵌位元感應開關(UIS)性能。第四個掩膜也用於製備通道終止。第五個掩膜為接觸掩膜,用於製備源極/本體和柵極接頭,第六個掩膜為金屬掩膜,用於將金屬層分成柵極和源極金屬區。 However, the conventional method of fabricating such a trench DMOS field effect transistor requires five to six masking techniques, which are not only expensive but also time consuming. The first mask is a deep well mask and is also used for high voltage cutoff. Whether or not to use the mask is selected depending on whether the prepared component is a high voltage component. The second mask is a trench mask used to fabricate trenches for gate and other component structures. The third mask is a bulk mask, which is also used to prepare the cut-off region and protect the gate. The gate oxide in the runner is not destroyed by being exposed to the gate potential, and the gate/gate trace is masked away from the drain voltage. The fourth mask is the source mask, moving the source region out of the gate runner and the cutoff region, thereby shifting the breakdown current out of these regions, improving the performance of the non-embedded sensor switch (UIS). The fourth mask is also used to prepare the channel termination. The fifth mask is a contact mask for preparing the source/body and gate contacts, and the sixth mask is a metal mask for separating the metal layer into gate and source metal regions.
第1圖表示溝槽MOSFET 100的剖面圖,該元件是利用上述傳統的六掩膜技術製成的。如第1圖所示,溝槽MOSFET100包含位於有源區中的有源晶胞102以及柵極滑道104。柵極滑道連接到有源晶胞102中的柵極上。P-反轉通道可能會沿N-外延層111的頂面,朝著晶片末端形成。如果P-反轉通道從結截止108開始,觸及晶片邊緣112,那麼就會在源極/本體和漏極之間,引起漏電流。重摻雜的N+通道終點106可以阻止這種p-反轉通道觸及晶片邊緣112,在晶片邊緣112處,它可以短接至漏極。 Figure 1 shows a cross-sectional view of trench MOSFET 100 fabricated using the conventional six mask technique described above. As shown in FIG. 1, trench MOSFET 100 includes active cell 102 and gate runner 104 in the active region. The gate runner is connected to the gate in the active cell 102. A P-inversion channel may be formed along the top surface of the N- epitaxial layer 111 toward the end of the wafer. If the P-inverting channel begins at junction stop 108 and touches wafer edge 112, then a leakage current is induced between the source/body and the drain. The heavily doped N+ channel end point 106 prevents such p-reverse channels from reaching the wafer edge 112, where it can be shorted to the drain.
本發明的目的是提供一種用於製備半導體元件的方法及半導體元件,以降低成本、簡化製作技術。 It is an object of the present invention to provide a method and a semiconductor element for fabricating a semiconductor device to reduce cost and simplify fabrication techniques.
本發明的技術方案是提供一種用於製備半導體元件的方法,包含:a)製備半導體襯底;b)在半導體襯底上方使用第一掩膜;並分別形成寬度為W1、W2的溝槽TR1、TR2,其中W1比W2窄,其中溝槽TR2包含連接到溝槽TR1上的第一柵極滑道溝槽和第二柵極滑 道溝槽,其中第一柵極滑道溝槽和第二柵極滑道溝槽中的至少一個緊靠並包圍著溝槽TR1;c)在厚度為T1、T2的溝槽TR1、TR2的底部和側壁上製備柵極絕緣物,其中T2大於T1;d)在溝槽TR1中製備導電材料,以形成柵極電極,在溝槽TR2中製備導電材料,以形成第一柵極滑道和第二柵極滑道以及截止結構,其中第一和第二柵極滑道與柵極電極電性連接;e)在半導體襯底的頂部製備一個本體層;f)在本體層的頂部製備一個源極層;g)在半導體襯底上方使用絕緣層;h)在絕緣層上方使用第二掩膜;i)利用第二掩膜,藉由絕緣層中的接觸開口形成電接頭,其中接觸開口包含在每個柵極電極附近的向著源極層的源極開口、向著柵極滑道的柵極滑道開口、向著截止結構的截止接觸開口以及晶片邊緣附近的向著源極層或本體層的短路接觸開口;以及j)在絕緣層上製備第一金屬區和第二金屬區,並且相互電性絕緣,其中第一金屬區與柵極滑道電連接,其中第二金屬區與源極接頭電連接,其中厚度T2足夠厚,能夠承載閉鎖電壓。 A technical solution of the present invention is to provide a method for fabricating a semiconductor device, comprising: a) preparing a semiconductor substrate; b) using a first mask over the semiconductor substrate; and forming trenches TR1 having widths W1, W2, respectively , TR2, wherein W1 is narrower than W2, wherein the trench TR2 includes a first gate runner trench and a second gate slip connected to the trench TR1 a trench, wherein at least one of the first gate runner trench and the second gate runner trench abuts and surrounds the trench TR1; c) at the trenches TR1, TR2 of thickness T1, T2 A gate insulator is prepared on the bottom and sidewalls, wherein T2 is greater than T1; d) a conductive material is prepared in trench TR1 to form a gate electrode, and a conductive material is prepared in trench TR2 to form a first gate runner and a second gate runner and a cutoff structure, wherein the first and second gate runners are electrically connected to the gate electrode; e) preparing a body layer on top of the semiconductor substrate; and f) preparing a top portion of the body layer a source layer; g) using an insulating layer over the semiconductor substrate; h) using a second mask over the insulating layer; i) using a second mask, forming an electrical contact by a contact opening in the insulating layer, wherein the contact opening Included in each of the gate electrodes is a source opening toward the source layer, a gate runner opening toward the gate runner, a cutoff contact opening toward the cutoff structure, and a source layer or body layer near the edge of the wafer Shorting the contact opening; and j) preparing the first metal region on the insulating layer A second metal region, and electrically insulated from each other, wherein the first metal runner and the gate region is electrically connected, wherein the second metal region and electrically connecting the source electrode, wherein a thickness T2 is thick enough, capable of carrying a blocking voltage.
以上所述的方法中:b)還包含製備寬度為W3的溝槽T3,其中W1比W3窄,其中溝槽TR3包含包圍著溝槽TR1和柵極滑道之溝槽TR2的截止溝槽;c)還包含在厚度為T3的溝槽TR3的底部和側壁上製備柵極絕緣物,其中T3大於T1; d)還包含在溝槽TR3中製備導電材料,以形成截止結構,其中截止結構與柵極滑道和柵極電極電絕緣;i)還包含利用第二掩膜,藉由絕緣層中的接觸開口,製備電接頭,其中接觸開口包含向著截止結構的截止接觸開口,以及晶片邊緣附近的向著源極層或本體層的短路接觸開口;以及j)還包含在絕緣層上製備第三金屬區,其中第三金屬區與截止接頭和短路接頭電連接,從而使截止結構在晶片邊緣處短接至本體區上,其中厚度T3足夠厚,能夠承載閉鎖電壓。 In the above method, b) further comprises preparing a trench T3 having a width W3, wherein W1 is narrower than W3, wherein the trench TR3 comprises a cut-off trench surrounding the trench TR2 and the trench TR2 of the gate runner; c) further comprising preparing a gate insulator on the bottom and sidewalls of the trench TR3 having a thickness T3, wherein T3 is greater than T1; d) further comprising preparing a conductive material in the trench TR3 to form a cutoff structure, wherein the cutoff structure is electrically insulated from the gate runner and the gate electrode; i) further comprising utilizing the second mask by contact in the insulating layer Opening, the electrical connector is prepared, wherein the contact opening comprises a cut-off contact opening toward the cut-off structure, and a short-circuit contact opening toward the source layer or the body layer near the edge of the wafer; and j) further comprising preparing a third metal region on the insulating layer, Wherein the third metal region is electrically connected to the cutoff joint and the shorting joint such that the cutoff structure is shorted to the body region at the edge of the wafer, wherein the thickness T3 is sufficiently thick to carry the latching voltage.
以上所述的方法中,步驟e)包含:在整個半導體襯底的頂部製備一個本體層。 In the method described above, step e) comprises: preparing a body layer on top of the entire semiconductor substrate.
以上所述的方法中,步驟j)包含:在絕緣層上方沉積一個金屬層;在金屬層上方使用一個金屬掩膜;以及蝕刻金屬層,以分離第一金屬區和第二金屬區。 In the above method, the step j) comprises: depositing a metal layer over the insulating layer; using a metal mask over the metal layer; and etching the metal layer to separate the first metal region and the second metal region.
以上所述的方法中,步驟c)包含:在厚度為T1、T2的溝槽TR1、TR2的底部和側壁上,利用掩膜製備柵極絕緣層,其中T2大於T1。 In the above method, step c) comprises: preparing a gate insulating layer by using a mask on the bottom and sidewalls of the trenches TR1, TR2 having thicknesses T1, T2, wherein T2 is greater than T1.
以上所述的方法中,步驟c)包含:在溝槽TR1、TR2的底部和側壁,製備一個第一柵極絕緣物;在薄絕緣層上方使用柵極絕緣物掩膜,其中柵極絕緣物掩膜覆蓋溝槽TR2,但不覆蓋溝槽TR1;從半導體襯底上沒有被含有溝槽TR1的第二掩膜覆蓋的部分,除 去第一柵極絕緣物;以及在溝槽TR1中製備第二柵極絕緣物,其中第二柵極絕緣物比第一柵極絕緣物薄。 In the above method, step c) comprises: preparing a first gate insulator at the bottom and sidewalls of the trenches TR1, TR2; using a gate insulator mask over the thin insulating layer, wherein the gate insulator The mask covers the trench TR2 but does not cover the trench TR1; the portion of the semiconductor substrate that is not covered by the second mask containing the trench TR1 is removed Removing the first gate insulator; and preparing a second gate insulator in the trench TR1, wherein the second gate insulator is thinner than the first gate insulator.
以上所述的方法中,藉由在相當高的能量下植入離子,進行步驟e),在此能量下,離子可以穿過第二柵極絕緣物和第一柵極絕緣物,植入到半導體襯底中。 In the above method, by implanting ions at a relatively high energy, step e) is performed, at which the ions can pass through the second gate insulator and the first gate insulator, implanted into In a semiconductor substrate.
以上所述的方法中,藉由植入一定能量的離子,進行步驟f),該能量能使離子穿過第二柵極絕緣物,但不穿過第一柵極絕緣物,植入到半導體襯底中。 In the above method, by implanting ions of a certain energy, step f) is performed, which enables ions to pass through the second gate insulator but not through the first gate insulator and implanted into the semiconductor In the substrate.
以上所述的方法中,源極層僅僅形成在溝槽TR1附近的本體層的頂部中。 In the above described method, the source layer is formed only in the top of the body layer near the trench TR1.
以上所述的方法中,步驟c)包含:在溝槽TR1、TR2的底部和側壁,製備第一柵極絕緣物;製備犧牲材料,完全填充溝槽TR1,但僅僅內襯在溝槽TR2中;回刻犧牲材料,除去TR2上的犧牲材料,但保留TR1中的犧牲材料;在溝槽TR2中製備一個柵極絕緣層;以及除去溝槽TR1中的犧牲材料,在溝槽TR1中製備柵極絕緣物,其中溝槽TR2中的柵極絕緣層厚度T2大於溝槽TR1中的柵極絕緣層厚度T1。 In the above method, step c) comprises: preparing a first gate insulator at the bottom and sidewalls of the trenches TR1, TR2; preparing a sacrificial material, completely filling the trench TR1, but merely lining the trench TR2 Retrieving the sacrificial material, removing the sacrificial material on TR2, but retaining the sacrificial material in TR1; preparing a gate insulating layer in trench TR2; and removing the sacrificial material in trench TR1, preparing the gate in trench TR1 A pole insulator in which the gate insulating layer thickness T2 in the trench TR2 is larger than the gate insulating layer thickness T1 in the trench TR1.
以上所述的方法中,源極層形成在整個半導體的頂部中。 In the method described above, the source layer is formed in the top of the entire semiconductor.
以上所述的方法中,完成步驟a)到步驟j)所用的掩膜不超過四個。 In the above-described method, no more than four masks are used to complete steps a) through j).
以上所述的方法中,完成步驟a)到步驟j)所用的掩膜不超過三個。 In the above-described method, no more than three masks are used to complete steps a) through j).
以上所述的方法中:b)還包含製備寬度為W3的溝槽T3,其中W3大於W2,其中溝槽TR3含有包圍著溝槽TR1和柵極滑道溝槽TR2的截止溝槽;其中本方法還包含:用電介質填充溝槽TR3,其中寬度W3足以承載閉鎖電壓。 In the above method: b) further comprising preparing a trench T3 having a width W3, wherein W3 is greater than W2, wherein the trench TR3 comprises a cut-off trench surrounding the trench TR1 and the gate runner trench TR2; The method also includes filling the trench TR3 with a dielectric, wherein the width W3 is sufficient to carry the latching voltage.
以上所述的方法中步驟a)到步驟j)僅需要三個掩膜。 Only a mask is required for steps a) through j) in the method described above.
以上所述方法中,步驟b)還包含在溝槽TR2下方製備重摻雜的通道終止區。 In the above method, step b) further comprises preparing a heavily doped channel termination region under trench TR2.
本發明還提供了一種半導體元件,其包含:在柵極絕緣層上方的多個柵極電極,形成在有源溝槽中,位於半導體襯底的有源區中;形成在半導體襯底中的第一柵極滑道,並且電連接到柵極電極上,其中第一柵極滑道緊靠並包圍著有源區;連接到第一柵極滑道上的第二柵極滑道,用於連接柵極金屬;以及其中柵極滑道溝槽中的絕緣層各自的厚度T2大於有源溝槽中的柵極絕緣層的厚度T1,其中厚度T2足以承載閉鎖電壓。 The present invention also provides a semiconductor device comprising: a plurality of gate electrodes over a gate insulating layer, formed in an active trench, in an active region of a semiconductor substrate; formed in a semiconductor substrate a first gate runner and electrically connected to the gate electrode, wherein the first gate runner abuts and surrounds the active region; and the second gate runner is connected to the first gate runner for Connecting the gate metal; and wherein the thickness T2 of each of the insulating layers in the gate runner trenches is greater than the thickness T1 of the gate insulating layer in the active trenches, wherein the thickness T2 is sufficient to carry the latching voltage.
以上所述元件中,還包含:包圍著第一柵極滑道和第二柵極滑道以及有源區的截止結構,其中截止結構包含半導體襯底中佈滿絕緣物的溝槽中的導電材料,其中截止結構短接至晶片邊緣附近的 半導體襯底的源極或本體層,從而構成元件的通道終點。 The above-mentioned device further includes: a cut-off structure surrounding the first gate runner and the second gate runner and the active region, wherein the cut-off structure includes conductive in the trench covered with the insulator in the semiconductor substrate Material in which the cutoff structure is shorted to the vicinity of the edge of the wafer The source or body layer of the semiconductor substrate, thereby constituting the channel end point of the element.
以上所述元件中還包含:一個電介質填充的溝槽,它包圍著第一柵極滑道和第二柵極滑道以及有源區。 The above described components further include: a dielectric filled trench that surrounds the first gate runner and the second gate runner and the active region.
以上所述元件中還包含一個位於電介質填充溝槽下方的重摻雜通道終止區。 The above described components also include a heavily doped channel termination region under the dielectric filled trench.
以上所述的元件中半導體襯底包含有源區和截止區中的本體層。 The semiconductor substrate of the above-described elements includes an active region and a body layer in the cut-off region.
以上所述元件中半導體襯底含有一個源極區。 The semiconductor substrate in the above described device contains a source region.
以上所述元件中源極區僅位於有源區中。 The source regions in the above described components are only located in the active region.
以上所述元件中第一柵極滑道含有一個形成在溝槽下方的通道終止區。 The first gate runner of the above described components includes a channel termination region formed below the trench.
以上所述元件中半導體襯底還包含具有重摻雜底層和次重摻雜頂層的半導體襯底,其中第一柵極滑道溝槽足夠深,能夠觸及重摻雜底層。 The semiconductor substrate of the above described device further comprises a semiconductor substrate having a heavily doped underlayer and a sub-doped top layer, wherein the first gate runner trench is sufficiently deep to reach the heavily doped underlayer.
以上所述元件中在截止結構所述的佈滿絕緣物的溝槽中的絕緣物足夠厚,能夠承載閉鎖電壓。 The insulator in the trench filled with insulation described in the cut-off structure is sufficiently thick to carry the latching voltage.
100、200、300、700‧‧‧溝槽MOSFET 100, 200, 300, 700‧‧‧ trench MOSFET
102‧‧‧有源晶胞 102‧‧‧Active unit cell
104、204、206、304、306、527‧‧‧柵極滑道 104, 204, 206, 304, 306, 527‧‧‧ gate slides
106‧‧‧N+通道終點 106‧‧‧N+ channel end point
108‧‧‧結截止 108‧‧‧End
111、211、311、404、504、704‧‧‧外延層 111, 211, 311, 404, 504, 704‧‧ ‧ epitaxial layer
112、213、313、413、713‧‧‧晶片邊緣 112, 213, 313, 413, 713‧‧‧ wafer edge
202、302、410、412、414、416、510、512、514、516、710、712、714、716‧‧‧溝槽 202, 302, 410, 412, 414, 416, 510, 512, 514, 516, 710, 712, 714, 716 ‧ ‧ trench
204a、208a、308a‧‧‧寄生電晶體 204a, 208a, 308a‧‧‧ parasitic crystal
207、307、707、742、744‧‧‧接頭 207, 307, 707, 742, 744‧‧ joints
208、308、529‧‧‧截止結構 208, 308, 529‧‧‧ cut-off structure
210、310、711‧‧‧有源晶胞區 210, 310, 711‧‧‧ active cell area
212、312、432、528‧‧‧本體層 212, 312, 432, 528‧‧‧ body layer
214、314、434、530、736‧‧‧源極層 214, 314, 434, 530, 736‧‧‧ source layer
248、348、456、550、754‧‧‧柵極金屬層 248, 348, 456, 550, 754‧‧‧ gate metal layer
250、350‧‧‧縫隙 250, 350 ‧ ‧ gap
252、352、454、552、752‧‧‧源極金屬 252, 352, 454, 552, 752‧‧‧ source metal
254、354、458、548‧‧‧截止金屬 254, 354, 458, 548 ‧ ‧ cut-off metal
304a‧‧‧寄生p-通道電晶體 304a‧‧‧Parasitic p-channel transistor
402、502、702‧‧‧襯底 402, 502, 702‧‧ ‧ substrate
406、436、522、532‧‧‧絕緣層 406, 436, 522, 532‧‧ insulation
408、508‧‧‧第一掩膜 408, 508‧‧‧ first mask
418、518‧‧‧柵極絕緣層 418, 518‧‧‧ gate insulation
420、520‧‧‧犧牲材料 420, 520‧‧‧ sacrificial materials
422‧‧‧氮化層 422‧‧‧nitriding layer
424‧‧‧第二掩膜 424‧‧‧second mask
426‧‧‧犧牲絕緣物 426‧‧‧ Sacrificial insulation
428、523、524‧‧‧柵極絕緣物 428, 523, 524‧‧‧ Grid insulators
430、526‧‧‧導電材料 430, 526‧‧‧ conductive materials
438、534、740‧‧‧接觸掩膜 438, 534, 740 ‧ ‧ contact mask
442、444、445、446、536、538、540、541、542‧‧‧接觸孔 442, 444, 445, 446, 536, 538, 540, 541, 542‧ ‧ contact holes
448‧‧‧勢壘金屬 448‧‧‧ barrier metal
543‧‧‧勢壘材料層 543‧‧‧ barrier material layer
450、544、748‧‧‧插頭 450, 544, 748‧‧‧ plug
452、546、750‧‧‧金屬層 452, 546, 750‧‧‧ metal layers
506、706、722‧‧‧氧化層 506, 706, 722‧‧ ‧ oxide layer
525‧‧‧有源柵極電極 525‧‧‧Active gate electrode
531‧‧‧頂部氧化層 531‧‧‧Top oxide layer
595、730‧‧‧通道終止區 595, 730 ‧ ‧ channel termination area
708‧‧‧溝槽掩膜 708‧‧‧ Trench mask
720、728‧‧‧多晶矽層 720, 728‧‧‧ polycrystalline layer
724‧‧‧柵極氧化物 724‧‧‧Gate oxide
726‧‧‧有源柵極氧化物 726‧‧‧Active Gate Oxide
732‧‧‧氧化物 732‧‧‧Oxide
734‧‧‧本體區 734‧‧‧ body area
738‧‧‧電介質層 738‧‧‧ dielectric layer
746‧‧‧勢壘金屬 746‧‧‧ barrier metal
第1圖表示傳統的溝槽MOSFET元件的剖面圖。 Figure 1 shows a cross-sectional view of a conventional trench MOSFET device.
第2A圖表示本發明的第一實施例所述的雙柵極氧化物溝槽MSOFET佈局的俯視圖。 Fig. 2A is a plan view showing the layout of the double gate oxide trench MSOFET according to the first embodiment of the present invention.
第2B-1圖表示第2A圖所示的雙柵極氧化物溝槽MOSFET 200佈局的另一個俯視圖。 Fig. 2B-1 shows another top view of the layout of the double gate oxide trench MOSFET 200 shown in Fig. 2A.
第2B-2圖表示第2A圖所示的雙柵極氧化物溝槽MOSFET沿線A-A和 B-B的剖面圖。 Figure 2B-2 shows the double-gate oxide trench MOSFET shown in Figure 2A along line A-A and Cross-sectional view of B-B.
第2C圖表示第2B-1圖和第2B-2圖所示的雙柵極氧化物溝槽MOSFET的等效電路圖。 Fig. 2C is an equivalent circuit diagram showing the double gate oxide trench MOSFET shown in Figs. 2B-1 and 2B-2.
第3A圖表示本發明的第二實施例所述的雙柵極氧化物溝槽MSOFET佈局的俯視圖。 Fig. 3A is a plan view showing the layout of a double gate oxide trench MSOFET according to a second embodiment of the present invention.
第3B圖表示第3A圖所示的雙柵極氧化物溝槽MOSFET沿線A-A和B-B的剖面圖。 Figure 3B shows a cross-sectional view of the double gate oxide trench MOSFET shown in Figure 3A along lines A-A and B-B.
第3C圖表示第3B圖所示的雙柵極氧化物溝槽MOSFET的電路圖。 Fig. 3C is a circuit diagram showing the double gate oxide trench MOSFET shown in Fig. 3B.
第4A-4R圖表示製備本發明的第一實施例所述的第2A-2B圖所示的雙柵極氧化物溝槽MOSFET步驟的剖面圖。 4A-4R is a cross-sectional view showing a step of preparing the double gate oxide trench MOSFET shown in Fig. 2A-2B of the first embodiment of the present invention.
第5A-5Q圖表示製備本發明的第二實施例所述的第3A-3B圖所示的雙柵極氧化物溝槽MOSFET步驟的剖面圖。 5A-5Q are cross-sectional views showing the steps of preparing the double gate oxide trench MOSFET shown in Fig. 3A-3B of the second embodiment of the present invention.
第6圖表示製備本發明的一個可選實施例所述的雙柵極氧化物溝槽MOSFET步驟的剖面圖。 Figure 6 is a cross-sectional view showing the steps of preparing a dual gate oxide trench MOSFET according to an alternative embodiment of the present invention.
第7A圖表示依據本發明的一個可選實施例,雙柵極氧化物溝槽MOSFET佈局的俯視圖。 Figure 7A shows a top view of a dual gate oxide trench MOSFET layout in accordance with an alternate embodiment of the present invention.
第7B圖表示第7A圖所示的雙柵極氧化物溝槽MOSFET沿線A-A和B-B的剖面圖。 Fig. 7B is a cross-sectional view showing the double gate oxide trench MOSFET shown in Fig. 7A along lines A-A and B-B.
第8A-8R圖表示製備第7A-7B圖所示的雙柵極氧化物溝槽MOSFET步驟的剖面圖。 Figures 8A-8R are cross-sectional views showing the steps of preparing the dual gate oxide trench MOSFET shown in Figures 7A-7B.
儘管為了解釋說明,以下詳細說明包含了許多具體細節,但是本領域的任何技術人員都應理解基於以下細節的多種變化和修正都屬本發明的範圍。因此,本發明的典型實施例的提出,對於請求 保護的發明沒有任何一般性的損失,而且不附加任何限制。 While the following detailed description contains numerous specific details Therefore, an exemplary embodiment of the present invention is proposed for a request The invention of protection does not have any general loss and is not subject to any restrictions.
在本發明的實施例中,傳統溝槽MOSFET中已有的結截止,可以用柵極滑道區中的厚柵極氧化物代替,以便終止有源晶胞區,從而消除結截止擊穿,提高UIS(非嵌位元感應開關)性能,又由於氧化物所需的空間比傳統的結截止所需的空間小得多,還節省結截止所占的空間。此外,藉由將嵌入式體二極體局限在有源區,可以提高反向恢復特性。 In an embodiment of the present invention, the existing junction cut-off in a conventional trench MOSFET can be replaced by a thick gate oxide in the gate runner region to terminate the active cell region, thereby eliminating junction breakdown breakdown. Improve UIS (non-embedded sensor switch) performance, and because the space required for oxide is much smaller than the space required for traditional junction cutoff, it also saves space for junction cutoff. In addition, the reverse recovery characteristic can be improved by confining the embedded body diode to the active region.
第2A圖表示本發明的第一實施例所述的雙柵極氧化物溝槽MSOFET 200佈局的俯視圖。第2B-2圖表示雙柵極截止的溝槽MOSFET 200沿線A-A和B-B的剖面圖。如第4A-4R圖所要詳述地那樣,用於製備氧化物截止溝槽MOSFET 200的方法僅需要四個掩膜:一個溝槽掩膜、一個柵極氧化物掩膜、一個接觸掩膜以及一個金屬掩膜。 Fig. 2A is a plan view showing the layout of the double gate oxide trench MSOFET 200 of the first embodiment of the present invention. Figure 2B-2 shows a cross-sectional view of trench MOSFET 200 with double gate turn-off along lines A-A and B-B. As described in detail in Figures 4A-4R, the method for fabricating the oxide-off trench MOSFET 200 requires only four masks: a trench mask, a gate oxide mask, a contact mask, and A metal mask.
如第2A圖和第2B-2圖所示,溝槽MOSFET 200包含形成在佈滿氧化物的溝槽202中的柵極電極,溝槽202位於有源晶胞區210中。柵極滑道形成在一套較寬的佈滿氧化物的溝槽中。柵極滑道包含第一部分204接觸並包圍有源晶胞區210。柵極滑道含有第二部分206,藉由接頭207,連接到柵極金屬層248(其輪廓如第2A圖中的虛線所示)上。截止結構208形成在另一個佈滿氧化物的溝槽中,該溝槽包圍著柵極滑道204、206以及有源區210。截止結構208可以藉由截止金屬254,以及在特定位置處適當的接頭,短接至元件200的本體或源極區上。柵極金屬248和源極金屬252藉由縫隙250,相互電絕緣,縫隙250可以用絕緣材料填充。短接的截 止結構208作為通道終點。作為示例,在第2B-2圖所示的實施例中,n-型(以n-通道MOSFT元件為例)源極層214可以僅形成在有源晶胞區中的p-本體層212的頂部上。有源區柵極溝槽202的柵極氧化物比柵極滑道204的柵極氧化物薄得多。柵極滑道204以及截止溝槽208的厚柵極氧化物的厚度(例如約為1000埃(Å)至2000埃(Å)),足以承受擊穿電壓;所需的厚度取決於元件的額定電壓。柵極滑道204、206之溝槽以及截止溝槽208中的柵極氧化物,比有源柵極溝槽202中的柵極氧化物厚,因此可以說元件200具有雙柵極氧化物厚度。柵極滑道206和204,以及有源區柵極溝槽202中的柵極電極,一起連接到元件柵極電勢上。截止溝槽208中的柵極電極可以藉由晶片邊緣213,連接到本體區上,晶片邊緣213位於元件漏極電勢。 As shown in FIGS. 2A and 2B-2, trench MOSFET 200 includes a gate electrode formed in trench 202 filled with oxide, trench 202 being located in active cell region 210. The gate runners are formed in a wider set of trenches filled with oxide. The gate runner includes a first portion 204 that contacts and surrounds the active cell region 210. The gate runner contains a second portion 206 connected by a joint 207 to a gate metal layer 248 (having a contour as indicated by the dashed line in Figure 2A). The cutoff structure 208 is formed in another trench filled with oxide that surrounds the gate runners 204, 206 and the active region 210. The cutoff structure 208 can be shorted to the body or source region of the component 200 by a cutoff metal 254 and a suitable joint at a particular location. The gate metal 248 and the source metal 252 are electrically insulated from each other by the slit 250, and the slit 250 may be filled with an insulating material. Short cut The stop structure 208 serves as the end point of the channel. As an example, in the embodiment shown in FIG. 2B-2, the n-type (in the case of an n-channel MOSFT device as an example) source layer 214 may be formed only in the p-body layer 212 in the active cell region. On the top. The gate oxide of the active region gate trench 202 is much thinner than the gate oxide of the gate runner 204. The thickness of the gate runner 204 and the thick gate oxide of the turn-off trench 208 (eg, about 1000 Å to 2,000 Å) is sufficient to withstand the breakdown voltage; the required thickness depends on the component rating. Voltage. The gate oxides of the gate runners 204, 206 and the gate oxide in the turn-off trench 208 are thicker than the gate oxide in the active gate trench 202, so it can be said that the component 200 has a double gate oxide thickness. . Gate runners 206 and 204, as well as gate electrodes in active region gate trenches 202, are connected together to the element gate potential. The gate electrode in the cutoff trench 208 can be connected to the body region by the wafer edge 213, which is at the element drain potential.
第2B-1圖表示第2A圖所示的雙柵極氧化物溝槽MOSFET 200的另一個俯視圖,但為了便於說明,第2B-1圖僅表示出了金屬層。源極金屬252覆蓋了有源區210,以及包圍的柵極滑道204。柵極金屬248覆蓋了柵極滑道的柵極拾取部分206,截止金屬254連接截止溝槽208包圍元件的那部分。在第2A圖和第2B-1圖所示的佈局中,截止金屬254在晶片的拐角處,連接截止溝槽208。 Fig. 2B-1 shows another top view of the double gate oxide trench MOSFET 200 shown in Fig. 2A. However, for convenience of explanation, Fig. 2B-1 shows only the metal layer. The source metal 252 covers the active region 210 and the enclosed gate runner 204. The gate metal 248 covers the gate pick-up portion 206 of the gate runner, and the cut-off metal 254 connects the portion of the cut-off trench 208 that surrounds the component. In the layout shown in FIGS. 2A and 2B-1, the cut-off metal 254 is connected to the cut-off trench 208 at the corner of the wafer.
第2C圖表示第2B-2圖所示的雙柵極氧化物截止溝槽MOSFET的等效電路圖。這些結構形成在半導體襯底中,半導體襯底含有一個在底部n+襯底層214上方的n-外延層211。如圖中電路圖所示,寄生p-通道(以n-通道元件為例)電晶體204a可以形成在柵極滑道204下方,從有源區210(位於元件源極電勢)中的p-本體層212開始,作為寄生電晶體204a的寄生漏極,在柵極滑道204另一側 的p-本體區,作為寄生電晶體204a的寄生源極,包圍著柵極滑道204的那部分n-外延層211,作為寄生電晶體204的寄生通道區。 要注意的是,如果元件200是n-通道MOSFET,寄生電晶體是p-通道電晶體,那麼元件漏極電勢就是寄生電晶體的源極電勢,反之亦然。寄生電晶體204a的寄生漏極位於元件源極電勢,因此寄生柵極(柵極滑道204中的柵極電極)短接至元件漏極電極,可以打開寄生電晶體204a。當MOSFET元件200斷開時,所有的柵極滑道204都通向元件源極電勢,可以打開寄生電晶體204a。這使得元件源極電勢,從有源區210,短接至晶片邊緣213處的漏極電勢,從而產生漏電流。 Fig. 2C is an equivalent circuit diagram showing the double gate oxide off-channel MOSFET shown in Fig. 2B-2. These structures are formed in a semiconductor substrate having an n- epitaxial layer 211 over the bottom n+ substrate layer 214. As shown in the circuit diagram of the figure, a parasitic p-channel (taking an n-channel element as an example) transistor 204a may be formed under the gate runner 204 from the active region 210 (located at the source potential of the component). Layer 212 begins as a parasitic drain of parasitic transistor 204a on the other side of gate runner 204 The p-body region, as the parasitic source of the parasitic transistor 204a, surrounds the portion of the n- epitaxial layer 211 of the gate runner 204 as the parasitic channel region of the parasitic transistor 204. It is noted that if component 200 is an n-channel MOSFET and the parasitic transistor is a p-channel transistor, then the component drain potential is the source potential of the parasitic transistor and vice versa. The parasitic drain of the parasitic transistor 204a is at the source potential of the element, so that the parasitic gate (the gate electrode in the gate runner 204) is shorted to the drain electrode of the element, and the parasitic transistor 204a can be turned on. When the MOSFET element 200 is turned off, all of the gate runners 204 lead to the source potential of the component, and the parasitic transistor 204a can be turned on. This causes the source potential of the element, from the active region 210, to be shorted to the drain potential at the edge 213 of the wafer, thereby generating a leakage current.
為了克服該問題,可以在元件週邊,晶片邊緣213和柵極滑道204之間,形成一個截止溝槽208。並且在截止溝槽208下方,形成一個p-通道寄生電晶體208a。然而,截止溝槽208中的柵極電極,藉由截止金屬254,短接至寄生電晶體208a的寄生源極端(晶片邊緣213端),因此寄生電晶體208a從未接通,以便作為一個通道終點,避免從元件源極短接至晶片邊緣213。要注意的是,由於接觸溝槽206不在有源區210周圍,因此所示的寄生電晶體並不用於柵極滑道接觸溝槽206。如果有必要,可以藉由在第一截止結構208和柵極滑道204之間,添加一個額外的通道終點,這其實是在第一常閉的寄生電晶體208a和寄生電晶體204a之間,添加了另一個常閉的寄生電晶體;從而提高了通道終點的電壓性能。 To overcome this problem, a cut-off trench 208 can be formed between the periphery of the component, between the wafer edge 213 and the gate runner 204. And below the cutoff trench 208, a p-channel parasitic transistor 208a is formed. However, the gate electrode in the cut-off trench 208 is shorted to the parasitic source terminal (the wafer edge 213 end) of the parasitic transistor 208a by the turn-off metal 254, so the parasitic transistor 208a is never turned on, so as to serve as a channel. End point, avoiding shorting from the source of the component to the edge 213 of the wafer. It is noted that since the contact trench 206 is not around the active region 210, the parasitic transistor shown is not used for the gate runner contact trench 206. If necessary, an additional channel end point can be added between the first cutoff structure 208 and the gate runner 204, which is actually between the first normally closed parasitic transistor 208a and the parasitic transistor 204a. Another normally closed parasitic transistor is added; this increases the voltage performance at the end of the channel.
也可以利用其他方法製備通道終點,例如共同轉讓的美國專利申請案12/731,112中所述的那些方法,特此引用該內容,以作參考。例如,可以藉由製備足夠深的柵極滑道溝槽204,觸及重摻雜 的底部襯底214,以形成通道終點。還可選擇,藉由在柵極滑道溝槽204的底部,製備一個重摻雜的n區,以形成通道終點。如果形成了可選的通道終點,那麼就可以省去截止結構208。柵極滑道溝槽204包圍著有源區,並且具有足夠厚的柵極氧化物,以承載閉鎖電壓。 Channel end points can also be prepared by other methods, such as those described in commonly assigned U.S. Patent Application Serial No. 12/731,112, the disclosure of which is hereby incorporated by reference. For example, heavy doping can be achieved by preparing a sufficiently deep gate runner trench 204 The bottom substrate 214 is formed to form a channel end point. Alternatively, a heavily doped n-region can be formed at the bottom of the gate runner trench 204 to form a channel end point. If an optional channel end point is formed, then the cutoff structure 208 can be omitted. The gate runner trench 204 surrounds the active region and has a sufficiently thick gate oxide to carry the latching voltage.
閉鎖電壓是元件的兩個主電流承載端(例如源極到漏極的電壓)之間的電壓。當元件處於斷開狀態時,較厚的柵極氧化物(例如柵極滑道溝槽或截止溝槽的氧化物)應該足以承載閉鎖電壓。換言之,氧化物足夠厚,閉鎖電壓不大,不能在氧化物上產生超過氧化物擊穿場的電場。理想情況是,截止區的擊穿電壓高於有源區的擊穿電壓,從而提高元件的耐用性。 The blocking voltage is the voltage between the two main current carrying ends of the component, such as the source-to-drain voltage. Thicker gate oxides (such as gate runner trenches or oxides of the turn-off trenches) should be sufficient to carry the latch-up voltage when the component is in the off state. In other words, the oxide is thick enough that the blocking voltage is not large and an electric field beyond the oxide breakdown field cannot be generated on the oxide. Ideally, the breakdown voltage of the cut-off region is higher than the breakdown voltage of the active region, thereby improving the durability of the component.
第3A圖表示本發明的第二實施例所述的雙柵極氧化物溝槽MOSFET 300佈局的俯視圖,第3B圖表示雙柵極截止溝槽MOSFET 300沿線A-A和B-B的剖面圖。雙柵極氧化物溝槽MOSFET 300與第2A-2B圖所示的雙柵極氧化物溝槽MOSFET 200類似。如第3A-3B圖所示,溝槽MOSFET 300含有形成在有源柵極溝槽302中的有源柵極電極,有源柵極溝槽302位於有源晶胞區310中。有源柵極電極電連接到柵極滑道304和306上,柵極滑道304和306形成在佈滿較厚氧化物的較寬的溝槽中。柵極滑道包含到達並包圍著有源晶胞區310的部分304,以及藉由接頭307,連接到柵極金屬348的部分306。 截止結構308包圍著柵極304、306和有源區310。藉由截止金屬354以及合適的接頭,截止結構308在晶片邊緣313附近,電性連接到源極層314和本體層312上。柵極金屬348和源極金屬352相互電絕緣,例如藉由縫隙350,可以用絕緣材料填充縫隙350。源極 金屬覆蓋有源區310以及周圍的柵極滑道304。如上所述,短接的截止結構308作為通道終點。在本實施例中,n-型源極層314可以形成在有源晶胞區310以及截止區中的p-本體層312的頂部,源極和本體都形成在n-型漂流/外延層311上方。如第5A-5Q圖所示,可以利用三掩膜技術,製備雙柵極氧化物溝槽MSOFET 300。 3A is a plan view showing the layout of the double gate oxide trench MOSFET 300 according to the second embodiment of the present invention, and FIG. 3B is a cross-sectional view showing the double gate turn-off trench MOSFET 300 along lines A-A and B-B. The dual gate oxide trench MOSFET 300 is similar to the dual gate oxide trench MOSFET 200 shown in FIGS. 2A-2B. As shown in FIGS. 3A-3B, trench MOSFET 300 includes an active gate electrode formed in active gate trench 302, which is located in active cell region 310. The active gate electrode is electrically coupled to gate runners 304 and 306, which are formed in a wider trench that is filled with thicker oxide. The gate runner includes a portion 304 that reaches and surrounds the active cell region 310, and a portion 306 that is connected to the gate metal 348 by a junction 307. A cutoff structure 308 surrounds the gates 304, 306 and the active region 310. The cutoff structure 308 is electrically connected to the source layer 314 and the body layer 312 near the wafer edge 313 by a turn-off metal 354 and a suitable joint. The gate metal 348 and the source metal 352 are electrically insulated from each other, for example by the slit 350, and the slit 350 may be filled with an insulating material. Source The metal covers the active region 310 and the surrounding gate runners 304. As noted above, the shorted cutoff structure 308 serves as the end of the channel. In the present embodiment, the n-type source layer 314 may be formed on the top of the active cell region 310 and the p-body layer 312 in the cut-off region, and the source and the body are both formed in the n-type drift/epitaxial layer 311. Above. As shown in Figures 5A-5Q, a dual gate oxide trench MSOFET 300 can be fabricated using a three mask technique.
第3C圖表示第3B圖所示的雙柵極氧化物截止溝槽MOSFET的等效電路圖。如同電路圖中所示,寄生p-通道電晶體304a形成在柵極滑道溝槽304下方,但於截止溝槽308減寬後,作為通道終點。寄生電晶體308a位於截止溝槽308下方,藉由截止金屬354,其寄生源極短接至寄生柵極,從而避免如上所述地接通。 Fig. 3C is an equivalent circuit diagram showing the double gate oxide off-channel MOSFET shown in Fig. 3B. As shown in the circuit diagram, the parasitic p-channel transistor 304a is formed under the gate runner trench 304, but after the cutoff trench 308 is widened, serves as the end of the channel. The parasitic transistor 308a is located below the turn-off trench 308, with the parasitic source being shorted to the parasitic gate by the turn-off metal 354, thereby avoiding switching on as described above.
第4A-4R圖表示上述第2A圖、第2B-1圖和第2B-2圖所示類型的雙柵極氧化物溝槽MOSFET的四掩膜製備方法的剖面圖。如第4A圖所示,製備半導體襯底的初始材料包含,例如相對輕摻雜的(例如n-)外延層404位於重摻雜的(例如n+)襯底402上方。還可選擇,外延層摻雜p-,襯底摻雜p+。初始絕緣層406可以形成在外延層404的頂面上。作為示例,但不作為局限,絕緣層406可以用氧化物製備,例如利用熱氧化作用和沉積低溫氧化物或高密度等離子(HDP)相結合。如第4B圖所示,在絕緣層406的上方,使用第一掩膜408(此處稱為溝槽掩膜),並形成帶開口的圖案,開口對應將要製備的溝槽。經過蝕刻,形成溝槽410、412、414和416,穿過絕緣層406、層404以及外延層404的頂部。可以利用溝槽410和412,在後續技術中製備第一和第二柵極滑道。為了簡便,溝槽410、412在此稱為第一和第二柵極滑道溝槽。利用另一個溝槽414,製備有源區的部分截止。為了簡便,溝槽414在此稱為截 止溝槽。利用溝槽416製備有源元件晶胞。為了簡便,這些溝槽416在此稱為有源溝槽。如果這些溝槽的寬度不同,那麼可以在共同的蝕刻步驟中,將這些溝槽蝕刻成不同深度。例如,柵極滑道溝槽410、412和截止溝槽414可以比有源溝槽416更寬,以便利用同一蝕刻技術,將柵極滑道溝槽410、412以及截止溝槽414蝕刻得比有源溝槽416更深。可以利用單一掩膜,蝕刻所有的溝槽。 4A-4R is a cross-sectional view showing a four mask preparation method of the double gate oxide trench MOSFET of the type shown in the above 2A, 2B-1, and 2B-2. As shown in FIG. 4A, the initial material for preparing the semiconductor substrate includes, for example, a relatively lightly doped (eg, n-) epitaxial layer 404 over the heavily doped (eg, n+) substrate 402. Alternatively, the epitaxial layer is doped with p- and the substrate is doped with p+. An initial insulating layer 406 may be formed on the top surface of the epitaxial layer 404. By way of example and not limitation, insulating layer 406 may be prepared with an oxide, such as by thermal oxidation combined with deposition of a low temperature oxide or high density plasma (HDP). As shown in FIG. 4B, above the insulating layer 406, a first mask 408 (herein referred to as a trench mask) is used and a pattern with openings is formed, the openings corresponding to the trenches to be prepared. After etching, trenches 410, 412, 414, and 416 are formed through insulating layer 406, layer 404, and the top of epitaxial layer 404. The first and second gate runners can be fabricated in subsequent techniques using trenches 410 and 412. For simplicity, the trenches 410, 412 are referred to herein as first and second gate runner trenches. A portion of the active region is turned off using another trench 414. For simplicity, the trench 414 is referred to herein as a truncation Stop the groove. The active element cells are fabricated using trenches 416. For simplicity, these trenches 416 are referred to herein as active trenches. If the widths of the trenches are different, the trenches can be etched to different depths in a common etching step. For example, the gate runner trenches 410, 412 and the turn-off trench 414 can be wider than the active trench 416 to etch the gate runner trenches 410, 412 and the turn-off trench 414 using the same etch technique. The active trench 416 is deeper. All trenches can be etched using a single mask.
如第4C圖所示,除去第一掩膜408。沉積厚柵極絕緣層418(例如一種氧化物),或藉由其他方式形成在溝槽410、412、414和416的底部和側壁上,以及外延層404的上方。厚柵極氧化層418的厚度約在800Å至1500Å之間。如第4D圖所示,在溝槽410、412、414和416中以及外延層404的頂部,沉積犧牲材料420。作為示例,但不作為局限,犧牲材料可以是導電或半導體材料,例如多晶矽。如第4E圖所示,在柵極絕緣層418的頂面下方,以及外延層404的頂面上方,可以利用蝕刻終點,回刻犧牲材料420。仍然可用犧牲材料420填充溝槽410、412、414和416。 As shown in FIG. 4C, the first mask 408 is removed. A thick gate insulating layer 418 (e.g., an oxide) is deposited, or otherwise formed on the bottom and sidewalls of trenches 410, 412, 414, and 416, and over epitaxial layer 404. The thick gate oxide layer 418 has a thickness between about 800 Å and 1500 Å. As shown in FIG. 4D, sacrificial material 420 is deposited in trenches 410, 412, 414, and 416 and on top of epitaxial layer 404. By way of example and not limitation, the sacrificial material can be a conductive or semiconductive material such as a polysilicon. As shown in FIG. 4E, below the top surface of the gate insulating layer 418, and above the top surface of the epitaxial layer 404, the sacrificial material 420 can be etched back using the etch end. The trenches 410, 412, 414, and 416 can still be filled with the sacrificial material 420.
如第4F圖所示,薄氧氣擴散勢壘層422(例如氮化物)沉積在溝槽410、412、414和416中的犧牲材料420上方,以及柵極絕緣層418上方。作為示例,薄氮化層422的厚度約為200Å至500Å。 As shown in FIG. 4F, a thin oxygen diffusion barrier layer 422 (eg, nitride) is deposited over the sacrificial material 420 in trenches 410, 412, 414, and 416, and over gate insulating layer 418. As an example, the thin nitride layer 422 has a thickness of about 200 Å to 500 Å.
在薄氮化層422上方,使用第二掩膜424(即柵極氧化物掩膜)。如第4G圖所示,柵極氧化物掩膜424僅覆蓋了位於柵極滑道區域和截止區中的溝槽410、412、414,但沒有覆蓋有源溝槽416。犧牲材料420確保光致抗蝕劑材料不會沉積在溝槽內,一旦沉積將難以除去。蝕刻掉沒有被第二掩膜424覆蓋的那部分薄氮化層422 ,然後蝕刻溝槽416中的犧牲材料420。溝槽416中以及外延層404上方,沒有被第二掩膜424覆蓋的厚柵極絕緣層418也被蝕刻掉。 Above the thin nitride layer 422, a second mask 424 (ie, a gate oxide mask) is used. As shown in FIG. 4G, the gate oxide mask 424 covers only the trenches 410, 412, 414 located in the gate runner region and the turn-off region, but does not cover the active trench 416. The sacrificial material 420 ensures that the photoresist material does not deposit within the trenches and will be difficult to remove once deposited. The portion of the thin nitride layer 422 that is not covered by the second mask 424 is etched away. The sacrificial material 420 in the trench 416 is then etched. Above trench 416 and over epitaxial layer 404, thick gate insulating layer 418, which is not covered by second mask 424, is also etched away.
除去第二掩膜424,然後在有源溝槽416的側壁和底部以及n-外延層404的上方,如第4H圖所示,製備(例如生長)薄犧牲絕緣物426。有種材料並沒有形成(例如生長)在薄氮化層422的材料上,犧牲絕緣物最好是由這種材料製成。作為示例,薄氮化層422可以由氮化物材料(例如氮化矽)製成,薄犧牲絕緣層426可以由生長氧化物材料(例如氧化矽)製成。犧牲絕緣物426的厚度約為200Å至500Å。 The second mask 424 is removed, and then a thin sacrificial insulator 426 is prepared (e.g., grown) as shown in FIG. 4H above the sidewalls and bottom of the active trench 416 and over the n- epitaxial layer 404. A material is not formed (e.g., grown) on the material of the thin nitride layer 422, and the sacrificial insulator is preferably made of such a material. As an example, the thin nitride layer 422 may be made of a nitride material such as tantalum nitride, and the thin sacrificial insulating layer 426 may be made of a grown oxide material such as hafnium oxide. The sacrificial insulator 426 has a thickness of about 200 Å to 500 Å.
如第4I圖所示,剝去薄氮化層422的剩餘部分。然後,蝕刻掉溝槽410、412、414中的犧牲材料420。薄氧氣擴散勢壘層422可以由能抵抗蝕刻犧牲絕緣層426的材料製成。此外,薄氧氣擴散勢壘層422也可以由一種利用犧牲絕緣層426可抵抗的技術,可以蝕刻的材料製成。 As shown in Fig. 4I, the remaining portion of the thin nitride layer 422 is stripped. The sacrificial material 420 in the trenches 410, 412, 414 is then etched away. The thin oxygen diffusion barrier layer 422 can be made of a material that resists etching the sacrificial insulating layer 426. In addition, the thin oxygen diffusion barrier layer 422 can also be made of a material that can be etched using a technique that is resistant to the sacrificial insulating layer 426.
犧牲絕緣層426比厚柵極絕緣層418薄,如第4J圖所示,可以從有源溝槽416上除去犧牲絕緣層426,同時完整地保留厚柵極絕緣層418。然後,在有源溝槽416的底部和側壁中形成薄柵極絕緣物428。薄柵極絕緣物428的厚度約為150Å至500Å。 The sacrificial insulating layer 426 is thinner than the thick gate insulating layer 418. As shown in FIG. 4J, the sacrificial insulating layer 426 can be removed from the active trench 416 while leaving the thick gate insulating layer 418 intact. A thin gate insulator 428 is then formed in the bottom and sidewalls of the active trench 416. The thin gate insulator 428 has a thickness of about 150 Å to 500 Å.
如第4K圖所示,在所有的溝槽410、412、414和416中,沉積導電材料430(例如多晶矽),還可以在厚柵極絕緣物418的上方以及位於外延層404上方的薄柵極絕緣物428的上方溢出。然後,如第4L圖所示,可以藉由外延層404頂面下方的終點,回刻導電材料430。 As shown in FIG. 4K, a conductive material 430 (eg, polysilicon) is deposited in all of the trenches 410, 412, 414, and 416, and may also be over the thick gate insulator 418 and a thin gate over the epitaxial layer 404. The top of the pole insulator 428 overflows. Then, as shown in FIG. 4L, the conductive material 430 can be etched back by the end point below the top surface of the epitaxial layer 404.
如第4M圖所示,在外延層404的頂部形成本體層432。例如,可以藉由垂直或帶角度的全面植入,並擴散具有與外延層404和襯底402相反導電類型的摻雜物,來製備本體層432。例如,如果襯底402和外延層404為n-型摻雜,那麼就可以藉由植入p-型摻雜物,製備本體層432,並且反之亦然。本體植入也可以在極高的能量下(例如80-120KeV)進行,厚柵極絕緣物418不會妨礙本體植入。 As shown in FIG. 4M, a body layer 432 is formed on top of the epitaxial layer 404. For example, the body layer 432 can be prepared by a full vertical or angled implant and diffusion of dopants having a conductivity type opposite to the epitaxial layer 404 and the substrate 402. For example, if substrate 402 and epitaxial layer 404 are n-type doped, then body layer 432 can be fabricated by implanting a p-type dopant, and vice versa. Bulk implants can also be performed at very high energies (e.g., 80-120 KeV), and thick gate insulators 418 do not interfere with bulk implantation.
如第4N圖所示,利用低能植入技術,在本體層432的頂部形成源極層434。如果源極植入是在極其低的能量下(例如20KeV左右)進行的,而且厚柵極絕緣物相當厚(例如氧化物的厚度約為1200Å),那麼由於厚柵極絕緣物418妨礙了植入,並且薄柵極氧化物428相當薄,使離子可以滲入,因此摻雜物僅植入到有源晶胞區。例如,藉由垂直或帶角度的植入和退火,製備源極層434。通常是藉由植入與本體摻雜物的導電類型相反的摻雜物,來製備源極層434。進行源極和本體植入時,無需使用額外的掩膜。 As shown in FIG. 4N, a source layer 434 is formed on top of the body layer 432 using a low energy implantation technique. If the source implant is performed at extremely low energy (e.g., around 20 KeV) and the thick gate insulator is relatively thick (e.g., the thickness of the oxide is about 1200 Å), then the thick gate insulator 418 hinders the implant. The thin gate oxide 428 is relatively thin so that ions can penetrate, so that the dopant is implanted only into the active cell region. Source layer 434 is prepared, for example, by vertical or angled implantation and annealing. Source layer 434 is typically prepared by implanting a dopant that is opposite in conductivity to the bulk dopant. No additional mask is required for source and body implantation.
如第4O圖所示,在該結構上方形成絕緣層436,然後壓實並平整。可以藉由化學機械平整化(CMP)來完成平整化。以上僅為示例,但不以此為限,絕緣層436可以是一種低溫氧化物和含有硼酸的矽玻璃(BPSG)。 As shown in Fig. 4O, an insulating layer 436 is formed over the structure, which is then compacted and planarized. The planarization can be accomplished by chemical mechanical planarization (CMP). The above is merely an example, but not limited thereto, the insulating layer 436 may be a low temperature oxide and a boric acid containing barium glass (BPSG).
如第4P圖所示,在絕緣層436上製備接觸掩膜438,並形成帶有定義接觸孔的開口圖案。接觸掩膜438是該技術中所用的第三掩膜。絕緣層436、源極層434以及有源晶胞區中的部分本體層432,都可以藉由掩膜438中的開口來蝕刻,以形成源極/本體接觸孔442。絕緣層436以及溝槽412、414中的部分導電材料430都向下 蝕刻,以形成柵極接觸孔444以及截止接觸孔445。位於截止區邊緣以及溝槽410附近的絕緣層436以及本體層432的頂部都可以向下蝕刻,以形成截止短路接觸孔446。 As shown in Fig. 4P, a contact mask 438 is formed on the insulating layer 436, and an opening pattern having a defined contact hole is formed. Contact mask 438 is the third mask used in the art. The insulating layer 436, the source layer 434, and a portion of the body layer 432 in the active cell region may be etched by openings in the mask 438 to form source/body contact holes 442. The insulating layer 436 and a portion of the conductive material 430 in the trenches 412, 414 are all downward Etching to form the gate contact hole 444 and the cut-off contact hole 445. The insulating layer 436 located at the edge of the cutoff region and adjacent the trench 410 and the top of the body layer 432 may be etched down to form an off short contact hole 446.
如第4Q圖所示,可以在接觸孔442、444、445和446中沉積勢壘材料(例如Ti/TiN)層448。然後利用導電(例如鎢(W))插頭450,填滿接觸孔442、444、445和446。接觸孔442中的勢壘金屬448和鎢插頭450,在有源區中作為源極/本體接頭。接觸孔444中的勢壘金屬448和鎢插頭450,在柵極接觸溝槽412上方作為柵極接頭。接觸孔445、446中的勢壘金屬448和鎢插頭450,在截止區中形成接頭,將截止溝槽電極短接至晶片邊緣附近的本體區。然後,可以在該結構的上方沉積一個金屬層452(最好選用Al-Si)。 As shown in FIG. 4Q, a barrier material (e.g., Ti/TiN) layer 448 can be deposited in contact holes 442, 444, 445, and 446. Contact holes 442, 444, 445, and 446 are then filled with a conductive (e.g., tungsten (W)) plug 450. Barrier metal 448 and tungsten plug 450 in contact hole 442 serve as source/body connections in the active region. The barrier metal 448 and the tungsten plug 450 in the contact hole 444 act as a gate contact over the gate contact trench 412. The barrier metal 448 and the tungsten plug 450 in the contact holes 445, 446 form a joint in the cut-off region, shorting the cut-off trench electrode to the body region near the edge of the wafer. A metal layer 452 (preferably Al-Si) can then be deposited over the structure.
在金屬層452上沉積一個帶圖案的金屬掩膜(圖中未示),然後藉由金屬蝕刻,將金屬層452分成電絕緣的部分,構成柵極、截止和源極金屬,例如柵極金屬456、截止連接金屬458以及源極金屬454,從而製成元件400,元件400與第2A圖、第2B-1圖和第2B-2圖所示的半導體元件300類似。金屬掩膜是該技術中的第四掩膜。接觸孔442中的勢壘金屬448和鎢插頭450,在源極區上方作為源極/本體接頭,從源極層434和本體層432開始,一直到源極金屬454。接觸孔444中的勢壘金屬448和鎢插頭450,在柵極滑道區上方作為垂直柵極滑道接頭,從柵極滑道開始,一直到柵極金屬456。接觸孔445、446中的勢壘金屬448和鎢插頭450,以及截止金屬458,將截止溝槽414的柵極短接至晶片邊緣413和截止溝槽414之間的本體區432上。 A patterned metal mask (not shown) is deposited on the metal layer 452, and then the metal layer 452 is divided into electrically insulating portions by metal etching to form a gate, a cutoff, and a source metal, such as a gate metal. 456. The connection metal 458 and the source metal 454 are cut off to form the element 400, which is similar to the semiconductor element 300 shown in FIGS. 2A, 2B-1, and 2B-2. Metal masks are the fourth mask in this technology. The barrier metal 448 and tungsten plug 450 in the contact hole 442 serve as a source/body junction over the source region, starting from the source layer 434 and the body layer 432, up to the source metal 454. Barrier metal 448 and tungsten plug 450 in contact hole 444 act as a vertical gate runner joint above the gate runner region, starting from the gate runner to gate metal 456. The barrier metal 448 and tungsten plug 450 in the contact holes 445, 446, and the turn-off metal 458, short the gate of the turn-off trench 414 to the body region 432 between the wafer edge 413 and the turn-off trench 414.
第5A-5Q圖表示用於製備上述第3A-3B圖所示類型的雙柵極氧化物溝槽MOSFET的三掩膜方法的剖面圖。用於製備雙柵極氧化物溝槽MOSFET 300的方法僅需要三個掩膜:一個溝槽掩膜、一個接觸掩膜以及一個金屬掩膜。在該方法中,可以省去第4A-4R圖所示的柵極氧化物掩膜。 5A-5Q are cross-sectional views showing a three mask method for preparing a double gate oxide trench MOSFET of the type shown in the above 3A-3B. The method used to fabricate the dual gate oxide trench MOSFET 300 requires only three masks: a trench mask, a contact mask, and a metal mask. In this method, the gate oxide mask shown in Fig. 4A-4R can be omitted.
如第5A圖所示,半導體襯底包含,例如位於重摻雜(例如n+)的襯底502上方的一個相對輕摻雜(例如n-)的外延層504。氧化層506形成在n-外延層504的頂面上。作為示例,可以藉由熱氧化和沉積低溫氧化物或高密度等離子(HDP)相結合,製備氧化物。 如第5B圖所示,在氧化層506上方,使用帶有定義溝槽的開口圖案的第一掩膜508(即溝槽掩膜)。穿過氧化層506、外延層504以及n+襯底502的頂部,藉由蝕刻製備溝槽510、512、514和516。可以使用溝槽510和512,在後續技術中製備第一和第二柵極滑道。為了簡便,溝槽510和512在此稱為第一和第二柵極滑道溝槽。可以使用另一個溝槽514,製備截止溝槽。為了簡便,溝槽514在此稱為截止溝槽。可以使用溝槽516製備有源元件晶胞。為了簡便,溝槽516在此稱為有源溝槽。柵極滑道溝槽510、512以及截止溝槽514可以比有源溝槽516寬,因此即使它們都是在同一個蝕刻技術中蝕刻的,柵極滑道溝槽510、512以及截止溝槽514也可以蝕刻得比有源溝槽516寬。 As shown in FIG. 5A, the semiconductor substrate includes, for example, a relatively lightly doped (e.g., n-) epitaxial layer 504 over a heavily doped (e.g., n+) substrate 502. An oxide layer 506 is formed on the top surface of the n- epitaxial layer 504. As an example, an oxide can be prepared by thermal oxidation and deposition of a low temperature oxide or high density plasma (HDP). As shown in FIG. 5B, above the oxide layer 506, a first mask 508 (i.e., a trench mask) having an opening pattern defining a trench is used. Trench 510, 512, 514, and 516 are prepared by etching through oxide layer 506, epitaxial layer 504, and the top of n+ substrate 502. The first and second gate runners can be fabricated in subsequent techniques using trenches 510 and 512. For simplicity, trenches 510 and 512 are referred to herein as first and second gate runner trenches. A cut-off trench can be prepared using another trench 514. For simplicity, trench 514 is referred to herein as a cut-off trench. The active element cells can be fabricated using trenches 516. For simplicity, trench 516 is referred to herein as an active trench. The gate runner trenches 510, 512 and the off trench 514 may be wider than the active trench 516, so even if they are both etched in the same etch technique, the gate runner trenches 510, 512 and the cutoff trench 514 can also be etched wider than active trench 516.
如第5C圖所示,除去第一掩膜508。在溝槽510、512、514和516的底部和側壁上,以及外延層504的上方,製備柵極絕緣層518(例如一種氧化物)。柵極絕緣層518的厚度約為500Å至1000Å。如第5D圖所示,沉積犧牲材料520(例如多晶矽)填滿有源溝槽516 ,並且沉積在外延層504的上方。與有源溝槽516相比,柵極滑道溝槽510、512以及截止溝槽514相當的寬,犧牲材料520僅僅佈滿了溝槽510、512、514的底部和側壁,並沒有填滿這些溝槽。然後,藉由蝕刻有源溝槽516中,厚柵極絕緣層518的頂面下方,以及外延層504的頂面上方的終點,各向異性地回刻犧牲材料520。 如第5E圖所示,可以從柵極滑道溝槽510、512以及截止溝槽514上完全除去犧牲材料520。在這種情況下,可以在柵極滑道溝槽510、512的底部,形成一個通道終點,例如藉由各向異性植入。 以上僅為示例,但不以此為限,對於n-通道MOSFET元件而言,通道終點可以是n+摻雜的。 As shown in FIG. 5C, the first mask 508 is removed. A gate insulating layer 518 (e.g., an oxide) is formed over the bottom and sidewalls of trenches 510, 512, 514, and 516, and over epitaxial layer 504. The gate insulating layer 518 has a thickness of about 500 Å to 1000 Å. As shown in FIG. 5D, a sacrificial material 520 (eg, polysilicon) is deposited to fill the active trenches 516. And deposited over the epitaxial layer 504. The gate runner trenches 510, 512 and the off trench 514 are relatively wide compared to the active trench 516, and the sacrificial material 520 only fills the bottom and sidewalls of the trenches 510, 512, 514 and is not filled. These grooves. The sacrificial material 520 is then anisotropically etched back by etching the active trench 516, under the top surface of the thick gate insulating layer 518, and at the end of the top surface of the epitaxial layer 504. As shown in FIG. 5E, the sacrificial material 520 can be completely removed from the gate runner trenches 510, 512 and the off trench 514. In this case, a channel end point can be formed at the bottom of the gate runner grooves 510, 512, for example by anisotropic implantation. The above is only an example, but not limited thereto. For n-channel MOSFET components, the channel end point can be n+ doped.
如第5F圖所示,在溝槽510、512、514的底部和側壁上,以及柵極絕緣物518的上方,沉積絕緣材料,以形成一個較厚的絕緣層522。一般來說,絕緣材料的類型可以與柵極絕緣物518的材料類型相同。作為示例,如果柵極絕緣物518是一種氧化物,那麼絕緣材料就可以利用氧化物沉積(例如高溫氧化物(HTO)沉積)來形成。因此,較厚的柵極絕緣層522形成在溝槽510、512、514中,而較薄的柵極絕緣層518形成在有源溝槽516中。然後,在表面上進行平整化(例如CMP),使絕緣物522的頂面與溝槽516中的犧牲材料520的表面相互平整,從而如第5G圖所示,裸露出犧牲材料520。然後,如第5H圖所示,從溝槽516上蝕刻掉犧牲材料520。這時,溝槽516的側壁和底部中的氧化層厚度(例如約為500Å至1000Å)小於溝槽510、512、514的側壁和底部中的氧化層厚度(例如約為1500Å至2000Å)。 As shown in FIG. 5F, an insulating material is deposited over the bottom and sidewalls of trenches 510, 512, 514, and over gate insulator 518 to form a thicker insulating layer 522. In general, the type of insulating material can be the same as the type of material of the gate insulator 518. As an example, if the gate insulator 518 is an oxide, the insulating material can be formed using oxide deposition, such as high temperature oxide (HTO) deposition. Thus, a thicker gate insulating layer 522 is formed in trenches 510, 512, 514, while a thinner gate insulating layer 518 is formed in active trench 516. Then, planarization (e.g., CMP) is performed on the surface such that the top surface of the insulator 522 and the surface of the sacrificial material 520 in the trench 516 are level with each other, thereby exposing the sacrificial material 520 as shown in Fig. 5G. Then, as shown in FIG. 5H, the sacrificial material 520 is etched away from the trench 516. At this time, the thickness of the oxide layer in the sidewalls and the bottom of the trench 516 (for example, about 500 Å to 1000 Å) is smaller than the thickness of the oxide layer (for example, about 1500 Å to 2000 Å) in the sidewalls and the bottom of the trenches 510, 512, and 514.
然後,藉由各向同性蝕刻,減薄絕緣物518和522,以便在有源溝 槽516中形成有源柵極絕緣物524,以及在柵極滑道溝槽510、512和截止溝槽514中形成較厚的柵極絕緣物523。最好選用簡短的蝕刻,從有源溝槽516上完全除去絕緣層518,同時最完整地保留溝槽510、512、514中較厚的絕緣層522;然後,在有源溝槽516中,形成(例如生長)薄有源柵極絕緣層524,同時在溝槽510、512、514中保留較厚的柵極絕緣物523。因此,該元件可以說是具有雙柵極絕緣物的厚度。有源柵極絕緣物524的厚度約在150Å至800Å之間,而較厚的柵極絕緣物523的厚度約在500Å至1200Å之間。 Then, by isotropic etching, the insulators 518 and 522 are thinned so as to be in the active trench An active gate insulator 524 is formed in the trench 516, and a thicker gate insulator 523 is formed in the gate runner trenches 510, 512 and the turnoff trench 514. Preferably, a short etch is used to completely remove the insulating layer 518 from the active trench 516 while leaving the thicker insulating layer 522 of the trenches 510, 512, 514 most intact; then, in the active trench 516, A thin active gate insulating layer 524 is formed (eg, grown) while leaving a thicker gate insulator 523 in the trenches 510, 512, 514. Therefore, the component can be said to have a thickness of a double gate insulator. The active gate insulator 524 has a thickness between about 150 Å and 800 Å, while the thicker gate insulator 523 has a thickness between about 500 Å and 1200 Å.
可以沉積或藉由其他方式形成導電的或半導電的材料526(例如多晶矽),如第5J圖所示,於頂面上填滿溝槽510、512、514和516。如果有必要的話,可以摻雜導電材料526,使它的導電性更強。然後,藉由外延層504的頂面下方的蝕刻終點,回刻導電材料526,如第5K圖所示,以形成有源柵極電極525、柵極滑道527以及截止結構529。 Conductive or semiconducting material 526 (e.g., polysilicon) may be deposited or otherwise formed, as shown in Figure 5J, filling trenches 510, 512, 514, and 516 on the top surface. If necessary, the conductive material 526 can be doped to make it more conductive. Then, the conductive material 526 is etched back by the etching end point below the top surface of the epitaxial layer 504, as shown in FIG. 5K to form the active gate electrode 525, the gate runner 527, and the cutoff structure 529.
如第5L圖所示,可以在外延層504的頂部,形成一個本體層528。 例如藉由垂直或帶角度的全面植入,並擴散合適的摻雜物,例如參照上述第4M圖所示,可以形成本體層528。如第5M圖所示,在本體層528的頂部,形成一個源極層530。例如藉由垂直或帶角度的方式植入合適的摻雜物並退火,例如參照上述第4N圖所示,可以形成源極層530。 As shown in FIG. 5L, a body layer 528 can be formed on top of the epitaxial layer 504. The body layer 528 can be formed, for example, by vertical or angular full implantation and diffusion of suitable dopants, such as shown in Figure 4M above. As shown in FIG. 5M, at the top of the body layer 528, a source layer 530 is formed. The source layer 530 can be formed, for example, by implanting a suitable dopant in a vertical or angled manner and annealing, for example, as described above with reference to FIG. 4N.
如第5N圖所示,可以在該結構上方,形成一個絕緣層532(例如低溫氧化物或含有硼酸的矽玻璃(BPSG)),然後壓實並CMP平整化。 As shown in Fig. 5N, an insulating layer 532 (e.g., a low temperature oxide or a boric acid containing barium glass (BPSG)) may be formed over the structure, followed by compaction and CMP planarization.
如第5O圖所示,在絕緣層532上形成一個接觸掩膜534,並形成帶有定義接觸孔開口的圖案。要注意的是,此時,接觸掩膜534僅僅是該技術中所用的第二個掩膜。藉由掩膜中的開口,可以蝕刻絕緣層532、源極層530以及有源晶胞區中的那部分本體層528,以形成源極接觸孔536。可以向下蝕刻絕緣層532以及溝槽512、514中的那部分材料526,以形成柵極滑道接觸孔540以及截止接觸孔541。向下蝕刻絕緣層532、源極層530,以及位於截止區邊緣和溝槽514附近的那部分本體層528,以形成截止短路接觸孔542。 As shown in Fig. 5O, a contact mask 534 is formed on the insulating layer 532, and a pattern having openings defining the contact holes is formed. It is noted that at this point, contact mask 534 is only the second mask used in the art. The insulating layer 532, the source layer 530, and the portion of the body layer 528 in the active cell region may be etched by openings in the mask to form source contact holes 536. The insulating layer 532 and the portion of the material 526 of the trenches 512, 514 may be etched down to form the gate runner contact hole 540 and the cutoff contact hole 541. The insulating layer 532, the source layer 530, and the portion of the body layer 528 located near the edge of the cutoff region and the trench 514 are etched down to form the turn-off shorting contact hole 542.
如第5P圖所示,可以在接觸孔536、540、541和542中以及氧化物532上方,沉積勢壘材料(例如Ti/TiN)層543。然後,利用導電(例如鎢(W))插頭544,填滿接觸孔536、540、541和542。接觸孔536中的勢壘材料543和鎢插頭544,在源極區530上方作為有源晶胞區中的源極/本體接頭。接觸孔540中的勢壘材料543和鎢插頭544,在柵極區或截止區上方作為柵極接頭。接觸孔541、542中的勢壘材料543和鎢插頭544,作為截止/通道終點短路的接頭。如第5P圖所示,在所製成的結構上方,沉積金屬層546,最好選用Al-Si。 As shown in FIG. 5P, a barrier material (e.g., Ti/TiN) layer 543 can be deposited in contact holes 536, 540, 541, and 542 and over oxide 532. Contact holes 536, 540, 541, and 542 are then filled with a conductive (e.g., tungsten (W)) plug 544. The barrier material 543 and tungsten plug 544 in the contact hole 536 act as a source/body junction in the active cell region above the source region 530. The barrier material 543 and the tungsten plug 544 in the contact hole 540 serve as gate contacts over the gate region or the turn-off region. The barrier material 543 and the tungsten plug 544 in the contact holes 541, 542 serve as a joint for short-circuiting the end of the cut-off/channel. As shown in Fig. 5P, a metal layer 546 is deposited over the resulting structure, preferably Al-Si.
在金屬層546上沉積一個帶圖案的金屬掩膜(圖中未示),然後利用金屬蝕刻,將金屬層546分成電絕緣部分,構成電絕緣金屬區,包含柵極金屬區550、源極金屬區552以及第3A-3B圖所示的半導體元件300的截止金屬區548,這就完成了元件的製備。該技術中所用的金屬掩膜是第三掩膜。接觸孔536、538中的勢壘材料543和鎢插頭544,在源極區上方作為源極/本體接頭,從源極層 534和本體層532開始,一直到源極金屬552。接觸孔540中的勢壘材料543和鎢插頭544,在柵極滑道區上方作為垂直滑道接頭,從第一和第二柵極接頭開始,一直到柵極金屬550。接觸孔541、542中的勢壘材料543和鎢插頭544,在截止/通道區上方作為到截止金屬548的接頭。在本方法中,省去了柵極氧化物掩膜。 A patterned metal mask (not shown) is deposited on the metal layer 546, and then the metal layer 546 is divided into electrically insulating portions by metal etching to form an electrically insulating metal region including the gate metal region 550 and the source metal. The region 552 and the cut-off metal region 548 of the semiconductor device 300 shown in FIGS. 3A-3B complete the fabrication of the device. The metal mask used in this technique is the third mask. The barrier material 543 and the tungsten plug 544 in the contact holes 536, 538 serve as a source/body joint above the source region, from the source layer 534 and body layer 532 begin up to source metal 552. The barrier material 543 and the tungsten plug 544 in the contact hole 540 serve as vertical rail joints above the gate runner region, starting from the first and second gate contacts, up to the gate metal 550. The barrier material 543 and the tungsten plug 544 in the contact holes 541, 542 serve as a joint to the cut-off metal 548 over the cut-off/channel region. In this method, the gate oxide mask is omitted.
在本方法的一個可選版本中,第5F圖所示的技術之後,可以在柵極滑道溝槽510、512的底部下方以及截止溝槽514下方,形成一個通道終止區。如第6圖所示,進行全面通道植入,以便在溝槽510、512、514下方形成一個重摻雜的通道終止區595(其導電類型與最終的源極區的導電類型相同)。作為示例,通道終止植入的能量足夠穿過溝槽510、512、514中的溝槽氧化物522,但卻不足以穿過第5A-5B圖中含有初始溝槽硬掩膜506的較厚的頂部氧化層531。頂部氧化層531以及有源溝槽516中的多晶矽520可以作為硬掩膜,使通道終止區595僅形成在柵極滑道溝槽510、512的底部下方以及截止溝槽514下方。還可選擇將溝槽510、512、514做得足夠深,以便觸及襯底,作為通道終點。如果通道終點形成在溝槽510、512處,那麼只要柵極滑道溝槽510、512中的氧化物522厚度足以承載閉鎖電壓,截止溝槽514就不是必須的。 In an alternative version of the method, after the technique illustrated in FIG. 5F, a channel termination region may be formed below the bottom of the gate runner trenches 510, 512 and below the trench 514. As shown in Fig. 6, full channel implantation is performed to form a heavily doped channel termination region 595 (having the same conductivity type as the final source region) under the trenches 510, 512, 514. As an example, the energy of the channel termination implant is sufficient to pass through the trench oxide 522 in the trenches 510, 512, 514, but not enough to pass through the thicker layer 5A-5B containing the initial trench hard mask 506. The top oxide layer 531. The top oxide layer 531 and the polysilicon 520 in the active trench 516 can serve as a hard mask such that the channel termination region 595 is formed only below the bottom of the gate runner trenches 510, 512 and below the trench 514. Optionally, the trenches 510, 512, 514 can be made deep enough to reach the substrate as the end of the channel. If the end of the channel is formed at the trenches 510, 512, the cutoff trench 514 is not necessary as long as the thickness of the oxide 522 in the gate runner trenches 510, 512 is sufficient to carry the latching voltage.
第7A-7B圖表示將本文所述的雙柵極氧化物與美國專利申請號12/731,112所述的氧化物截止溝槽相結合的一種可選結構,特此引用美國專利申請號12/731,112所述的氧化物截止溝槽以作參考。第7A圖表示本發明一個實施例的雙柵極氧化物溝槽MOSFET元件700佈局的俯視圖,第7B圖表示雙柵極氧化物MOSFET 700的氧化物截止溝槽沿線A-A和B-B的剖面圖。用於製備氧化物截止溝槽 MOSFET 700的方法僅需要三個掩膜:一個溝槽掩膜、一個接觸掩膜以及一個金屬掩膜,這將在第8A-8R圖中詳細介紹。 7A-7B shows an alternative structure for combining the dual gate oxide described herein with the oxide cut-off trench described in U.S. Patent Application Serial No. 12/731,112, the disclosure of which is incorporated herein by reference. The oxide cut-off trench is for reference. Fig. 7A is a plan view showing the layout of a double gate oxide trench MOSFET device 700 according to an embodiment of the present invention, and Fig. 7B is a cross-sectional view showing the oxide cutoff trench of the double gate oxide MOSFET 700 along lines A-A and B-B. Used to prepare oxide cut-off trenches The MOSFET 700 method requires only three masks: a trench mask, a contact mask, and a metal mask, which will be described in detail in Figures 8A-8R.
如第7A-7B圖所示,溝槽MOSFET 700包含形成在位於有源晶胞區711中的佈滿氧化物的溝槽716中的柵極電極。柵極滑道形成在一套較寬的佈滿氧化物的溝槽中。柵極滑道包含鄰近並包圍著有源晶胞區711的第一部分710。柵極滑道包含藉由接頭707連接到柵極金屬層754(其外形如第7A圖中的虛線所示)上的第二部分712。氧化物截止溝槽714是一個用氧化物填充的溝槽,氧化物包圍著柵極滑道710、712以及有源區711。氧化物截止溝槽714具有一個位於氧化物截止溝槽714下方的重摻雜(n+)通道終止區730。 作為示例,在第7B圖所示的實施例中,n-型(以n-通道MOSFET元件為例)源極層736可能僅形成在有源晶胞區中的p-本體層734的頂部。源極金屬層752連接到有源區711中的源極/本體區。有源晶胞柵極溝槽716的柵極氧化物比柵極滑道710、712的柵極氧化物薄得多。柵極滑道710、712的厚柵極氧化物很厚(例如約為1000Å至2000Å),足以承載閉鎖電壓。另外,氧化物截止溝槽714很寬,並用電介質材料填充,足以承載相當於閉鎖電壓的高擊穿場。元件700形成在含有一個n-外延層704的半導體襯底上,n-外延層704形成在重摻雜的底部襯底702上方。 As shown in FIGS. 7A-7B, the trench MOSFET 700 includes a gate electrode formed in an oxide-filled trench 716 located in the active cell region 711. The gate runners are formed in a wider set of trenches filled with oxide. The gate runner includes a first portion 710 that is adjacent to and surrounds the active cell region 711. The gate runner includes a second portion 712 that is connected by a joint 707 to a gate metal layer 754 (having an outline as shown by the dashed line in Figure 7A). The oxide cutoff trench 714 is a trench filled with oxide that surrounds the gate runners 710, 712 and the active region 711. The oxide cutoff trench 714 has a heavily doped (n+) channel termination region 730 below the oxide cutoff trench 714. As an example, in the embodiment illustrated in FIG. 7B, the n-type (in the case of an n-channel MOSFET device as an example) source layer 736 may only be formed on top of the p-body layer 734 in the active cell region. A source metal layer 752 is connected to the source/body regions in the active region 711. The gate oxide of active cell gate trench 716 is much thinner than the gate oxide of gate runners 710, 712. The thick gate oxide of the gate runners 710, 712 is very thick (e.g., about 1000 Å to 2000 Å) sufficient to carry the latch-up voltage. Additionally, the oxide cut-off trench 714 is wide and filled with a dielectric material sufficient to carry a high breakdown field equivalent to the latch-up voltage. Element 700 is formed on a semiconductor substrate containing an n- epitaxial layer 704 formed over heavily doped underlying substrate 702.
第8A-8R圖表示一種僅需要三個掩膜製備圖7A-7B所示的元件700的方法。在第8A圖中,初始半導體襯底(例如具有一個位於底部襯底702上方的n-外延層704)具有一個形成在它上面的氧化層706。在第8B圖中,溝槽掩膜708是該技術中的第一個掩膜,藉由溝槽掩膜708中的開口,將溝槽蝕刻到外延層704中。溝槽包含有 源溝槽716、鄰近並包圍著有源溝槽716的柵極滑道溝槽710、柵極滑道溝槽712以及截止溝槽714。柵極滑道溝槽710和712比有源溝槽716寬,截止溝槽714比柵極滑道溝槽710、712寬。在第8C圖中,除去溝槽掩膜708,在溝槽710、712、714、716的底部和側壁上形成犧牲氧化物718。在第8D圖中,一個臨時的多晶矽層720形成在該元件上方。多晶矽層720的厚度足以完全填充較窄的有源716,但卻僅能佈滿較寬溝槽710、712、714的側壁和底部。藉由(各向同性的)蝕刻,除去溝槽710、712、714的多晶矽720,但保留有源溝槽716中的多晶矽720,如第8E圖所示。在第8F圖中,在該元件上形成一個氧化層722。這使得溝槽710、712、714中的氧化層變厚,並覆蓋有源溝槽716中的多晶矽720。平整化(例如藉由CMP)頂部氧化物722,使多晶矽720的頂部裸露出來,但保留溝槽710、712、714中的氧化物722,如第8G圖所示。在第8H圖中,除去臨時的多晶矽720。在第8I圖中,蝕刻掉有源溝槽716中的氧化物,並形成有源柵極氧化物。可以選擇在形成有源柵極氧化物726之前,生長並除去犧牲氧化物。由於溝槽710、712、714中的氧化物比有源溝槽716中的氧化物厚,因此在氧化物的蝕刻過程中並不能完全蝕刻掉,最後形成在溝槽710、712、714中的厚柵極氧化物724,比有源溝槽716中的有源柵極氧化物726更厚。在第8J圖中,在該元件上沉積一個多晶矽層728,多晶矽層728雖然填充了溝槽710、712、716,但僅僅內襯在很寬的氧化物截止溝槽714中。在第8K圖中,各向同性地回刻多晶矽材料728,使它保留在溝槽710、712、716中,但不再存在於很寬的氧化物截止溝槽714中。此時,可以在很寬的氧化物截止溝槽714的底部,例如藉由各向異性的植入,形成一個重摻雜的(n+)通道終止 區730。溝槽710、712、716中的多晶矽層728阻擋了到這些溝槽底部的植入。在該元件上沉積氧化物732,以便填充剩餘的氧化物截止溝槽714,並覆蓋多晶矽層728。然後,如第8L圖所示,平整氧化物732到外延層704的表面。 Figures 8A-8R show a method in which only three masks are needed to prepare the element 700 shown in Figures 7A-7B. In Figure 8A, the initial semiconductor substrate (e.g., having an n- epitaxial layer 704 overlying the bottom substrate 702) has an oxide layer 706 formed thereon. In FIG. 8B, trench mask 708 is the first mask in the art, and trenches are etched into epitaxial layer 704 by openings in trench mask 708. The groove contains The source trench 716, the gate runner trench 710 adjacent to and surrounding the active trench 716, the gate runner trench 712, and the turnoff trench 714. Gate runner trenches 710 and 712 are wider than active trenches 716, which are wider than gate runner trenches 710, 712. In FIG. 8C, trench mask 708 is removed, and sacrificial oxide 718 is formed on the bottom and sidewalls of trenches 710, 712, 714, 716. In Fig. 8D, a temporary polysilicon layer 720 is formed over the element. The thickness of the polysilicon layer 720 is sufficient to completely fill the narrower active 716, but only to fill the sidewalls and bottom of the wider trenches 710, 712, 714. The polysilicon 720 of the trenches 710, 712, 714 is removed by an (isotropic) etch, but the polysilicon 720 in the active trench 716 is retained, as shown in FIG. 8E. In Fig. 8F, an oxide layer 722 is formed on the element. This thickens the oxide layer in trenches 710, 712, 714 and overlies polysilicon 720 in active trench 716. The top oxide 722 is planarized (e.g., by CMP) to expose the top of the polysilicon 720, but retains the oxide 722 in the trenches 710, 712, 714 as shown in Figure 8G. In the 8H picture, the temporary polysilicon 720 is removed. In FIG. 8I, the oxide in active trench 716 is etched away and an active gate oxide is formed. The sacrificial oxide can be grown and removed prior to forming the active gate oxide 726. Since the oxides in the trenches 710, 712, 714 are thicker than the oxides in the active trenches 716, they are not completely etched away during the etching of the oxide, and finally formed in the trenches 710, 712, 714. Thick gate oxide 724 is thicker than active gate oxide 726 in active trench 716. In FIG. 8J, a polysilicon layer 728 is deposited over the device. The polysilicon layer 728, while filling the trenches 710, 712, 716, is only lined in a wide oxide cut-off trench 714. In FIG. 8K, polycrystalline germanium material 728 is isotropically etched back in trenches 710, 712, 716, but is no longer present in a wide oxide cut-off trench 714. At this point, a heavily doped (n+) channel termination can be formed at the bottom of a wide oxide cut-off trench 714, for example by anisotropic implantation. Area 730. The polysilicon layer 728 in trenches 710, 712, 716 blocks implantation to the bottom of these trenches. An oxide 732 is deposited over the component to fill the remaining oxide cutoff trenches 714 and cover the polysilicon layer 728. Then, as shown in FIG. 8L, the oxide 732 is planarized to the surface of the epitaxial layer 704.
在第8M圖中,在整個晶片上製備一個(p-型)本體區734。在第8N圖中,在本體區734上方,製備一個(n-型)源極區736。無需掩膜,就可以形成本體和源極區,作為全面植入。在第8O圖中,可以在該元件的上方,例如藉由LTO和BPSG沉積,形成很厚的電介質層738,在第8P圖中,使用了一個接觸掩膜740。接觸掩膜740僅是該技術中的第二個掩膜。在BPSG 738、源極區736以及本體區734中,蝕刻有源晶胞源極/本體接頭742。在裸露的本體區734中,可以進行(P+)本體接觸植入(圖中未示)。在BPSG 738中以及柵極滑道溝槽712中的多晶矽中,蝕刻柵極接頭744。 在第8Q圖中,除去接觸掩膜740,在接頭742、744中形成導電(例如鎢)插頭748。在形成鎢插頭748之前,可以先製備一個勢壘金屬746。在該元件上方,製備一個金屬層750(例如鋁)。在第8R圖中,利用金屬掩膜(圖中未示),在源極金屬752和柵極金屬754中,蝕刻金屬層750,從而僅利用三個掩膜就完成了雙柵極氧化物MOSFET元件700。儘管沒有說明,但是無需使用掩膜,就可以在該元件的背面形成漏極金屬。 In Figure 8M, a (p-type) body region 734 is prepared over the entire wafer. In the 8N figure, above the body region 734, an (n-type) source region 736 is prepared. The body and source regions can be formed without a mask as a full implant. In FIG. 8O, a very thick dielectric layer 738 can be formed over the component, such as by LTO and BPSG deposition, and in FIG. 8P, a contact mask 740 is used. Contact mask 740 is only the second mask in the art. In the BPSG 738, the source region 736, and the body region 734, the active cell source/body connector 742 is etched. In the bare body region 734, a (P+) body contact implant (not shown) can be performed. Gate junction 744 is etched in BPSG 738 and in the polysilicon in gate runner trench 712. In the 8Q diagram, the contact mask 740 is removed and a conductive (e.g., tungsten) plug 748 is formed in the joints 742, 744. A barrier metal 746 may be prepared prior to forming the tungsten plug 748. Above the element, a metal layer 750 (e.g., aluminum) is prepared. In the 8R picture, the metal layer 750 is etched in the source metal 752 and the gate metal 754 by using a metal mask (not shown), thereby completing the double gate oxide MOSFET using only three masks. Element 700. Although not illustrated, a drain metal can be formed on the back side of the element without using a mask.
儘管本發明關於某些較佳的版本已經做了詳細的敍述,但是仍可能存在其他版本。例如,一個適合可供替代絕緣體可能被作為氧化物。同時,根據上述描述,n-通道元件的例子被作為典型使用;然而,本發明的實施例也可運用於p-通道元件,藉由反轉適當 的導電型。因此,本發明的範圍不應由上述說明決定,與之相反,本發明的範圍應參照申請專利範圍及其全部等效內容。任何可選件(無論首選與否),都可與其他任何可選件(無論首選與否)組合。在申請專利範圍中,除非特別聲明,否則不定冠詞“一個”或“一種”都指下文內容中的一個或多個專案的數量。除非用“意思是”明確指出限定功能,否則所附的申請專利範圍並不應認為是意義和功能的局限。 Although the invention has been described in detail with respect to certain preferred versions, other versions are possible. For example, a suitable alternative insulator may be used as an oxide. Meanwhile, according to the above description, an example of an n-channel element is used as a typical; however, embodiments of the present invention can also be applied to a p-channel element by reversing the appropriate Conductive type. Therefore, the scope of the invention should not be determined by the description of the invention. Any option (whether preferred or not) can be combined with any other option (whether preferred or not). In the context of the patent application, the indefinite article "a" or "an" The scope of the appended claims should not be construed as limiting the meaning and function unless the meaning of the function is clearly indicated by the meaning.
儘管本發明的內容已經藉由上述優選實施例作了詳細介紹,但應當認識到上述的描述不應被認為是對本發明的限制。在本領域技術人員閱讀了上述內容後,對於本發明的多種修改和替代都將是顯而易見的。因此,本發明的保護範圍應由所附的申請專利範圍來限定。 Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the foregoing description should not be construed as limiting. Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.
200‧‧‧溝槽MOSFET 200‧‧‧ trench MOSFET
202‧‧‧溝槽 202‧‧‧ trench
204‧‧‧柵極滑道 204‧‧‧Gate slide
206‧‧‧柵極滑道 206‧‧‧Gate slide
207‧‧‧接頭 207‧‧‧Connector
208‧‧‧截止結構 208‧‧‧ cut-off structure
210‧‧‧有源區 210‧‧‧Active area
213‧‧‧晶片邊緣 213‧‧‧ wafer edge
248‧‧‧柵極金屬層 248‧‧‧gate metal layer
250‧‧‧縫隙 250‧‧‧ gap
252‧‧‧源極金屬 252‧‧‧ source metal
254‧‧‧截止金屬 254‧‧‧cut-off metal
Claims (26)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/782,573 US8394702B2 (en) | 2010-03-24 | 2010-05-18 | Method for making dual gate oxide trench MOSFET with channel stop using three or four masks process |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201142929A TW201142929A (en) | 2011-12-01 |
TWI528423B true TWI528423B (en) | 2016-04-01 |
Family
ID=44981998
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW100117201A TWI528423B (en) | 2010-05-18 | 2011-05-17 | Methods for fabricating semiconductor device and semiconductor device |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN102254826B (en) |
TW (1) | TWI528423B (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103413765B (en) * | 2013-08-27 | 2016-08-10 | 矽力杰半导体技术(杭州)有限公司 | Groove MOSFET device and preparation method thereof |
US10395970B2 (en) | 2013-12-05 | 2019-08-27 | Vishay-Siliconix | Dual trench structure |
TWI560883B (en) * | 2014-05-09 | 2016-12-01 | Sinopower Semiconductor Inc | Trench type power semiconductor device, wafer structure and fabrication method thereof |
CN104638011B (en) * | 2015-01-23 | 2018-05-11 | 无锡同方微电子有限公司 | A kind of groove MOSFET device and preparation method thereof |
CN111755526A (en) * | 2020-07-24 | 2020-10-09 | 华羿微电子股份有限公司 | Trench MOS device and preparation method |
CN113764527B (en) * | 2021-09-06 | 2023-03-24 | 华羿微电子股份有限公司 | MOSFET device groove terminal and preparation method |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070075360A1 (en) * | 2005-09-30 | 2007-04-05 | Alpha &Omega Semiconductor, Ltd. | Cobalt silicon contact barrier metal process for high density semiconductor power devices |
US7799642B2 (en) * | 2007-10-02 | 2010-09-21 | Inpower Semiconductor Co., Ltd. | Trench MOSFET and method of manufacture utilizing two masks |
-
2011
- 2011-05-16 CN CN201110142449.8A patent/CN102254826B/en active Active
- 2011-05-17 TW TW100117201A patent/TWI528423B/en active
Also Published As
Publication number | Publication date |
---|---|
TW201142929A (en) | 2011-12-01 |
CN102254826B (en) | 2014-02-26 |
CN102254826A (en) | 2011-11-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9214545B2 (en) | Dual gate oxide trench MOSFET with channel stop trench | |
TWI489559B (en) | Oxide terminated trench mosfet with three or four masks | |
TWI470676B (en) | Direct contact in trench with three-mask shield gate process | |
US9865694B2 (en) | Split-gate trench power mosfet with protected shield oxide | |
US9806175B2 (en) | Power MOSFET device structure for high frequency applications | |
US9000514B2 (en) | Fabrication of trench DMOS device having thick bottom shielding oxide | |
US8860131B2 (en) | Method for manufacturing a power device being integrated on a semiconductor substrate, in particular having a field plate vertical structure and corresponding device | |
US20150221734A1 (en) | Thicker bottom oxide for reduced miller capacitance in trench metal oxide semiconductor field effect transistor (mosfet) | |
TW201427022A (en) | High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices | |
TWI528423B (en) | Methods for fabricating semiconductor device and semiconductor device | |
US8564051B2 (en) | Power semiconductor device with buried source electrode | |
CN116682733A (en) | Split gate silicon carbide device with stepped groove structure and manufacturing method thereof |