TWI527241B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI527241B
TWI527241B TW103120135A TW103120135A TWI527241B TW I527241 B TWI527241 B TW I527241B TW 103120135 A TW103120135 A TW 103120135A TW 103120135 A TW103120135 A TW 103120135A TW I527241 B TWI527241 B TW I527241B
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type
region
doped
semiconductor device
doped region
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TW103120135A
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TW201547025A (zh
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張家偉
陳柏安
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新唐科技股份有限公司
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Priority to TW103120135A priority Critical patent/TWI527241B/zh
Priority to CN201410376872.8A priority patent/CN105304631B/zh
Priority to US14/680,482 priority patent/US9263447B2/en
Publication of TW201547025A publication Critical patent/TW201547025A/zh
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Publication of TWI527241B publication Critical patent/TWI527241B/zh

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Description

半導體裝置
本發明實施例係有關於半導體裝置，且特別有關於可避免拴鎖(latch-up)的半導體裝置。
拴鎖(latch-up)效應常見於互補式金氧半導體(Complementary Metal Oxide Semiconductor，CMOS)裝置中，主要形成原因在於互補式金氧半導體的N型金氧半導體(N-type Metal Oxide Semiconductor，NMOS)與P型金氧半導體(P-type Metal Oxide Semiconductor，PMOS)之間的寄生矽控整流(Silicon Controlled Rectifier)元件被觸發。一旦寄生SCR元件被觸發，則會產生非預期的大電流，影響半導體裝置的正常運作，甚至進一步造成晶片承受過大電流而燒毀。
第1A圖所示為習知CMOS裝置10的示意圖。CMOS裝置10包括P型基板100、形成於P型基板100中的P型井區102以及N型井區104、形成於P型井區102中的P+型摻雜區110和N+型摻雜區111以及形成於N型井區104中的P+型摻雜區112和N+型摻雜區113。如第1A圖所示，CMOS裝置10裝置中存在有一對寄生雙極性接面電晶體(Bipolar Junction Transistor，BJT)，即寄生PNP型雙極性接面電晶體Q1和寄生NPN型雙極性接面電晶體Q2。寄生雙極性接面電晶體Q1和Q2、N型井區104的電阻RNW以及P型井區102的電阻RPW構成第1B圖所示的寄生矽控 整流元件140。當寄生矽控整流元件140被觸發時，寄生NPN型雙極性接面電晶體Q2導通，且寄生NPN型雙極性接面電晶體Q2導通後所產生的基極電流會流經寄生PNP型雙極性接面電晶體Q1的集極端，使得Q1的集極電壓上升至超過導通電壓，因此導通寄生PNP型雙極性接面電晶體Q1，而寄生PNP型雙極性接面電晶體Q1導通後所產生的基極電流又會流至寄生NPN型雙極性接面電晶體Q2，進而產生更大的電流，此種正回饋的現象造成電流不斷增加，最後導致半導體裝置的損傷。
以下以功率電路(power circuit)為例說明CMOS裝置中的寄生矽控整流元件如何被觸發。第2A圖所示為習知功率電路的電路圖。功率電路包括功率PMOS電晶體P1、靜電放電(Electrostatic Discharge，ESD)NMOS電晶體N1、電阻R以及輸出端VOUT。第2B圖所示為習知功率電路在短路測試下的電路圖，如第2B圖所示，在短路測試(Short Circuit Test，SCT)中，輸出端VOUT連接至接地端，產生負偏壓，而此負偏壓落在寄生NPN型雙極性接面電晶體Q2的射極端，如第2C圖所示，使得寄生NPN型雙極性接面電晶體Q2導通，產生電流INMOS，並使得寄生PNP型雙極性接面電晶體Q1隨之導通，因此產生拴鎖電流，造成功率電路元件損傷。
綜上所述，需要發展可以避免拴鎖的半導體裝置。
本發明一實施例提供一種半導體裝置，包括：一P型基板；一N型區，接觸該P型基板；一N+型摻雜區，位於該N 型區中；一第一P+型摻雜區，位於該N型區中；一第二P+型摻雜區，位於該N型區中；一P型埋層，位於該N型區下方的該P型基板中並與該N型區接觸；以及一N型摻雜區，位於該P型埋層與該N型區接觸之接觸面下方的該P型基板中。
本發明另一實施例提供一種半導體裝置，包括：一P型基板；一N型金氧半導體裝置；以及一P型金氧半導體裝置，包括：一第一N型區，接觸該P型基板；一第一N+型摻雜區，位於該第一N型區中；一第一P+型摻雜區，位於該第一N型區中；一第二P+型摻雜區，位於該第一N型區中；一第一閘極結構，位於該第一P+型摻雜區與該第二P+型摻雜區之間的該N型區上；一P型埋層，位於該第一N型區下方的該P型基板中並與該第一N型區接觸；以及一N型摻雜區，位於該P型埋層與該第一N型區接觸之接觸面下方的該P型基板中。
10‧‧‧互補式金氧半導體裝置
30、40、50‧‧‧半導體裝置
100、300‧‧‧P型基板
102‧‧‧P型井區
104‧‧‧N型井區
110、112‧‧‧P+型摻雜區
111、113‧‧‧N+型摻雜區
140‧‧‧寄生矽控整流元件
310‧‧‧N型摻雜區
320‧‧‧P型埋層
330‧‧‧磊晶層
331、333、335‧‧‧高電壓N型井區
332、334‧‧‧高電壓P型井區
338‧‧‧P型基體區
339‧‧‧P型重摻雜汲極區
341、342、343、344、345、346‧‧‧N+型摻雜區
351、352、353、354、355‧‧‧P+型摻雜區
361、362、363、364、365、366、367、368、369‧‧‧隔離結構
371、372、373‧‧‧閘極結構
GS1、GS2、GS3‧‧‧防護環裝置
I_PMOS‧‧‧隔離式P型金氧半導體裝置
INMOS‧‧‧電流
N1‧‧‧N型金氧半導體電晶體
NMOS‧‧‧N型金氧半導體裝置
P1‧‧‧P型金氧半導體電晶體
PA1、PA2‧‧‧路徑
Q1、Q2‧‧‧寄生雙極性接面電晶體
R、RNW、RPW‧‧‧電阻
VDD、VSS‧‧‧電壓
VOUT‧‧‧輸出端
第1A圖所示為習知CMOS裝置10的示意圖。
第1B圖所示為習知CMOS裝置中的寄生SCR元件的電路圖。
第2A圖所示為習知功率電路的電路圖。
第2B圖所示為習知功率電路在短路測試下的電路圖。
第2C圖所示為習知功率電路的寄生SCR元件在短路測試下的電路圖。
第3圖所示為根據本發明一實施例之半導體裝置的示意圖。
第4圖所示為根據本發明一實施例之半導體裝置的示意圖。
第5圖所示為根據本發明一實施例之半導體裝置的示意圖。
第6圖所示為根據本發明一實施例之半導體裝置的示意圖。
第7圖所示為根據本發明一實施例之半導體裝置的示意圖。
以下說明為本發明的實施例。其目的是要舉例說明本發明一般性的原則，不應視為本發明之限制，本發明之範圍當以申請專利範圍所界定者為準。
值得注意的是，以下所揭露的內容可提供多個用以實踐本發明之不同特點的實施例或範例。以下所述之特殊的元件範例與安排僅用以簡單扼要地闡述本發明之精神，並非用以限定本發明之範圍。此外，以下說明書可能在多個範例中重複使用相同的元件符號或文字。然而，重複使用的目的僅為了提供簡化並清楚的說明，並非用以限定多個以下所討論之實施例以及/或配置之間的關係。此外，以下說明書所述之一個特徵連接至、耦接至以及/或形成於另一特徵之上等的描述，實際可包含多個不同的實施例，包括該等特徵直接接觸，或者包含其它額外的特徵形成於該等特徵之間等等，使得該等特徵並非直接接觸。
第3圖所示為根據本發明一實施例之半導體裝置 30的示意圖，半導體裝置30包括P型基板300以及隔離式P型金氧半導體(P-type Metal Oxide Semiconductor，PMOS)裝置I_PMOS。隔離式P型金氧半導體裝置I_PMOS包括N型摻雜區310、P型埋層320、磊晶層(epitaxial layer)330、高電壓N型井區335、P型重摻雜汲極區(P-type Heavily Doped Drain，PHDD)339、N+型摻雜區346、P+型摻雜區354和355、隔離結構365和366以及閘極結構372。在製程方面，首先N型摻雜區310形成於P型基板300中，P型埋層320形成於N型摻雜區310中，接著磊晶層330形成於P型埋層320上，磊晶層330可為N型或P型磊晶層，然後在磊晶層330中形成高電壓N型井區335等特徵。高電壓N型井區335位於磊晶層330中，N+型摻雜區346、P+型摻雜區354和P型重摻雜汲極區339位於高電壓N型井區335中，P+型摻雜區355位於P型重摻雜汲極區339中，其中P+型摻雜區354為隔離式PMOS裝置I_PMOS的源極區，P+型摻雜區355為隔離式PMOS裝置I_PMOS的汲極區，N+型摻雜區346為隔離式PMOS裝置I_PMOS的基極區。隔離結構365位於N+型摻雜區346以及P+型摻雜區354之間的高電壓N型井區335表面，而隔離結構366位於P型重摻雜汲極區339表面並緊鄰P+型摻雜區355。閘極結構372位於P+型摻雜區354以及P+型摻雜區355之間並覆蓋部份高電壓N型井區335以及部份隔離結構366。P型埋層320位於高電壓N型井區335下方的N型摻雜區310中並與高電壓N型井區335接觸，P型埋層320與N型摻雜區310接觸之一面的面積大於P型埋層320與高電壓N型井區335接觸之一面的面積，如第3圖所示。在一實施例中，N型摻雜區310為一N型埋層，而在 另一實施例中，N型摻雜區310為一深N型井區(deep N-type well)。隔離式PMOS裝置I_PMOS具有使高電壓N型井區335之下表面不直接接觸P型基板300的P型埋層320和N型摻雜區310，因此在此說明書中稱為隔離式PMOS裝置。
第3圖之隔離式PMOS裝置I_PMOS為一隔離式高電壓PMOS(High Voltage PMOS，HVPMOS)裝置，而本發明另一實施例可提供一隔離式低電壓PMOS(Low Voltage PMOS，LVPMOS)裝置，隔離式LVPMOS裝置與隔離式HVPMOS裝置的差別在於隔離式LVPMOS裝置沒有隔離結構366以及P型重摻雜汲極區339，且閘極結構372位於P+型摻雜區354以及P+型摻雜區355之間並僅覆蓋部份高電壓N型井區335以導通一通道。
第4圖所示為根據本發明一實施例之半導體裝置40的示意圖。半導體裝置40為一互補式金氧半導體(Complementary Metal Oxide Semiconductor，CMOS)裝置，包括P型基板300、N型金氧半導體(N-type Metal Oxide Semiconductor，NMOS)裝置NMOS以及隔離式PMOS裝置I_PMOS。在一實施例中，NMOS裝置NMOS為普通CMOS裝置的NMOS裝置，在另一實施例中，NMOS裝置NMOS為一橫向擴散N型金氧半導體(Laterally Diffused N-type Metal Oxide Semiconductor，LDNMOS)裝置。在NMOS裝置NMOS為LDNMOS裝置的實施例中，NMOS裝置NMOS包括高電壓N型井區331、P型基體區338、P+型摻雜區351、N+型摻雜區341、342、343和344、隔離結構361和362以及閘極結構371和373。高電壓N型井區331位於磊晶層330中，P型基體區338位於高電壓N型 井區331中。P+型摻雜區351位於P型基體區338中，N+型摻雜區342位於P型基體區338中並緊鄰P+型摻雜區351之一側，N+型摻雜區343位於P型基體區338中並緊鄰P+型摻雜區351與N+型摻雜區342相鄰之一側的對向側。N+型摻雜區341和344位於高電壓N型井區331中且分別位於P型基體區338之兩側。其中，P+型摻雜區351為NMOS裝置NMOS的基極區(bulk area)，N+型摻雜區342和343為NMOS裝置NMOS的源極區，而N+型摻雜區341和344為NMOS裝置NMOS的汲極區。隔離結構361位於P型基體區338與N+型摻雜區341之間的高電壓N型井區331表面，而隔離結構362位於P型基體區338與N+型摻雜區344之間的高電壓N型井區331表面。閘極結構371位於N+型摻雜區343與N+型摻雜區344之間並覆蓋部份P型基體區338以及部份隔離結構362。閘極結構373位於N+型摻雜區341與N+型摻雜區342之間並覆蓋部份P型基體區338以及部份隔離結構361。隔離式PMOS裝置I_PMOS與第3圖一樣因此不再複述。
第5圖所示為根據本發明一實施例之半導體裝置50的示意圖。半導體裝置50包括基底300、NMOS裝置NMOS、隔離式PMOS裝置I_PMOS以及防護環(guard ring)裝置GS1、GS2和GS3。NMOS裝置NMOS可為普通CMOS裝置的NMOS裝置或是LDNMOS裝置，在NMOS裝置NMOS為LDNMOS裝置的實施例中，NMOS裝置NMOS包括高電壓N型井區331、P型基體區338、P+型摻雜區351、N+型摻雜區341、342、343和344、隔離結構361和362以及閘極結構371和373。高電壓N型井區331形成於磊晶層330(未圖示)中，磊晶層330可為N型或P型磊晶層， P型基體區338位於高電壓N型井區331中。P+型摻雜區351位於P型基體區338中，N+型摻雜區342位於P型基體區338中並緊鄰P+型摻雜區351之一側，N+型摻雜區343位於P型基體區338中並緊鄰P+型摻雜區351與N+型摻雜區342相鄰之一側的對向側。N+型摻雜區341和344位於高電壓N型井區331中且分別位於P型基體區338之兩側。其中，P+型摻雜區351為NMOS裝置NMOS的基極區，N+型摻雜區342和343為NMOS裝置NMOS的源極區，而N+型摻雜區341和344為NMOS裝置NMOS的汲極區。隔離結構361位於P型基體區338與N+型摻雜區341之間的高電壓N型井區331表面，而隔離結構362位於P型基體區338與N+型摻雜區344之間的高電壓N型井區331表面。閘極結構371位於N+型摻雜區343與N+型摻雜區344之間並覆蓋部份P型基體區338以及部份隔離結構362，閘極結構373位於N+型摻雜區341與N+型摻雜區342之間並覆蓋部份P型基體區338以及部份隔離結構361。
隔離式PMOS裝置I_PMOS包括N型摻雜區310、P型埋層320、高電壓N型井區335、P型重摻雜汲極區339、N+型摻雜區346、P+型摻雜區354和355、隔離結構365和366以及閘極結構372。高電壓N型井區335形成於磊晶層330(未圖示)中，N+型摻雜區346以及P+型摻雜區354位於高電壓N型井區335中，P型重摻雜汲極區339位於高電壓N型井區335中，且P+型摻雜區355位於P型重摻雜汲極區339中，其中P+型摻雜區354為隔離式PMOS裝置I_PMOS的源極區，P+型摻雜區355為隔離式PMOS裝置I_PMOS的汲極區，N+型摻雜區346為隔離式PMOS裝置 I_PMOS的基極區。隔離結構365位於N+型摻雜區346以及P+型摻雜區354之間的高電壓N型井區335表面，而隔離結構366位於P+型摻雜區354以及P+型摻雜區355之間的高電壓N型井區339表面。閘極結構372位於P+型摻雜區354以及P+型摻雜區355之間並覆蓋部份高電壓N型井區335以及部份隔離結構366。P型埋層320位於高電壓N型井區335下方的N型摻雜區310中並與高電壓P型井334以及高電壓N型井區335接觸，P型埋層320與N型摻雜區310接觸之一面的面積大於P型埋層320與高電壓N型井區335接觸之一面的面積。在一實施例中，N型摻雜區310為一N型埋層，而在另一實施例中，N型摻雜區310為一深N型井區(deep N-type well)。
在製程方面，首先N型摻雜區310形成於P型基板300中，P型埋層320形成於N型摻雜區310中，接著磊晶層330形成於P型埋層320上，磊晶層330可為N型或P型磊晶層，然後在磊晶層330中形成高電壓N型井區331、333和335以及高電壓P型井區332和334。
如第5圖所示，防護環裝置GS1位於磊晶層330中並圍繞高電壓N型井區335，防護環裝置GS1包括位於磊晶層330(未繪示)中並圍繞高電壓N型井區335的高電壓P型井區334以及位於高電壓P型井334區中的P+型摻雜區353，其中高電壓P型井區334與P型埋層320接觸，例如第5圖所示，高電壓P型井區334之內環部份皆與P型埋層320接觸。防護環裝置GS2位於磊晶層330中並圍繞防護環裝置GS1，防護環裝置GS2包括位於磊晶層330中並圍繞高電壓P型井區334的高電壓N型井區333以及 位於高電壓N型井區333中的N+型摻雜區345，其中高電壓N型井區333與N型摻雜區310接觸，例如第5圖所示，高電壓N型井區333的下表面皆與N型摻雜區310接觸。防護環裝置GS3位於磊晶層330中並圍繞NMOS裝置NMOS，防護環裝置GS3包括位於磊晶層330中並圍繞高電壓N型井區331的高電壓P型井區332以及位於高電壓P型井332區中的P+型摻雜區352。隔離裝置363位於P+型摻雜區352與N+型摻雜區345之間的高電壓P型井區332和高電壓N型井區333表面並覆蓋部份高電壓P型井區332以及部份高電壓N型井區333。隔離裝置369位於N+型摻雜區345與P+型摻雜區353之間的高電壓N型井區333和高電壓P型井區334表面並覆蓋部份高電壓N型井區333以及部份高電壓P型井區334。隔離裝置364位於P+型摻雜區353與N+型摻雜區346之間的高電壓P型井區334和高電壓N型井區335表面並覆蓋部份高電壓P型井區334以及部份高電壓N型井區335。隔離裝置367位於P+型摻雜區355與P+型摻雜區353之間的高電壓N型井區335和高電壓P型井區334表面並覆蓋部份高電壓N型井區335以及部份高電壓P型井區334。
如上所述，第5圖之隔離式PMOS裝置I_PMOS為一隔離式HVPMOS裝置，但本發明並不侷限於此。舉例而言，本發明另一實施例可提供一隔離式LVPMOS裝置，隔離式LVPMOS裝置與隔離式HVPMOS裝置的差別在於隔離式LVPMOS裝置沒有隔離結構366以及P型重摻雜汲極區339，且閘極結構372位於P+型摻雜區354以及P+型摻雜區355之間並僅覆蓋部份高電壓N型井區335以導通一通道。
第6圖所示為根據本發明一實施例之半導體裝置60的示意圖。半導體裝置60包括基底300、NMOS裝置NMOS1、隔離式PMOS裝置I_PMOS1以及防護環裝置GS1、GS2和GS3。第6圖之半導體裝置60與第5圖之半導體裝置50的差異在於高電壓N型井區331形成於N型磊晶層337中時其下表面並未接觸基板300，高電壓N型井區333形成於N型磊晶層337中時其下表面並未接觸N型摻雜區310，且高電壓N型井區335形成於N型磊晶層337中時其下表面並未接觸P型埋層320。在製程方面，首先N型摻雜區310形成於P型基板300中，P型埋層320形成於N型摻雜區310中，接著N型磊晶層337形成於P型埋層320上，然後在N型磊晶層337中形成高電壓N型井區331、333和335以及高電壓P型井區332和334，其中高電壓N型井區331、333和335的深度小於N型磊晶層337的厚度，而高電壓P型井區332和334的深度等於N型磊晶層337的厚度使得高電壓P型井區332接觸基板300而高電壓P型井區334接觸N型摻雜區310和P型埋層320。由於高電壓N型井區331、333和335是藉由同一道製程形成於N型磊晶層337中，因此高電壓N型井區331、333和335下方的N型磊晶層337厚度皆相同。半導體裝置60的其餘部份皆與半導體裝置50類似，因此不再複述。
第7圖所示為根據本發明一實施例之半導體裝置70的示意圖。半導體裝置70包括基底300、NMOS裝置NMOS2、隔離式PMOS裝置I_PMOS2以及防護環裝置GS1、GS2和GS3。第7圖之半導體裝置70與第5圖之半導體裝置50的差異在於半導體裝置70沒有高電壓N型井區331、333和335。在製程方面， 首先N型摻雜區310形成於P型基板300中，P型埋層320形成於N型摻雜區310中，接著N型磊晶層337形成於P型埋層320上，然後在N型磊晶層337中形成高電壓P型井區332和334，其中高電壓P型井區332和334的深度等於N型磊晶層337的厚度使得高電壓P型井區332接觸基板300而高電壓P型井區334接觸N型摻雜區310和P型埋層320。藉由高電壓P型井區332和334所劃分出來的磊晶層337各個區域可發揮與第5圖之高電壓N型井區331、333和335相似的功效。半導體裝置70的其餘部份皆與半導體裝置50類似，因此不再複述。
在第5圖之實施例的另一變化實施例中，可省略磊晶層300而直接在基板300中形成高電壓N型井區331、333和335以及高電壓P型井區332和334。
在上述實施例中，各隔離結構可為場氧化層(FOX)結構或淺溝渠隔離(STI)結構。須注意的是，在上述實施例中雖以不同標號表示各隔離結構，但各隔離結構並不限定為分離的隔離結構而可為一相連隔離結構的一部分。例如一環狀隔離結構可包括隔離結構364以及隔離結構367，此環狀隔離結構位於高電壓N型井區335與高電壓P型井區334交界處的磊晶層330上並覆蓋部份高電壓N型井區335以及部份高電壓P型井區334。
在上述實施例中，如第3~7圖所示，N型摻雜區310位於P型埋層320與高電壓N型井區335或N型磊晶層337接觸之接觸面下方的P型基板300中，且P型埋層320的上表面與P型基板300以及N型摻雜區310的上表面切齊，但本發明並不侷限於此。舉例而言，在一實施例中，P型埋層320會向上擴散而使得 P型埋層320的一部分突出於P型基板300以及N型摻雜區310的表面之外，也就是說，P型埋層320的一部分位於N型摻雜區310中而P型埋層320的其他部份不位於N型摻雜區310中。
如上列所述，本發明之一實施例係在PMOS裝置下方配置了P型埋層和N型摻雜區以形成隔離式HVPMOS裝置。由於若在NMOS裝置側增加上述製程可能造成NMOS裝置的參數改變，例如閾值電壓Vt、飽和電流IdSAT、汲極-源極崩潰電壓BVDss和導通電阻Ron等，因此本發明之一實施例在PMOS裝置側增加上述製程相較於在NMOS裝置側增加上述製程可避免增加調整製程參數的時間與成本，也可避免降低靜電放電能力。除此之外，如第5圖所示，對於水平路徑PA1而言，藉由防護環GS1、GS2和GS3的設置可以消除水平SCR路徑，而對於垂直路徑PA2而言，藉由在PMOS裝置下方增加P型埋層320和N型摻雜區310可以消除垂直SCR路徑，因此，不論水平路徑上或垂直路徑上皆可消除SCR路徑，達成避免拴鎖的半導體裝置。
以上所述為實施例的概述特徵。所屬技術領域中具有通常知識者應可以輕而易舉地利用本發明為基礎設計或調整以實行相同的目的和/或達成此處介紹的實施例的相同優點。所屬技術領域中具有通常知識者也應了解相同的配置不應背離本創作的精神與範圍，在不背離本創作的精神與範圍下他們可做出各種改變、取代和交替。說明性的方法僅表示示範性的步驟，但這些步驟並不一定要以所表示的順序執行。可另外加入、取代、改變順序和/或消除步驟以視情況而作調整，並與所揭露的實施例精神和範圍一致。
30‧‧‧半導體裝置
300‧‧‧P型基板
310‧‧‧N型摻雜區
320‧‧‧P型埋層
330‧‧‧磊晶層
335‧‧‧高電壓N型井區
339‧‧‧P型重摻雜汲極區
346‧‧‧N+型摻雜區
354、355‧‧‧P+型摻雜區
365、366‧‧‧隔離結構
372‧‧‧閘極結構
I_PMOS‧‧‧隔離式P型金氧半導體裝置

Claims (21)

  1. 一種半導體裝置，包括：一P型基板；一N型區，接觸該P型基板；一N+型摻雜區，位於該N型區中；一第一P+型摻雜區，位於該N型區中；一第二P+型摻雜區，位於該N型區中；一P型埋層，位於該N型區下方的該P型基板中並與該N型區接觸；以及一N型摻雜區，位於該P型埋層與該N型區接觸之接觸面下方的該P型基板中。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該P型埋層之一部分位於該N型摻雜區中，該P型埋層之其他部份不位於該N型摻雜區中。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該N型摻雜區為一N型埋層或一深N型井區。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該P型埋層與該N型摻雜區接觸之一面的面積大於該P型埋層與該N型區接觸之一面的面積。
  5. 如申請專利範圍第1項所述之半導體裝置，更包括：一磊晶層，形成於該P型埋層上；其中該N型區為一高電壓N型井區且位於該磊晶層中。
  6. 如申請專利範圍第1項所述之半導體裝置，其中該N型區包括： 一N型磊晶層，形成於該P型埋層上；以及一高電壓N型井區，位於該N型磊晶層中，該高電壓N型井區不接觸該P型埋層。
  7. 如申請專利範圍第1項所述之半導體裝置，其中該N型區為一N型磊晶層或一高電壓N型井區。
  8. 如申請專利範圍第1項所述之半導體裝置，更包含一閘極結構，位於該第一P+型摻雜區與該第二P+型摻雜區之間的該N型區上。
  9. 如申請專利範圍第1項所述之半導體裝置，更包括：一第一隔離結構，位於該N+型摻雜區與該第一P+型摻雜區之間的該N型區表面。
  10. 如申請專利範圍第1項所述之半導體裝置，更包括：一P型重摻雜汲極區，位於該第一N型區中，其中該第二P+型摻雜區位於該P型重摻雜汲極區中；以及一第二隔離結構，位於該P型重摻雜汲極區之表面並緊鄰該第二P+型摻雜區，其中該第一閘極結構之一部分覆蓋該第二隔離結構。
  11. 一種半導體裝置，包括：一P型基板；一N型金氧半導體裝置；以及一P型金氧半導體裝置，包括：一第一N型區，接觸該P型基板；一第一N+型摻雜區，位於該第一N型區中；一第一P+型摻雜區，位於該第一N型區中； 一第二P+型摻雜區，位於該第一N型區中；一第一閘極結構，位於該第一P+型摻雜區與該第二P+型摻雜區之間的該N型區上；一P型埋層，位於該第一N型區下方的該P型基板中並與該第一N型區接觸；以及一N型摻雜區，位於該P型埋層與該第一N型區接觸之接觸面下方的該P型基板中。
  12. 如申請專利範圍第11項所述之半導體裝置，其中該N型摻雜區為一N型埋層或一深N型井區。
  13. 如申請專利範圍第11項所述之半導體裝置，其中該P型埋層與該N型摻雜區接觸之一面的面積大於該P型埋層與該第一N型區接觸之一面的面積。
  14. 如申請專利範圍第11項所述之半導體裝置，其中該P型金氧半導體裝置更包括：一第一隔離結構，位於該第一N+型摻雜區與該第一P+型摻雜區之間的該第一N型區表面。
  15. 如申請專利範圍第11項所述之半導體裝置，其中該P型金氧半導體裝置更包括：一P型重摻雜汲極區，位於該第一N型區中，其中該第二P+型摻雜區位於該P型重摻雜汲極區中；以及一第二隔離結構，位於該P型重摻雜汲極區之表面並緊鄰該第二P+型摻雜區，其中該第一閘極結構之一部分覆蓋該第二隔離結構。
  16. 如申請專利範圍第11項所述之半導體裝置，其中該N型金氧 半導體裝置為一橫向擴散N型金氧半導體裝置。
  17. 如申請專利範圍第11項所述之半導體裝置，其中該N型金氧半導體裝置包括：一第二N型區，接觸該P型基板；一P型基體區，位於該第二N型區中；一第三P+型摻雜區，位於該P型基體區中；一第二N+型摻雜區，位於該P型基體區中並緊鄰該第三P+型摻雜區之一側；一第三N+型摻雜區，位於該P型基體區中並緊鄰該第三P+型摻雜區之另一側；一第四N+型摻雜區，位於該第二N型區中；一第五N+型摻雜區，位於該第二N型區中；以及一第二閘極結構，位於該第三N+型摻雜區與該第四N+型摻雜區之間的該第二N型區上，並覆蓋部份該P型基體區。
  18. 如申請專利範圍第17項所述之半導體裝置，其中該N型金氧半導體裝置更包括：一第三隔離結構，位於該P型基體區與該第五N+型摻雜區之間的該第二N型區表面；以及一第四隔離結構，位於該P型基體區與該第四N+型摻雜區之間的該第二N型區表面，其中該第二閘極結構覆蓋部份該第四隔離結構。
  19. 如申請專利範圍第11項所述之半導體裝置，更包括：一第一防護環裝置，接觸該P型基板並圍繞該第一N型區；一第二防護環裝置，接觸該P型基板並圍繞該第一防護環裝 置；以及一第三防護環裝置，接觸該P型基板並圍繞該N型金氧半導體裝置。
  20. 如申請專利範圍第19項所述之半導體裝置，其中該P型埋層與一第一高電壓P型井區接觸。
  21. 如申請專利範圍第19項所述之半導體裝置，其中該N型摻雜區與一第三N型區接觸。
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US20150364471A1 (en) 2015-12-17
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US9263447B2 (en) 2016-02-16

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