TWI527163B - 半導體晶片堆疊組件 - Google Patents
半導體晶片堆疊組件 Download PDFInfo
- Publication number
- TWI527163B TWI527163B TW101144779A TW101144779A TWI527163B TW I527163 B TWI527163 B TW I527163B TW 101144779 A TW101144779 A TW 101144779A TW 101144779 A TW101144779 A TW 101144779A TW I527163 B TWI527163 B TW I527163B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor wafer
- wafer
- substrate
- electrical
- semiconductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0233—Mounting configuration of laser chips
- H01S5/02345—Wire-bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0235—Method for mounting laser chips
- H01S5/02355—Fixing laser chips on mounts
- H01S5/0237—Fixing laser chips on mounts by soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Wire Bonding (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Semiconductor Integrated Circuits (AREA)
- Light Receiving Elements (AREA)
- Semiconductor Lasers (AREA)
Description
本發明之實施例大體上關於半導體裝置、半導體裝置封裝、半導體裝置堆疊組件、及光學通訊及資料轉移。
積體電路(IC)晶片性能、電力管理、及尺寸改進使用於組合IC晶片之封裝及組合的材料及技術之需求不斷地增加。通常,積體電路晶片亦已知做為微晶片、矽晶片、半導體晶片、晶片、或晶粒。IC晶片易於各類常見裝置中發現,諸如電腦、汽車、電視、CD播放器、智慧型手機及行動電話中之微處理器。在製造後,半導體晶片典型地以一種方式封裝,其考量將置放半導體晶片之裝置所提供之操作環境。通常,半導體晶片之封裝保護晶片免於損害並用於電子連接,其將半導體晶片連接至電源及其他電子組件(實施例如輸入/輸出功能)。隨著半導體晶片傾向朝向較高帶寬性能及使用者所欲較小外形尺寸,半導體晶片之封裝必須符合尺寸、熱管理、電力輸送、互連密度、及整合挑戰。
本發明之實施例提供半導體晶片堆疊組件,其提供第一半導體裝置與第二半導體裝置之直接附接。依據本發明之實施例的半導體晶片組件可為覆晶,黏合至基板或直接
黏合至主機板。本發明之實施例提供低z-高度外形尺寸封裝及組件,同時提供所欲3D系統整合。本發明之實施例可用於例如矽光子學裝置至驅動器或裝置至信號轉換器、邏輯至記憶體、記憶體至記憶體、及邏輯至邏輯介面堆疊組件。依據本發明之實施例的封裝組件對於例如具雷射之封裝驅動器及具光檢測器之轉換阻抗放大器是有用的。
圖1A-B描繪半導體裝置之封裝組件。在圖1A-B中,基板105容納及電耦合至第一半導體晶片110。基板105為例如印刷電路板、有芯或無芯封裝基板、母板(主機板或邏輯板)、或包含電互連之其他基板,電互連可電互連計算系統之各式元件,諸如半導體晶片、感應器、裝置(例如RF開關、溫度感應器、加速計、陀螺儀、振盪器、壓電阻感應器、RFID系統、天線、及/或GPS系統)、及/或電源。在本發明之實施例中,基板105可***或電連接至主機板。在本發明之實施例中,半導體晶片110為矽光子學裝置,諸如光感應器或光檢測器晶片(包含一或多個光感應器或光檢測器之基板)或雷射晶片(包含一或多個雷射之基板)。光感應器及光檢測器包括例如晶片,包含崩瀉光二極體或PIN二極體;以及雷射晶片包括例如垂直腔表面發射雷射(VCSEL)晶片、二極體雷射晶片、混合半導體雷射晶片。在本發明之替代實施例中,半導體晶片110為邏輯晶片、處理器、圖形晶片、記憶體晶片、DSP(數位信號處理器)晶片或如文中所說明之其他半導體晶片。在圖1B中,基板包含凹區107。
在本發明之實施例中,與第一半導體晶片110有關之電互連115可為例如導電柱、焊接墊、凸塊、行、接腳、或其他導電結構。與基板105有關之電互連(未顯示)可為例如導電柱、焊接墊、凸塊、行、接腳、或其他導電結構。第一半導體晶片110與基板105之間之電連接可以或不具焊接劑形成。半導體晶片110經由例如可選擇的焊接劑接頭120電耦合至基板105。焊接劑接頭120黏合至並與半導體晶片110上之電互連115及基板105上之相應電互連(未顯示)電連接。在本發明之實施例中,基板105之電互連為墊,第一半導體晶片110之相應電互連115為凸塊、行、或接腳,且電連接係以焊接劑接頭120形成。
不具焊接劑而形成之電互連及導電柱、焊接墊、凸塊、行、接腳或其他導電結構之間之金屬-金屬黏合,例如可經由晶片之熱壓黏合、熱超聲黏合、及/或環氧樹脂黏合而予完成。在本發明之實施例中,柱、焊接墊、凸塊、行、接腳、或其他導電結構可包含金或銅,並使用熱壓黏合予以結合。在本發明之實施例中,電互連包含金屬。形成電互連115及與基板105有關者之金屬可為例如銅、金、鎢、鉑、及/或鋁。
第二半導體晶片125係設於基板105與第一半導體晶片110之間。第二半導體晶片125直接黏合至第一半導體晶片110並經由電互連130而與第一半導體晶片110電互連。黏合可經由焊接劑區。第一半導體晶片110及第二半導體晶片125上之相應電互連區為例如導電柱、焊接墊、
凸塊、行、接腳、或其他導電結構。電互連及導電柱、焊接墊、凸塊、行、接腳、或其他導電結構之間之金屬-金屬黏合亦可經由例如熱壓黏合、熱超聲黏合、及/或環氧樹脂予以完成。形成電互連130之金屬可為例如銅、金、鎢、鉑、及/或鋁。在本發明之實施例中,第二半導體晶片125為雷射之驅動器或光檢測器之轉換阻抗放大器。通常,轉換阻抗放大器(TIA)將來自光檢測器之電流信號轉換為電壓信號並予放大。在進一步本發明之實施例中,第二半導體晶片125為邏輯晶片、記憶體晶片、處理器、圖形晶片、無線通訊晶片、或無線通訊晶片組。在本發明之實施例中,第二半導體晶片125為薄型半導體晶片。半導體晶片125之高度可薄至50 μm或更少,或高度介於100 μm與20 μm之間。
圖1A及圖1B中第一半導體晶片110之第一側與基板105之近處側之間之距離分別以「h1」及「h2」代表。在本發明之實施例中,第一半導體晶片110與基板105之間之間隙135的高度h1可為例如介於75與150 μm之間之值。可估算焊接劑接頭120之尺寸,以製造具有所欲高度之間隙135。在本發明之實施例中,焊接劑接頭高度可為25至145 μm或80至145 μm。基板105中凹區107接近第二半導體晶片125,並允許高度h2小於高度h1。在本發明之實施例中,第一半導體晶片110與基板105之間間隙135之高度h2可為例如介於15與125 μm之間之值。
第一半導體晶片110可以覆晶的方式黏合至基板105。可選擇地,底部填充材料係置於間隙135中。底部填充材料可包含例如流動性介電材料,諸如具或不具填料粒子之環氧樹脂,或具或不具填料粒子之聚合物或無機材料。
圖2A-B提供半導體裝置之額外封裝組件。圖2A-B之組件的元件與相對於圖1A-B所討論者相同。然而,在圖2A-B中,第一半導體晶片110延伸部分超過基板105,且部分可選擇的校準單元140接觸第一半導體晶片110延伸超過基板105之區域。校準單元用以校準矽光子學晶片與轉移計算系統之元件間之光的光轉移系統之光學耦合器是有用的。
圖3A-B提供半導體裝置之進一步額外封裝組件。圖3A-B之組件的元件與相對於圖1A-B所討論者相同。然而,在圖3A-B中,電互連115及130與第一及第二半導體晶片110及125之相對配置改變。本發明之實施例並不侷限於特別互連形樣或相對於彼此之半導體晶片的配置。
圖4提供實施例其中本發明之封裝組件經安裝而具基板上之邏輯晶片。在圖4中,基板405容納IC晶片410及封裝組件415及417。基板405為例如印刷電路板、有芯或無芯封裝基板、母板(主機板或邏輯板)、或包含可電互連計算系統之各式元件的電互連之其他基板。IC晶片410為例如處理器、記憶體控制器集線器、圖形晶片、網路晶片、或包含諸如邏輯晶片及記憶體晶片的一或多個
晶片之封裝。封裝組件415及417為依據圖1A-B、圖2A-B、及/或圖3A-B之組件。封裝組件415及417經由基板405而與IC晶片410電互連。在本發明之實施例中,封裝組件415包含雷射晶片及雷射驅動器,且封裝組件417包含光檢測器及轉換阻抗放大器。光檢測器/轉換阻抗放大器允許輸入光學資料輸入IC晶片410中作為電信號。雷射晶片/雷射驅動器允許電子資料從IC晶片410輸出至輸出作為光學信號。其他數量之半導體晶片410及與基板405有關之組件415及417亦可。可與圖4之組件有關之其他元件包括例如熱管理系統及光學互連系統。當然,亦存在使用本發明之封裝組件的許多其他方式。
圖5提供使用光學資料轉移系統之示範計算系統。在圖5中,計算系統包含經由光學互連515連接至記憶體控制器集線器510之處理器505。光學互連515(為求描繪清晰未顯示細節)包含雷射晶片、可選擇地耦合至雷射晶片之光學耦合器、光檢測器、可選擇地耦合至光檢測器之光學耦合器、及可選擇地耦合至光學耦合器並可導引其間之光的一或多個波導。雷射晶片、光檢測器晶片、或二者依據圖1A-B、圖2A-B、及/或圖3A-B而與驅動器晶片或轉換阻抗放大器組合於封裝組件中。雷射晶片可接收來自輸出邏輯晶片之資料,且光檢測器可發送資料至輸入邏輯晶片。雙向I/O通訊系統包含與諸如處理器之第一IC晶片有關之至少一雷射晶片及至少一光檢測器,及與第二IC晶片有關之至少一雷射晶片及至少一光檢測器。與第
一IC晶片有關之雷射晶片可選擇地耦合至與第二IC晶片有關之光檢測器,且與第二IC晶片有關之雷射晶片可選擇地耦合至與第一IC晶片有關之光檢測器。在本發明之實施例中,光學互連515為雙向鏈路及/或與例如VCSEL晶片之陣列及相應光檢測器之陣列有關之複數光學連接。在圖5之計算系統中,記憶體控制器集線器510經由光學互連515耦合至記憶體晶片520,經由光學互連515耦合至圖形晶片525,及經由光學互連515耦合至輸入/輸出控制器晶片530。輸入/輸出控制器晶片530經由光學互連515連接至輸入/輸出裝置535。輸入/輸出裝置535包括例如USB(通用序列匯流排)、USB2、SATA(序列先進技術附件)、音頻、PCI(週邊組件互連)、及PCI express裝置。在本發明之實施例中,計算系統之一或多個元件(例如505、510、520、525、530、及/或535)經由電互連而非光學互連515相耦合,且經由電互連可具有資料輸入/輸出功能。當然,其他組態及元件可用於計算系統。
文中所討論之半導體晶片可為任何類型積體電路裝置,諸如邏輯晶片、處理器(單核心或多核心)、記憶體晶片、類比晶片、數位晶片、圖形晶片、及/或MEMS裝置。例如,第一半導體晶片可為處理器、堆疊記憶體/邏輯單元、或複數堆疊記憶體晶片,且第二半導體晶片可為記憶體晶片或邏輯晶片。可形成組合之其他示範晶片包括微處理器、圖形處理器、信號處理器、網路處理器、具
有多功能單元(諸如一或多個處理單元、圖形單元、通訊單元、信號處理單元、安全單元)之系統單晶片(SoC)、無線通訊晶片、及/或無線通訊晶片組。「處理器」用詞可指處理來自暫存器及/或記憶體之電子資料而將該電子資料轉換為可儲存於暫存器及/或記憶體中之其他電子資料的任何裝置或部分裝置。記憶體晶片可為例如靜態隨機存取記憶體(SRAM)晶片、及/或動態隨機存取記憶體(DRAM)晶片、及/或非揮發性記憶體晶片。無線通訊晶片可針對資料轉移至及自計算裝置而實施無線通訊。用詞並未暗示相關裝置不包含任何線路,儘管在若干實施例中可能未包含線路。無線通訊晶片可實施任何無線標準或協定,包括但不侷限於Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、其衍生以及指定做為3G、4G、5G、及以上之任何其他無線協定。第一無線通訊晶片可專用於較短距離無線通訊,諸如Wi-Fi及藍牙,且第二無線通訊晶片可專用於較長距離無線通訊,諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、及其他,第一及第二通訊晶片可形成通訊晶片組。在本發明之替代實施例中,第一半導體晶片為矽光子學裝置,諸如光檢測器晶片或雷射晶片,且第二半導體晶片為驅動器晶片或轉換阻抗放大器晶片。
依據本發明之實施例之封裝結構可包含部分任何類型
計算系統,諸如手持式計算系統(例如行動電話、智慧型手機、或音樂播放器)、行動計算系統(例如膝上型電腦、小筆電、或平板電腦)、桌上型計算系統、伺服器、或超級電腦。封裝結構可安裝於主機板組件上而整合進入計算系統。通常,主機板可包含任何適當類型之電路板或可提供置於板上之計算系統的一或多個各式組件之間及置於板上之各式組件與計算系統之其他連接的遠端元件之間之電通訊的其他基板。
相關技術中技術熟練人士將理解,在揭露通篇中之修改及變化是可能的,取代所顯示及說明之各式組件。本說明書中所提「一實施例」或「實施例」表示結合實施例所說明之特徵、結構、材料、或特性係包括於本發明之至少一實施例中,但不一定表示其出現於每一實施例中。此外,實施例中所揭露之特徵、結構、材料、或特性可以任何適當方式組合於一或多個實施例中。在其他實施例中,可包括各式額外層及/或結構,及/或可省略所說明之特徵。
105、405‧‧‧基板
107‧‧‧凹區
110‧‧‧第一半導體晶片
115、130‧‧‧電互連
120‧‧‧焊接劑接頭
125‧‧‧第二半導體晶片
135‧‧‧間隙
140‧‧‧校準單元
410‧‧‧IC晶片
415、417‧‧‧封裝組件
505‧‧‧處理器
510‧‧‧記憶體控制器集線器
515‧‧‧光學互連
520‧‧‧記憶體晶片
525‧‧‧圖形晶片
530‧‧‧輸入/輸出控制器晶片
535‧‧‧輸入/輸出裝置
圖1A-B為示意圖,描繪半導體晶片之堆疊封裝組件。
圖2A-B為示意圖,描繪半導體晶片之額外堆疊封裝組件。
圖3A-B為示意圖,描繪半導體晶片之進一步堆疊封
裝組件。
圖4描繪組件,包含堆疊半導體晶片組件及額外半導體晶片。
圖5為計算系統,其中可使用半導體晶片之堆疊組件。
105‧‧‧基板
110‧‧‧第一半導體晶片
115、130‧‧‧電互連
120‧‧‧焊接劑接頭
125‧‧‧第二半導體晶片
135‧‧‧間隙
Claims (14)
- 一種裝置,包含:具有第一表面之第一半導體晶片,其中,該第一表面具有置於該第一表面上之第一組電互連區及第二組電互連區,且其中,該第一半導體晶片為雷射晶片;具有面對該第一表面的第二表面之第二半導體晶片,其中,該第二表面具有置於其上之電互連區,且其中,該第一半導體晶片之該第一表面的該第一組電互連區電連接該第二半導體晶片之該第二表面的該電互連區,且其中,該第二半導體晶片為雷射驅動器晶片;以及具有第三表面之基板,其中,該第三表面具有置於其上之電互連區,其中,該基板之該第三表面的該電互連區電連接至該第一半導體晶片之該第一表面的該第二組電互連區,且其中,該第二半導體晶片位於該第一半導體晶片與該基板之間,且該第二表面在垂直於該第二表面的方向上係位於該第一表面與該第三表面之間。
- 如申請專利範圍第1項之裝置,其中,該第二半導體晶片為薄型半導體晶片。
- 如申請專利範圍第1項之裝置,其中,該第二半導體晶片為具有介於100μm與20μm之間之高度的半導體晶片。
- 如申請專利範圍第1項之裝置,其中,該基板為印刷電路板、封裝基板、或主機板。
- 如申請專利範圍第1項之裝置,其中,該第一半導 體晶片之該第一表面的該電互連區以焊接劑連接至該基板之該第三表面的該電互連區。
- 如申請專利範圍第1項之裝置,其中,該第一半導體晶片之該第一表面的該電互連區以焊接劑連接至該第二半導體晶片之該第二表面的該電互連區。
- 如申請專利範圍第1項之裝置,其中,該基板包含接近該第二半導體晶片之凹區。
- 一種裝置,包含:具有第一表面之第一半導體晶片,其中,該第一表面具有置於該第一表面上之第一組電互連區及第二組電互連區,且其中,該第一半導體晶片為光檢測器晶片;具有面對該第一表面的第二表面之第二半導體晶片,其中,該第二表面具有置於其上之電互連區,且其中,該第一半導體晶片之該第一表面的該第一組電互連區電連接該第二半導體晶片之該第二表面的該電互連區,且其中,該第二半導體晶片為轉換阻抗放大器;以及具有第三表面之基板,其中,該第三表面具有置於其上的電互連區,其中,該基板之該第三表面的該電互連區電連接至該第一半導體晶片之該第二組電互連區,且其中,該第二半導體晶片位於該第一半導體晶片與該基板之間,且該第二表面在垂直於該第二表面的方向上係位於該第一表面與該第三表面之間。
- 如申請專利範圍第8項之裝置,其中,該第二半導體晶片為薄型半導體晶片。
- 如申請專利範圍第8項之裝置,其中,該第二半導體晶片為具有介於100μm與20μm之間之高度的半導體晶片。
- 如申請專利範圍第8項之裝置,其中,該基板為印刷電路板、封裝基板、或主機板。
- 如申請專利範圍第8項之裝置,其中,該第一半導體晶片之該第一表面的該電互連區以焊接劑連接至該基板之該第三表面的該電互連區。
- 如申請專利範圍第8項之裝置,其中,該第一半導體晶片之該第一表面的該電互連區以焊接劑連接至該第二半導體晶片之該第二表面的該電互連區。
- 如申請專利範圍第8項之裝置,其中,該基板包含接近該第二半導體晶片之凹區。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2011/063601 WO2013085497A1 (en) | 2011-12-06 | 2011-12-06 | Semiconductor chip stacking assemblies |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201342539A TW201342539A (zh) | 2013-10-16 |
TWI527163B true TWI527163B (zh) | 2016-03-21 |
Family
ID=48574712
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW101144779A TWI527163B (zh) | 2011-12-06 | 2012-11-29 | 半導體晶片堆疊組件 |
Country Status (4)
Country | Link |
---|---|
US (2) | US9263424B2 (zh) |
CN (1) | CN104081519B (zh) |
TW (1) | TWI527163B (zh) |
WO (1) | WO2013085497A1 (zh) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013085497A1 (en) | 2011-12-06 | 2013-06-13 | Intel Corporation | Semiconductor chip stacking assemblies |
US9196586B2 (en) * | 2014-02-13 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package including an embedded surface mount device and method of forming the same |
US9881850B2 (en) * | 2015-09-18 | 2018-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and method of forming the same |
US9941230B2 (en) | 2015-12-30 | 2018-04-10 | International Business Machines Corporation | Electrical connecting structure between a substrate and a semiconductor chip |
US20170288780A1 (en) * | 2016-03-31 | 2017-10-05 | Intel Corporation | Optoelectronic transceiver assemblies |
US11598850B2 (en) * | 2016-11-30 | 2023-03-07 | Sony Semiconductor Solutions Corporation | Apparatus and method for illumination |
JP2019096722A (ja) * | 2017-11-22 | 2019-06-20 | 富士通株式会社 | 光モジュール |
US10600770B2 (en) | 2018-05-14 | 2020-03-24 | Micron Technology, Inc. | Semiconductor dice assemblies, packages and systems, and methods of operation |
TW202034478A (zh) * | 2019-02-04 | 2020-09-16 | 日商索尼半導體解決方案公司 | 電子裝置 |
CN110052760B (zh) * | 2019-03-18 | 2021-10-01 | 苏州领裕电子科技有限公司 | 一种不同平面焊接技术及应用其的焊接设备 |
USD945326S1 (en) | 2020-06-08 | 2022-03-08 | Ineos Automotive Limited | Motor vehicle (pick up truck) |
CN111725198B (zh) * | 2020-07-01 | 2022-02-15 | 无锡中微亿芯有限公司 | 通过硅连接层的配置电路实现全可编程的多裸片fpga |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0179921B1 (ko) | 1996-05-17 | 1999-03-20 | 문정환 | 적측형 반도체 패키지 |
US6091138A (en) * | 1998-02-27 | 2000-07-18 | Advanced Micro Devices, Inc. | Multi-chip packaging using bump technology |
US6150724A (en) * | 1998-03-02 | 2000-11-21 | Motorola, Inc. | Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces |
JP2001059923A (ja) * | 1999-06-16 | 2001-03-06 | Seiko Epson Corp | 光モジュール及びその製造方法、半導体装置並びに光伝達装置 |
US6624444B1 (en) * | 2002-03-28 | 2003-09-23 | Intel Corporation | Electrical-optical package with capacitor DC shunts and associated methods |
US20050104211A1 (en) | 2002-05-07 | 2005-05-19 | Shinji Baba | Semiconductor device having semiconductor chips mounted on package substrate |
TW550770B (en) * | 2002-06-20 | 2003-09-01 | Advanced Semiconductor Eng | Optical integrated circuit element package and process for making the same |
US7224910B2 (en) | 2002-10-25 | 2007-05-29 | Gennum Corporation | Direct attach optical receiver module and method of testing |
US6963119B2 (en) * | 2003-05-30 | 2005-11-08 | International Business Machines Corporation | Integrated optical transducer assembly |
US7476040B2 (en) * | 2004-02-02 | 2009-01-13 | Jds Uniphase Corporation | Compact optical sub-assembly with ceramic package |
CN1851888A (zh) * | 2006-03-23 | 2006-10-25 | 美新半导体(无锡)有限公司 | 圆片级封装集成电路的方法 |
US7880310B2 (en) | 2007-09-28 | 2011-02-01 | Intel Corporation | Direct device attachment on dual-mode wirebond die |
JP5195087B2 (ja) * | 2008-06-30 | 2013-05-08 | 富士通株式会社 | 光電気変換デバイス、光電気変換モジュールおよび光電気変換デバイスの製造方法 |
US9057853B2 (en) | 2009-02-20 | 2015-06-16 | The Hong Kong University Of Science And Technology | Apparatus having an embedded 3D hybrid integration for optoelectronic interconnects |
WO2013085497A1 (en) | 2011-12-06 | 2013-06-13 | Intel Corporation | Semiconductor chip stacking assemblies |
-
2011
- 2011-12-06 WO PCT/US2011/063601 patent/WO2013085497A1/en active Application Filing
- 2011-12-06 US US13/977,242 patent/US9263424B2/en not_active Expired - Fee Related
- 2011-12-06 CN CN201180075381.4A patent/CN104081519B/zh not_active Expired - Fee Related
-
2012
- 2012-11-29 TW TW101144779A patent/TWI527163B/zh not_active IP Right Cessation
-
2016
- 2016-02-09 US US15/019,850 patent/US9633983B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US9263424B2 (en) | 2016-02-16 |
US20160247791A1 (en) | 2016-08-25 |
CN104081519A (zh) | 2014-10-01 |
TW201342539A (zh) | 2013-10-16 |
WO2013085497A1 (en) | 2013-06-13 |
US20130285261A1 (en) | 2013-10-31 |
US9633983B2 (en) | 2017-04-25 |
CN104081519B (zh) | 2017-08-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI527163B (zh) | 半導體晶片堆疊組件 | |
US9391013B2 (en) | 3D integrated circuit package with window interposer | |
US10199354B2 (en) | Die sidewall interconnects for 3D chip assemblies | |
US9607947B2 (en) | Reliable microstrip routing for electronics components | |
US20200117627A1 (en) | Stacked Semiconductor Device Assembly in Computer System | |
US8471376B1 (en) | Integrated circuit packaging configurations | |
US10242976B2 (en) | In-package photonics integration and assembly architecture | |
US9418964B2 (en) | Chip package structure | |
US20130032947A1 (en) | Semiconductor package and method of manufacturing the same | |
KR20150005113A (ko) | 광학 신호 경로를 포함하는 반도체 패키지 | |
US20230352412A1 (en) | Multiple die package using an embedded bridge connecting dies | |
WO2019054998A1 (en) | ACTIVE SILICON BRIDGE | |
JP2016526306A (ja) | スケーラブルパッケージアーキテクチャ並びに関連する技法及び構造 | |
KR101950976B1 (ko) | 반도체 패키지 | |
US9224682B2 (en) | Semiconductor device | |
TWI802446B (zh) | 用於銲線接合應用之封裝結構中的中介層設計 | |
TW201724408A (zh) | 半導體元件中之功能性晶片島狀部的積體堆疊層 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |