TWI524464B - ＦｉｎＦＥＴ元件與其形成方法 - Google Patents

ＦｉｎＦＥＴ元件與其形成方法 Download PDF

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TWI524464B
TWI524464B TW102146833A TW102146833A TWI524464B TW I524464 B TWI524464 B TW I524464B TW 102146833 A TW102146833 A TW 102146833A TW 102146833 A TW102146833 A TW 102146833A TW I524464 B TWI524464 B TW I524464B
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TW201434109A (zh
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郭志偉
趙元舜
陳豪育
楊士洪
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台灣積體電路製造股份有限公司
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Description

FinFET元件與其形成方法
本發明係關於半導體元件，更特別關於FinFET元件與其形成方法。
半導體積體電路(IC)產業快速成長，新一代的IC具有較大的功能密度(比如固定晶片面積中的內連線元件數目)，與較小的尺寸(比如製程形成的最小構件或連線)。製程尺寸縮小往往有利於增加製程效率並降低相關成本，但亦增加製程複雜度。然而製程尺寸縮小的優點顯而易見，因此需要更小的IC製程。
舉例來說，當半導體產業採用奈米技術製程節點以達成更高元件密度、更高效能、與更低成本時，將同時面臨製作與設計的挑戰，這造就三維(3D)元件如鰭狀場效電晶體(FinFET)的發展。然而FinFET元件的現有形成方法無法讓其通道區具有一致的臨界電壓。綜上所述，雖然現存的FinFET元件與其製作方法適用於特定目的，但無法完全符合所有需求。
本發明一實施例提供一種FinFET元件，包括：基板，包括鰭狀結構，且鰭狀結構包括第一鰭狀物與第二鰭狀物；淺溝槽隔離結構，位於基板上，並位於第一鰭狀物與第二 鰭狀物之間；閘極介電層，位於第一鰭狀物與第二鰭狀物上；以及閘極結構，位於閘極介電層上，閘極結構橫越第一鰭狀物、第二鰭狀物、與第一鰭狀物與第二鰭狀物之間的淺溝槽隔離結構上，且閘極結構具有縱向階梯形狀。
本發明一實施例提供一種FinFET元件，包括：半導體基板；鰭狀結構，包括一或多個鰭狀物形成於半導體基板上；隔離材料，形成於鰭狀物之間；介電層，形成於部份鰭狀結構上；閘極結構，形成於介電層上；以及多個閘極間隔物形成於閘極結構的側壁上，其中閘極結構具有縱向階梯形狀。
本發明一實施例提供一種FinFET元件的形成方法，包括：提供基板，基板包括具有多個鰭狀物的鰭狀結構，以及淺溝槽隔離結構位於鰭狀結構的鰭狀物之間；形成第一閘極結構於鰭狀結構上；形成多個第一閘極間隔物於第一閘極結構的側壁上；移除部份第一閘極間隔物，並保留部分第一閘極間隔物於鰭狀結構與第一閘極結構交會的角落中；形成第二閘極間隔物於第一閘極結構的側壁上；形成介電層於鰭狀結構、第一閘極結構、與第二閘極間隔物上；移除第一閘極結構與部份第一閘極間隔物，以露出第二閘極間隔物的側壁；以及形成第二閘極結構於一區域中的鰭狀結構上，其中區域係第一閘極結構與部份第一閘極間隔物被移除的位置。
b-b、c-c、d-d、e-e‧‧‧線段
w1、w2、w3、w4、w5‧‧‧寬度
100‧‧‧方法
102、104、106、108、110、112、114、116、118‧‧‧步驟
200‧‧‧FinFET元件
210‧‧‧基板
212‧‧‧鰭狀結構
214‧‧‧STI結構
216‧‧‧第一絕緣層
218‧‧‧第一閘極結構
220‧‧‧第一閘極間隔物
222‧‧‧第二閘極間隔物
224‧‧‧S/D結構
226‧‧‧ILD層
228‧‧‧第二絕緣層
230‧‧‧閘極介電層
232‧‧‧閘極結構
第1圖係本發明多種實施例中，製作半導體元件之方法的流程圖； 第2A至2C與第3A至11A圖係依據第1圖之方法，形成一實施例之半導體元件的製程透視圖； 第3B至11B圖係分別對應第3A至11A圖之半導體元件的上視圖；以及第3C至11C、3D至11D、及3E至11E圖係分別對應第3A至11A圖之半導體元件的剖視圖。
本發明提供多個不同實施例或實例，以實施多種實施例中的不同特徵。下述元件與組合的特定實例係用以簡化本發明，僅用以舉例而非侷限本發明。舉例來說，形成第一結構於第二結構上的敘述，包括第一與第二結構直接接觸或隔有額外結構的情況。此外，本發明之多個實例可重複採用相同標號以簡化說明，但具有相同標號的元件並不必然具有相同的對應關係。另一方面，下述構件的排列、組合、或形態，在不背離本發明範圍的情況下可不同於實施例。可以理解的是本技術領域中具有通常知識者，可用說明書未直接揭露的其他類似方式實施本發明概念。
本發明一或多種實施例可運用的元件為半導體元件，比如鰭狀場效電晶體(FinFET)。FinFET元件可為p型金氧半(PMOS)FinFET元件、n型金氧半(NMOS)FinFET元件、或互補式金氧半(CMOS)FinFET元件。下述內容將說明本發明多種實施例中的FinFET元件。可以理解的是，除了申請專利範圍以外，本發明不受限於特定種類的元件。
如第1與2至11圖所示，方法100將搭配FinFET元件 200進行說明。第1圖係本發明多種實施例中，製作積體電路元件之方法100的流程圖。在此實施例中，方法100係用以製作包含FinFET元件的積體電路元件。方法100之起始步驟102提供基板。在步驟104中，形成鰭狀結構於基板上。鰭狀結構的形成方法包括圖案化遮罩層、以遮罩層蝕刻半導體基板以定義鰭狀結構、以及形成淺溝槽隔離(STI)結構於鰭狀結構的每一鰭狀物之間。STI結構的形成方法包括沉積介電材料於鰭狀結構上，以及回蝕刻介電層以露出鰭狀結構的側壁。在形成鰭狀結構的過程中，可將鍺、碳化物、或任何合適材料佈植至鰭狀結構，以形成井區、輕掺雜源極/汲極(LDD)區、與重掺雜源極/汲極(HDD)區於鰭狀結構中。接著進行步驟106，形成絕緣層於鰭狀結構上、形成虛置閘極結構於絕緣層上、以及形成虛置閘極間隔物於虛置閘極結構的側壁上。絕緣層可橫越鰭狀結構。接著進行步驟108，實質上移除虛置閘極間隔物，並保留虛置閘極間隔物於鰭狀結構的核心(鰭狀結構與虛置閘極結構接觸的地方)中。接著進行步驟110，形成閘極間隔物於虛置閘極結構的側壁上，而源極與汲極(S/D)結構係形成於鰭狀結構上。接著進行步驟112，形成層間介電(ILD)層於半導體元件上。接著可進行化學機械研磨(CMP)製程，以移除多餘的介電材料並平坦化半導體元件的上表面。接著進行步驟114，移除虛置閘極結構、核心中的虛置閘極間隔物、以及絕緣材料。接著進行步驟116，形成絕緣材料於鰭狀結構上且位於閘極間隔物之間，並形成閘極結構於絕緣層上。上述絕緣材料的形成方法可為熱氧化鰭狀結構或沉積介電材料。閘極結構橫越鰭狀結構，並分隔 S/D結構。方法100接著進行步驟118，完成製作積體電路元件。在方法之前、之中、與之後可進行額外步驟，而其他實施例的方法可省略或以其他步驟取代上述步驟。依據第1圖之方法100，可形成多種實施例之積體電路元件如下述。
第2A、2B、2C、及3A至11A圖係依據第1圖之方法製作一實施例之半導體元件的製程透視圖。第3B至11B圖係分別對應第3A至11A圖之半導體元件的上視圖。第3C至11C、3D至11D、及3E至11E圖係分別對應第3A至11A圖之半導體元件的剖視圖。FinFET元件200可包含於微處理器、記憶單元、及/或其他積體電路元件。必需注意的是，已簡化第2至11圖以利了解本發明概念。FinFET元件200中可具有額外結構，而其他實施例之FinFET元件200可省略或置換下述某些結構。
如第2A圖所示，提供基板(比如晶圓)210。基板210可為基體基板，比如半導體元素如結晶結構的矽或鍺，半導體化合物如矽鍺合金、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦，或上述之組合。在另一實施例中，基板210包含絕緣層上矽(SOI)基板。SOI基板的製作方法可為佈植氧隔離(SIMOX)、晶圓接合、及/或其他合適方法。
如第2B圖所示，形成鰭狀結構212於基板210中。鰭狀結構212包含多個鰭狀物，其形成方法可為任何合適製程，比如微影與蝕刻製程。舉例來說，此實施例中的鰭狀結構212之形成方法為曝光光阻層、曝光後烘烤光阻層、以及顯影光阻層以圖案化光阻層。光阻層的圖案化方法包含塗佈光阻、軟烘烤、對準光罩、曝光圖案、曝光後烘烤、顯影光阻、與硬 烘烤。上述圖案化步驟可置換其他合適方法，比如無光罩微影、電子束直寫、離子束直寫、與分子壓印。接著可採用圖案化之光阻層進行蝕刻製程，蝕刻基板210以形成鰭狀結構212。採用圖案化之光阻層的蝕刻製程，可定義FinFET元件200中欲蝕刻的區域並保護其他區域。蝕刻製程可為濕蝕刻、乾蝕刻、或上述之組合。鰭狀結構212的形成方法可為蝕刻製程，比如反應性離子蝕刻(RIE)及/或其他合適製程。在一實施例中，用以蝕刻基板210的乾蝕刻製程所用的化學品包括含氟氣體。在又一實施例中，乾蝕刻的化學品包含四氟化碳、六氟化硫、或三氟化氮。在另一實施例中，鰭狀結構212的形成方法為雙圖案化微影(DPL)製程。DPL係將圖案分成兩個交錯的圖案以形成圖案於基板上的方法。DPL可增加結構(如鰭狀物)的密度。DPL包含雙重曝光(採用雙重光罩組)。鰭狀結構212可佈植有材料如鍺、碳化物、或任何合適材料，以形成井區於其中。
如第2B圖所示，形成STI結構214於鰭狀結構212的每一鰭狀物之間。STI結構214的形成方法包含以任何合適製程形成介電層。STI結構214可為不同介電材料形成的多層結構。在此實施例中，STI結構214包含任何合適製程形成的介電材料如氧化矽。在多種實施例中，氧化矽的形成方法可為乾式或濕式熱氧化、物理氣相沉積(PVD)、原子層沉積(ALD)、高密度電漿CVD(HDPCVD)、其他合適方法、及/或上述之組合。舉例來說，CVD製程可採用化學品如六氯乙矽烷(Si2Cl6，HCD)、二氯矽烷(SiH2Cl2，DCS)、雙(第三丁基胺基)矽烷(C8H22N2Si，BTBAS)、或乙矽烷(Si2H6，DS)。STI結構214可具有多層結構， 比如熱氧化襯墊層與形成其上的氧化矽層或氮化矽層。
如第2C圖所示，使鰭狀結構212之鰭狀物之間的STI結構214其介電材料凹陷化，以露出鰭狀結構212的側壁。使STI結構214的介電材料凹陷化的方法可為蝕刻製程，比如濕蝕刻製程、乾蝕刻製程、或上述之組合。在一實施例中，用以蝕刻STI結構的介電材料之濕蝕刻製程採用氫氟酸或緩衝氫氟酸。
第3A圖係一實施例中，FinFET元件200之透視圖。第3B圖係沿著第3A圖中的線段b-b之上視圖。第3C、3D、與3E圖係分別沿著第3A圖中的線段c-c、d-d、與e-e之剖視圖。在第3A圖中，線段c-c實質上沿著一鰭狀物(如右側的鰭狀物)之中心線，線段d-d與中心線隔有第一距離，線段e-e與中心線隔有第二距題，且第二距離大於第一距離。
如第3A至3E圖所示，第一絕緣層216係形成於FinFET元件200上。第一絕緣層216橫越鰭狀結構212，並形成於鰭狀結構與STI結構214的中心部份上。第一絕緣層216可為任何合適的介電材料。第一絕緣層216之形成方法可包含合適製程如沉積、微影圖案化、與蝕刻製程。在多種實施例中，第一絕緣層216的形成方法可為濕式或乾式熱氧化、物理氣相沉積(PVD)、原子層沉積(ALD)、高密度電漿CVD(HDPCVD)、其他合適技術、及/或上述之組合。在此實施例中，第一絕緣層216可為ALD製程形成的氧化矽。
如第3A至3E圖所示，第一閘極結構218係形成於第一絕緣層216上。在此實施例中，第一閘極結構218為之後移除 的虛置閘極結構。第一閘極結構218可由任何合適材料如多晶矽形成。第一閘極結構218之形成方法可包含任何合適製程如沉積、微影圖案化、與蝕刻製程。沉積製程可為化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、高密度電漿CVD(HDPCVD)、有機金屬CVD(MOCVD)、遠端電漿CVD(RPCVD)、電漿增強CVD(PECVD)、低壓CVD(LPCVD)、原子層CVD(ALCVD)、常壓CVD(APCVD)、電鍍、其他合適方法、或上述之組合。微影圖案化製程包括塗佈光阻(比如旋塗法)、軟烘烤、對準光罩、曝光、曝光後烘烤、顯影光阻、潤濕、乾燥(比如硬烘烤)、其他合適製程、或上述之組合。在另一實施例中，可採用其他方法取代微影曝光製程，比如無光罩微影、電子束直寫、或離子束直寫。在又一實施例中，微影圖案化製程可採用奈米壓印技術。蝕刻製程可包括乾蝕刻、濕蝕刻、上述之組合、及/或其他蝕刻方法。在形成第一閘極結構218後，可將材料如鍺、碳化物、或任何合適材料佈植至鰭狀結構212露出的部份，以形成輕掺雜源極/汲極(LDD)區於其中。
如第4A至4E圖所示，形成第一閘極間隔物220於第一閘極結構218的側壁上。在此實施例中，第一閘極間隔物220為之後移除的虛置間隔物。第一閘極間隔物220可由合適技術形成，並包含任何合適介電材料如氧化矽、氮化矽、或任何合適材料。舉例來說，為減少後續蝕刻製程步驟，第一閘極間隔物220採用之介電材料可與第一絕緣層216之介電材料相同。在此實施例中，第一閘極間隔物220包含氧化矽。在形成第一閘極間隔物220後，將材料如鍺、碳化物、或任何合適材料佈植 至鰭狀結構212露出的部份，以形成重掺雜源極/汲極(HDD)區於其中。
如第5A至5E圖所示，自第一閘極結構218的側壁實質上移除第一閘極間隔物220，並保留部份的第一閘極間隔物220於鰭狀結構212與第一閘極結構218交會的垂直方向的角落中。實質上移除第一閘極間隔物220的方法可為任何合適製程。在此實施例中，實質上移除第一閘極間隔物220的方法為蝕刻製程。蝕刻製程可為乾蝕刻、濕蝕刻、上述之組合、及/或其他蝕刻方法。
如第6A至6E圖所示，第二閘極間隔物222係形成於第一閘極結構218之側壁上與第一閘極間隔物220上。第二閘極間隔物222可由合適製程形成，並可包含任何合適介電材料如氧化矽、氮化矽、或任何合適材料。為了使第一閘極間隔物220在後續製程中，可保留於鰭狀結構212與第一閘極結構218交會的角落中，第二閘極間隔物222與第一閘極間隔物220的材料不同。在此實施例中，第二閘極間隔物222包含氮化矽。
如第7A至7E圖所示，S/D(源極與汲極)結構224係形成於鰭狀結構212的上表面上，且S/D結構224之間隔有第一閘極結構218下的通道區。S/D結構224包含高掺雜區與輕掺雜區。在一實施例中，S/D結構224的形成方法包括蝕刻鰭狀結構212的頂部，再沉積掺雜的半導體材料於鰭狀結構212被蝕刻的部份上。掺雜的半導體材料之沉積方法可為磊晶成長半導體材料如矽鍺合金、碳化矽、或任何合適材料。
如第8A至8E圖所示，ILD(層間介電)層226係形成 於FinFET元件200上。ILD層226可包含氮化矽、氧化矽、氮氧化矽、低介電常數之材料如氟化氧化矽玻璃(FSG)、掺雜碳之氧化矽、Black Diamond®(購自加州Santa Clara的Applied Materials)、乾凝膠、氣膠、非晶氟化碳、聚對二甲苯、苯并環丁烯(BCB)、SiLK(購自密西根州之密德蘭的Dow Chemical)、聚亞醯胺、及/或其他合適材料。ILD層226之形成方法可為任何合適製程，比如化學氣相沉積(CVD)、高密度電漿CVD(HDP-CVD)、旋塗法、物理氣相沉積(PVD)、濺鍍、或其他合適方法。舉例來說，CVD製程可採用化學品如六氯乙矽烷(Si2Cl6，HCD)、二氯矽烷(SiH2Cl2，DCS)、雙(第三丁基胺基)矽烷(C8H22N2Si，BTBAS)、或乙矽烷(Si2H6，DS)。
如第9A至9E圖所示，移除第一閘極結構218，其移除方法可為任何合適製程。在此實施例中，移除第一閘極結構218的方法為蝕刻製程。上述蝕刻製程可為乾蝕刻、濕蝕刻、上述之組合、及/或其他蝕刻方法。
如第10A至10E圖所示，移除第一絕緣層216與部份第一閘極間隔物220，以露出鰭狀結構212的側壁與STI結構的上表面。第一絕緣層216與部份第一閘極間隔物220的移除方法可為任何合適製程。在此實施例中，移除第一絕緣層216與部份第一閘極間隔物220的方法為蝕刻製程。上述蝕刻製程可為乾蝕刻、濕蝕刻、上述之組合、及/或其他蝕刻方法。在一實施例中，移除第一絕緣層216與部份第一閘極間隔物220的乾蝕刻製程採用的化學品包括含氟氣體。在又一實施例中，乾蝕刻的化學品包括四氟化碳、六氟化硫、或三氟化氮。在特定實施 例中，第一絕緣層216與部份第一閘極間隔物220為氧化矽，且上述兩者的移除製程可同時進行。在另一實施例中，第一絕緣層216與部份第一閘極間隔物220為不同材料，且上述兩者的移除製程為多重步驟，比如先移除第一絕緣層216再移除部份第一閘極間隔物220。
如第11A至11E圖所示，形成第二絕緣層228。在此實施例中，第二絕緣層228作為保護鰭狀結構212的界面層。第二絕緣層226橫越鰭狀結構212其分隔S/D結構224之中心部份，請見第11B與11C圖。第二絕緣層228可為任何合適介電材料，比如氧化矽、氮化矽、或任何合適材料。第二絕緣層228之形成方法可為合適製程，比如乾式或濕式熱氧化、物理氣相沉積(PVD)、原子層沉積(ALD)、高密度電漿CVD(HDPCVD)、其他合適方法、及/或上述之組合。在此實施例中，第二絕緣層228可為熱氧化製程形成的氧化矽，因此第二絕緣層228只形成於鰭狀結構212露出的部份(比如上表面與側壁)上，而不形成於介電層214露出的上表面上(請見第11D與11E圖)。
如第11A至11E圖所示，閘極介電層230與閘極結構232係形成於第二絕緣層228上。閘極介電層230包含介電材料如氧化矽、高介電常數之介電材料、其他合適的介電材料、或上述之組合。高介電常數之介電材料包含氧化鉿、氧化鉿矽、氮氧化鉿矽、氧化鉿鉭、氧化鉿鈦、氧化鉿鋯、氧化鋯、氧化鋁、氧化鉿-氧化鋁合金、其他合適的高介電常數之介電材料、及/或上述之組合。在此實施例中，閘極介電層230為高介電常數層如氧化鉿。閘極結構232可為多晶矽及/或金屬如鋁、銅、 鈦、鉭、鎢、鉬、氮化鉭、鎳矽化物、鈷矽化物、氮化鈦、氮化鎢、鈦鋁合金、氮化鈦鋁、碳氮化鉭、碳化鉭、氮矽化鉭、其他導電材料、或上述之組合。閘極結構232可包含多個其他層如功函數金屬層、蓋層、界面層、擴散層、阻障層、或上述之組合。硬遮罩層可形成於閘極結構232上。硬遮罩層可為氧化矽、氮化矽、氮氧化矽、碳化矽、其他合適材料、或上述之組合。
閘極介電層230與閘極結構232的形成方法可為任何合適製程。舉例來說，閘極介電層230之形成方法可為合適製程如原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、熱氧化、UV-臭氧氧化、或上述之組合。此外，閘極結構232的形成方法可為沉積製程如化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、高密度電漿CVD(HDPCVD)、有機金屬CVD(MOCVD)、遠端電漿CVD(RPCVD)、電漿增強CVD(PECVD)、低壓CVD(LPCVD)、原子層CVD(ALCVD)、常壓CVD(APCVD)、電鍍、其他合適方法、或上述之組合。
如第11A至11E圖所示，進行平坦化製程於FinFET元件200上。在一實施例中，平坦化製程包括化學機械研磨(CMP)，可移除多餘的閘極介電層230與閘極結構232，並露出鰭狀結構212之每一鰭狀物其實質上平坦的上表面。
第11A至11E圖即FinFET元件200。在此實施例中，FinFET元件200包含基板210，而基板210具有鰭狀結構212形成其中。鰭狀結構212之每一鰭狀物之間隔有STI結構214。鰭狀 結構212的每一鰭狀物包含第二絕緣層228，其橫越中心區中的每一鰭狀物。閘極介電層230形成於第二絕緣層228上，而閘極結構232橫越每一鰭狀物並形成於閘極介電層230上。第二閘極間隔物222位於閘極結構232的側壁上。閘極間隔物222並非線狀，並具有與鰭狀結構212相鄰的縱向階梯形狀，可讓閘極結構232具有較大的有效閘極長度。閘極結構232分隔S/D結構224，並位於通道區上。鰭狀結構212的每一鰭狀物可具有井區、LDD區、與HDD區。閘極介電層230在鰭狀結構212之一鰭狀物的中心線(沿著線段c-c)外第一距離(沿著線段d-d)具有寬度w1，在鰭狀結構212之一鰭狀物的中心線(沿著線段c-c)外第二距離(沿著線段e-e)具有寬度w2，第二距離大於第一距離，且寬度w1大於寬度w2。寬度w1比寬度w2大至少3%。在此實施例中，寬度w1比寬度w2大了約3%至約10%。此外，閘極結構232具有縱向的階梯形狀，其包含多種寬度。閘極結構232在中心線具有寬度w3，在與中心線相隔第一距離處具有寬度w4，而寬度w3小於寬度w4。寬度w4比寬度w3大至少3%。在此實施例中，寬度w4比寬度w3大了約3%至約10%。此外，閘極結構232在與中心線相隔第二距離處具有寬度w5，且寬度w5小於寬度w4。寬度w5的測量點高於寬度w4的測量點(與中心線相隔第一距離處)。寬度w4比寬度w5大至少3%。在此實施例中，寬度w4比寬度w5大了約3%至約10%。
FinFET元件200可包含後續製程形成的額外結構。舉例來說，多種接點/通孔/線路與多層內連線結構(如金屬層與層間介電層)可形成於基板210上，以連接FinFET元件200 之多種結構。上述額外結構可提供電性內連線至FinFET元件200。舉例來說，多層內連線包括垂直內連線如習知通孔或接點，與水平內連線如金屬線路。多種內連線結構可採用多種導電材料如銅、鎢、及/或矽化物。在一實施例中，鑲嵌及/或雙鑲嵌製程可用以形成有關銅的多層內連線結構。可以理解的是，FinFET元件200可包含於具有其他結構的半導體元件/積體電路中，而其他結構可為電晶體、電容、電阻、電感、保護層、接合墊、封裝、與類似物，不過已簡化上述實施例而不贅述於此。
上述方法100與FinFET元件200具有較大的有效閘極長度，因此在通道方向(沿著S/D結構224之間的鰭狀結構212之長邊)具有改良的臨界電壓。舉例來說，階梯形狀的閘極(比如較大的寬度w4)可最小化閘極角落圓潤化的現象，其有效閘極長度大於習知元件的有效閘極長度，使LDD區得以延伸至通道區，進而改善通道方向中的臨界電壓一致性。
本發明提供之FinFET元件包括：基板，其包含之鰭狀結構包括第一鰭狀物與第二鰭狀物。FinFET元件亦包括淺溝槽隔離(STI)結構位於基板上，並位於第一鰭狀物與第二鰭狀物之間。FinFET元件更包括閘極介電層位於第一鰭狀物與第二鰭狀物上。FinFET元件更包括閘極結構位於閘極介電層上。閘極結構橫越第一鰭狀物、第二鰭狀物、與第一鰭狀物與第二鰭狀物之間的STI結構上，且閘極結構具有縱向階梯形狀。
在某些實施例中FinFET元件更包括界面層位於鰭狀結構與閘極介電層之間；以及多個閘極間隔物位於閘極結構之側壁上，且閘極間隔物之縱向階梯形狀對應閘極結構之縱向 階梯形狀。
在某些實施例中，界面層位於鰭狀結構上，而不位於淺溝槽隔離結構上。在多種實施例中，閘極結構之縱向階梯形狀在第一鰭狀物的中心線外第一距離處具有第一寬度，在第一鰭狀物的中心線外第二距離處具有第二寬度，第二距離大於第一距離，且第一寬度大於第二寬度。在此實施例中，界面層包括氧化矽，且閘極間隔物包括氮化矽。在又一實施例中，基板係基體矽基板。在某些實施例中，閘極結構之材料係擇自鋁、銅、與鎢。
本發明另一實施例提供之FinFET元件包括半導體基板。FinFET元件更包括鰭狀結構，其包括一或多個鰭狀物形成於半導體基板上。FinFET元件更包括隔離材料形成於鰭狀物之間。FinFET元件更包括介電層形成於部份鰭狀結構上，與閘極結構形成於介電層上。FinFET元件更包括多個閘極間隔物形成於閘極結構的側壁上。閘極結構具有縱向階梯形狀。
在某些實施例中，介電層係形成於部份鰭狀結構上，而不形成於鰭狀結構之鰭狀物之間的隔離材料上。在多種實施例中，閘極結構之縱向階梯形狀在第一鰭狀物的中心線外第一距離處具有第一寬度，在第一鰭狀物的中心線外第二距離處具有第二寬度，第二距離大於第一距離，且第一寬度大於第二寬度。在此實施例中，介電層包括氧化矽，而閘極間隔物包括氮化矽。在又一實施例中，半導體基板係基體矽基板或絕緣層上矽(SOI)基板。在某些實施例中，閘極結構之材料係擇自鋁、銅、與鎢。
本發明亦提供FinFET元件的形成方法，包括：提供基板，基板包括具有第一與第二鰭狀物的鰭狀結構。上述方法更包括形成淺溝槽隔離(STI)結構於第一與第二鰭狀物之間。上述方法更包括形成閘極介電層於第一與第二鰭狀物上，以及形成閘極結構於閘極介電層上。閘極結構橫越第一鰭狀物、第二鰭狀物、及第一與第二鰭狀物之間的STI結構。閘極結構具有縱向階梯形狀。
在某些實施例中，上述方法更包括形成界面層於鰭狀結構與閘極介電層之間，以及形成閘極間隔物於閘極結構的側壁上。閘極間隔物之縱向階梯形狀對應閘極結構之縱向階梯形狀。
在某些實施例中，界面層位於鰭狀結構上而不位於STI結構上。在多種實施例中，閘極結構之縱向階梯形狀在第一鰭狀物的中心線外第一距離處具有第一寬度，在第一鰭狀物的中心線外第二距離處具有第二寬度，第二距離大於第一距離，且第一寬度大於第二寬度。在此實施例中，形成界面層之步驟包括形成氧化矽，且形成閘極間隔物之步驟包括沉積氮化矽。在又一實施例中，提供半導體基板之步驟包括提供基體矽基板或絕緣層上矽(SOI)基板。在某些實施例中，形成閘極結構之步驟包括沉積材料，其擇自鋁、銅、與鎢。
本發明亦提供另一種FinFET元件的形成方法，包括：提供基板，基板包括具有多個鰭狀物的鰭狀結構，以及淺溝槽隔離結構位於鰭狀結構的鰭狀物之間。上述方法更包括形成第一閘極結構於鰭狀結構上。上述方法更包括形成多個第一 閘極間隔物於第一閘極結構的側壁上。上述方法更包括移除部份第一閘極間隔物，並保留部分第一閘極間隔物於鰭狀結構與第一閘極結構交會的角落中。上述方法更包括形成第二閘極間隔物於第一閘極結構的側壁上。上述方法更包括形成介電層於鰭狀結構、第一閘極結構、與第二閘極間隔物上。上述方法更包括移除第一閘極結構與部份第一閘極間隔物，以露出第二閘極間隔物的側壁。上述方法更包括形成第二閘極結構於區域中的鰭狀結構上，其中區域係第一閘極結構與部份第一閘極間隔物被移除的位置。
在某些實施例中，上述方法更包括形成絕緣層於鰭狀結構與第一閘極介電層之間，以及形成閘極介電層於第二閘極結構與鰭狀結構之間。在多種實施例中，上述方法更包括形成界面層於閘極介電層與鰭狀結構之間。
在某些實施例中，界面層位於鰭狀結構上而不位於STI結構上。在多種實施例中，形成界面層之步驟包括形成氧化矽，且形成第二閘極間隔物之步驟包括沉積氮化矽。在此實施例中，提供半導體基板之步驟包括提供基體矽基板或絕緣層上矽(SOI)基板。在又一實施例中，形成第二閘極結構之步驟包括沉積材料，其擇自鋁、銅、與鎢。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
b-b、c-c、d-d、e-e‧‧‧線段
210‧‧‧基板
212‧‧‧鰭狀結構
214‧‧‧STI結構
222‧‧‧第二閘極間隔物
224‧‧‧S/D結構
226‧‧‧ILD層
230‧‧‧閘極介電層
232‧‧‧閘極結構

Claims (10)

  1. 一種FinFET元件，包括：一基板，包括一鰭狀結構，且該鰭狀結構包括一第一鰭狀物與一第二鰭狀物；一淺溝槽隔離結構，位於該基板上，並位於該第一鰭狀物與該第二鰭狀物之間；一閘極介電層，位於該第一鰭狀物與該第二鰭狀物上；以及一閘極結構，位於該閘極介電層上，該閘極結構橫越該第一鰭狀物、該第二鰭狀物、與該第一鰭狀物與該第二鰭狀物之間的該淺溝槽隔離結構上，且該閘極結構具有一縱向階梯形狀，其中該閘極結構的該縱向階梯形狀，在距該第一鰭狀物與該第二鰭狀物之中心處外第一距離處具有一第一寬度與一第二寬度，該第一寬度對應該閘極結構之頂部，該第二寬度對應該閘極結構之底部，且該第一寬度小於該第二寬度。
  2. 如申請專利範圍第1項所述之FinFET元件，更包括：一界面層，位於該鰭狀結構與該閘極介電層之間；以及多個閘極間隔物，位於該閘極結構之側壁上，且該閘極間隔物之縱向階梯形狀對應該閘極結構之縱向階梯形狀。
  3. 如申請專利範圍第2項所述之FinFET元件，其中該界面層位於該鰭狀結構上，而不位於該淺溝槽隔離結構上。
  4. 如申請專利範圍第1項所述之FinFET元件，其中該閘極結構之縱向階梯形狀在該第一鰭狀物的中心線外第二距離處具 有一第三寬度，在該第一鰭狀物的中心線外第三距離處具有一第四寬度，該第三距離大於該第二距離，且該第三寬度大於該第四寬度。
  5. 一種FinFET元件，包括：一半導體基板；一鰭狀結構，包括一或多個鰭狀物形成於該半導體基板上；一隔離材料，形成於該些鰭狀物之間；一介電層，形成於部份該鰭狀結構上；一閘極結構，形成於該介電層上；以及多個閘極間隔物形成於該閘極結構的側壁上，其中該閘極結構具有一縱向階梯形狀，其中該閘極結構的該縱向階梯形狀，在距該第一鰭狀物的中心線外第一距離處具有一第一寬度與一第二寬度，該第一寬度對應該閘極結構之頂部，該第二寬度對應該閘極結構之底部，且該第一寬度小於該第二寬度。
  6. 如申請專利範圍第5項所述之FinFET元件，其中該介電層係形成於部份該鰭狀結構上，而不形成於該鰭狀結構之鰭狀物之間的該隔離材料上。
  7. 如申請專利範圍第5項所述之FinFET元件，其中該閘極結構之縱向階梯形狀在該第一鰭狀物的中心線外第二距離處具有一第三寬度，在該第一鰭狀物的中心線外第三距離處具有一第四寬度，該第三距離大於該第二距離，且該第三寬度大於該第四寬度。
  8. 一種FinFET元件的形成方法，包括： 提供一基板，該基板包括具有多個鰭狀物的一鰭狀結構，以及一淺溝槽隔離結構位於該鰭狀結構的該些鰭狀物之間；形成一第一閘極結構於該鰭狀結構上；形成多個第一閘極間隔物於該第一閘極結構的側壁上；移除部份該些第一閘極間隔物，並保留部分該些第一閘極間隔物於該鰭狀結構與該第一閘極結構交會的角落中；形成一第二閘極間隔物於該第一閘極結構的側壁上；形成一介電層於該鰭狀結構、該第一閘極結構、與該第二閘極間隔物上；移除該第一閘極結構與部份該些第一閘極間隔物，以露出該第二閘極間隔物的側壁；以及形成一第二閘極結構於一區域中的該鰭狀結構上，其中該區域係該第一閘極結構與部份該些第一閘極間隔物被移除的位置。
  9. 如申請專利範圍第8項所述之FinFET元件的形成方法，更包括：形成一絕緣層於該第一閘極結構與該鰭狀結構之間；形成一閘極介電層於該第二閘極結構與該鰭狀結構之間；以及形成一界面層於該閘極介電層與該鰭狀結構之間。
  10. 如申請專利範圍第9項所述之FinFET元件的形成方法，其中該界面層位於該鰭狀結構上，而不位於該淺溝槽隔離結構上。
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