TWI496313B - Method for manufacturing back contact solar cell using punch-through - Google Patents

Method for manufacturing back contact solar cell using punch-through Download PDF

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TWI496313B
TWI496313B TW101131817A TW101131817A TWI496313B TW I496313 B TWI496313 B TW I496313B TW 101131817 A TW101131817 A TW 101131817A TW 101131817 A TW101131817 A TW 101131817A TW I496313 B TWI496313 B TW I496313B
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electrode
oxide
semiconductor substrate
passivation film
solar cell
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TW201330304A (en
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Yong Hwa Lee
Jae Eock Cho
Hong Gu Lee
Se Young Seo
Deoc Hwan Hyun
Gang Il Kim
Woo Won Jung
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Hanwha Chemical Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441Electrode arrangements specially adapted for back-contact solar cells
    • H01L31/022458Electrode arrangements specially adapted for back-contact solar cells for emitter wrap-through [EWT] type solar cells, e.g. interdigitated emitter-base back-contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1864Annealing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/547Monocrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Description

藉由穿通方式之背接式太陽電池製造方法Back-through solar cell manufacturing method by punch-through method 【交叉參照之相關申請案】[Cross-reference related application]

本申請案主張2011年8月31日於韓國智慧財產局所提出之韓國專利申請案第10-2011-0088032號之優先權,其整體揭露內容在此併入參考。The present application claims priority to Korean Patent Application No. 10-2011-0088032, filed on Jan. 31, 2011, the entire disclosure of which is hereby incorporated by reference.

以下的公開係關於一種太陽電池及其製造方法,特別關於一種背接式太陽電池的製造方法,其能夠降低貴金屬的使用量以及最小化由半導體基板與電極的接觸而造成的表面缺陷,同時顯著地降低電極的電阻。The following disclosure relates to a solar cell and a method of manufacturing the same, and more particularly to a method of manufacturing a back-mounted solar cell capable of reducing the amount of precious metal used and minimizing surface defects caused by contact of the semiconductor substrate with the electrode, while being remarkable Ground reduces the resistance of the electrode.

矽太陽電池已經從1950年起開發,但在1980年,一種能夠顯著地增加電壓與電流,同時藉由使用用於微電子的氧化矽膜的矽表面鈍化技術來減少基板表面缺陷的高效率的太陽電池已在1980年確切地出現。矽Solar cells have been developed since 1950, but in 1980, a high efficiency that can significantly increase the voltage and current while reducing the surface defects of the substrate by using the yttrium surface passivation technology for yttrium oxide films for microelectronics. Solar cells have appeared exactly in 1980.

影響基於半導體的無機太陽電池(為最常見的太陽電池)效率的因素主要分為三個。The factors affecting the efficiency of semiconductor-based inorganic solar cells, which are the most common solar cells, are largely divided into three.

作為增加太陽電池效率的第一因素,太陽電池的結構應該被設計為能夠最大化光的吸收。為此,結晶矽太陽電池具有被不均勻紋理化的表面以降低反射率。我們看到的太陽電池的表面顯示成深藍色,其透過覆蓋一抗反射膜以儘可能最大地增加入射到太陽電池的光量。此外,有需要藉由最小化電極的區域以最大化地確保光接收區域。As a first factor in increasing solar cell efficiency, the structure of solar cells should be designed to maximize light absorption. To this end, crystalline germanium solar cells have surfaces that are unevenly textured to reduce reflectivity. The surface of the solar cell we see is shown in dark blue, which covers the anti-reflective film to maximize the amount of light incident on the solar cell. In addition, there is a need to maximize the light receiving area by minimizing the area of the electrodes.

作為增加太陽電池效率的第二因素,需要儘可能最大化地增加載體的壽命,這是由於即使光的吸收已經被最大化地增加,當在太陽電池中被光激發的電子與電洞進入到基態時,電無法被產生。由於被稱為「載體 」的電子與電洞會因為雜質與基板表面的缺陷而重新結合並消失,需要藉由進行一使用高純度矽或去除雜質的吸氣製程,以及一去除表面缺陷的鈍化製程,來最大化地增加載體的壽命。所以,為了產生電,電子與電洞在重新結合之前需要移動到表面電極。今天,鈍化減少太陽電池表面缺陷的氮化矽層係作為抗反射膜,其對降低成本非常有利。As a second factor in increasing the efficiency of solar cells, it is necessary to maximize the lifetime of the carrier as much as even though the absorption of light has been maximally increased, when electrons and holes excited by light in the solar cell enter In the ground state, electricity cannot be generated. Because of the carrier The electrons and holes will recombine and disappear due to impurities and defects on the substrate surface, and it is necessary to maximize the passivation process using high-purity germanium or impurities, and a passivation process to remove surface defects. Increase the life of the carrier. Therefore, in order to generate electricity, the electrons and holes need to be moved to the surface electrode before recombining. Today, passivation of a tantalum nitride layer which reduces surface defects of solar cells is used as an antireflection film, which is very advantageous for cost reduction.

作為增加太陽電池效率的第三因素,由於太陽電池為一電子元件,需要考慮在載體運動期間與和外部電極接觸時能夠最小化各種電阻耗損的電極配置、材料選擇之類。尤其,魚骨型的表面電極需要增加導電性同時最小化光遮蔽耗損,因此,線寬、電極數量、以及類似者,應該依據裝置的特性而被最佳化。As a third factor for increasing the efficiency of the solar cell, since the solar cell is an electronic component, it is necessary to consider an electrode configuration, a material selection, and the like which can minimize various resistance loss during contact with the external electrode during the movement of the carrier. In particular, the fishbone type surface electrode needs to increase conductivity while minimizing light shading loss, and therefore, the line width, the number of electrodes, and the like should be optimized depending on the characteristics of the device.

作為太陽電池市場中的主流產品,用於增加晶體矽太陽電池的效率的最受矚目的技術是背接式太陽電池。射極穿孔捲繞式(emitter wrap through,EWT)太陽電池是背接式太陽電池的一種,其可收集由太陽光在其前面與背面所產生的載體,因此不像使用n型高階基板的指叉式背接式(interdigitated back contact,IBC)太陽電池,是一種如韓國專利公開公報第2006-0035657號所述,能夠使用p型低階基板實現高效率的太陽電池。As a mainstream product in the solar cell market, the most attractive technology for increasing the efficiency of crystalline germanium solar cells is the back-mounted solar cell. An emitter wrap through (EWT) solar cell is a type of back-mounted solar cell that collects the carrier generated by sunlight on its front and back sides, and thus is not like an index using an n-type high-order substrate. An interdigitated back contact (IBC) solar cell is a solar cell capable of realizing high efficiency using a p-type low-order substrate as described in Korean Patent Laid-Open Publication No. 2006-0035657.

至於所有電極都位於背面以最大化光接收面的背接式太陽電池,SUNPOWER公司達到最高的效率為24.2%,且現代重工公司和韓華化學公司目前正在研究。As for the back-mounted solar cells with all electrodes on the back to maximize the light-receiving surface, SUNPOWER achieved a maximum efficiency of 24.2%, and Hyundai Heavy Industries and Hanwha Chemical are currently researching.

由於電極並未設在光接收面上,背接式太陽電池具有以整個光接收面吸收太陽光的優點,達到0%的電極遮光耗損。Since the electrode is not disposed on the light receiving surface, the back-mounted solar cell has the advantage of absorbing sunlight by the entire light receiving surface, and reaches 0% of the electrode shading loss.

在這種背接式太陽電池的結構中,所有的射極電極都進行局部的接觸。然而,電極形成在背面的太陽電池需要大尺寸的電極,因此需要使用大量的包括銀在內的高價貴金屬,這成為太陽電池在商業化上的障礙。此外,用於實現局部連接結構的相關技術具有局限性,其需要使用光刻製程以形成電極,且鈍化層被損壞,從而在電極形成過程中,增加了表面缺陷。In the structure of such a back-mounted solar cell, all of the emitter electrodes are in local contact. However, a solar cell in which an electrode is formed on the back side requires a large-sized electrode, and thus it is necessary to use a large amount of expensive noble metal including silver, which becomes a barrier to commercialization of a solar cell. Further, the related art for realizing a partial connection structure has limitations in that it requires a photolithography process to form an electrode, and the passivation layer is damaged, thereby increasing surface defects during electrode formation.

[相關技術文獻][Related technical literature] [專利文獻][Patent Literature]

(專利文獻1)韓國專利公開公報第2006-0035657號(Patent Document 1) Korean Patent Publication No. 2006-0035657

本發明的一實施例提供一種背接式太陽電池的製造方法,其能夠最小化高價貴金屬的使用,在即使不使用光刻製程之下形成電極,最小化由於電極的形成造成的鈍化薄膜的耗損,以及展現卓越的電特性。An embodiment of the present invention provides a method of fabricating a back-contact solar cell capable of minimizing the use of expensive noble metal, forming an electrode without using a photolithography process, and minimizing wear of the passivation film due to electrode formation. And show excellent electrical characteristics.

以一般的觀點,提供了一種背接式太陽電池的製造方法,此方法包括:(a)使用雷射形成導通孔以貫通一p型半導體基板的兩個相對表面;(b)在n型雜質存在之下在半導體基板上進行熱處理,從而掺雜n型雜質到半導體基板中;(c)在半導體基板的兩個表面的一表面上形成一抗反射膜,以及在半導體基板的該表面的相反表面上形成一鈍化膜;(d)塗佈在熱處理時貫通鈍化膜的一第一電極材料,從而在相反表面側的導通孔的開口部與鈍化膜鄰近導通孔的開口部的部份上形成第一電極以覆蓋導通孔的開口部,以及塗佈在熱處理時不貫通鈍化膜的一第二電極材料,從而形成第二電極以覆蓋第一電極;(e)塗佈在熱處理時貫通鈍化膜的一第三電極材料,從而在鈍化膜上形成第三電極,以及塗佈在熱處理時不貫通鈍化膜的一第四電極材料,從而形成第四電極以覆蓋第三電極;以及(f)在具有第一、第二、第三和第四電極的半導體基板上進行熱處理,從而在第一、第二、第三和第四電極之中只允許第一和第三電極與半導體基板透過穿通現象選擇性地連接。From a general point of view, a method of manufacturing a back-mounted solar cell is provided, the method comprising: (a) forming a via hole using a laser to penetrate two opposite surfaces of a p-type semiconductor substrate; (b) n-type impurity Forming a heat treatment on the semiconductor substrate to dope the n-type impurity into the semiconductor substrate; (c) forming an anti-reflection film on one surface of both surfaces of the semiconductor substrate, and opposing the surface of the semiconductor substrate Forming a passivation film on the surface; (d) coating a first electrode material penetrating the passivation film during heat treatment, thereby forming an opening portion of the via hole on the opposite surface side and a portion of the passivation film adjacent to the opening portion of the via hole The first electrode covers the opening of the via hole, and a second electrode material that does not penetrate the passivation film during heat treatment, thereby forming a second electrode to cover the first electrode; (e) coating the passivation film during heat treatment a third electrode material, thereby forming a third electrode on the passivation film, and coating a fourth electrode material that does not penetrate the passivation film during heat treatment, thereby forming a fourth electrode to cover the third electrode And (f) performing heat treatment on the semiconductor substrate having the first, second, third, and fourth electrodes, thereby allowing only the first and third electrodes among the first, second, third, and fourth electrodes The semiconductor substrate is selectively connected to the through-pass phenomenon.

第一電極可具有一點狀,其直徑為導通孔的開口部的直徑的1到20倍,且第二電極可具有一點狀,其直徑為第一電極的直徑的1.5到30倍。The first electrode may have a dot shape having a diameter which is 1 to 20 times the diameter of the opening portion of the via hole, and the second electrode may have a dot shape having a diameter of 1.5 to 30 times the diameter of the first electrode.

此時,在第二電極具有一覆蓋第一電極的點狀的情況下,此方法可更包括,在階段d)之後,形成第五電極,其各具有一帶狀且覆蓋複數個在一直線上彼此分開的第二電極。At this time, in the case where the second electrode has a dot shape covering the first electrode, the method may further include, after the stage d), forming a fifth electrode each having a strip shape and covering a plurality of in-line a second electrode that is separated from each other.

第一電極可具有一點狀,其直徑為導通孔的開口部的直徑的1到20倍,且第二電極可具有一帶狀,其較短長度為第一電極直徑的1.5到30倍,第二電極連接複數個在一直線上彼此分開的第一電極。The first electrode may have a dot shape having a diameter which is 1 to 20 times the diameter of the opening portion of the via hole, and the second electrode may have a strip shape having a shorter length of 1.5 to 30 times the diameter of the first electrode, The two electrodes are connected to a plurality of first electrodes that are separated from each other in a straight line.

第三電極可具有一點狀,其直徑為10 μm到150 μm,且第四電極可具有一帶狀,其連接複數個在一直線上彼此分開的第三電極。帶狀第四電極的較短長度可較佳地為第三電極直徑的1.5到30倍。The third electrode may have a dot shape having a diameter of 10 μm to 150 μm, and the fourth electrode may have a strip shape connecting a plurality of third electrodes separated from each other in a straight line. The shorter length of the strip-shaped fourth electrode may preferably be 1.5 to 30 times the diameter of the third electrode.

第一電極材料或第三電極材料可包括:一或二或更多選自銀(Ag)、銅(Cu)、鈦(Ti)、金(Au)、鋁(Al)、鎢(W)、鎳(Ni)、鉻(Cr)、鉬(Mo)、鉑(Pt)、鉛(Pb)、鈀(Pd)、及其合金的導電材料;以及一玻璃料,其含有含有氧化鉛的鉛玻璃或含有氧化鉍的無鉛玻璃。The first electrode material or the third electrode material may include: one or two or more selected from the group consisting of silver (Ag), copper (Cu), titanium (Ti), gold (Au), aluminum (Al), tungsten (W), a conductive material of nickel (Ni), chromium (Cr), molybdenum (Mo), platinum (Pt), lead (Pb), palladium (Pd), and alloys thereof; and a glass frit containing lead glass containing lead oxide Or lead-free glass containing cerium oxide.

覆蓋第一電極的第二電極材料或覆蓋第三電極的第四電極材料包括:一或二或更多選自銀(Ag)、銅(Cu)、鈦(Ti)、金(Au)、鋁(Al)、鎢(W)、鎳(Ni)、鉻(Cr)、鉬(Mo)、鉑(Pt)、鉛(Pb)、鈀(Pd)、及其合金的導電材料;以及一二氧化矽基或磷酸鹽基且不含硼、鉍和鉛的玻璃料。The second electrode material covering the first electrode or the fourth electrode material covering the third electrode includes: one or two or more selected from the group consisting of silver (Ag), copper (Cu), titanium (Ti), gold (Au), aluminum (Al), tungsten (W), nickel (Ni), chromium (Cr), molybdenum (Mo), platinum (Pt), lead (Pb), palladium (Pd), and alloys thereof; and a second oxidation A glass frit based on sulfhydryl or phosphate groups and free of boron, antimony and lead.

階段f)中的熱處理可在溫度為600℃到1000℃下進行。在熱處理時,第一電極與第二電極中,只有第一電極透過穿通現象選擇性地與半導體基板連接,且第三電極與第四電極中,只有第三電極透過穿通現象選擇性地與半導體基板連接。The heat treatment in stage f) can be carried out at a temperature of from 600 ° C to 1000 ° C. During the heat treatment, only the first electrode and the second electrode are selectively connected to the semiconductor substrate through the punch-through phenomenon, and only the third electrode and the fourth electrode are selectively penetrating through the semiconductor. The substrate is connected.

1‧‧‧導通孔1‧‧‧through hole

2‧‧‧前射極2‧‧‧Pre-shoot

3‧‧‧導通孔射極3‧‧‧Through hole emitter

4‧‧‧背射極4‧‧‧Back shot

100‧‧‧半導體基板100‧‧‧Semiconductor substrate

200‧‧‧抗反射膜200‧‧‧Anti-reflective film

300‧‧‧鈍化膜300‧‧‧passivation film

400‧‧‧n型電極400‧‧‧n type electrode

410‧‧‧第一電極410‧‧‧First electrode

420‧‧‧第二電極420‧‧‧second electrode

430‧‧‧第五電極430‧‧‧ fifth electrode

500‧‧‧p型電極500‧‧‧p-type electrode

510‧‧‧第三電極510‧‧‧ third electrode

520‧‧‧第四電極520‧‧‧fourth electrode

1a‧‧‧開口部1a‧‧‧ openings

1b‧‧‧開口部1b‧‧‧ openings

A‧‧‧n型匯流排電極A‧‧‧n type bus bar electrode

B‧‧‧n形指狀電極B‧‧‧n-shaped finger electrode

圖1為一流程圖,顯示依本發明的太陽電池製造方法。1 is a flow chart showing a method of manufacturing a solar cell according to the present invention.

圖2為一視圖,顯示一基板的前面,以解釋依本發明的n型電極的一個例子。Fig. 2 is a view showing the front surface of a substrate to explain an example of an n-type electrode according to the present invention.

圖3為一視圖,顯示一基板的背面,以解釋依本發明的n型電極的另一個例子,圖3的(a)顯示基板的背面,其中一依本發明的n型電極具有一帶狀,圖3的(b)顯示基板的背面,其中一依本發明的n型電極具有一點狀;且圖4為一視圖,顯示一基板的背面,以解釋依本發明的n型電極與p型電極的一個例子。Figure 3 is a view showing the back surface of a substrate to explain another example of the n-type electrode according to the present invention, and (a) of Figure 3 shows the back surface of the substrate, wherein an n-type electrode according to the present invention has a strip shape (b) of FIG. 3 shows the back surface of the substrate, wherein an n-type electrode according to the present invention has a dot shape; and FIG. 4 is a view showing the back surface of a substrate to explain the n-type electrode and p-type according to the present invention. An example of an electrode.

以下參考隨附的圖式,詳細說明依本發明的背接式太陽電池的製造方法。以下舉例說明的圖式係以實施例的方式提供,使本發明的精神可以充份地傳達給本發明所屬領域的技術人員。所以,本發明不限於以下提出的圖式,並可以以不同的形式來實施,且以下提出的圖式可以被誇張 化以便釐清本發明的精神。另外,相同的標號在整個說明書中表示相同的元件。The method of manufacturing the back-mounted solar cell according to the present invention will be described in detail below with reference to the accompanying drawings. The drawings exemplified below are provided by way of example, and the spirit of the invention may be fully conveyed to those skilled in the art to which the invention belongs. Therefore, the present invention is not limited to the drawings presented below, and may be embodied in different forms, and the drawings presented below may be exaggerated. In order to clarify the spirit of the present invention. In addition, the same reference numerals denote the same elements throughout the specification.

此時,除非另有說明,在本說明書中使用的術語,包括技術和科學術語,具有與本發明所屬領域的技術人員所通常理解者相同的意義,而且可能模糊本發明主旨的已知功能與成份的詳細說明將被省略。In this regard, the terms used in the specification, including technical and scientific terms, have the same meaning as commonly understood by those skilled in the art to which the invention belongs, and may obscure the known functions of the subject matter of the present invention. A detailed description of the ingredients will be omitted.

圖1為一流程圖,顯示依本發明的背接式太陽電池的製造方法。如圖1所示,根據本發明的背接式太陽電池的製造方法可包括:a)使用雷射形成導通孔1以貫通一p型半導體基板100的兩個相對表面;b)在n型雜質存在的情況之下在半導體基板100上進行熱處理,從而掺雜n型雜質到半導體基板100中;c)在半導體基板100的兩個表面的一表面上形成一抗反射膜200,以及在半導體基板100的該表面的相反表面上形成一鈍化膜300;d)塗佈在熱處理時貫通鈍化膜300的一第一電極材料,從而在相反表面側的導通孔1的開口部與鈍化膜300鄰近導通孔1的開口部的部份上形成第一電極410以覆蓋導通孔1的開口部,以及塗佈在熱處理時不貫通鈍化膜300的一第二電極材料,從而形成第二電極420以覆蓋第一電極410;e)塗佈在熱處理時貫通鈍化膜300的一第三電極材料,從而在鈍化膜300上形成第三電極510,以及塗佈在熱處理時不貫通鈍化膜300的一第四電極材料,從而形成第四電極520以覆蓋第三電極510;以及f)在具有第一、第二、第三和第四電極410、420、510、和520的半導體基板100上進行熱處理,從而在第一、第二、第三和第四電極410、420、510、和520之中只允許第一和第三電極410和510與半導體基板100透過穿通現象選擇性地連接。1 is a flow chart showing a method of manufacturing a back-mounted solar cell according to the present invention. As shown in FIG. 1, a method of manufacturing a back-mounted solar cell according to the present invention may include: a) forming a via hole 1 using a laser to penetrate two opposite surfaces of a p-type semiconductor substrate 100; b) n-type impurity The heat treatment is performed on the semiconductor substrate 100 to dope the n-type impurity into the semiconductor substrate 100; c) forming an anti-reflection film 200 on one surface of both surfaces of the semiconductor substrate 100, and on the semiconductor substrate A passivation film 300 is formed on the opposite surface of the surface of 100; d) a first electrode material penetrating through the passivation film 300 during heat treatment, so that the opening portion of the via hole 1 on the opposite surface side is adjacent to the passivation film 300 A first electrode 410 is formed on a portion of the opening of the hole 1 to cover the opening of the via hole 1, and a second electrode material that does not penetrate the passivation film 300 during heat treatment is applied, thereby forming the second electrode 420 to cover the second electrode 420. An electrode 410; e) coated with a third electrode material penetrating the passivation film 300 during heat treatment, thereby forming a third electrode 510 on the passivation film 300, and coating a fourth electrode that does not penetrate the passivation film 300 during heat treatment material Forming a fourth electrode 520 to cover the third electrode 510; and f) performing heat treatment on the semiconductor substrate 100 having the first, second, third, and fourth electrodes 410, 420, 510, and 520, thereby Among the first, third, and fourth electrodes 410, 420, 510, and 520, only the first and third electrodes 410 and 510 are allowed to be selectively connected to the semiconductor substrate 100 through the punch-through phenomenon.

具體而言,半導體基板100的例子可包括第4族半導體基板,包括矽(Si)、鍺(Ge)或矽鍺(SiGe);第3~5族半導體基板,包括砷化鎵(GaAs)、磷化銦(InP)、或磷化鎵(GaP);第2~6族半導體基板,包括硫化鎘(CdS),碲化鋅(ZnTe);以及第4~6族半導體基板,包括硫化鉛(PbS)。Specifically, examples of the semiconductor substrate 100 may include a Group 4 semiconductor substrate including germanium (Si), germanium (Ge) or germanium (SiGe); a group 3 to 5 semiconductor substrate including gallium arsenide (GaAs), Indium phosphide (InP), or gallium phosphide (GaP); Group 2-6 semiconductor substrates, including cadmium sulfide (CdS), zinc telluride (ZnTe); and Group 4-6 semiconductor substrates, including lead sulfide ( PbS).

就結晶而言,半導體基板的例子可包括單晶、多晶、或非晶質基板。As far as crystallization is concerned, examples of the semiconductor substrate may include single crystal, polycrystalline, or amorphous substrates.

在階段a),使用雷射形成導通孔1,其貫通半導體基板100 兩個相對面,較佳地為一接收太陽光的光接收面,以及與光接收面為相反面的背面。導通孔1的直徑較佳地可為20 μm至120 μm。In stage a), a via hole 1 is formed using a laser penetrating through the semiconductor substrate 100 The two opposite faces are preferably a light receiving face that receives sunlight and a back face that is opposite to the light receiving face. The diameter of the via hole 1 may preferably be 20 μm to 120 μm.

在階段a)中,彼此分開的多個導通孔1被可靠地形成於半導體基板100。In the stage a), a plurality of via holes 1 separated from each other are reliably formed on the semiconductor substrate 100.

具體而言,如圖2所示,彼此分開且二維地安排的導通孔的開口部1a係形成在欲形成n形指狀電極B的區域。較佳地,導通孔的開口部1b係形成於欲形成連接多個n型指狀電極的n型匯流排電極A的區域。Specifically, as shown in FIG. 2, the opening portion 1a of the via hole which is separated from each other and which is two-dimensionally arranged is formed in a region where the n-shaped finger electrode B is to be formed. Preferably, the opening portion 1b of the via hole is formed in a region where the n-type bus bar electrode A for connecting a plurality of n-type finger electrodes is to be formed.

以照射雷射形成導通孔1涉及半導體基板100的熱損壞,所以,進行蝕刻製程以移除損壞區域(損壞去除蝕刻)是較佳的。Forming the via hole 1 by the irradiation of the laser involves thermal damage of the semiconductor substrate 100, and therefore, it is preferable to perform an etching process to remove the damaged region (damage removal etching).

然後,具有導通孔1的半導體基板100在n型雜質存在下被施以熱處理,使n型雜質被掺雜在半導體基板100中。Then, the semiconductor substrate 100 having the via holes 1 is subjected to heat treatment in the presence of n-type impurities, so that n-type impurities are doped in the semiconductor substrate 100.

n型雜質的掺雜被進行,以在半導體基板100的兩表面其中形成有導通孔1的開口部的表面上形成一前射極2,在導通孔1上形成一導通孔射極3,以及在半導體基板100的兩表面其中形成有導通孔1的開口部的另一表面上的一部份形成背射極4,該另一表面的該部份與導通孔1的開口部接觸。Doping of the n-type impurity is performed to form a front emitter 2 on the surface of the opening portion of the semiconductor substrate 100 in which the via hole 1 is formed, and a via hole emitter 3 is formed on the via hole 1, and A portion on the other surface of the both surfaces of the semiconductor substrate 100 in which the opening portion of the via hole 1 is formed forms the back emitter 4, and this portion of the other surface is in contact with the opening portion of the via hole 1.

在製造具有背接式結構的太陽電池時,形成前射極、導通孔射極、以及背射極的n型雜質的掺雜,可透過經常用於具有背接式結構的太陽電池的掺雜方法來進行。In the fabrication of a solar cell having a back-up structure, doping of the front emitter, the via emitter, and the n-type impurity of the back emitter is permeable to the doping that is often used for solar cells having a back-up structure The method is carried out.

例如,選自液相POCl3 與P2 O5 的至少一種材料的n型雜質係與惰性氣體的載體氣體混合,此混合物被供應,然後半導體基板100在800到900℃的溫度下被施以熱處理10到60分鐘,使n型雜質掺雜至半導體基板100中。此時,載體氣體對n型雜質的混合比例,較佳地為1:1至8:1。此時,當雷射照射到半導體基板的局部區域上時,較高濃度的n型雜質可被局部摻雜在半導體基板中。在熱處理後,可進行一步驟以去除因掺雜後之熱處理而產生的雜質膜,例如磷矽酸鹽玻璃。For example, an n-type impurity selected from at least one material of a liquid phase of POCl 3 and P 2 O 5 is mixed with a carrier gas of an inert gas, the mixture is supplied, and then the semiconductor substrate 100 is applied at a temperature of 800 to 900 ° C. The n-type impurity is doped into the semiconductor substrate 100 by heat treatment for 10 to 60 minutes. At this time, the mixing ratio of the carrier gas to the n-type impurity is preferably 1:1 to 8:1. At this time, when the laser is irradiated onto a partial region of the semiconductor substrate, a higher concentration of n-type impurities may be locally doped in the semiconductor substrate. After the heat treatment, a step may be performed to remove an impurity film such as a phosphonate glass which is generated by the heat treatment after doping.

在掺雜n型雜質時,形成於光接收面以接收太陽光的前射極2較佳地具有50Ω/單位面積~100Ω/單位面積的薄層電阻;導通孔射極3較佳地具有10Ω/單位面積~50Ω/單位面積的薄層電阻;且形成在背面,其為接收太陽光的光接收面的相反面,的背射極4較佳地具有10Ω/單位面積~ 50Ω/單位面積的薄層電阻。When the n-type impurity is doped, the front emitter 2 formed on the light receiving surface to receive sunlight preferably has a sheet resistance of 50 Ω/unit area to 100 Ω/unit area; the via hole emitter 3 preferably has 10 Ω. / sheet resistance of unit area ~ 50 Ω / unit area; and formed on the back side, which is the opposite side of the light receiving surface receiving sunlight, the back emitter 4 preferably has 10 Ω / unit area ~ Sheet resistance of 50 Ω/unit area.

背射極4較佳地與導通孔1的開口部具有一同心結構,且較佳地具有一多邊形形狀或一圓形形狀,其直徑為導通孔1的開口部的直徑的2到30倍。The back emitter 4 preferably has a concentric structure with the opening of the via hole 1, and preferably has a polygonal shape or a circular shape having a diameter which is 2 to 30 times the diameter of the opening portion of the via hole 1.

在掺雜n型雜質之後,抗反射膜200形成在被導通孔1貫通的兩個面的一面上,且鈍化膜300形成在被導通孔1貫通的兩個面的另一面上。After the n-type impurity is doped, the anti-reflection film 200 is formed on one surface of the two faces penetrating through the via hole 1, and the passivation film 300 is formed on the other surface of the two faces penetrated by the via hole 1.

形成在半導體基板100的一面上,較佳地在半導體基板的光接收面的抗反射膜200,係用於防止太陽電池接收的光從太陽電池逸出,且鈍化在半導體基板100的表面上作為電子陷阱之處的表面缺陷。The anti-reflection film 200 formed on one surface of the semiconductor substrate 100, preferably on the light receiving surface of the semiconductor substrate, is for preventing light received by the solar cell from escaping from the solar cell and being passivated on the surface of the semiconductor substrate 100 as Surface defects at electronic traps.

在抗反射作用與鈍化作用係由單一材料進行的情況下,抗反射膜200可為一單一層薄膜,在反射作用與鈍化作用係由不同材料進行的情況下,抗反射膜200亦可為一不同材料層堆疊的多層薄膜。In the case where the anti-reflection effect and the passivation are performed by a single material, the anti-reflection film 200 may be a single layer film, and in the case where the reflection and the passivation are performed by different materials, the anti-reflection film 200 may also be a film. Multilayer film stacked with different material layers.

此外,即使在抗反射作用與鈍化作用係由單一材料進行的情況下,為了最大化抗反射作用與有效地鈍化缺陷,抗反射膜200可為不同材料層堆疊的多層薄膜。Further, even in the case where the antireflection effect and the passivation action are performed by a single material, in order to maximize the antireflection effect and effectively passivate the defects, the antireflection film 200 may be a multilayer film in which different material layers are stacked.

較佳地,防反射膜200可包括一單一膜,其選自半導體氧化物、半導體氮化物、含氮半導體氧化物、含氫半導體氮化物,半導體碳化物、氧化鋁、氟化鎂、硫化鋅、二氧化鈦與氧化鈰的至少一者,或一選自上述之至少二者所堆疊的多層薄膜。Preferably, the anti-reflection film 200 may comprise a single film selected from the group consisting of semiconductor oxides, semiconductor nitrides, nitrogen-containing semiconductor oxides, hydrogen-containing semiconductor nitrides, semiconductor carbides, aluminum oxides, magnesium fluorides, zinc sulfides. And at least one of titanium dioxide and cerium oxide, or a multilayer film selected from at least two of the foregoing.

作為矽太陽電池的一個例子,單膜型的抗反射膜200可為一氮化矽膜、含氫氮化矽膜,或氮氧化矽膜,且一多層薄膜型的抗反射膜200可包括一堆疊薄膜,其中堆疊有至少兩層選自氧化矽、氮化矽、碳化矽、氧化鋁、氟化鎂、硫化鋅、二氧化鈦、二氧化鈰的膜。As an example of the tantalum solar cell, the single film type anti-reflection film 200 may be a tantalum nitride film, a hafnium hydroxide film, or a hafnium oxynitride film, and a multi-layer film type anti-reflection film 200 may include A stacked film in which at least two layers of a film selected from the group consisting of cerium oxide, cerium nitride, cerium carbide, aluminum oxide, magnesium fluoride, zinc sulfide, titanium oxide, and cerium oxide are stacked.

在另一表面,即,半導體基板100背面上形成的鈍化膜300係用以鈍化在半導體基板100的表面上作為電子陷阱之處的表面缺陷的膜。On the other surface, that is, the passivation film 300 formed on the back surface of the semiconductor substrate 100 is used to passivate a film which is a surface defect at the surface of the semiconductor substrate 100 as an electron trap.

較佳地,鈍化膜300可包括半導體氧化物、半導體氮化物、含氮半導體氧化物、含氫半導體氮化物、半導體碳化物、或二氧化鈦膜,或其堆疊的薄膜。Preferably, the passivation film 300 may include a semiconductor oxide, a semiconductor nitride, a nitrogen-containing semiconductor oxide, a hydrogen-containing semiconductor nitride, a semiconductor carbide, or a titanium dioxide film, or a stacked film thereof.

作為一個矽太陽能電池的例子,鈍化膜300可為氮化矽膜、含氫氮化矽膜、氧化矽膜、碳化矽膜、或氮氧化矽膜,且多層薄膜型鈍化膜 可包括一堆疊薄膜,其中堆疊有兩層選自氮化矽膜、含氫氮化矽膜、氧化矽膜、氮氧化矽膜、碳化矽膜、和二氧化鈦膜。As an example of a tantalum solar cell, the passivation film 300 may be a tantalum nitride film, a hafnium hydroxide film, a hafnium oxide film, a tantalum carbide film, or a hafnium oxynitride film, and a multilayer film type passivation film. A stacked film may be included in which two layers are selected from the group consisting of a tantalum nitride film, a hafnium hydroxide containing film, a hafnium oxide film, a hafnium oxynitride film, a tantalum carbide film, and a titanium dioxide film.

抗反射膜200與鈍化膜300可藉由使用傳統上在半導體鈍化製程中採用的薄膜形成方法來形成,且可用選自物理氣相沉積(physical vapor deposition,PVD)、化學氣相沉積(chemical vapor deposition,CVD)、電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)、和熱蒸鍍的至少一種來形成。The anti-reflection film 200 and the passivation film 300 can be formed by using a thin film forming method conventionally employed in a semiconductor passivation process, and can be selected from physical vapor deposition (PVD), chemical vapor deposition (chemical vapor deposition). At least one of deposition, CVD), plasma enhanced chemical vapor deposition (PECVD), and thermal evaporation is formed.

之後,n型電極和p型電極形成在鈍化膜300上。Thereafter, an n-type electrode and a p-type electrode are formed on the passivation film 300.

n型電極400(n型指狀電極)可包括第一電極410和第二電極420。n型電極的形成可藉由在導通孔1的開口部與鈍化膜300鄰近導通孔1的開口部的部份形成第一電極410來進行,從而覆蓋位於半導體基板100背面,其為光接收面的相反面,的導通孔1的開口部,且形成覆蓋第一電極的第二電極。The n-type electrode 400 (n-type finger electrode) may include a first electrode 410 and a second electrode 420. The formation of the n-type electrode can be performed by forming the first electrode 410 at a portion of the opening portion of the via hole 1 and the opening portion of the passivation film 300 adjacent to the passivation film 1, so as to cover the back surface of the semiconductor substrate 100, which is a light receiving surface. On the opposite side, the opening of the via 1 is formed, and a second electrode covering the first electrode is formed.

第一電極410由於在熱處理時的穿通現象而貫通鈍化膜300,從而與半導體基板100連接,且第二電極410在熱處理時不貫通鈍化膜300。The first electrode 410 penetrates the passivation film 300 due to the punch-through phenomenon at the time of heat treatment, thereby being connected to the semiconductor substrate 100, and the second electrode 410 does not penetrate the passivation film 300 at the time of heat treatment.

如上所述,由於在第一電極410與第二電極420之間,只有第一電極410選擇性地貫通鈍化膜300,n型電極400與半導體基板100連接。此時,第一電極410形成在鈍化膜300上以覆蓋導通孔1的開口部,且因此第一電極410與半導體基板100的背射極4透過穿通現象而連接。As described above, since only the first electrode 410 selectively penetrates the passivation film 300 between the first electrode 410 and the second electrode 420, the n-type electrode 400 is connected to the semiconductor substrate 100. At this time, the first electrode 410 is formed on the passivation film 300 to cover the opening of the via hole 1, and thus the first electrode 410 and the back emitter 4 of the semiconductor substrate 100 are connected by the punch-through phenomenon.

第一電極410與半導體基板100透過穿通的連接,意謂第一電極的材料由於與鈍化膜300的介面反應而貫通鈍化膜300,且因此第一電極的材料係與背射極4物理接觸且電連接。關於穿通現象的具體機制,請見J.Hoomstra,等人,31st IEEE PVSC Florida 2005。The through-through connection of the first electrode 410 and the semiconductor substrate 100 means that the material of the first electrode penetrates the passivation film 300 due to the reaction with the interface of the passivation film 300, and thus the material of the first electrode is in physical contact with the back emitter 4 and Electrical connection. For specific mechanisms for punch-through, see J. Hoomstra, et al., 31st IEEE PVSC Florida 2005.

具體地,第一電極410的形成是藉由採用由於在熱處理時的穿通現象而貫通鈍化膜300的第一電極材料,且第二電極420的形成是藉由採用在熱處理時不會貫通鈍化膜300的第二電極材料。Specifically, the first electrode 410 is formed by using the first electrode material penetrating the passivation film 300 due to the punch-through phenomenon at the time of heat treatment, and the second electrode 420 is formed by using the passivation film without being penetrated during the heat treatment. The second electrode material of 300.

第一電極410較佳地係藉由印刷含有第一電極材料的墨水來形成,且第二電極420較佳地係藉由印刷含有第二電極材料的墨水來形成。The first electrode 410 is preferably formed by printing ink containing the first electrode material, and the second electrode 420 is preferably formed by printing ink containing the second electrode material.

此時,用於形成第一電極410或第二電極420的印刷,較佳地以至少一選自網版印刷、凹版印刷、膠版印刷、輥對輥印刷、噴墨印刷來 進行,並使用一供給器,且考慮生產成本與量產能力,網版印刷是較佳的。At this time, the printing for forming the first electrode 410 or the second electrode 420 is preferably at least one selected from the group consisting of screen printing, gravure printing, offset printing, roll-to-roll printing, and inkjet printing. Screening is preferred, and a feeder is used, and considering production cost and mass production capability.

第一電極材料含有蝕刻鈍化膜300的導電金屬材料和玻璃料。含在第一電極材料中的導電金屬材料可為選自下列之一或兩或多者:銀(Ag)、銅(Cu)、鈦(Ti)、金(Au)、鋁(Al)、鎢(W)、鎳(Ni)、鉻(Cr)、鉬(Mo)、鉑(Pt)、鉛(Pb)、鈀(Pd),及其合金。由於低熔點和優異的導電性,銀、銅、鎳、鋁、或其合金是較佳的,更佳的是銀。The first electrode material contains a conductive metal material and a glass frit that etch the passivation film 300. The conductive metal material contained in the first electrode material may be one or more selected from the group consisting of silver (Ag), copper (Cu), titanium (Ti), gold (Au), aluminum (Al), tungsten. (W), nickel (Ni), chromium (Cr), molybdenum (Mo), platinum (Pt), lead (Pb), palladium (Pd), and alloys thereof. Silver, copper, nickel, aluminum, or an alloy thereof is preferred because of its low melting point and excellent electrical conductivity, and more preferably silver.

第一電極材料中所含的玻璃料,為蝕刻鈍化膜300的玻璃料,且包括含氧化鉛的鉛玻璃、含氧化鉍和氧化硼的無鉛玻璃、或其混合物。The glass frit contained in the first electrode material is a frit that etches the passivation film 300, and includes lead glass containing lead oxide, lead-free glass containing cerium oxide and boron oxide, or a mixture thereof.

基於鉛玻璃的玻璃料的例子可包括氧化鉛-二氧化矽-氧化硼-氧化鋁玻璃料、氧化鉛-二氧化矽-氧化硼-氧化鋁-氧化鋯玻璃料、氧化鉛-二氧化矽-氧化硼-氧化鋁-氧化鋅玻璃料、或氧化鉛-二氧化矽-氧化硼-氧化鋁-氧化鋅-氧化鈦玻璃料。基於無鉛玻璃的玻璃料的例子可包括氧化鉍-氧化鋅-二氧化矽-氧化硼-氧化鋁玻璃料、氧化鉍-氧化鍶-二氧化矽-氧化硼-氧化鋁玻璃料、氧化鉍-氧化鋅-二氧化矽-氧化硼-氧化鑭-氧化鋁玻璃料、氧化鉍-氧化鋅-二氧化矽-氧化硼-氧化鈦玻璃料、氧化鉍-二氧化矽-氧化硼-氧化鍶玻璃料、或氧化鉍-二氧化矽-氧化硼-氧化鋅-氧化鍶玻璃料。此時,鉛玻璃或無鉛玻璃可更包括由一或兩種或多種選自氧化組、氧化銻、氧化鉛、氧化銦、氧化鎵、氧化釔、與氧化鐿的添加劑。由塗佈第一電極材料形成的第一電極410較佳地包括重量百分比3%至5%的鉛玻璃或無鉛玻璃。Examples of lead glass-based glass frits may include lead oxide-cerium oxide-boron oxide-alumina frit, lead oxide-cerium oxide-boron oxide-alumina-zirconia glass frit, lead oxide-cerium oxide- Boron oxide-alumina-zinc oxide frit, or lead oxide-ceria-boride-alumina-zinc oxide-titanium oxide frit. Examples of glass frits based on lead-free glass may include yttria-zinc oxide-ceria-boria-alumina frit, yttria-yttria-cerium oxide-boron oxide-alumina frit, yttria-oxidation Zinc-cerium oxide-boron oxide-cerium oxide-alumina glass frit, cerium oxide-zinc oxide-cerium oxide-boron oxide-titanium oxide glass frit, cerium oxide-cerium oxide-boron oxide-cerium oxide glass frit, Or cerium oxide-cerium oxide-boron oxide-zinc oxide-cerium oxide frit. At this time, the lead glass or the lead-free glass may further include one or two or more additives selected from the group consisting of an oxidation group, ruthenium oxide, lead oxide, indium oxide, gallium oxide, ruthenium oxide, and ruthenium oxide. The first electrode 410 formed of the coated first electrode material preferably includes 3% to 5% by weight of lead glass or lead-free glass.

如上所述,在第一電極410和第二電極420之間,第二電極420不貫通鈍化膜300,僅第一電極410選擇性地貫通鈍化膜300與基板連接。第二電極420不貫通鈍化膜300的意思,是第二電極材料不會與鈍化膜300發生介面反應,且即使在施加熱能時,第二電極材料穿通鈍化膜300也不會發生。As described above, between the first electrode 410 and the second electrode 420, the second electrode 420 does not penetrate the passivation film 300, and only the first electrode 410 selectively penetrates the passivation film 300 to be connected to the substrate. The second electrode 420 does not penetrate the passivation film 300, meaning that the second electrode material does not undergo an interface reaction with the passivation film 300, and the second electrode material does not pass through the passivation film 300 even when heat energy is applied.

第二電極材料含有不與鈍化膜300反應的導電性金屬材料和玻璃料。含在第二電極材料中的導電金屬材料,可為選自下列之一或二或更多者:銀(Ag)、銅(Cu)、鈦(Ti)、金(Au)、鋁(Al)、鎢(W)、鎳(Ni)、鉻(Cr)、鉬(Mo)、鉑(Pt)、鉛(Pb)、鈀(Pd),及其合金。含在第二電極材料中的玻璃料為不蝕刻鈍化膜300的玻璃料,且較 佳地為一般二氧化矽基或磷酸鹽基且不含硼、鉍和鉛的玻璃。The second electrode material contains a conductive metal material and a glass frit that do not react with the passivation film 300. The conductive metal material contained in the second electrode material may be one or two or more selected from the group consisting of silver (Ag), copper (Cu), titanium (Ti), gold (Au), and aluminum (Al). Tungsten (W), nickel (Ni), chromium (Cr), molybdenum (Mo), platinum (Pt), lead (Pb), palladium (Pd), and alloys thereof. The glass frit contained in the second electrode material is a glass frit that does not etch the passivation film 300, and Preferably, the glass is a general cerium oxide or phosphate based glass and does not contain boron, bismuth or lead.

更佳地,含在第二電極材料中的玻璃料,較佳地為二氧化矽基或磷酸鹽基且不含硼、鉍和鉛,且其玻璃化轉變溫度(Tg)為第一電極材料所含的玻璃料的1.2到2倍。More preferably, the glass frit contained in the second electrode material is preferably a cerium oxide group or a phosphate group and contains no boron, germanium or lead, and has a glass transition temperature (Tg) of the first electrode material. Contains 1.2 to 2 times the glass frit.

二氧化矽基玻璃料較佳地含有一或二或多種選自氧化鋰、氧化鈉、氧化鉀、氧化鎂、氧化鈣、氧化鋇、氧化鍶、氧化鋅、氧化鋁、氧化鈦、氧化鋯、氧化鉭、氧化銻、氧化鉛、氧化銦、氧化鎵、氧化釔、與氧化鐿的材料,且使用二氧化矽作為網路形成成份。磷酸鹽基玻璃料是釩磷酸鹽基玻璃,氧化磷-氧化釩,或鋅-銻-磷酸鹽基玻璃,氧化磷-氧化鋅-氧化銻。磷酸鹽基玻璃料較佳地含有一或二或更多選自氧化鉀、氧化鐵、氧化銻、氧化鋅、二氧化鈦、氧化鋁、氧化鎢的材料。此時,塗佈第二電極材料形成的第二電極420較佳地含有重量百分比3至5%的二氧化矽基或磷酸鹽基玻璃。The ceria-based glass frit preferably contains one or two or more selected from the group consisting of lithium oxide, sodium oxide, potassium oxide, magnesium oxide, calcium oxide, barium oxide, barium oxide, zinc oxide, aluminum oxide, titanium oxide, zirconium oxide, A material of cerium oxide, cerium oxide, lead oxide, indium oxide, gallium oxide, cerium oxide, and cerium oxide, and using cerium oxide as a network forming component. The phosphate-based glass frit is vanadium phosphate-based glass, phosphorus oxide-vanadium oxide, or zinc-bismuth-phosphate-based glass, phosphorus oxide-zinc oxide-yttrium oxide. The phosphate-based glass frit preferably contains one or two or more materials selected from the group consisting of potassium oxide, iron oxide, cerium oxide, zinc oxide, titanium oxide, aluminum oxide, and tungsten oxide. At this time, the second electrode 420 formed by coating the second electrode material preferably contains 3 to 5% by weight of cerium oxide-based or phosphate-based glass.

如圖3的(a)和(b)所示,第一電極的特徵在於成一點狀,且第二電極420的特徵在於成一帶狀(圖3的(a))或一點狀(圖3的(b))。As shown in (a) and (b) of FIG. 3, the first electrode is characterized by a point shape, and the second electrode 420 is characterized by a strip shape ((a) of FIG. 3) or a dot shape (of FIG. 3). (b)).

為了最小化由於鈍化膜300被第一電極410穿通的損傷而造成的表面缺陷的增加,以及降低接觸電阻,與n型掺雜區域由於熱處理時的穿通而連接的第一電極410的直徑,較佳地為位於半導體基板相反面的導通孔1開口部的1到20倍。此時,第一電極410的厚度較佳地為0.5μm至30μm。In order to minimize the increase in surface defects due to damage of the passivation film 300 by the first electrode 410, and to reduce the contact resistance, the diameter of the first electrode 410 connected to the n-type doped region due to the punch-through during heat treatment is compared. Preferably, it is 1 to 20 times larger than the opening of the via hole 1 on the opposite side of the semiconductor substrate. At this time, the thickness of the first electrode 410 is preferably from 0.5 μm to 30 μm.

在覆蓋第一電極410的第二電極420具有一點狀的情況下,第二電極420的直徑較佳地為第一電極410直徑的1.5到30倍,且第一電極410與第二電極420具有同心結構。In a case where the second electrode 420 covering the first electrode 410 has a dot shape, the diameter of the second electrode 420 is preferably 1.5 to 30 times the diameter of the first electrode 410, and the first electrode 410 and the second electrode 420 have Concentric structure.

由於第一電極410覆蓋導通孔1的開口部1a,且第二電極420覆蓋第一電極,第一電極410與第二電極420被安排成一圖案,其與多個形成在半導體基板100中的導通孔1所定義的圖案,即,形成在半導體基板100的背面的導通孔1的開口部1a所定義的圖案相同。Since the first electrode 410 covers the opening portion 1a of the via hole 1 and the second electrode 420 covers the first electrode, the first electrode 410 and the second electrode 420 are arranged in a pattern which is electrically connected to the plurality of semiconductor substrates 100. The pattern defined by the hole 1, that is, the pattern defined by the opening portion 1a of the via hole 1 formed on the back surface of the semiconductor substrate 100 is the same.

至於導通孔1的開口部1a的圖案,其由安排形成於n型指狀電極區域中的多數個導通孔1所定義,當由多個在一直線上彼此分開的開口部1a所構成的結構被指定為一個單位時,兩或多個單位更佳地係彼此分 開且平行,如圖2所示。As for the pattern of the opening portion 1a of the via hole 1, which is defined by a plurality of via holes 1 arranged in the n-type finger electrode region, when a structure composed of a plurality of opening portions 1a which are separated from each other in a straight line is When specified as one unit, two or more units are better divided into one another Open and parallel, as shown in Figure 2.

因此,亦作為第一電極410和第二電極420的圖案,當由多個在一直線上彼此分開的點形電極所構成的結構被指定為一個單元時,二或多個單元彼此分開,且較佳地彼此分開且平行。Therefore, also as a pattern of the first electrode 410 and the second electrode 420, when a structure composed of a plurality of dot electrodes separated from each other on a straight line is designated as one unit, two or more units are separated from each other, and The good places are separated and parallel to each other.

如圖3的(a)所示,在第二電極420具有帶狀的情況下,第二電極420具有一覆蓋多個第一電極410的帶狀,且多個第一電極410藉由第二電極420彼此電連接。As shown in (a) of FIG. 3, in the case where the second electrode 420 has a strip shape, the second electrode 420 has a strip shape covering the plurality of first electrodes 410, and the plurality of first electrodes 410 are provided by the second The electrodes 420 are electrically connected to each other.

具體地,第二電極420具有一覆蓋在一直線上彼此分開的第一電極410的帶狀,且多個依據位於一直線上的第一電極的第二電極可彼此分開且平行。Specifically, the second electrode 420 has a strip shape covering the first electrodes 410 separated from each other in a straight line, and the plurality of second electrodes according to the first electrodes located on the straight line may be separated and parallel to each other.

較佳地,帶狀的第二電極具有一50μm至1,000μm的寬度(較小的長度)。Preferably, the strip-shaped second electrode has a width (smaller length) of 50 μm to 1,000 μm.

如圖3(b)所示,在第二電極420具有點狀的情況下,在第二電極420上形成一具有一帶狀的第五電極430是較佳地,其覆蓋多個在一直線上彼此分開的第二電極420。此時,依據位於一直線上的第二電極的第五電極430可彼此分開且彼此平行。As shown in FIG. 3(b), in the case where the second electrode 420 has a dot shape, it is preferable to form a fifth electrode 430 having a strip shape on the second electrode 420, which covers a plurality of in-line The second electrode 420 is separated from each other. At this time, the fifth electrodes 430 according to the second electrodes located on the straight line may be separated from each other and parallel to each other.

多數個第一電極410與第二電極420係藉由第五電極430彼此電連接。具有帶狀的第五電極430較佳地具有50μm至1,000μm的寬度(較小的長度)。The plurality of first electrodes 410 and second electrodes 420 are electrically connected to each other by the fifth electrode 430. The fifth electrode 430 having a strip shape preferably has a width (smaller length) of 50 μm to 1,000 μm.

第五電極可透過塗佈導電金屬材料來形成,其含有一或二或更多選自銀(Ag)、銅(Cu)、鈦(Ti)、金(Au)、鋁(Al)、鎢(W)、鎳(Ni)、鉻(Cr)、鉬(Mo)、鉑(Pt)、鉛(Pb)、鈀(Pd)、及其合金的材料,且較佳地用以印刷來塗佈。The fifth electrode is formed by coating a conductive metal material containing one or two or more selected from the group consisting of silver (Ag), copper (Cu), titanium (Ti), gold (Au), aluminum (Al), and tungsten ( Materials of W), nickel (Ni), chromium (Cr), molybdenum (Mo), platinum (Pt), lead (Pb), palladium (Pd), and alloys thereof, and are preferably coated by printing.

由點狀的第一電極410、點狀的第二電極420、以及帶狀的第五電極430所構成的n型電極將鈍化膜300的損害降到最小,其非常低的電阻也將電阻損耗降到最小。The n-type electrode composed of the dot-shaped first electrode 410, the dot-shaped second electrode 420, and the strip-shaped fifth electrode 430 minimizes damage of the passivation film 300, and its very low resistance also causes resistance loss. Minimized.

n型電極包括第一電極410、點狀的第二電極420、以及第五電極430,或是第一電極410與帶狀的第二電極420,從而將鈍化膜300的損耗降到最小,且允許製造出具有10-6 Ωcm2 級接觸電阻的電極。The n-type electrode includes a first electrode 410, a dot-shaped second electrode 420, and a fifth electrode 430, or a first electrode 410 and a strip-shaped second electrode 420, thereby minimizing loss of the passivation film 300, and It is allowed to manufacture an electrode having a contact resistance of 10 -6 Ωcm 2 .

如圖4所示,p型電極500(p型指狀電極)可包括第三電極 510與第四電極520。p型電極500可藉由在鈍化膜300上形成第三電極510,以及形成覆蓋第三電極510的第四電極520來形成。As shown in FIG. 4, the p-type electrode 500 (p-type finger electrode) may include a third electrode 510 and fourth electrode 520. The p-type electrode 500 can be formed by forming the third electrode 510 on the passivation film 300 and forming the fourth electrode 520 covering the third electrode 510.

第三電極510由於熱處理時的穿通現象而貫通鈍化膜300,從而與半導體基板100連接,且第四電極520不貫通鈍化膜300。The third electrode 510 penetrates the passivation film 300 due to the punch-through phenomenon at the time of heat treatment, and is connected to the semiconductor substrate 100, and the fourth electrode 520 does not penetrate the passivation film 300.

如上所述,p型電極500的第三電極510與第四電極520中,只有第三電極510選擇性地貫通鈍化膜300而與基板100連接。此時,第三電極510與n型電極分開,並藉著穿通現象而與p型半導體基板100,即,半導體基板100的背面未掺雜n型雜質的一部份連接。As described above, of the third electrode 510 and the fourth electrode 520 of the p-type electrode 500, only the third electrode 510 selectively penetrates the passivation film 300 to be connected to the substrate 100. At this time, the third electrode 510 is separated from the n-type electrode, and is connected to the p-type semiconductor substrate 100, that is, a portion of the back surface of the semiconductor substrate 100 which is not doped with n-type impurities by a punch-through phenomenon.

第三電極510與半導體基板100藉由穿通的連接,意謂第三電極材料由於與鈍化膜300的介面反應而貫通鈍化膜300,且因此第三電極材料與半導體基板100的背面物理接觸並電連接。The connection of the third electrode 510 and the semiconductor substrate 100 by punch-through means that the third electrode material penetrates the passivation film 300 due to the reaction with the interface of the passivation film 300, and thus the third electrode material is in physical contact with the back surface of the semiconductor substrate 100 and is electrically connection.

具體而言,第三電極510係藉由塗佈第三電極材料而形成,第三電極材料在熱處理時因穿通現象而貫通鈍化膜300,且第四電極520係藉由塗佈第四電極材料而形成,第四電極材料在熱處理時不會貫通鈍化膜300。Specifically, the third electrode 510 is formed by coating a third electrode material, the third electrode material penetrates the passivation film 300 due to the punch-through phenomenon during heat treatment, and the fourth electrode 520 is coated with the fourth electrode material. On the other hand, the fourth electrode material does not penetrate the passivation film 300 during heat treatment.

第三電極510較佳地係由印刷含有第三電極材料的墨水而形成,且第四電極520較佳地係由印刷含有第四電極材料的墨水而形成。The third electrode 510 is preferably formed by printing ink containing a third electrode material, and the fourth electrode 520 is preferably formed by printing ink containing a fourth electrode material.

此時,用於形成第三電極510或第四電極520的印刷,較佳地以至少一選自網版印刷、凹版印刷、膠版印刷、輥對輥印刷、噴墨印刷來進行,並使用供給器,且考量生產成本與量產能力,網版印刷是較佳的。At this time, the printing for forming the third electrode 510 or the fourth electrode 520 is preferably performed by at least one selected from the group consisting of screen printing, gravure printing, offset printing, roll-to-roll printing, inkjet printing, and using a supply. Screen printing, and taking into account production costs and mass production capabilities, screen printing is preferred.

第三電極材料含有導電金屬材料與蝕刻鈍化膜300的玻璃料。第三電極材料所含的導電金屬材料可為一或二或更多選自銀(Ag)、銅(Cu)、鈦(Ti)、金(Au)、鋁(Al)、鎢(W)、鎳(Ni)、鉻(Cr)、鉬(Mo)、鉑(Pt)、鉛(Pb)、鈀(Pd)、及其合金的材料。The third electrode material contains a conductive metal material and a frit that etches the passivation film 300. The conductive material of the third electrode material may be one or two or more selected from the group consisting of silver (Ag), copper (Cu), titanium (Ti), gold (Au), aluminum (Al), tungsten (W), Materials of nickel (Ni), chromium (Cr), molybdenum (Mo), platinum (Pt), lead (Pb), palladium (Pd), and alloys thereof.

第三電極材料所含的玻璃料為蝕刻鈍化膜300的玻璃料,且包括含有氧化鉛的鉛玻璃、含有氧化鉍和氧化硼的無鉛玻璃、或其混合物。The glass frit contained in the third electrode material is a glass frit that etches the passivation film 300, and includes lead glass containing lead oxide, lead-free glass containing cerium oxide and boron oxide, or a mixture thereof.

鉛玻璃基玻璃料的例子可包括氧化鉛-二氧化矽-氧化硼-氧化鋁玻璃料、氧化鉛-二氧化矽-氧化硼-氧化鋁-氧化鋯玻璃料、氧化鉛-二氧化矽-氧化硼-氧化鋁-氧化鋅玻璃料、或氧化鉛-二氧化矽-氧化硼-氧化鋁-氧化鋅-氧化鈦玻璃料。無鉛玻璃基玻璃料的例子可包括氧化鉍-氧化鋅-二氧化矽- 氧化硼-氧化鋁玻璃料、氧化鉍-氧化鍶-二氧化矽-氧化硼-氧化鋁玻璃料、氧化鉍-氧化鋅-二氧化矽-氧化硼-氧化鑭-氧化鋁玻璃料、氧化鉍-氧化鋅-二氧化矽-氧化硼-氧化鈦玻璃料、氧化鉍-二氧化矽-氧化硼-氧化鍶玻璃料、或氧化鉍-二氧化矽-氧化硼-氧化鋅-氧化鍶玻璃料。此時,鉛玻璃或無鉛玻璃可包括由一或二或更多選自氧化組、氧化銻、氧化鉛、氧化銦、氧化鎵、氧化釔、與氧化鐿的添加劑。由塗佈第三電極材料所形成的第三電極510較佳地包括重量百分比3%至5%的鉛玻璃或無鉛玻璃。Examples of lead glass-based glass frits may include lead oxide-cerium oxide-boron oxide-alumina frit, lead oxide-cerium oxide-boron oxide-alumina-zirconia glass frit, lead oxide-cerium oxide-oxidation Boron-alumina-zinc oxide frit, or lead oxide-ceria-boride-alumina-zinc oxide-titanium oxide frit. Examples of lead-free glass-based glass frits may include cerium oxide-zinc oxide-cerium oxide- Boron oxide-alumina glass frit, cerium oxide-cerium oxide-cerium oxide-boron oxide-alumina glass frit, cerium oxide-zinc oxide-cerium oxide-boron oxide-cerium oxide-alumina glass frit, cerium oxide- Zinc oxide-cerium oxide-boron oxide-titanium oxide glass frit, cerium oxide-cerium oxide-boron oxide-cerium oxide glass frit, or cerium oxide-cerium oxide-boron oxide-zinc oxide-yttria glass frit. At this time, the lead glass or the lead-free glass may include an additive selected from one or two or more selected from the group consisting of an oxidation group, ruthenium oxide, lead oxide, indium oxide, gallium oxide, ruthenium oxide, and ruthenium oxide. The third electrode 510 formed by coating the third electrode material preferably comprises 3% to 5% by weight of lead glass or lead-free glass.

如上所述,關於第三電極510和第四電極520,第四電極520不貫通鈍化膜300,只有第三電極510選擇性地貫通鈍化膜300與基板連接。第四電極520不貫通鈍化膜300意謂第四電極材料不會與鈍化膜300進行介面反應,且即使在施加熱能的情況下,第四電極材料穿通鈍化膜300也不會發生。As described above, with respect to the third electrode 510 and the fourth electrode 520, the fourth electrode 520 does not penetrate the passivation film 300, and only the third electrode 510 selectively penetrates the passivation film 300 to be connected to the substrate. The fact that the fourth electrode 520 does not penetrate the passivation film 300 means that the fourth electrode material does not undergo an interface reaction with the passivation film 300, and even if thermal energy is applied, the fourth electrode material does not pass through the passivation film 300.

第四電極材料含有不會與鈍化膜300反應的導電金屬材料和玻璃料。第四電極材料所含的導電金屬材料可為一或二或更多個選自銀(Ag)、銅(Cu)、鈦(Ti)、金(Au)、鋁(Al)、鎢(W)、鎳(Ni)、鉻(Cr)、鉬(Mo)、鉑(Pt)、鉛(Pb)v鈀(Pd)、及其合金的材料。第四電極材料所含的玻璃料為不會蝕刻鈍化膜300的玻璃料,較佳地為不含硼、鉍和鉛的一般二氧化矽基或磷酸鹽基玻璃。The fourth electrode material contains a conductive metal material and a glass frit that do not react with the passivation film 300. The conductive material of the fourth electrode material may be one or two or more selected from the group consisting of silver (Ag), copper (Cu), titanium (Ti), gold (Au), aluminum (Al), and tungsten (W). Materials of nickel (Ni), chromium (Cr), molybdenum (Mo), platinum (Pt), lead (Pb) v palladium (Pd), and alloys thereof. The glass frit contained in the fourth electrode material is a glass frit which does not etch the passivation film 300, and is preferably a general ceria-based or phosphate-based glass which does not contain boron, antimony or lead.

更佳地,包括在第四電極材料裡的玻璃料之玻璃化轉變溫度(Tg)為第三電極材料所包括的玻璃料的1.2到2倍,且較佳地為不含硼、鉍和鉛的二氧化矽基或磷酸基的玻璃。More preferably, the glass transition temperature (Tg) of the glass frit included in the fourth electrode material is 1.2 to 2 times that of the glass frit included in the third electrode material, and preferably is free of boron, antimony and lead. A cerium oxide-based or phosphoric acid-based glass.

二氧化矽基玻璃料較佳地含有一或二或多種選自氧化鋰、氧化鈉、氧化鉀、氧化鎂、氧化鈣、氧化鋇、氧化鍶、氧化鋅、氧化鋁、氧化鈦、氧化鋯、氧化組、氧化銻、氧化鉛、氧化銦、氧化鎵、氧化釔、與氧化鐿的材料,且使用二氧化矽做為網路形成成份。磷酸鹽基玻璃料是釩磷酸鹽基玻璃,氧化磷-氧化釩,或鋅-銻-磷酸鹽基玻璃,氧化磷-氧化鋅-氧化銻。磷酸鹽基玻璃料較佳地含有一或二或多種選自氧化鉀、三氧化二鐵、氧化銻、氧化鋅、二氧化鈦、氧化鋁、與氧化鎢的材料。此時,由塗佈第四電極材料形成的第四電極520較佳地包括3至5%(重量百分比)的二氧化矽基或磷酸鹽基玻璃。The ceria-based glass frit preferably contains one or two or more selected from the group consisting of lithium oxide, sodium oxide, potassium oxide, magnesium oxide, calcium oxide, barium oxide, barium oxide, zinc oxide, aluminum oxide, titanium oxide, zirconium oxide, An oxidation group, ruthenium oxide, lead oxide, indium oxide, gallium oxide, ruthenium oxide, and ruthenium oxide materials, and using ruthenium dioxide as a network forming component. The phosphate-based glass frit is vanadium phosphate-based glass, phosphorus oxide-vanadium oxide, or zinc-bismuth-phosphate-based glass, phosphorus oxide-zinc oxide-yttrium oxide. The phosphate-based glass frit preferably contains one or two or more materials selected from the group consisting of potassium oxide, ferric oxide, cerium oxide, zinc oxide, titanium oxide, aluminum oxide, and tungsten oxide. At this time, the fourth electrode 520 formed of the fourth electrode material is preferably included in an amount of 3 to 5% by weight of cerium oxide-based or phosphate-based glass.

如圖4所示,第三電極510的特徵為一點狀,且第四電極的特徵為一覆蓋多個第三電極510的帶狀。As shown in FIG. 4, the third electrode 510 is characterized by a dot shape, and the fourth electrode is characterized by a strip shape covering the plurality of third electrodes 510.

具體地,在第三電極510具有點狀的情況下,當由多個在一直線上彼此分開的點所構成的結構被指定為一個單位時,二或多個單元較佳地係彼此以一預定距離分開,且較佳地彼此分開且平行。Specifically, in the case where the third electrode 510 has a dot shape, when a structure composed of a plurality of points separated from each other on a straight line is designated as one unit, the two or more units are preferably predetermined for each other. The distances are separate and preferably separated from each other and parallel.

第四電極520具有多數個彼此分開的帶狀,且各帶狀的第四電極520的特徵為電連接點狀的第三電極510。The fourth electrode 520 has a plurality of strips separated from each other, and each of the strip-shaped fourth electrodes 520 is characterized by electrically connecting the third electrodes 510 in a dot shape.

第三電極510有10μm至300μm的點直徑,且較佳地為10μm到150μm。點直徑的尺寸使第三電極510與半導體基板100連接且最小化鈍化膜的損傷。The third electrode 510 has a dot diameter of 10 μm to 300 μm, and preferably 10 μm to 150 μm. The size of the dot diameter connects the third electrode 510 to the semiconductor substrate 100 and minimizes damage of the passivation film.

形成在第三電極510上且覆蓋的點狀的第三電極510的帶狀第四電極520較佳地具有50μm至1,000μm的寬度(較小的長度)。這個寬度的尺寸降低了因第三電極510與半導體基板局部微接觸而增加的電阻,且具體地,此由第三電極510與第四電極520所構成的p型電極具有3~6×10-6 Ωcm的電阻。The strip-shaped fourth electrode 520 formed on the third electrode 510 and covering the dot-shaped third electrode 510 preferably has a width (smaller length) of 50 μm to 1,000 μm. The size of the width reduces the resistance increased by the partial contact of the third electrode 510 with the semiconductor substrate, and specifically, the p-type electrode composed of the third electrode 510 and the fourth electrode 520 has 3 to 6×10 − 6 Ωcm resistor.

如圖3與4所示,n型電極400包括點狀的第一電極410以及連接位於一直線上的第一電極410的帶狀的第二電極420,或是點狀的第一電極410、點狀的第二電極420、以及帶狀的第五電極430。多個n型電極400的末端係由一n型共同電極10(n型匯流排電極)彼此連接。As shown in FIGS. 3 and 4, the n-type electrode 400 includes a dot-shaped first electrode 410 and a strip-shaped second electrode 420 connected to the first electrode 410 on a straight line, or a dot-shaped first electrode 410, a dot. The second electrode 420 and the strip-shaped fifth electrode 430. The ends of the plurality of n-type electrodes 400 are connected to each other by an n-type common electrode 10 (n-type bus bar electrode).

p型電極500包括的點狀的第三電極510以及連接位於一直線上的多個第三電極510的帶狀的第四電極520,且p型電極500係位於兩個彼此相鄰的n型電極400之間。較佳地,複數個p型電極500的末端透過p型共同電極20(p型匯流排電極)彼此連接。The p-type electrode 500 includes a dot-shaped third electrode 510 and a strip-shaped fourth electrode 520 that connects the plurality of third electrodes 510 on a straight line, and the p-type electrode 500 is located at two n-type electrodes adjacent to each other. Between 400. Preferably, the ends of the plurality of p-type electrodes 500 are connected to each other through the p-type common electrode 20 (p-type bus bar electrode).

如同n型電極400,n型共同電極10可較佳地包括點狀第一共同電極11,以及一覆蓋多個第一共同電極11且連接多個n型電極400末端的帶狀第二共同電極12,如圖3(a)所示。Like the n-type electrode 400, the n-type common electrode 10 may preferably include a dot-shaped first common electrode 11, and a strip-shaped second common electrode covering the plurality of first common electrodes 11 and connecting the ends of the plurality of n-type electrodes 400 12, as shown in Figure 3 (a).

此外,如同p型電極500,p型共同電極20較佳地包括點狀第三共同電極21,以及一覆蓋多個第三共同電極21且連接多個p型電極500末端的帶狀第四共同電極22,如圖4所示。Further, like the p-type electrode 500, the p-type common electrode 20 preferably includes a dot-shaped third common electrode 21, and a strip-shaped fourth common that covers the plurality of third common electrodes 21 and connects the ends of the plurality of p-type electrodes 500 Electrode 22 is shown in FIG.

與n型電極的第一電極410與第二電極420類似地,n型共同 電極10的特徵,為在第一共同電極11與第二共同電極12中,只有第一共同電極11透過穿通現象與半導體基板的射極層選擇性地連接,如圖3的(a)和(b)所示。第一共同電極11可藉由塗佈與第一電極材料相似的材料形成,第二共同電極12可藉由塗佈與第二電極材料相似的材料形成。The first electrode 410 and the second electrode 420 of the n-type electrode are similar to the n-type common The electrode 10 is characterized in that, among the first common electrode 11 and the second common electrode 12, only the first common electrode 11 is selectively connected to the emitter layer of the semiconductor substrate through the punch-through phenomenon, as shown in (a) and (a) of FIG. b) shown. The first common electrode 11 may be formed by coating a material similar to the first electrode material, and the second common electrode 12 may be formed by coating a material similar to the second electrode material.

與p型電極500的第三電極510與第四電極520類似地,p型共同電極20的特徵,為在第三共同電極21與第四共同電極22中,只有第三共同電極21透過穿通現象選擇性地與半導體基板的p型區域連接。第三共同電極21可藉由塗佈與第三電極材料相似的材料形成,第四共同電極22可藉由塗佈與第四電極材料相似的材料形成。Similarly to the third electrode 510 and the fourth electrode 520 of the p-type electrode 500, the p-type common electrode 20 is characterized in that, among the third common electrode 21 and the fourth common electrode 22, only the third common electrode 21 penetrates through. Optionally connected to the p-type region of the semiconductor substrate. The third common electrode 21 may be formed by coating a material similar to the third electrode material, and the fourth common electrode 22 may be formed by coating a material similar to the fourth electrode material.

n型共同電極10可在形成n型電極400的階段,透過使用與形成n型電極400的方法類似的方法來形成,且p型共同電極20可在形成p型電極500的階段,透過使用與形成p型電極500的方法類似的方法來形成。The n-type common electrode 10 can be formed by a method similar to the method of forming the n-type electrode 400 at the stage of forming the n-type electrode 400, and the p-type common electrode 20 can be used at the stage of forming the p-type electrode 500. A method of forming the p-type electrode 500 is formed in a similar manner.

較佳地,用於透過穿通選擇性地連接的熱處理,在以印刷形成n型電極400、p型電極500、n型共同電極10、以及p型共同電極20之後進行是較佳的。Preferably, the heat treatment for selectively connecting through the through-pass is preferably performed after the n-type electrode 400, the p-type electrode 500, the n-type common electrode 10, and the p-type common electrode 20 are formed by printing.

所以,p型電極500或n型電極400係形成為梳齒狀,其一端係透過共同電極彼此連接。p型電極500與n型電極400較佳地以一指叉結構或一魚骨結構形成在半導體基板100的背面其中p型電極500與n型電極400彼此指叉。Therefore, the p-type electrode 500 or the n-type electrode 400 is formed in a comb-tooth shape, and one end thereof is connected to each other through a common electrode. The p-type electrode 500 and the n-type electrode 400 are preferably formed on the back surface of the semiconductor substrate 100 in an interdigitated structure or a fishbone structure in which the p-type electrode 500 and the n-type electrode 400 are interdigitated with each other.

具體地,上述的n型電極和p型電極,較佳地n型電極400、p型電極500、n型共同電極10、p型共同電極20係形成在鈍化膜300上,然後進行熱處理,使得在構成n型電極的第一電極410與第二電極420中,只有第一電極410選擇性地連接到半導體基板100的背射極,且在構成p型電極的第三電極510與第四電極520中,只有第三電極510選擇性地與半導體基板100的p型掺雜區域連接。Specifically, the n-type electrode and the p-type electrode, preferably the n-type electrode 400, the p-type electrode 500, the n-type common electrode 10, and the p-type common electrode 20 are formed on the passivation film 300, and then heat-treated, so that Among the first electrode 410 and the second electrode 420 constituting the n-type electrode, only the first electrode 410 is selectively connected to the back emitter of the semiconductor substrate 100, and the third electrode 510 and the fourth electrode constituting the p-type electrode In 520, only the third electrode 510 is selectively connected to the p-type doping region of the semiconductor substrate 100.

此時,在進行p型電極500的印刷與n型電極400的印刷之後,半導體基板與n型及p型電極由於穿通的連接較佳地透過熱處理來進行。用於形成p型電極500和n型電極400的熱處理較佳地以600℃到1000℃進行。At this time, after the printing of the p-type electrode 500 and the printing of the n-type electrode 400 are performed, the connection between the semiconductor substrate and the n-type and p-type electrodes is preferably performed by heat treatment. The heat treatment for forming the p-type electrode 500 and the n-type electrode 400 is preferably performed at 600 ° C to 1000 ° C.

依本發明的太陽電池製造方法,在掺雜n型雜質之前,可更進行一蝕刻半導體基板100以在表面形成微細凹凸的表面紋理化階段。此蝕刻包括乾或濕蝕刻,且紋理化表面包括一表面,其中布置了複數個倒金字塔形的微細的凹凸圖案。According to the solar cell manufacturing method of the present invention, before the n-type impurity is doped, a surface texture stage in which the semiconductor substrate 100 is etched to form fine concavities and convexities on the surface can be further performed. The etching includes dry or wet etching, and the textured surface includes a surface in which a plurality of inverted pyramid-shaped fine concavo-convex patterns are disposed.

此外,在形成導通孔之前,可更進行一形成背面場(back surface field,BSF)表面層的步驟,以透過在與光接收面相反的背面上塗佈含有p型雜質的掺雜液,以及接著在塗佈了含有p型雜質的掺雜液的半導體基板上進行熱處理,在半導體基板100的背面上產生一背電場。此時,由於只有第三電極選擇性地穿通,在p型電極的第三電極和第四電極中,第三電極可與形成在半導體基板背面的背面場區域電性與物理性連接。此外,當射極層透過塗佈n型雜質而形成時,射極層可以可靠地在n型共同電極下方形成。Further, before forming the via hole, a step of forming a back surface field (BSF) surface layer may be further performed to apply a doping liquid containing a p-type impurity on the back surface opposite to the light receiving surface, and Next, heat treatment is performed on the semiconductor substrate coated with the dopant containing the p-type impurity to generate a back electric field on the back surface of the semiconductor substrate 100. At this time, since only the third electrode is selectively punched through, among the third electrode and the fourth electrode of the p-type electrode, the third electrode may be electrically and physically connected to the back surface field formed on the back surface of the semiconductor substrate. Further, when the emitter layer is formed by applying an n-type impurity, the emitter layer can be reliably formed under the n-type common electrode.

如上所述,依本發明的太陽電池製造方法,可以最大限度地減少使用高價的貴金屬,包括銀,從而減少了處理成本;即使不使用高價的裝置與多階段製程,包括光刻製程的情況下,形成了電極,從而迅速和簡單地以低成本製造太陽電池;且防止由於基板因形成電極而造成的基板劣化而導致的效率下降;最小化由於鈍化層因微接觸或局部接觸的損傷而造成的缺陷,從而最小化載體的消失;以及達到與半導體基板連接的p型與n型電極的低串聯電阻。As described above, according to the solar cell manufacturing method of the present invention, it is possible to minimize the use of expensive precious metals, including silver, thereby reducing processing costs; even without using expensive devices and multi-stage processes, including lithography processes. Forming an electrode to quickly and simply manufacture the solar cell at low cost; and preventing a decrease in efficiency due to substrate degradation due to the formation of the electrode; minimizing damage due to microcontact or local contact of the passivation layer Defects, thereby minimizing the disappearance of the carrier; and achieving low series resistance of the p-type and n-type electrodes connected to the semiconductor substrate.

如上所述,雖然本發明透過例如具體的元件等具體事項、例示性的實施例、和附圖來描述,它們僅提供用於協助本發明的完整理解。因此,本發明並不限於例示性的實施例。本發明所屬領域的技術人員可從這些描述而進行各種修改和變化。As described above, the present invention has been described in terms of specific matters, exemplary embodiments, and the accompanying drawings, such as the specific elements, which are merely provided to facilitate a complete understanding of the present invention. Therefore, the invention is not limited to the illustrative embodiments. Various modifications and changes can be made by those skilled in the art from this description.

因此,本發明的精神,不應該被限定於上述的例示性實施例中,且後續的申請專利範圍以及與申請專利範圍相同或均等的修改均落入本發明的精神和範圍內。Therefore, the spirit of the present invention should not be limited to the above-described exemplary embodiments, and the scope of the following claims and the modifications of the same or equivalents are intended to fall within the spirit and scope of the invention.

1‧‧‧導通孔1‧‧‧through hole

2‧‧‧前射極2‧‧‧Pre-shoot

3‧‧‧導通孔射極3‧‧‧Through hole emitter

4‧‧‧背射極4‧‧‧Back shot

100‧‧‧半導體基板100‧‧‧Semiconductor substrate

200‧‧‧抗反射膜200‧‧‧Anti-reflective film

300‧‧‧鈍化膜300‧‧‧passivation film

410‧‧‧第一電極410‧‧‧First electrode

420‧‧‧第二電極420‧‧‧second electrode

510‧‧‧第三電極510‧‧‧ third electrode

520‧‧‧第四電極520‧‧‧fourth electrode

Claims (8)

一種背接式太陽電池的製造方法,該方法包含:(a)使用雷射形成導通孔以貫通-p型半導體基板的兩個相對表面;(b)在n型雜質存在之下在該半導體基板上進行熱處理,從而掺雜該n型雜質到該半導體基板中;(c)在該半導體基板的該兩個表面的一表面上形成-抗反射膜,以及在該半導體基板的該表面的相反表面上形成-鈍化膜;(d)塗佈在熱處理時貫通該鈍化膜的一第一電極材料,從而在該相反表面側的該導通孔的開口部與該鈍化膜鄰近該導通孔的開口部的部份上形成第一電極以覆蓋該導通孔的該開口部,以及塗佈在熱處理時不貫通該鈍化膜的一第二電極材料,從而形成第二電極以覆蓋該第一電極;(e)塗佈在熱處理時貫通該鈍化膜的一第三電極材料,從而在該鈍化膜上形成第三電極,以及塗佈在熱處理時不貫通該鈍化膜的一第四電極材料,從而形成第四電極以覆蓋該第三電極;以及(f)在具有該第一、第二、第三和第四電極的該半導體基板上進行熱處理,從而在該第一、第二、第三和第四電極之中只允許該第一和第三電極與該半導體基板透過穿通現象選擇性地連接。 A method of manufacturing a back-mounted solar cell, the method comprising: (a) forming a via hole using a laser to penetrate two opposite surfaces of a -p type semiconductor substrate; (b) in the presence of an n-type impurity on the semiconductor substrate Performing a heat treatment to dope the n-type impurity into the semiconductor substrate; (c) forming an anti-reflection film on a surface of the two surfaces of the semiconductor substrate, and an opposite surface of the surface of the semiconductor substrate Forming a passivation film thereon; (d) coating a first electrode material penetrating the passivation film during heat treatment, so that an opening portion of the via hole on the opposite surface side and the passivation film are adjacent to an opening portion of the via hole Forming a first electrode on the portion to cover the opening portion of the via hole, and coating a second electrode material not penetrating the passivation film during heat treatment, thereby forming a second electrode to cover the first electrode; (e) Coating a third electrode material penetrating the passivation film during heat treatment to form a third electrode on the passivation film, and coating a fourth electrode material that does not penetrate the passivation film during heat treatment, thereby forming a fourth electrode Covering the third electrode; and (f) performing heat treatment on the semiconductor substrate having the first, second, third, and fourth electrodes, thereby among the first, second, third, and fourth electrodes Only the first and third electrodes are allowed to be selectively connected to the semiconductor substrate through a punch-through phenomenon. 如申請專利範圍第1項的背接式太陽電池的製造方法,其中該第一電極具有一點狀,其直徑為該導通孔的該開口部的直徑的1到20倍,且該第二電極具有一點狀,其直徑為該第一電極的直徑的1.5到30倍。 The method of manufacturing a back-mounted solar cell according to claim 1, wherein the first electrode has a point shape having a diameter of 1 to 20 times a diameter of the opening portion of the via hole, and the second electrode has It is a point shape having a diameter of 1.5 to 30 times the diameter of the first electrode. 如申請專利範圍第1項的背接式太陽電池的製造方法,更包含,在申請專利範圍第1項所載之階段d)之後,形成第五電極,其各具有一帶狀且覆蓋複數個在一直線上彼此分開的該第二電極。 The method for manufacturing a back-mounted solar cell according to claim 1, further comprising forming a fifth electrode each having a strip shape and covering a plurality of stages after the stage d) of claim 1 The second electrode is separated from each other in a straight line. 如申請專利範圍第1項的背接式太陽電池的製造方法,其中該第一電極具有一點狀,其直徑為該導通孔的該開口部的直徑的1到20倍,且該第二電極具有一帶狀,其連接複數個在一直線上彼此分開的該第一電極。 The method of manufacturing a back-mounted solar cell according to claim 1, wherein the first electrode has a point shape having a diameter of 1 to 20 times a diameter of the opening portion of the via hole, and the second electrode has A strip shape connecting a plurality of the first electrodes separated from each other in a straight line. 如申請專利範圍第1項的背接式太陽電池的製造方法,其中該第三電極具有一點狀,其直徑為10μm到150μm,且該第四電極具有一帶狀,其連接複數個在一直線上彼此分開的該第三電極。 The method for manufacturing a back-mounted solar cell according to the first aspect of the invention, wherein the third electrode has a dot shape having a diameter of 10 μm to 150 μm, and the fourth electrode has a strip shape connecting the plurality of lines in a line. The third electrode is separated from each other. 如申請專利範圍第1項的背接式太陽電池的製造方法,其中該第一電極材料或該第三電極材料包括:一或二或更多選自銀(Ag)、銅(Cu)、鈦(Ti)、金(Au)、鋁(Al)、鎢(W)、鎳(Ni)、鉻(Cr)、鉬(Mo)、鉑(Pt)、鉛(Pb)、鈀(Pd)、及其合金的導電材料;以及一玻璃料,其含有包含氧化鉛的鉛玻璃或包含氧化鉍的無鉛玻璃。 The method for manufacturing a back-mounted solar cell according to claim 1, wherein the first electrode material or the third electrode material comprises: one or two or more selected from the group consisting of silver (Ag), copper (Cu), and titanium. (Ti), gold (Au), aluminum (Al), tungsten (W), nickel (Ni), chromium (Cr), molybdenum (Mo), platinum (Pt), lead (Pb), palladium (Pd), and a conductive material of the alloy; and a glass frit containing lead glass containing lead oxide or lead-free glass containing cerium oxide. 如申請專利範圍第1項的背接式太陽電池的製造方法,其中該第二電極材料或該第四電極材料包括:一或二或更多選自銀(Ag)、銅(Cu)、鈦(Ti)、金(Au)、鋁(Al)、鎢(W)、鎳(Ni)、鉻(Cr)、鉬(Mo)、鉑(Pt)、鉛(Pb)、鈀(Pd)、及其合金的導電材料;以及一二氧化矽基或磷酸鹽基且不含硼、鉍和鉛的玻璃料。 The method for manufacturing a back-mounted solar cell according to claim 1, wherein the second electrode material or the fourth electrode material comprises: one or two or more selected from the group consisting of silver (Ag), copper (Cu), and titanium. (Ti), gold (Au), aluminum (Al), tungsten (W), nickel (Ni), chromium (Cr), molybdenum (Mo), platinum (Pt), lead (Pb), palladium (Pd), and a conductive material of the alloy; and a frit containing a cerium oxide or phosphate group and containing no boron, antimony or lead. 如申請專利範圍第1項的背接式太陽電池的製造方法,其中申請專利範圍第1項所載之階段f)中的熱處理係在溫度為600℃到1000℃下進行。 The method for producing a back-mounted solar cell according to claim 1, wherein the heat treatment in the stage f) of the first application of the patent application is carried out at a temperature of 600 ° C to 1000 ° C.
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