TWI491010B - 微小化電磁干擾防護結構及其製作方法 - Google Patents
微小化電磁干擾防護結構及其製作方法 Download PDFInfo
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Description
本發明有關於一種電磁防護結構,且特別是有關於一種微小化電磁干擾防護結構及其製作方法。
電子元件是目前科技產品中不可缺少的一種產品,其用途極為廣泛。例如:各式家電用品、各式3C商品及各種需要透過電路加以控制的產品。於上述產品之電子元件中,皆具有至少一電磁干擾防護結構(EMI Shielding Structure)。其最主要的用途為防止該電子元件對外部環境造成干擾,或電子元件內各單元組件互相干擾現象。構造上主要由基板單元、電子電路單元、金屬防護單元、電性連接單元所組合而成。透過電磁干擾防護結構的屏蔽效果,來加以確保電子元件能在不受到干擾的環境下正常運作。
目前的相關技術於製作電磁干擾防護結構上,仍有諸多待改善的空間。例如:整體結構過於複雜、成品厚度過厚、屏蔽效果不佳或結構表面容易氧化生鏽。因此,致力於研發結構簡單、構造輕薄微型化、電磁屏蔽效果良好及結構表面具有防鏽抗氧化能力的電磁干擾防護結構,為當前電磁干擾防護結構研發改良的首要目的。
本發明實施例在於提供一種具有電磁防護功效的微小化電磁干擾防護結構及其製作方法。
本發明實施例提供一種微小化電磁干擾防護結構,其包括:一基板及多個晶片模組。基板表面上具有多個接地部。晶片模組設置於基板的表面上,其中每一個晶片模組包括:至少一晶片單元、至少一導電凸塊、一封裝膠層及一電磁防護層。晶片單元設置於基板的表面上且電性連接於基板。導電凸塊設置於基板的表面上且鄰近晶片單元,導電凸塊與基板上的接地部形成電性連接。封裝膠層設置於基板上且覆蓋晶片單元的表面及導電凸塊的表面。一電磁防護層覆蓋封裝膠層的表面並與導電凸塊電性連接,以使得電磁防護層電性連接於接地部。
除此之外,本發明實施例還提供一種微小化電磁干擾防護結構的製作方法,其包括步驟:設置多個晶片單元於一基板表面上,並且基板的表面上設置有多個接地部。成形多個設置於基板表面上且分別電性連接於接地部的導電凸塊,其中導電凸塊鄰近晶片單元。成形一封裝單元於基板上,以覆蓋晶片單元及導電凸塊。切割封裝單元及每一個導電凸塊,以使得封裝單元被切割成多個分別覆蓋晶片單元的封裝膠層,並使得每一個導電凸塊形成一從封裝膠層的側表面裸露出的裸露表面。將一電磁防護單元同時覆蓋每一個封裝膠層的表面及每一個導電凸塊的裸露表面。最後,沿著每兩個封裝膠層之間切割電磁防護單元,以使得電磁防護單元被切割成多個分別覆蓋封裝膠層的電磁防護層,即可得到本發明之微小化電磁干擾防護結構。
綜上所述,本發明實施例所提供的微小化電磁干擾防護結構具有電磁防護結構微型化的功效。藉由切除一部分的封裝單元、導電凸塊及電磁防護單元,以使得每一晶片模組達到微小化的設計,並且每一晶片模組個別具有防止電磁干擾的效果。
為使能更進一步瞭解本發明之特徵及技術內容,請參閱以下有關本發明之詳細說明與附圖,但是此等說明與所附圖式僅係用來說明本發明,而非對本發明的權利範圍作任何的限制。
請參閱圖1至圖6所示,其分別為本發明之第一實施例的第一、二、三、四、五及六步驟製作方法的剖面示意圖。根據本發明微小化電磁干擾防護結構M的製作方法,其包括步驟:
第一步驟(請參閱圖1),首先,設置多個晶片單元2於一基板1表面上,並且基板1的表面上設置有多個接地部11。
第二步驟(請參閱圖2),成形多個設置於基板1表面上且分別電性連接於接地部11的導電凸塊3,其中導電凸塊3鄰近晶片單元2。導電凸塊3為一金屬材質的凸塊,其可為各種導體金屬材質所形成。
第三步驟(請參閱圖3),成形一封裝單元4於基板1上,以覆蓋晶片單元2及導電凸塊3。也就是說,封裝單元4覆蓋基板1上的所有元件。
第四步驟(請參閱圖4),切割封裝單元4及導電凸塊3,以使得封裝單元4被切割成多個分別覆蓋晶片單元2的封裝膠層4’(示意圖僅標示一個晶片單元2作為代表)。藉由將一部分的封裝單元4及導電凸塊3切除,使得封裝單元4被切割分離成多個封裝膠層4’,並使得每一個導電凸塊3形成一從封裝膠層4’的側表面裸露出的裸露表面31。
第五步驟(請參閱圖5),將一電磁防護單元5同時覆蓋每一個封裝膠層4’的表面及每一個導電凸塊3的裸露表面31。也就是說,電磁防護單元5覆蓋基板1上的所有元件之表面。並且電磁防護單元5與導電凸塊3因為接觸而形成電性連接關係。
第六步驟(請參閱圖6),沿著每兩個封裝膠層4’之間切割電磁防護單元5,以使得電磁防護單元5被切割成多個分別覆蓋封裝膠層4’的電磁防護層5’。也就是說,藉由將一部分的電磁防護單元5切除,以使得電磁防護單元5分離成眾多微小部分。因此每一個晶片單元2分別具有獨立的電磁干擾防護結構。第一實施例可選擇性地到第五步驟結束或到第六步驟結束,不管是那一種,皆可完成本發明的微小化電磁干擾防護結構M。
上述第四步驟,其中切割的動作只針對封裝單元4及導電凸塊3,並不加以切穿基板1。倘若第四步驟將基板1切割分離成多個塊狀基板,將造成下一步驟的濺鍍或無電解電鍍作業無法直接批次進行。因為切割分離之後而需要先將多個塊狀基板進行排列方可進入濺鍍或無電解電鍍製程,將易形成時間及成本上的耗費。
上述第五步驟,其中電磁防護單元5包含多個用以防止晶片單元2與外部環境產生電磁干擾作用的金屬濺鍍層51。亦即,本發明微小化電磁干擾防護結構M的金屬濺鍍層51可分別為一覆蓋封裝膠層4’的表面及上述至少一導電凸塊3的裸露表面的第一不鏽鋼濺鍍層511、一覆蓋第一不鏽鋼濺鍍層511表面的第一銅濺鍍層512及一覆蓋第一銅濺鍍層512表面的第二不鏽鋼濺鍍層513(請參閱圖7,其為電磁防護層5’的局部示意圖)。
請參閱圖8所示,其為本發明微小化電磁干擾防護結構的製作方法之各步驟流程示意圖。圖中之S801~S806分別為本發明第一實施例的第一步驟至第六步驟。透過圖8可更為了解本發明之整體製作方法流程。
復參閱圖6所示,其為本發明的微小化電磁干擾防護結構M之第一實施例的剖面示意圖。根據本發明微小化電磁干擾防護結構的第一實施例,其包括:一基板1及多個晶片模組A。
基板1可為一印刷電路板或矽晶圓基板,其表面上具有多個接地部11。晶片模組A設置於基板1的表面上,並且每一個晶片模組A包括:至少一晶片單元2(示意圖僅標示一個晶片單元2作為代表)、至少一導電凸塊3、一封裝膠層4’及一電磁防護層5’。
晶片單元2設置於基板1的表面上且電性連接於基板1。導電凸塊3設置於基板1的表面上且鄰近晶片單元2,本發明第一實施例的導電凸塊3配置於晶片單元的鄰近兩側。並且不限定導電凸塊3的個數,導電凸塊3也可為一個或三個以上。上述至少一導電凸塊3與基板1上的第一接地部11形成電性連接。
封裝膠層4’設置於基板1上且覆蓋晶片單元2及導電凸塊3的表面。另外,電磁防護層5’覆蓋封裝膠層4’的表面及導電凸塊3的裸露表面。也就是說,電磁防護層5’覆蓋每一個封裝膠層4’的表面及導電凸塊3裸露出封裝膠層4’的部分,以使得電磁防護層5’透過導電凸塊3與接地部11形成電性連接的關係。
其中,電磁防護層5’包含有多個依序成形且用於防止晶片單元2彼此互相干擾的金屬濺鍍層51(請參閱圖7,其為電磁防護層5’的局部示意圖)。經由實驗研究及實際測試發現,當不鏽鋼濺鍍層與銅濺鍍層依序鍍著於結構體表面時,產生最佳的電磁屏蔽效果及防止表面發生氧化作用。但不限定,亦可為其他具有良好的電傳導性質及抗氧化性質的金屬材料。上述金屬濺鍍層51係經由不斷研究測試所發展出較佳的濺鍍層配置方式,可達到良好的電磁屏蔽作用及鍍層表面防止氧化的效果。其中上述濺鍍製程所製作之電磁防護層51亦可為一由無電解電鍍製程所製作之金屬層。
請參閱圖1至圖4以及圖9至圖11所示,其分別為本發明之第二實施例的第一、二、三、四、五、六及七步驟製作方法的剖面示意圖。第二實施例的前四個步驟與第一實施例相同,其步驟流程及元件符號可參考上述第一實施例之說明。根據本發明微小化電磁干擾防護結構M第二實施例的製作方法,其包括步驟:承圖1至圖4所示,由第一步驟至第四步驟可得到一表面具有導電凸塊3的基板1,並且每一個導電凸塊3具有一從封裝膠層4’的側表面裸露出的裸露表面31。其中,每兩個封裝膠層4’之間形成一容置空間6。因此本創作第二實施例中,容置空間6的數量為複數個。
接著第五步驟(請參閱圖9),分別成形多個導電層52於該些容置空間6內。亦即,導電層52設置於每兩個封裝膠層4’之間。並且導電層52分別與導電凸塊3的裸露表
面31及接地部11相互接觸,而相互形成電性連接的關係。其中,導電層52可為銀膠或各種導電膠體之材料所形成。
第六步驟(請參閱圖10),將一屏蔽層53同時覆蓋每一個導電層52的表面及每一個封裝膠層4’的表面。也就是說,屏蔽層53與導電層52因為接觸而形成電性連接。因此,屏蔽層53與接地部11透過導電層52而形成電性連接關係。值得一提的是,導電層52可為銀膠或各種導電膠體,屏蔽層53可以是金屬濺鍍層51,因為導電膠體與金屬濺鍍層不同,因此導電層52與屏蔽層53可以是不同材料。其中上述濺鍍製程所製作之屏蔽層53亦可為一由無電解電鍍製程所製作之金屬層。
第七步驟(請參閱圖11),切割屏蔽層53及每一個導電層52。其中屏蔽層53被切割成多個第一金屬層53’,每一個導電層52被切割成至少兩個第二金屬層52’。第一金屬層53’分別覆蓋封裝膠層4’的上表面及該第二金屬層52’的上表面而未覆蓋該第二金屬層52’的一側表面,第二金屬層52’的另一側表面分別同時覆蓋封裝膠層4’的側表面及導電凸塊3的裸露表面31,第二金屬層52’的下表面覆蓋該基板1的部份上表面,同時,該第二金屬層52’分別與該導電凸塊3形成電性連接,並且該導電凸塊3為金屬凸塊。其中,該屏蔽層53及該導電層52的切割方式為雷射切割。也就是說,每一個導電層52分別被切割成兩個各自獨立的個體。藉由將一部分的屏蔽層53及導電層52切除,而形成多個電磁防護層5’,其中每一個電磁防護層5’分別是由第一金屬層53’及第二金屬層
52’所構成。第二實施例可選擇性地到第六步驟結束或到第七步驟結束,不管是那一種,皆可完成本發明的微小化電磁干擾防護結構M。需說明的是,經過切割步驟後的第一金屬層53’及第二金屬層52’可以是不同材料,舉例來說,第一金屬層53’可以包含多個依序成形以用於防止外部環境對於該晶片單元產生電磁干擾作用的金屬濺鍍層51,第二金屬層52’可以由銀膠或各種導電膠體之材料所形成。其中上述濺鍍製程所製作之第一金屬層53’亦可為一由無電解電鍍製程所製作之金屬層。
本發明第二實施例藉由第二金屬層52’覆蓋封裝膠層4’的側表面,並且配合第一金屬層53’覆蓋封裝膠層4’的上表面,進而達成電磁屏蔽的功效,防止電子元件對外部環境造成干擾,或電子元件內各單元組件互相干擾之現象。
根據本發明實施例,上述的微小化電磁干擾防護結構藉由切除一部分的封裝單元、導電凸塊及電磁防護單元,以使得每一晶片模組達到微小化的設計,並且每一晶片模組個別具有防止電磁干擾的效果。
以上所述僅為本發明之實施例,其並非用以侷限本發明之專利範圍。
M‧‧‧微小化電磁干擾防護結構
1‧‧‧基板
11‧‧‧接地部
A‧‧‧晶片模組
2‧‧‧晶片單元
3‧‧‧導電凸塊
31‧‧‧裸露表面
4‧‧‧封裝單元
4’‧‧‧封裝膠層
5‧‧‧電磁防護單元
5’‧‧‧電磁防護層
51‧‧‧金屬濺鍍層
511‧‧‧第一不鏽鋼濺鍍層
512‧‧‧第一銅濺鍍層
513‧‧‧第二不鏽鋼濺鍍層
52‧‧‧導電層
52’‧‧‧第二金屬層
53‧‧‧屏蔽層
53’‧‧‧第一金屬層
6‧‧‧容置空間
圖1為本發明微小化電磁干擾防護結構的第一實施例之第一步驟剖面示意圖。
圖2為本發明微小化電磁干擾防護結構的第一實施例之第二步驟剖面示意圖。
圖3為本發明微小化電磁干擾防護結構的第一實施例之第三步驟剖面示意圖。
圖4為本發明微小化電磁干擾防護結構的第一實施例之第四步驟剖面示意圖。
圖5為本發明微小化電磁干擾防護結構的第一實施例之第五步驟剖面示意圖。
圖6為本發明微小化電磁干擾防護結構的第一實施例之第六步驟剖面示意圖。
圖7為本發明微小化電磁干擾防護結構的第一實施例之電磁防護層的局部示意圖。
圖8為本發明微小化電磁干擾防護結構的第一實施例製作方法之各步驟流程示意圖。
圖9為本發明微小化電磁干擾防護結構的第二實施例之第五步驟剖面示意圖。
圖10為本發明微小化電磁干擾防護結構的第二實施例之第六步驟剖面示意圖。
圖11為本發明微小化電磁干擾防護結構的第二實施例之第七步驟剖面示意圖。
M...微小化電磁干擾防護結構
1...基板
11...接地部
A...晶片模組
2...晶片單元
3...導電凸塊
31...裸露表面
4’...封裝膠層
5’...電磁防護層
Claims (10)
- 一種微小化電磁干擾防護結構,其包括:一基板,其表面上具有多個接地部;以及多個晶片模組,其設置於該基板的表面上,其中每一個晶片模組包括:至少一晶片單元,其設置於該基板的表面上且電性連接於該基板;至少一導電凸塊,其設置於該基板的表面上且鄰近上述至少一晶片單元,上述至少一導電凸塊與該基板上的接地部形成電性連接;一封裝膠層,其設置於該基板上且覆蓋該晶片單元及上述至少一導電凸塊的表面;以及一電磁防護層,其覆蓋該封裝膠層的表面並與上述至少一導電凸塊的裸露表面電性連接,以使得該電磁防護層電性連接於該基板上的接地部;其中該電磁防護層包括一第一金屬層及一第二金屬層,該第一金屬層與該第二金屬層為不同材料;其中該第一金屬層覆蓋該封裝膠層的上表面及該第二金屬層的上表面而未覆蓋該第二金屬層的一側表面,該第二金屬層的另一側表面覆蓋該封裝膠層的側表面及上述至少一導電凸塊的裸露表面,該第二金屬層的下表面覆蓋該基板的部份上表面。
- 如申請專利範圍第1項所述之微小化電磁干擾防護結構,其中該基板為印刷電路板或矽晶圓基板。
- 如申請專利範圍第1項所述之微小化電磁干擾防護結構,其中該第一金屬層包含有多個依序成形且用於防止外 部環境對於該晶片單元產生電磁干擾作用的金屬濺鍍層。
- 如申請專利範圍第3項所述之微小化電磁干擾防護結構,其中該些金屬濺鍍層分別為一覆蓋該封裝膠層的表面及上述至少一導電凸塊的裸露表面的第一不鏽鋼濺鍍層、一覆蓋該第一不鏽鋼濺鍍層表面的第一銅濺鍍層及一覆蓋該第一銅濺鍍層表面的第二不鏽鋼濺鍍層。
- 如申請專利範圍第1項所述之微小化電磁干擾防護結構,其中該第一金屬層為一由無電解電鍍製程所製作之金屬層。
- 一種微小化電磁干擾防護結構的製作方法,其包括步驟:設置多個晶片單元於一基板表面上,並且該基板的表面上設置有多個接地部;成形多個設置於該基板表面上且分別電性連接於該些接地部的導電凸塊,其中該些導電凸塊分別鄰近該些晶片單元;成形一封裝單元於該基板上,以覆蓋該些晶片單元及該些導電凸塊;切割該封裝單元及每一個導電凸塊,其中該封裝單元被切割成多個分別覆蓋該些晶片單元的封裝膠層,每兩個封裝膠層之間形成一容置空間,且每一個導電凸塊被切割而形成一從該封裝膠層的側表面裸露出的裸露表面;分別成形多個導電層於該些容置空間內;將一屏蔽層同時覆蓋每一個導電層的表面及每一個封裝 膠層的表面;以及切割該屏蔽層及每一個導電層,其中該屏蔽層被切割成多個第一金屬層,上述每一個導電層被切割成至少兩個第二金屬層,該些第一金屬層分別覆蓋該些封裝膠層的上表面,該些第二金屬層分別同時覆蓋該些封裝膠層的側表面及該些導電凸塊的裸露表面。
- 如申請專利範圍第6項所述之微小化電磁干擾防護結構的製作方法,其中該些第二金屬層分別與該些導電凸塊形成電性連接,並且該些導電凸塊為金屬凸塊。
- 如申請專利範圍第6項所述之微小化電磁干擾防護結構的製作方法,其中該屏蔽層及該導電層的切割方式為雷射切割。
- 如申請專利範圍第6項所述之微小化電磁干擾防護結構的製作方法,其中每一個第一金屬層分別包含多個依序成形以用於防止外部環境對於該晶片單元產生電磁干擾作用的金屬濺鍍層,該些第二金屬層為導電膠體。
- 如申請專利範圍第9項所述之微小化電磁干擾防護結構的製作方法,其中該些依序成形的金屬濺鍍層包括一第一不鏽鋼濺鍍層、一第一銅濺鍍層覆蓋該第一不鏽鋼濺鍍層及一第二不鏽鋼濺鍍層覆蓋該第一銅濺鍍層,該些導電膠體為銀膠體。
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US20120243191A1 (en) | 2012-09-27 |
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