TWI484757B - Schmitt trigger - Google Patents
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Description
本發明是有關於一種觸發器，且特別是有關於一種史密特觸發器。The present invention relates to a trigger, and more particularly to a Schmitt trigger.
一般而言，無論是數位或是類比電路都容易受到雜訊的干擾，進而導致資料在判讀上的錯誤或是讓電路產生不必要的轉態動作。為了避免上述情形，一般的電路往往都會利用史密特觸發器(Schmitt trigger)對訊號的波形進行整形，進而提升電路的抗雜訊能力。In general, both digital and analog circuits are susceptible to noise interference, which can lead to errors in the interpretation of the data or to cause unnecessary transitions in the circuit. In order to avoid the above situation, the general circuit often uses the Schmitt trigger to shape the waveform of the signal, thereby improving the anti-noise capability of the circuit.
在操作上，當輸入訊號大於高臨界電壓時，史密特觸發器之輸出訊號將切換至高邏輯位準。當輸入訊號小於低臨界電壓時，史密特觸發器之輸出訊號將切換至低邏輯位準。此外，當輸入訊號介在高臨界電壓與低臨界電壓之間時，史密特觸發器之輸出訊號將不會產生變動。換言之，史密特觸發器的轉移特性曲線具有遲滯(Hysteresis)現象，故具有抗雜訊的功能。In operation, when the input signal is greater than the high threshold voltage, the output signal of the Schmitt trigger will switch to the high logic level. When the input signal is less than the low threshold voltage, the output signal of the Schmitt trigger will switch to the low logic level. In addition, when the input signal is between the high threshold voltage and the low threshold voltage, the output signal of the Schmitt trigger will not change. In other words, the transfer characteristic curve of the Schmitt trigger has hysteresis, so it has the function of anti-noise.
然而，就現有之差動式史密特觸發器而言，當史密特觸發器維持在共模模式(common mode)附近時，例如史密特觸發器的差動輸入端浮接或是兩輸入訊號過於接近時，史密特觸發器的輸出訊號將會不斷地跳動。舉例來說，圖1為現有之差動式史密特觸發器的模擬波形圖，如圖1所示，當兩輸入訊號I11與I12過於接近時，史密特觸發器 的輸出訊號OT1將會不斷地上下晃動，進而導致史密特觸發器失去抗雜訊的功能。However, with the existing differential Schmitt trigger, when the Schmitt trigger is maintained in the vicinity of the common mode, for example, the differential input of the Schmitt trigger is floating or two When the input signal is too close, the output signal of the Schmitt trigger will continue to jump. For example, FIG. 1 is an analog waveform diagram of a conventional differential Schmitt trigger. As shown in FIG. 1, when the two input signals I11 and I12 are too close, the Schmitt trigger The output signal OT1 will constantly sway up and down, which will cause the Schmitt trigger to lose its anti-noise function.
本發明提供一種史密特觸發器，利用控制電路來致使操作在共模模式附近的史密特觸發器具有抗雜訊的功能。The present invention provides a Schmitt trigger that utilizes a control circuit to cause a Schmitt trigger operating near the common mode to have an anti-noise function.
本發明提出一種史密特觸發器，包括鎖存電路、信號轉換電路與控制電路。鎖存電路透過差動輸入級接收差動輸入訊號，並據以產生差動觸發訊號。差動輸入級包括第一N型電晶體與第二N型電晶體，且第一N型電晶體的閘極接收差動輸入訊號中的第一輸入訊號，第二N型電晶體的閘極接收差動輸入訊號中的第二輸入訊號。信號轉換電路依據差動觸發訊號切換一輸出訊號的位準。控制電路包括至少一第三N型電晶體與至少一第四N型電晶體。此外，控制電路依據輸出訊號將至少一第三N型電晶體與第一N型電晶體相互並接，或是將至少一第四N型電晶體與第二N型電晶體相互並接。The invention provides a Schmitt trigger comprising a latch circuit, a signal conversion circuit and a control circuit. The latch circuit receives the differential input signal through the differential input stage and generates a differential trigger signal accordingly. The differential input stage includes a first N-type transistor and a second N-type transistor, and the gate of the first N-type transistor receives the first input signal in the differential input signal, and the gate of the second N-type transistor Receiving a second input signal in the differential input signal. The signal conversion circuit switches the level of an output signal according to the differential trigger signal. The control circuit includes at least one third N-type transistor and at least one fourth N-type transistor. In addition, the control circuit connects the at least one third N-type transistor and the first N-type transistor to each other according to the output signal, or the at least one fourth N-type transistor and the second N-type transistor are connected to each other.
在本發明之一實施例中，上述之第二N型電晶體的汲極用以產生差動觸發訊號中的第一觸發訊號。第一N型電晶體的汲極用以產生差動觸發訊號中的第二觸發訊號。此外，當第一觸發訊號大於第二觸發訊號時，信號轉換電路將輸出訊號切換至高邏輯位準。當第一觸發訊號小於第二觸發訊號時，信號轉換電路將輸出訊號切換至低邏輯位準。In an embodiment of the invention, the drain of the second N-type transistor is used to generate a first trigger signal in the differential trigger signal. The drain of the first N-type transistor is used to generate a second trigger signal in the differential trigger signal. In addition, when the first trigger signal is greater than the second trigger signal, the signal conversion circuit switches the output signal to a high logic level. When the first trigger signal is smaller than the second trigger signal, the signal conversion circuit switches the output signal to a low logic level.
在本發明之一實施例中，當輸出訊號被切換至高邏輯 位準時，上述之控制電路將至少一第三N型電晶體與第一N型電晶體相互並接。此外，當輸出訊號被切換至低邏輯位準時，上述之控制電路將至少一第四N型電晶體與第二N型電晶體相互並接。In an embodiment of the invention, when the output signal is switched to high logic In the timing, the control circuit described above connects at least one third N-type transistor and the first N-type transistor to each other. In addition, when the output signal is switched to the low logic level, the control circuit described above connects at least one of the fourth N-type transistor and the second N-type transistor to each other.
在本發明之一實施例中，當第一輸入訊號與第二輸入訊號之間的差值大於高臨界電壓時，上述之信號轉換電路將輸出訊號切換至高邏輯位準，以致使控制電路將至少一第三N型電晶體與第一N型電晶體相互並接。此外，當第一輸入訊號小於第二輸入訊號之間的差值小於低臨界電壓時，上述之信號轉換電路將輸出訊號切換至低邏輯位準，以致使控制電路將至少一第四N型電晶體與第二N型電晶體相互並接。In an embodiment of the invention, when the difference between the first input signal and the second input signal is greater than the high threshold voltage, the signal conversion circuit switches the output signal to a high logic level, so that the control circuit will at least A third N-type transistor and the first N-type transistor are connected to each other. In addition, when the difference between the first input signal and the second input signal is less than the low threshold voltage, the signal conversion circuit switches the output signal to a low logic level, so that the control circuit will at least have a fourth N-type power. The crystal and the second N-type transistor are connected to each other.
基於上述，本發明之控制電路會依據輸出訊號，而致使至少一N型電晶體與鎖存電路之差動輸入級中的一N型電晶體相互並接。藉此，鎖存電路所產生之兩觸發訊號的差值將可相對地被拉大，進而致使史密特觸發器的輸出訊號可以更容易地維持在高邏輯位準或是低邏輯位準。此外，隨著兩觸發訊號之差值的變大，將可致使操作在共模模式附近的史密特觸發器依舊具有抗雜訊的功能。Based on the above, the control circuit of the present invention causes at least one N-type transistor to be connected to an N-type transistor in the differential input stage of the latch circuit in accordance with the output signal. Thereby, the difference between the two trigger signals generated by the latch circuit can be relatively enlarged, so that the output signal of the Schmitt trigger can be more easily maintained at a high logic level or a low logic level. In addition, as the difference between the two trigger signals becomes larger, the Schmitt trigger operating near the common mode will still have an anti-noise function.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖2為依據本發明一示範性實施例之史密特觸發器的 電路示意圖。參照圖2，史密特觸發器200包括鎖存電路(latch circuit)210、信號轉換電路220與控制電路230。其中，鎖存電路210具有差動輸入與差動輸出的電路組態。因此，在本實施例中，鎖存電路210會透過差動輸入級211來接收一差動輸入訊號IN，並據以產生一差動觸發訊號TR。其中，差動輸入訊號IN是由第一輸入訊號IN_P與第二輸入訊號IN_N所構成，且差動觸發訊號TR是由第一觸發訊號TR_P與第二觸發訊號TR_N。2 is a Schmitt trigger in accordance with an exemplary embodiment of the present invention. Circuit diagram. Referring to FIG. 2, the Schmitt trigger 200 includes a latch circuit 210, a signal conversion circuit 220, and a control circuit 230. Among them, the latch circuit 210 has a circuit configuration of a differential input and a differential output. Therefore, in the present embodiment, the latch circuit 210 receives a differential input signal IN through the differential input stage 211, and accordingly generates a differential trigger signal TR. The differential input signal IN is composed of the first input signal IN_P and the second input signal IN_N, and the differential trigger signal TR is composed of the first trigger signal TR_P and the second trigger signal TR_N.
鎖存電路210的差動輸入級211包括N型電晶體MN1與N型電晶體MN2。其中，N型電晶體MN1的閘極用以接收第一輸入訊號IN_P，且N型電晶體MN1的汲極用以產生第二觸發訊號TR_N。此外，N型電晶體MN2的閘極用以接收第二輸入訊號IN_N，且N型電晶體MN2的汲極用以產生第一觸發訊號TR_P。The differential input stage 211 of the latch circuit 210 includes an N-type transistor MN1 and an N-type transistor MN2. The gate of the N-type transistor MN1 is configured to receive the first input signal IN_P, and the drain of the N-type transistor MN1 is used to generate the second trigger signal TR_N. In addition, the gate of the N-type transistor MN2 is used to receive the second input signal IN_N, and the drain of the N-type transistor MN2 is used to generate the first trigger signal TR_P.
再者，信號轉換電路220會依據差動觸發訊號TR切換一輸出訊號OUT的位準，並將輸出訊號OUT回傳給控制電路230。其中，信號轉換電路220可例如是由一比較器所構成。此外，控制電路230會依據輸出訊號OUT來控制其內部多個電晶體與N型電晶體MN1~MN2的連接狀態。Moreover, the signal conversion circuit 220 switches the level of an output signal OUT according to the differential trigger signal TR, and returns the output signal OUT to the control circuit 230. The signal conversion circuit 220 can be constituted, for example, by a comparator. In addition, the control circuit 230 controls the connection state of the plurality of transistors and the N-type transistors MN1 MN MN2 according to the output signal OUT.
舉例來說，在本實施例中，控制電路230包括N型電晶體MN3、N型電晶體MN4、開關SW1與開關SW2。其中，N型電晶體MN3的汲極電性連接N型電晶體MN1的汲極，且N型電晶體MN3的閘極電性連接N型電晶體 MN1的閘極。此外，開關SW1的第一端電性連接N型電晶體MN3的源極，開關SW1的第二端電性連接N型電晶體MN1的源極。藉此，當開關SW1導通(turn on)時，N型電晶體MN3與N型電晶體MN1將相互並接。For example, in the present embodiment, the control circuit 230 includes an N-type transistor MN3, an N-type transistor MN4, a switch SW1, and a switch SW2. Wherein, the drain of the N-type transistor MN3 is electrically connected to the drain of the N-type transistor MN1, and the gate of the N-type transistor MN3 is electrically connected to the N-type transistor. The gate of MN1. In addition, the first end of the switch SW1 is electrically connected to the source of the N-type transistor MN3, and the second end of the switch SW1 is electrically connected to the source of the N-type transistor MN1. Thereby, when the switch SW1 is turned on, the N-type transistor MN3 and the N-type transistor MN1 will be connected to each other.
另一方面，N型電晶體MN4的汲極電性連接N型電晶體MN2的汲極，且N型電晶體MN4的閘極電性連接N型電晶體MN2的閘極。此外，開關SW2的第一端電性連接N型電晶體MN4的源極，且開關SW2的第二端電性連接N型電晶體MN2的源極。藉此，當開關SW2導通時，N型電晶體MN4與N型電晶體MN2將相互並接。On the other hand, the drain of the N-type transistor MN4 is electrically connected to the drain of the N-type transistor MN2, and the gate of the N-type transistor MN4 is electrically connected to the gate of the N-type transistor MN2. In addition, the first end of the switch SW2 is electrically connected to the source of the N-type transistor MN4, and the second end of the switch SW2 is electrically connected to the source of the N-type transistor MN2. Thereby, when the switch SW2 is turned on, the N-type transistor MN4 and the N-type transistor MN2 will be connected to each other.
在操作上，當第一輸入訊號IN_P與第二輸入訊號IN_N之間的差值大於高臨界電壓時，N型電晶體MN1將導通，且N型電晶體MN2將無法導通。藉此，第一觸發訊號TR_P的電壓位準將趨近於電源電壓VD，且第二觸發訊號TR_N的電壓位準將趨近於接地電壓。此外，當第一觸發訊號TR_P大於第二觸發訊號TR_N時，信號轉換電路220會將輸出訊號OUT切換至高邏輯位準。再者，控制電路230將依據具有高邏輯位準的輸出訊號OUT導通開關SW1，並將開關SW2維持在不導通的狀態。In operation, when the difference between the first input signal IN_P and the second input signal IN_N is greater than the high threshold voltage, the N-type transistor MN1 will be turned on, and the N-type transistor MN2 will be incapable of being turned on. Thereby, the voltage level of the first trigger signal TR_P will approach the power supply voltage VD, and the voltage level of the second trigger signal TR_N will approach the ground voltage. In addition, when the first trigger signal TR_P is greater than the second trigger signal TR_N, the signal conversion circuit 220 switches the output signal OUT to a high logic level. Furthermore, the control circuit 230 turns on the switch SW1 according to the output signal OUT having a high logic level, and maintains the switch SW2 in a non-conducting state.
換言之，當輸出訊號OUT被切換至高邏輯位準時，控制電路230會將N型電晶體MN3與N型電晶體MN1相互並接。此外，隨著N型電晶體MN3與N型電晶體MN1的相互並接，第二觸發訊號TR_N的電壓位準將會被下拉至更低的位準，進而致使第二觸發訊號TR_N的電壓 位準更加地趨近於接地電壓。此外，隨著第二觸發訊號TR_N之電壓位準的再次下降，輸出訊號OUT將更加地容易維持在高邏輯位準。In other words, when the output signal OUT is switched to the high logic level, the control circuit 230 will connect the N-type transistor MN3 and the N-type transistor MN1 to each other. In addition, as the N-type transistor MN3 and the N-type transistor MN1 are connected to each other, the voltage level of the second trigger signal TR_N will be pulled down to a lower level, thereby causing the voltage of the second trigger signal TR_N. The level is closer to the ground voltage. In addition, as the voltage level of the second trigger signal TR_N drops again, the output signal OUT will be more easily maintained at a high logic level.
另一方面，當第一輸入訊號IN_P與第二輸入訊號IN_N之間的差值小於低臨界電壓時，N型電晶體MN1將無法導通，且N型電晶體MN2將導通。藉此，第一觸發訊號TR_P的電壓位準將趨近於接地電壓，且第二觸發訊號TR_N的電壓位準將趨近於電源電壓VD。此外，當第一觸發訊號TR_P小於第二觸發訊號TR_N時，信號轉換電路220會將輸出訊號OUT切換至低邏輯位準。再者，控制電路230將依據具有低邏輯位準的輸出訊號OUT導通開關SW2，並將開關SW1維持在不導通的狀態。On the other hand, when the difference between the first input signal IN_P and the second input signal IN_N is less than the low threshold voltage, the N-type transistor MN1 will not be turned on, and the N-type transistor MN2 will be turned on. Thereby, the voltage level of the first trigger signal TR_P will approach the ground voltage, and the voltage level of the second trigger signal TR_N will approach the power supply voltage VD. In addition, when the first trigger signal TR_P is smaller than the second trigger signal TR_N, the signal conversion circuit 220 switches the output signal OUT to a low logic level. Furthermore, the control circuit 230 turns on the switch SW2 according to the output signal OUT having a low logic level, and maintains the switch SW1 in a non-conducting state.
換言之，當輸出訊號OUT被切換至低邏輯位準時，控制電路230會將N型電晶體MN4與N型電晶體MN2相互並接。此外，隨著N型電晶體MN4與N型電晶體MN2的相互並接，第一觸發訊號TR_P的電壓位準將會被下拉至更低的位準，進而致使第一觸發訊號TR_P的電壓位準更加地趨近於接地電壓。此外，隨著第一觸發訊號TR_P之電壓位準的再次下降，輸出訊號OUT將更加地容易維持在低邏輯位準。In other words, when the output signal OUT is switched to the low logic level, the control circuit 230 will connect the N-type transistor MN4 and the N-type transistor MN2 to each other. In addition, as the N-type transistor MN4 and the N-type transistor MN2 are connected to each other, the voltage level of the first trigger signal TR_P will be pulled down to a lower level, thereby causing the voltage level of the first trigger signal TR_P. More close to the ground voltage. In addition, as the voltage level of the first trigger signal TR_P drops again, the output signal OUT will be more easily maintained at a low logic level.
總體而言，隨著N型電晶體MN3與N型電晶體MN4之連接狀態的改變，兩觸發訊號TR_P與TR_N之間的差值將相對地被拉大，進而致使輸出訊號OUT可以更容易地維持在高邏輯位準或是低邏輯位準。如此一來，將可相 對地提高史密特觸發器200的高臨界電壓，並降低史密特觸發器200的低臨界電壓，進而有助於擴張史密特觸發器200的遲滯視窗(Hysteresis Window)。In general, as the connection state between the N-type transistor MN3 and the N-type transistor MN4 changes, the difference between the two trigger signals TR_P and TR_N will be relatively enlarged, thereby making the output signal OUT easier. Maintain a high logic level or a low logic level. In this way, it will be comparable Increasing the high threshold voltage of the Schmitt trigger 200 to ground and lowering the low threshold voltage of the Schmitt trigger 200, thereby contributing to the expansion of the Hysteresis Window of the Schmitt trigger 200.
舉例來說，圖3為依據本發明之一示範性實施例之史密特觸發器的轉移特性曲線圖，其中X軸為兩輸入訊號IN_P與IN_N的差值△IN，Y軸為輸出訊號OUT。此外，曲線310為史密特觸發器在沒有設置控制電路230下的轉移特性曲線，且曲線320為史密特觸發器在設置控制電路230下的轉移特性曲線。如曲線310所示，當沒有設置控制電路230時，高臨界電壓為TH1，且低臨界電壓為TH2。再者，如曲線320所示，當設置控制電路230時，高臨界電壓將變更為TH1’，且低臨界電壓將變更為TH2’。換言之，隨著控制電路230的設置，史密特觸發器200的遲滯視窗將分別朝向左右延伸。For example, FIG. 3 is a transfer characteristic diagram of a Schmitt trigger according to an exemplary embodiment of the present invention, wherein the X axis is the difference ΔIN between the two input signals IN_P and IN_N, and the Y axis is the output signal OUT. . In addition, curve 310 is the transfer characteristic of the Schmitt trigger under the control circuit 230, and curve 320 is the transfer characteristic of the Schmitt trigger under the set control circuit 230. As shown by curve 310, when control circuit 230 is not provided, the high threshold voltage is TH1 and the low threshold voltage is TH2. Further, as shown by the curve 320, when the control circuit 230 is provided, the high threshold voltage is changed to TH1', and the low threshold voltage is changed to TH2'. In other words, with the setting of the control circuit 230, the hysteresis windows of the Schmitt trigger 200 will respectively extend toward the left and right.
除此之外，由於兩觸發訊號TR_P與TR_N之間的差值可以相對地被拉大，因此即使史密特觸發器200維持在共模模式附近，其依舊具有抗雜訊的功能。舉例來說，圖4為依據本發明之一示範性實施例之史密特觸發器的模擬波形圖，如圖4所示，當兩輸入訊號IN_P與IN_N過於接近時，由於兩觸發訊號TR_P與TR_N之間的差值可以相對地被拉大，因此史密特觸發器200的輸出訊號OUT依舊可以維持在高邏輯位準。In addition, since the difference between the two trigger signals TR_P and TR_N can be relatively widened, even if the Schmitt trigger 200 is maintained in the vicinity of the common mode, it still has an anti-noise function. For example, FIG. 4 is an analog waveform diagram of a Schmitt trigger according to an exemplary embodiment of the present invention. As shown in FIG. 4, when the two input signals IN_P and IN_N are too close, the two trigger signals TR_P and The difference between TR_N can be relatively large, so the output signal OUT of the Schmitt trigger 200 can still be maintained at a high logic level.
值得一提的是，在圖2實施例中，控制電路230僅透過單一的N型電晶體MN3與開關SW1來與N型電晶體 MN1並聯，並透過單一的N型電晶體MN4與開關SW2來與N型電晶體MN2並聯。然而，在另一示範性實施例中，控制電路230也可例如是包括多個N型電晶體MN3、多個開關SW1、多個N型電晶體MN4與多個開關SW2。其中，這些N型電晶體MN3與這些開關SW1一對一對應，且每一N型電晶體MN3與相應的開關SW1串接在N型電晶體MN1的兩端。相似地，這些N型電晶體MN4與這些開關SW2一對一對應，且每一N型電晶體MN4與相應的開關SW2串接在N型電晶體MN2的兩端。It is worth mentioning that in the embodiment of FIG. 2, the control circuit 230 transmits only the single N-type transistor MN3 and the switch SW1 to the N-type transistor. The MN1 is connected in parallel and is connected in parallel with the N-type transistor MN2 through a single N-type transistor MN4 and a switch SW2. However, in another exemplary embodiment, the control circuit 230 may also include, for example, a plurality of N-type transistors MN3, a plurality of switches SW1, a plurality of N-type transistors MN4, and a plurality of switches SW2. The N-type transistors MN3 are in one-to-one correspondence with the switches SW1, and each of the N-type transistors MN3 and the corresponding switch SW1 are connected in series at both ends of the N-type transistor MN1. Similarly, these N-type transistors MN4 are in one-to-one correspondence with the switches SW2, and each of the N-type transistors MN4 and the corresponding switch SW2 are connected in series at both ends of the N-type transistor MN2.
藉此，當輸出訊號OUT被切換至高邏輯位準時，控制電路230中的多個N型電晶體MN3將會與N型電晶體MN1相互並接。此外，當輸出訊號OUT被切換至低邏輯位準時，控制電路230中的多個N型電晶體MN4將會與N型電晶體MN2相互並接。換言之，雖然圖2實施例列舉了控制電路230的實施型態，但其並非用以限定本發明，本領域具有通常知識者可依據設計所需，更改N型電晶體MN3、開關SW1、N型電晶體MN4與開關SW2的配置個數。Thereby, when the output signal OUT is switched to the high logic level, the plurality of N-type transistors MN3 in the control circuit 230 will be mutually connected with the N-type transistor MN1. In addition, when the output signal OUT is switched to the low logic level, the plurality of N-type transistors MN4 in the control circuit 230 will be connected to each other with the N-type transistor MN2. In other words, although the embodiment of FIG. 2 exemplifies the implementation of the control circuit 230, it is not intended to limit the present invention. Those skilled in the art can change the N-type transistor MN3, the switch SW1, and the N type according to the design requirements. The number of configurations of the transistor MN4 and the switch SW2.
請繼續參照圖2。鎖存電路210更包括P型電晶體MP1~MP4與電流源212。其中，P型電晶體MP1的源極接收一電源電壓VD，且P型電晶體MP1的汲極電性連接N型電晶體MN1的汲極。P型電晶體MP2的源極接收電源電壓VD，P型電晶體MP2的汲極電性連接N型電晶體MN2的汲極與P型電晶體MP1的閘極，且P型電晶體MP2 的閘極電性連接P型電晶體MP1的汲極。P型電晶體MP3的源極接收電源電壓VD，且P型電晶體MP3的閘極與汲極電性連接P型電晶體MP1的汲極。P型電晶體MP4的源極接收電源電壓VD，且P型電晶體MP4的閘極與汲極電性連接P型電晶體MP2的汲極。此外，電流源212的第一端電性連接N型電晶體MN1與MN2的源極，且電流源212的第二端電性連接至接地端。Please continue to refer to Figure 2. The latch circuit 210 further includes P-type transistors MP1 MP MP4 and a current source 212. The source of the P-type transistor MP1 receives a power supply voltage VD, and the drain of the P-type transistor MP1 is electrically connected to the drain of the N-type transistor MN1. The source of the P-type transistor MP2 receives the power supply voltage VD, and the drain of the P-type transistor MP2 is electrically connected to the drain of the N-type transistor MN2 and the gate of the P-type transistor MP1, and the P-type transistor MP2 The gate is electrically connected to the drain of the P-type transistor MP1. The source of the P-type transistor MP3 receives the power supply voltage VD, and the gate and the drain of the P-type transistor MP3 are electrically connected to the drain of the P-type transistor MP1. The source of the P-type transistor MP4 receives the power supply voltage VD, and the gate and the drain of the P-type transistor MP4 are electrically connected to the drain of the P-type transistor MP2. In addition, the first end of the current source 212 is electrically connected to the sources of the N-type transistors MN1 and MN2, and the second end of the current source 212 is electrically connected to the ground.
在操作上，當N型電晶體MN1導通，且N型電晶體MN2無法導通時，P型電晶體MP2與MP4將因應第二觸發訊號TR_N之電壓位準的降低而導通，進而將第一觸發訊號TR_P閂鎖在高準位。另一方面，P型電晶體MP1與MP3將因應第一觸發訊號TR_P之電壓位準的提高而無法導通，進而將第二觸發訊號TR_N閂鎖在低準位。此時，信號轉換電路220會將輸出訊號OUT切換至高邏輯位準，以致使N型電晶體MN3與N型電晶體MN1相互並接。此外，隨著N型電晶體MN3與N型電晶體MN1的相互並接，流經P型電晶體MP1與MP3的電流將變大，進而致使第二觸發訊號TR_N的電壓位準被下拉至更低的位準。亦即，此時的第二觸發訊號TR_N將會更加地趨近於接地電壓，進而提高兩觸發訊號TR_P與TR_N之間的差值，並致使輸出訊號OUT可以更容易地維持在高邏輯位準。In operation, when the N-type transistor MN1 is turned on and the N-type transistor MN2 is unable to be turned on, the P-type transistors MP2 and MP4 will be turned on according to the voltage level of the second trigger signal TR_N, and then the first trigger The signal TR_P is latched at a high level. On the other hand, the P-type transistors MP1 and MP3 will not be able to conduct according to the increase of the voltage level of the first trigger signal TR_P, thereby latching the second trigger signal TR_N at a low level. At this time, the signal conversion circuit 220 switches the output signal OUT to a high logic level so that the N-type transistor MN3 and the N-type transistor MN1 are connected to each other. In addition, as the N-type transistor MN3 and the N-type transistor MN1 are connected to each other, the current flowing through the P-type transistors MP1 and MP3 will become larger, thereby causing the voltage level of the second trigger signal TR_N to be pulled down to Low level. That is, the second trigger signal TR_N at this time will be closer to the ground voltage, thereby increasing the difference between the two trigger signals TR_P and TR_N, and causing the output signal OUT to be more easily maintained at a high logic level. .
相對地，當N型電晶體MN1無法導通，且N型電晶體MN2導通時，第一觸發訊號TR_P將被閂鎖在低準位， 且第二觸發訊號TR_N將被閂鎖在高準位。相對地，信號轉換電路220會將輸出訊號OUT切換至低邏輯位準，以致使N型電晶體MN4與N型電晶體MN2相互並接。此外，隨著N型電晶體MN4與N型電晶體MN2的相互並接，流經P型電晶體MP2與MP4的電流將變大，進而致使第一觸發訊號TR_P的電壓位準被下拉至更低的位準。如此一來，將可提高兩觸發訊號TR_P與TR_N之間的差值，進而致使輸出訊號OUT可以更容易地維持在低邏輯位準。In contrast, when the N-type transistor MN1 is unable to conduct and the N-type transistor MN2 is turned on, the first trigger signal TR_P will be latched at a low level. And the second trigger signal TR_N will be latched at a high level. In contrast, the signal conversion circuit 220 switches the output signal OUT to a low logic level so that the N-type transistor MN4 and the N-type transistor MN2 are connected to each other. In addition, as the N-type transistor MN4 and the N-type transistor MN2 are connected to each other, the current flowing through the P-type transistors MP2 and MP4 will become larger, thereby causing the voltage level of the first trigger signal TR_P to be pulled down to Low level. In this way, the difference between the two trigger signals TR_P and TR_N can be increased, so that the output signal OUT can be more easily maintained at a low logic level.
值得一提的是，對鎖存電路210而言，P型電晶體MP1與MP2可分別等效為一負載電阻，而P型電晶體MP3與MP4則是分別用以增加負載電阻的線性度。因此，在實際應用上，本領域具有通常知識者可依據設計所需，而決定是否配置P型電晶體MP3與MP4。此外，雖然圖2實施例列舉了鎖存電路210的實施型態，但其並非用以限定本發明。其中，依據本發明之示範性實施例的揭露，本領域具有通常知識者皆可明瞭，任何具有差動輸入級的鎖存電路，皆在本發明的應用範圍內。It is worth mentioning that, for the latch circuit 210, the P-type transistors MP1 and MP2 can be equivalent to a load resistor, respectively, and the P-type transistors MP3 and MP4 are respectively used to increase the linearity of the load resistance. Therefore, in practical applications, those skilled in the art can decide whether to configure the P-type transistors MP3 and MP4 according to the design requirements. Moreover, although the embodiment of FIG. 2 exemplifies the implementation of the latch circuit 210, it is not intended to limit the invention. In view of the disclosure of the exemplary embodiments of the present invention, it is apparent to those skilled in the art that any latch circuit having a differential input stage is within the scope of the present invention.
綜上所述，本發明之控制電路會依據輸出訊號，而致使至少一N型電晶體與鎖存電路之差動輸入級中的一N型電晶體相互並接。藉此，鎖存電路所產生之兩觸發訊號的差值將可相對地被拉大，進而致使史密特觸發器的輸出訊號可以更容易地維持在高邏輯位準或是低邏輯位準。此外，還可擴張史密特觸發器的遲滯視窗，並可提升史密特 觸發器的判別速度。再者，隨著兩觸發訊號之差值的變大，將可致使操作在共模模式附近的史密特觸發器依舊具有抗雜訊的功能。In summary, the control circuit of the present invention causes at least one N-type transistor to be connected to an N-type transistor in the differential input stage of the latch circuit in accordance with the output signal. Thereby, the difference between the two trigger signals generated by the latch circuit can be relatively enlarged, so that the output signal of the Schmitt trigger can be more easily maintained at a high logic level or a low logic level. In addition, you can expand the hysteresis window of the Schmitt trigger and enhance Schmidt The discriminating speed of the trigger. Furthermore, as the difference between the two trigger signals becomes larger, the Schmitt trigger operating near the common mode will still have an anti-noise function.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
I11、I12‧‧‧輸入訊號I11, I12‧‧‧ input signal
OT1‧‧‧輸出訊號OT1‧‧‧ output signal
200‧‧‧史密特觸發器200‧‧‧Schmitt trigger
210‧‧‧鎖存電路210‧‧‧Latch circuit
211‧‧‧差動輸入級211‧‧‧Differential input stage
212‧‧‧電流源212‧‧‧current source
220‧‧‧信號轉換電路220‧‧‧Signal Conversion Circuit
230‧‧‧控制電路230‧‧‧Control circuit
MN1~MN4‧‧‧N型電晶體MN1~MN4‧‧‧N type transistor
MP1~MP4‧‧‧P型電晶體MP1~MP4‧‧‧P type transistor
SW1、SW2‧‧‧開關SW1, SW2‧‧‧ switch
VD‧‧‧電源電壓VD‧‧‧Power supply voltage
IN‧‧‧差動輸入訊號IN‧‧‧Differential input signal
IN_P‧‧‧第一輸入訊號IN_P‧‧‧first input signal
IN_N‧‧‧第二輸入訊號IN_N‧‧‧Second input signal
TR‧‧‧差動觸發訊號TR‧‧‧Differential trigger signal
TR_P‧‧‧第一觸發訊號TR_P‧‧‧First trigger signal
TR_N‧‧‧第二觸發訊號TR_N‧‧‧second trigger signal
OUT‧‧‧輸出訊號OUT‧‧‧ output signal
310、320‧‧‧曲線310, 320‧‧‧ Curve
△IN‧‧‧兩輸入訊號的差值△IN‧‧‧The difference between the two input signals
TH1、TH1’‧‧‧高臨界電壓TH1, TH1'‧‧‧ high threshold voltage
TH2、TH2’‧‧‧低臨界電壓TH2, TH2'‧‧‧ low threshold voltage
圖1為現有之差動式史密特觸發器的模擬波形圖。FIG. 1 is an analog waveform diagram of a conventional differential Schmitt trigger.
圖2為依據本發明一示範性實施例之史密特觸發器的電路示意圖。2 is a circuit diagram of a Schmitt trigger in accordance with an exemplary embodiment of the present invention.
圖3為依據本發明之一示範性實施例之史密特觸發器的轉移特性曲線圖。3 is a graph showing a transfer characteristic of a Schmitt trigger in accordance with an exemplary embodiment of the present invention.
圖4為依據本發明之一示範性實施例之史密特觸發器的模擬波形圖。4 is an analog waveform diagram of a Schmitt trigger in accordance with an exemplary embodiment of the present invention.
200‧‧‧史密特觸發器200‧‧‧Schmitt trigger
210‧‧‧鎖存電路210‧‧‧Latch circuit
211‧‧‧差動輸入級211‧‧‧Differential input stage
212‧‧‧電流源212‧‧‧current source
220‧‧‧信號轉換電路220‧‧‧Signal Conversion Circuit
230‧‧‧控制電路230‧‧‧Control circuit
MN1~MN4‧‧‧N型電晶體MN1~MN4‧‧‧N type transistor
MP1~MP4‧‧‧P型電晶體MP1~MP4‧‧‧P type transistor
SW1、SW2‧‧‧開關SW1, SW2‧‧‧ switch
VD‧‧‧電源電壓VD‧‧‧Power supply voltage
IN_P‧‧‧第一輸入訊號IN_P‧‧‧first input signal
IN_N‧‧‧第二輸入訊號IN_N‧‧‧Second input signal
TR‧‧‧差動觸發訊號TR‧‧‧Differential trigger signal
TR_P‧‧‧第一觸發訊號TR_P‧‧‧First trigger signal
TR_N‧‧‧第二觸發訊號TR_N‧‧‧second trigger signal
OUT‧‧‧輸出訊號OUT‧‧‧ output signal
Claims (8)
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| TW101132184A TWI484757B (en) | 2012-09-04 | 2012-09-04 | Schmitt trigger |
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| TW101132184A TWI484757B (en) | 2012-09-04 | 2012-09-04 | Schmitt trigger |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6154066A (en) * | 1998-12-15 | 2000-11-28 | Oak Technology, Inc. | Apparatus and method for interfacing integrated circuits having incompatible I/O signal levels |
| TWI317204B (en) * | 2006-08-02 | 2009-11-11 | Winbond Electronics Corp | Differential difference amplifier |
| CN101917811A (en) * | 2010-08-02 | 2010-12-15 | 西安新光明电子科技有限公司 | Anti-noise jamming high-side drive circuit |
| EP2385616A2 (en) * | 2008-07-18 | 2011-11-09 | Peregrine Semiconductor Corporation | Low-noise high efficiency bias generation circuits and method |
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2012
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6154066A (en) * | 1998-12-15 | 2000-11-28 | Oak Technology, Inc. | Apparatus and method for interfacing integrated circuits having incompatible I/O signal levels |
| TWI317204B (en) * | 2006-08-02 | 2009-11-11 | Winbond Electronics Corp | Differential difference amplifier |
| EP2385616A2 (en) * | 2008-07-18 | 2011-11-09 | Peregrine Semiconductor Corporation | Low-noise high efficiency bias generation circuits and method |
| CN101917811A (en) * | 2010-08-02 | 2010-12-15 | 西安新光明电子科技有限公司 | Anti-noise jamming high-side drive circuit |
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