TWI484600B - Coreless package and method of fabricating the same - Google Patents
Coreless package and method of fabricating the same Download PDFInfo
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本發明係有關一種封裝基板及其製法，尤指一種無核心封裝基板及其製法。The invention relates to a package substrate and a preparation method thereof, in particular to a coreless package substrate and a preparation method thereof.
隨著電子產業的蓬勃發展，電子產品也逐漸朝向多功能與高效能的趨勢。為了滿足半導體封裝件的高整合度（integration）及微型化（miniaturization）的封裝需求，以供更多主、被動元件及線路的載接，半導體封裝基板亦逐漸由雙層電路板演變成多層電路板（multi-layer board），俾於有限的空間下運用層間連接技術（interlayer connection）以擴大半導體封裝基板上可供利用的線路佈局面積，並能配合高線路密度之積體電路（integrated circuit）的使用需求，且降低封裝基板的厚度，而能使封裝件達到輕薄短小及提高電性功能之目的。With the booming electronics industry, electronic products are gradually moving towards versatility and high performance. In order to meet the requirements of high integration and miniaturization of semiconductor packages for more active and passive components and lines, semiconductor package substrates have gradually evolved from two-layer boards to multilayer circuits. Multi-layer board, which uses an interlayer connection to expand the available layout area on a semiconductor package substrate in a limited space, and can be combined with a high line density integrated circuit. The use requirements, and reduce the thickness of the package substrate, can make the package to be light and thin, and improve the electrical function.
習知技術中，封裝基板係由一核心板及對稱形成於其兩側之線路增層結構所構成，因使用核心板將導致導電路徑之長度及整體結構之厚度增加，難以滿足電子產品功能不斷提昇與體積不斷縮小的需求，遂發展出無核心層（coreless）結構之封裝基板，而能縮短導電路徑之長度及降低整體結構之厚度以符合高頻化與微小化的趨勢。In the prior art, the package substrate is composed of a core plate and a line build-up structure symmetrically formed on both sides thereof. The use of the core plate will increase the length of the conductive path and the thickness of the overall structure, and it is difficult to meet the functions of the electronic product. The need for improvement and shrinkage of volume has led to the development of a package substrate having a coreless structure, which can shorten the length of the conductive path and reduce the thickness of the overall structure to meet the trend of high frequency and miniaturization.
習知無核心層封裝基板（例如第200730062號本國專利）為了抑制翹曲產生，其線路增層方式係需要電鍍高厚度的銅；惟，電鍍形成高厚度的銅容易有均勻性不佳、成本高與產率低等問題，導致整體良率較低。Conventionally, a core-free package substrate (for example, Japanese Patent No. 200730062) is required to plate a high-thickness copper in order to suppress warpage. However, plating to form a high-thickness copper tends to have poor uniformity and cost. Problems such as high yield and low yield lead to lower overall yield.
因此，如何克服上述習知技術中之均勻性不佳、良率較低與成本較高之問題，實已成目前亟欲解決的課題。Therefore, how to overcome the problems of poor uniformity, low yield and high cost in the above-mentioned prior art has become a problem that is currently being solved.
鑑於上述習知技術之種種缺失，本發明揭露一種無核心封裝基板，係包括：第一介電層，係具有相對之第一表面與第二表面；複數金屬柱，係埋設於該第一介電層中， 並具有相對之第一端面與第二端面，且該第一介電層之第一表面具有複數對應外露各該金屬柱之部份第一端面的第一盲孔，各該金屬柱之第二端面係完全外露於該第一介電層之第二表面，該金屬柱之高度係100微米以上；增層結構，係設於該第一介電層之第一表面上，該增層結構係包括至少一第二介電層、形成於該第二介電層上的線路層、複數形成於該第二介電層中的第二盲孔、與複數形成於該第二盲孔內且電性連接該線路層的導電盲孔，且該增層結構底層之各該導電盲孔係對應延伸至各該第一盲孔內並電性連接各該金屬柱之第一端面；以及絕緣保護層，係形成於該第一介電層之第二表面上，且形成有複數對應外露各該金屬柱之部份第二端面的絕緣保護層開孔。In view of the above-mentioned various deficiencies of the prior art, the present invention discloses a coreless package substrate, comprising: a first dielectric layer having a first surface and a second surface; and a plurality of metal pillars embedded in the first dielectric layer The first layer has a first end surface and a second end surface, and the first surface of the first dielectric layer has a plurality of first blind holes corresponding to a portion of the first end surface of each of the metal pillars, each of the metal The second end surface of the pillar is completely exposed on the second surface of the first dielectric layer, the height of the metal pillar is 100 micrometers or more; and the build-up structure is disposed on the first surface of the first dielectric layer, The build-up structure includes at least one second dielectric layer, a circuit layer formed on the second dielectric layer, a plurality of second blind vias formed in the second dielectric layer, and a plurality of forms formed in the second blind a conductive blind hole electrically connected to the circuit layer, and each of the conductive blind holes of the bottom layer of the build-up structure extends into each of the first blind holes and electrically connects the first end faces of the metal posts; And an insulating protective layer formed on the first dielectric layer And forming a plurality of insulating protective layer openings corresponding to a portion of the second end surface of each of the metal pillars.
本發明復揭露一種無核心封裝基板之製法，係包括：提供一承載件，其至少一表面上依序形成有蝕刻終止層與第二金屬層；於該第二金屬層上形成阻層，該阻層具有複數外露該第二金屬層的阻層開孔；蝕刻移除該阻層開孔中的第二金屬層，而形成複數金屬柱；移除該阻層，而外露該金屬柱原為該阻層所覆蓋之第一端面；於該蝕刻終止層上形成包覆該等金屬柱之第一介電層；於該第一介電層上形成增層結構，該增層結構係包括至少一第二介電層、形成於該第二介電層上的線路層、複數形成於該第二介電層中的第二盲孔、與複數形成於該第二盲孔內且電性連接該線路層的導電盲孔，且該第一介電層形成有對應外露各該金屬柱之部份第一端面的複數第一盲孔，且該增層結構底層之各該導電盲孔係對應延伸至各該第一盲孔內並電性連接各該金屬柱之第一端面；移除該承載件；以及移除部分該蝕刻終止層，以形成複數對應外露各該金屬柱之部份第二端面的蝕刻終止層開孔。The invention discloses a method for manufacturing a coreless package substrate, comprising: providing a carrier member having an etch stop layer and a second metal layer sequentially formed on at least one surface thereof; forming a resist layer on the second metal layer, The resist layer has a plurality of resist layer openings exposing the second metal layer; etching removes the second metal layer in the resist layer opening to form a plurality of metal pillars; removing the resist layer, and exposing the metal pillar a first end surface covered by the resist layer; a first dielectric layer covering the metal pillars is formed on the etch stop layer; and a build-up structure is formed on the first dielectric layer, the build-up structure includes at least a second dielectric layer, a circuit layer formed on the second dielectric layer, a plurality of second blind vias formed in the second dielectric layer, and a plurality of electrically formed in the second blind via and electrically connected a conductive blind via of the circuit layer, and the first dielectric layer is formed with a plurality of first blind vias corresponding to a portion of the first end surface of each of the metal pillars, and each of the conductive blind vias corresponding to the bottom layer of the build-up structure corresponds to Extending into each of the first blind holes and electrically connecting each of the metal pillars End surface; the carrier is removed; and removing portions of the etch stop layer to form a plurality of portions for exposing the etch stop layer, metal pillar opening a second end face.
由上可知，本發明係以例如ABF做為蝕刻終止層的材質，因而不需電鍍厚銅之步驟，進而解決習知技術之厚銅均勻性不佳、成本高、產率低及應力高等問題，使得本發明之無核心封裝基板具有整體良率較高、成本較低與抑制翹曲等優點。As can be seen from the above, the present invention uses, for example, ABF as the material of the etch stop layer, so that the step of plating thick copper is not required, thereby solving the problems of poor uniformity of copper thickness, high cost, low yield and high stress in the prior art. The coreless package substrate of the present invention has the advantages of high overall yield, low cost, and suppression of warpage.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「端面」、「頂」、「底」、「上」、「下」、「側」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第一實施例
第1A至1P圖所示者，係為本發明之無核心封裝基板及其製法之第一實施例的剖視圖，其中，第1P圖係第1O圖之應用例。
如第1A圖所示，提供一承載件10，其至少一表面上依序形成有離型層11與第一子金屬層121，該承載件10係包括承載板100及形成於該承載板100的至少一表面上之金屬箔101。
如第1B圖所示，於該第一子金屬層121上形成材質例如為銅的第二子金屬層122，且該第二子金屬層122復形成於該承載件10、離型層11與第一子金屬層121之側表面上，該第一子金屬層121與第二子金屬層122係共同定義成第一金屬層12。
如第1C圖所示，於該第二子金屬層122上形成蝕刻終止層13，該蝕刻終止層13之材質可為ABF（Ajinomoto Build-up Film），且該蝕刻終止層13亦為絕緣保護層的一種。
如第1D圖所示，於該蝕刻終止層13上形成第二金屬層14，該第二金屬層14係較佳為100微米厚的銅箔。
如第1E圖所示，於該第二金屬層14上形成阻層15，該阻層15具有複數外露該第二金屬層14的阻層開孔150。
如第1F圖所示，蝕刻移除該阻層開孔150中的第二金屬層14，而形成複數金屬柱141，此時，該蝕刻終止層13並不會被蝕刻。
如第1G圖所示，移除該阻層15，而外露該金屬柱141原為該阻層15所覆蓋之第一端面141a。
如第1H圖所示，於該蝕刻終止層13上形成包覆該等金屬柱141之第一介電層16，並藉由雷射移除部分該第一介電層16，以形成複數對應外露部分該第一端面141a的第一盲孔160，其中，該第一介電層16之材質係為模壓化合物（molding compound）或例如為型號GX-E4之ABF（Ajinomoto Build-up Film）、BCB（Benzocyclo-buthene）、SINR、PBO、甲基系矽膠、乙基系矽膠、環苯系矽膠或環氧樹脂等高分子樹脂。
如第1I圖所示，於該第一介電層16與金屬柱141上形成第二介電層171。
如第1J圖所示，於對應各該第一盲孔160之處移除部分該第二介電層171，以形成複數外露該第一端面141a的第二盲孔1710，且該第二盲孔1710之下部份之孔徑係小於該第一盲孔160之孔徑並設於該第一盲孔160之內。
如第1K圖所示，於該第二介電層171上形成線路層172，並於該第二盲孔1710中形成電性連接該線路層172與金屬柱141的導電盲孔173，且重複進行前述增層步驟，以構成增層結構17，該增層結構17係包括至少一第二介電層171、形成於該第二介電層171上的線路層172、與複數形成於該第二介電層171中之第二盲孔1710內且電性連接該線路層172的導電盲孔173，該增層結構17底層之各該導電盲孔173係接觸該第二盲孔1710而未接觸該第一盲孔160，且所接觸之第二盲孔1710之下部份之孔徑係小於該第一盲孔160之孔徑並設於該第一盲孔160之內。
如第1L圖所示，於該增層結構17上覆蓋例如乾膜的保護層18，並沿邊緣切除側表面的該第二子金屬層122，且移除該承載件10與離型層11。
如第1M圖所示，移除該保護層18與第一金屬層12。
如第1N圖所示，移除部分該蝕刻終止層13，以形成複數對應外露各該金屬柱141之部份第二端面141b的蝕刻終止層開孔130。
如第1O圖所示，於該蝕刻終止層開孔130所外露的金屬柱141之部份第二端面141b與該增層結構17頂層之外露之該線路層172上形成表面處理層19，至此即完成本發明之無核心封裝基板。
如第1P圖所示，於該增層結構17頂層之線路層172上的表面處理層19上接置半導體晶片20，而形成封裝結構。
要補充說明的是，以一般實際的製程而言，第10圖所示已完成之無核心封裝基板為由複數封裝基板單元(unit)所組成之整版面(panel)的狀態，復經切割即可得到分離之複數封裝基板單元，由於此非本發明之重點所在，故圖式僅以一封裝基板單元來呈現；第1P圖所示之封裝結構，可以是整版面之封裝結構，亦可以是經切割分離後之單元封裝結構。
第二實施例The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. At the same time, the terms "end", "top", "bottom", "upper", "lower", "side" and "one" are used in this manual for the convenience of description, not The scope of the present invention is to be construed as being limited to the scope of the invention.
1A to 1P are cross-sectional views showing a first embodiment of the coreless package substrate and the method of manufacturing the same according to the first embodiment of the present invention, wherein the first P diagram is an application example of the first embodiment.
As shown in FIG. 1A, a carrier member 10 is provided on which at least one surface is sequentially formed with a release layer 11 and a first sub-metal layer 121. The carrier member 10 includes a carrier board 100 and is formed on the carrier board 100. At least one surface of the metal foil 101.
As shown in FIG. 1B, a second sub-metal layer 122 of a material such as copper is formed on the first sub-metal layer 121, and the second sub-metal layer 122 is formed on the carrier 10 and the release layer 11 and On the side surface of the first sub-metal layer 121, the first sub-metal layer 121 and the second sub-metal layer 122 are collectively defined as the first metal layer 12.
As shown in FIG. 1C, an etch stop layer 13 is formed on the second sub-metal layer 122. The material of the etch stop layer 13 can be ABF (Ajinomoto Build-up Film), and the etch stop layer 13 is also insulated. One of the layers.
As shown in FIG. 1D, a second metal layer 14 is formed on the etch stop layer 13, and the second metal layer 14 is preferably a 100 micron thick copper foil.
As shown in FIG. 1E, a resist layer 15 is formed on the second metal layer 14, and the resist layer 15 has a plurality of resistive opening 150 for exposing the second metal layer 14.
As shown in FIG. 1F, the second metal layer 14 in the resist opening 150 is etched away to form a plurality of metal pillars 141. At this time, the etch stop layer 13 is not etched.
As shown in FIG. 1G, the resist layer 15 is removed, and the metal post 141 is exposed as the first end surface 141a covered by the resist layer 15.
As shown in FIG. 1H, a first dielectric layer 16 covering the metal pillars 141 is formed on the etch stop layer 13, and a portion of the first dielectric layer 16 is removed by laser to form a complex correspondence. The first blind via 160 of the first end surface 141a is exposed, wherein the first dielectric layer 16 is made of a molding compound or an ABF (Ajinomoto Build-up Film) such as the model GX-E4. Polymer resin such as BCB (Benzocyclo-buthene), SINR, PBO, methyl silicone, ethyl silicone, cyclophenyl silicone or epoxy resin.
As shown in FIG. 1I, a second dielectric layer 171 is formed on the first dielectric layer 16 and the metal pillars 141.
As shown in FIG. 1J, a portion of the second dielectric layer 171 is removed at a portion corresponding to each of the first blind vias 160 to form a plurality of second blind vias 1710 exposing the first end surface 141a, and the second blind is The aperture of the portion below the hole 1710 is smaller than the aperture of the first blind hole 160 and is disposed within the first blind hole 160.
As shown in FIG. 1K, a wiring layer 172 is formed on the second dielectric layer 171, and a conductive via 173 electrically connected to the wiring layer 172 and the metal pillar 141 is formed in the second blind via 1710, and is repeated. Performing the step of forming a layer to form a build-up structure 17 comprising at least a second dielectric layer 171, a circuit layer 172 formed on the second dielectric layer 171, and a plurality of layers formed thereon The second blind via 1710 of the second dielectric layer 171 is electrically connected to the conductive via 173 of the circuit layer 172. The conductive via 173 of the bottom layer of the buildup structure 17 contacts the second blind via 1710. The first blind via 160 is in contact with the aperture of the lower portion of the second blind via 1710 that is smaller than the aperture of the first blind via 160 and is disposed within the first blind via 160.
As shown in FIG. 1L, a protective layer 18 such as a dry film is covered on the build-up structure 17, and the second sub-metal layer 122 of the side surface is cut along the edge, and the carrier 10 and the release layer 11 are removed. .
The protective layer 18 and the first metal layer 12 are removed as shown in FIG. 1M.
As shown in FIG. 1N, a portion of the etch stop layer 13 is removed to form a plurality of etch stop layer openings 130 corresponding to portions of the second end surface 141b of each of the metal pillars 141.
As shown in FIG. 10, a surface treatment layer 19 is formed on the second end surface 141b of the metal pillar 141 exposed by the etch stop layer opening 130 and the wiring layer 172 exposed on the top layer of the buildup structure 17. That is, the coreless package substrate of the present invention is completed.
As shown in FIG. 1P, the semiconductor wafer 20 is attached to the surface treatment layer 19 on the wiring layer 172 on the top layer of the buildup structure 17, to form a package structure.
It should be added that, in the general practical process, the completed coreless package substrate shown in FIG. 10 is a state of a full-panel panel composed of a plurality of package substrate units, and the complex cut is A plurality of packaged substrate units can be obtained. Since this is not the focus of the present invention, the drawing is only presented by a package substrate unit; the package structure shown in FIG. 1P may be a package structure of a full-page surface, or may be The unit package structure after cutting and separating.
Second embodiment
第2A至2D圖所示者，係為本發明之無核心封裝基板及其製法之第二實施例的剖視圖。
本實施例基本上相同於前一實施例，其主要不同之處在於：該第一盲孔160係與該增層結構17底層之第二介電層171之第二盲孔1710同時形成，且該增層結構17底層之各該導電盲孔173係具有與各該第二盲孔1710接觸之上部份與各該第一盲孔160接觸之下部份，且所接觸之第二盲孔1710之側壁係與所接觸之第一盲孔160之側壁相連接。在此僅說明與前一實施例有差異的步驟。
如第2A圖所示，係延續自第1G圖，於該蝕刻終止層13上形成包覆該等金屬柱141之第一介電層16。
2A to 2D are cross-sectional views showing a second embodiment of the coreless package substrate and the method of manufacturing the same according to the present invention.
The embodiment is substantially the same as the previous embodiment, and the main difference is that the first blind via 160 is formed simultaneously with the second blind via 1710 of the second dielectric layer 171 of the bottom layer of the build-up structure 17 , and Each of the conductive vias 173 of the bottom layer of the build-up structure 17 has a portion in contact with each of the second blind vias 1710 and a portion in contact with each of the first blind vias 160, and a second blind via which is in contact The sidewalls of 1710 are connected to the sidewalls of the first blind via 160 that are in contact. Only the steps that differ from the previous embodiment will be described herein.
As shown in FIG. 2A, the first dielectric layer 16 covering the metal pillars 141 is formed on the etch stop layer 13 as shown in FIG.
如第2B圖所示，於該第一介電層16上形成第二介電層171。
As shown in FIG. 2B, a second dielectric layer 171 is formed on the first dielectric layer 16.
如第2C圖所示，藉由雷射移除部分該第一介電層16與第二介電層171，以同時形成複數對應外露部分該金屬柱141之第一端面141a的第一盲孔160與第二盲孔1710，且該增層結構17底層之各該導電盲孔173係具有與各該第二盲孔1710接觸之上部份與各該第一盲孔160接觸之下部份，且所接觸之第二盲孔1710之側壁係與所接觸之第一盲孔160之側壁相連接。
如第2D圖所示，進行增層步驟，以於該第一介電層16上形成電性連接該金屬柱141之增層結構17。
As shown in FIG. 2C, a portion of the first dielectric layer 16 and the second dielectric layer 171 are removed by laser to simultaneously form a plurality of first blind holes corresponding to the first end surface 141a of the exposed portion of the metal pillar 141. And the second blind hole 1710, and each of the conductive blind holes 173 of the bottom layer of the build-up structure 17 has a portion in contact with each of the second blind holes 1710 and a portion in contact with each of the first blind holes 160 And the sidewall of the second blind hole 1710 that is in contact is connected to the sidewall of the first blind hole 160 that is in contact.
As shown in FIG. 2D, a build-up step is performed to form a build-up structure 17 electrically connected to the metal pillar 141 on the first dielectric layer 16.
參照第1N圖，本發明復提供一種無核心封裝基板，係包括：第一介電層16，係具有相對之第一表面16a與第二表面16b；複數金屬柱141，係埋設於該第一介電層16中， 並具有相對之第一端面141a與第二端面141b，且該第一介電層16之第一表面16a具有複數對應外露各該金屬柱141之部份第一端面141a的第一盲孔160，該第一介電層16之第二表面16b係完全外露各該金屬柱141之第二端面141b，該金屬柱141之高度係100微米（μm）以上；增層結構17，係設於該第一介電層16之第一表面16a上，該增層結構17係包括至少一第二介電層171、形成於該第二介電層171上的線路層172、與複數形成於該第二介電層171中之第二盲孔1710內且電性連接該線路層172的導電盲孔173，且該增層結構17底層之各該導電盲孔173係對應延伸至各該第一盲孔160內並電性連接各該金屬柱141之第一端面141a；以及絕緣保護層（蝕刻終止層13），係形成於該第一介電層16之第二表面16b上，且形成有複數對應外露各該金屬柱141之部份第二端面141b的絕緣保護層開孔（蝕刻終止層開孔130）。
Referring to FIG. 1N, the present invention further provides a coreless package substrate, comprising: a first dielectric layer 16 having a first surface 16a and a second surface 16b opposite thereto; and a plurality of metal pillars 141 embedded in the first The dielectric layer 16 has a first end surface 141a and a second end surface 141b opposite to each other, and the first surface 16a of the first dielectric layer 16 has a plurality of first end faces 141a corresponding to the portions of the metal pillars 141. The second blind hole 160, the second surface 16b of the first dielectric layer 16 completely exposes the second end surface 141b of each of the metal pillars 141, the height of the metal pillar 141 is 100 micrometers (μm) or more; the layered structure 17 Is provided on the first surface 16a of the first dielectric layer 16, the build-up structure 17 includes at least a second dielectric layer 171, a circuit layer 172 formed on the second dielectric layer 171, and A plurality of conductive vias 173 are formed in the second via hole 1710 of the second dielectric layer 171 and electrically connected to the conductive layer 172 of the circuit layer 172, and the conductive vias 173 of the bottom layer of the buildup structure 17 are correspondingly extended to Each of the first blind holes 160 is electrically connected to the first end surface 141a of each of the metal pillars 141; and insulation protection a layer (etching stop layer 13) is formed on the second surface 16b of the first dielectric layer 16, and is formed with a plurality of insulating protective layer openings corresponding to a portion of the second end surface 141b of each of the metal pillars 141 ( Etching stop layer opening 130).
於前所述之無核心封裝基板中，復包括表面處理層19，係形成於該絕緣保護層開孔（蝕刻終止層開孔130）所外露的金屬柱141之部份第二端面141b與該增層結構17頂層之外露之該線路層172上。
In the coreless package substrate, the surface treatment layer 19 is formed on a portion of the second end surface 141b of the metal pillar 141 exposed by the opening (the etch stop layer opening 130) of the insulating protective layer. The top layer of the build-up structure 17 is exposed on the circuit layer 172.
於本發明之無核心封裝基板中，該增層結構17底層之各該導電盲孔173係具有與各該第二盲孔1710接觸之上部份與各該第一盲孔160接觸之下部份，且所接觸之第二盲孔1710之側壁係與所接觸之第一盲孔160之側壁相連接，或者，該增層結構17底層之各該導電盲孔173係接觸該第二盲孔1710而未接觸該第一盲孔160，且所接觸之第二盲孔1710之下部份之孔徑係小於該第一盲孔160之孔徑並設於該第一盲孔160之內。
In the coreless package substrate of the present invention, each of the conductive vias 173 of the bottom layer of the build-up structure 17 has a portion in contact with each of the second blind vias 1710 and a portion in contact with each of the first blind vias 160. And the sidewall of the second blind via 1710 that is in contact with the sidewall of the first blind via 160 that is in contact with the contact, or the conductive via 173 of the bottom layer of the buildup structure 17 contacts the second blind via The first blind via 160 is not contacted, and the aperture of the lower portion of the second blind via 1710 is smaller than the aperture of the first blind via 160 and is disposed within the first blind via 160.
於本發明之無核心封裝基板中，由於該金屬柱141可能以蝕刻方式形成，故該金屬柱141之第一端面141a係可小於該金屬柱之第二端面141b，且該金屬柱141之連接該第一端面141a與第二端面141b之側壁係可為內凹之曲面。
In the coreless package substrate of the present invention, since the metal pillar 141 may be formed by etching, the first end surface 141a of the metal pillar 141 may be smaller than the second end surface 141b of the metal pillar, and the metal pillar 141 is connected. The sidewalls of the first end surface 141a and the second end surface 141b may be concave curved surfaces.
綜上所述，相較於習知技術，本發明係以例如ABF做為蝕刻終止層的材質，因而不需電鍍厚銅之步驟，進而解決習知技術之厚銅均勻性不佳、成本高、產率低及應力高等問題，使得本發明之無核心封裝基板具有整體良率較高、成本較低與抑制翹曲等優點。
In summary, compared with the prior art, the present invention uses, for example, ABF as the material of the etch stop layer, so that the step of plating thick copper is not required, thereby solving the problem of poor uniformity of copper and high cost of the prior art. The problem of low yield and high stress makes the coreless package substrate of the invention have the advantages of high overall yield, low cost and suppression of warpage.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
10．．．承載件10. . . Carrier
100．．．承載板100. . . Carrier board
101．．．金屬箔101. . . Metal foil
11．．．離型層11. . . Release layer
12．．．第一金屬層12. . . First metal layer
121．．．第一子金屬層121. . . First sub-metal layer
122．．．第二子金屬層122. . . Second sub-metal layer
13．．．蝕刻終止層13. . . Etch stop layer
130．．．蝕刻終止層開孔130. . . Etch stop layer opening
14．．．第二金屬層14. . . Second metal layer
141．．．金屬柱141. . . Metal column
141a．．．第一端面141a. . . First end face
141b．．．第二端面141b. . . Second end face
15．．．阻層15. . . Resistance layer
150．．．阻層開孔150. . . Resistive opening
16．．．第一介電層16. . . First dielectric layer
16a．．．第一表面16a. . . First surface
16b．．．第二表面16b. . . Second surface
160．．．第一盲孔160. . . First blind hole
17．．．增層結構17. . . Layered structure
171．．．第二介電層171. . . Second dielectric layer
1710．．．第二盲孔1710. . . Second blind hole
172．．．線路層172. . . Circuit layer
173．．．導電盲孔173. . . Conductive blind hole
18．．．保護層18. . . The protective layer
19．．．表面處理層19. . . Surface treatment layer
20．．．半導體晶片20. . . Semiconductor wafer
第1A至1P圖所示者係為本發明之無核心封裝基板及其製法之第一實施例的剖視圖，其中，第1P圖係第1O圖之應用例；以及1A to 1P are cross-sectional views showing a first embodiment of the coreless package substrate of the present invention and a method of manufacturing the same, wherein the first P diagram is an application example of FIG. 10;
第2A至2D圖所示者係為本發明之無核心封裝基板及其製法之第二實施例的剖視圖。2A to 2D are cross-sectional views showing a second embodiment of the coreless package substrate and the method of manufacturing the same according to the present invention.
13．．．蝕刻終止層13. . . Etch stop layer
130．．．蝕刻終止層開孔130. . . Etch stop layer opening
141．．．金屬柱141. . . Metal column
141a．．．第一端面141a. . . First end face
141b．．．第二端面141b. . . Second end face
16．．．第一介電層16. . . First dielectric layer
16a．．．第一表面16a. . . First surface
16b．．．第二表面16b. . . Second surface
160．．．第一盲孔160. . . First blind hole
17．．．增層結構17. . . Layered structure
171．．．第二介電層171. . . Second dielectric layer
1710．．．第二盲孔1710. . . Second blind hole
172．．．線路層172. . . Circuit layer
173．．．導電盲孔173. . . Conductive blind hole
Claims (11)
第一介電層，係具有相對之第一表面與第二表面；
複數金屬柱，係埋設於該第一介電層中，並具有相對之第一端面與第二端面，該第一介電層之第一表面具有複數對應外露各該金屬柱之部份第一端面的第一盲孔，且各該金屬柱之第二端面係完全外露於該第一介電層之第二表面，該金屬柱並具100微米以上之高度；
增層結構，係設於該第一介電層之第一表面上，該增層結構係包括至少一第二介電層、形成於該第二介電層上的線路層、複數形成於該第二介電層中的第二盲孔、與複數形成於該第二盲孔內且電性連接該線路層的導電盲孔，且該增層結構底層之各該導電盲孔係對應延伸至各該第一盲孔內，以電性連接各該金屬柱之第一端面；以及
絕緣保護層，係形成於該第一介電層之第二表面上，且形成有複數對應外露各該金屬柱之部份第二端面的絕緣保護層開孔。A coreless package substrate includes:
a first dielectric layer having opposite first and second surfaces;
a plurality of metal pillars embedded in the first dielectric layer and having opposite first and second end faces, the first surface of the first dielectric layer having a plurality of portions corresponding to the exposed portions of the metal pillars a first blind hole of the end surface, and the second end surface of each of the metal pillars is completely exposed on the second surface of the first dielectric layer, and the metal pillar has a height of 100 micrometers or more;
The build-up structure is disposed on the first surface of the first dielectric layer, the build-up structure includes at least one second dielectric layer, a circuit layer formed on the second dielectric layer, and a plurality of layers formed thereon a second blind hole in the second dielectric layer, and a plurality of conductive blind holes formed in the second blind hole and electrically connected to the circuit layer, and each of the conductive blind holes of the bottom layer of the build-up structure is extended to Each of the first blind holes is electrically connected to the first end surface of each of the metal pillars; and an insulating protective layer is formed on the second surface of the first dielectric layer, and a plurality of corresponding metal bodies are formed correspondingly An insulating protective layer of a portion of the second end of the column is opened.
提供一承載件，其至少一表面上依序形成有蝕刻終止層與第二金屬層；
於該第二金屬層上形成阻層，該阻層具有複數外露該第二金屬層的阻層開孔；
蝕刻移除該阻層開孔中的第二金屬層，而形成複數金屬柱；
移除該阻層，而外露該金屬柱原為該阻層所覆蓋之第一端面；
於該蝕刻終止層上形成包覆該等金屬柱之第一介電層；
於該第一介電層上形成增層結構，該增層結構係包括至少一第二介電層、形成於該第二介電層上的線路層、複數形成於該第二介電層中的第二盲孔、與複數形成於該第二盲孔內且電性連接該線路層的導電盲孔，且該第一介電層形成有對應外露各該金屬柱之部份第一端面的複數第一盲孔，且該增層結構底層之各該導電盲孔係對應延伸至各該第一盲孔內並電性連接各該金屬柱之第一端面；
移除該承載件；以及
移除部分該蝕刻終止層，以形成複數對應外露各該金屬柱之部份第二端面的蝕刻終止層開孔。A method for manufacturing a coreless package substrate includes:
Providing a carrier member having an etch stop layer and a second metal layer sequentially formed on at least one surface thereof;
Forming a resist layer on the second metal layer, the resist layer having a plurality of resist layer openings exposing the second metal layer;
Etching removes the second metal layer in the opening of the resist layer to form a plurality of metal pillars;
Removing the resist layer, and exposing the metal post to be the first end surface covered by the resist layer;
Forming a first dielectric layer covering the metal pillars on the etch stop layer;
Forming a build-up structure on the first dielectric layer, the build-up structure comprising at least one second dielectric layer, a circuit layer formed on the second dielectric layer, and a plurality of layers formed in the second dielectric layer a second blind via, and a plurality of conductive blind vias formed in the second blind via and electrically connected to the circuit layer, and the first dielectric layer is formed with a corresponding first end surface of each of the metal pillars a plurality of first blind holes, and each of the conductive blind holes of the bottom layer of the build-up structure extends into each of the first blind holes and electrically connects the first end faces of the metal posts;
Removing the carrier; and removing a portion of the etch stop layer to form a plurality of etch stop layer openings corresponding to portions of the second end surface of each of the metal posts.
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