TWI411362B - Coreless package substrate and manufacturing method thereof - Google Patents
Coreless package substrate and manufacturing method thereof Download PDFInfo
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- TWI411362B TWI411362B TW100128439A TW100128439A TWI411362B TW I411362 B TWI411362 B TW I411362B TW 100128439 A TW100128439 A TW 100128439A TW 100128439 A TW100128439 A TW 100128439A TW I411362 B TWI411362 B TW I411362B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
本發明係有關一種封裝基板及其製法，尤指一種無核心層之封裝基板及其製法。The invention relates to a package substrate and a preparation method thereof, in particular to a package substrate without a core layer and a preparation method thereof.
隨著電子產業的蓬勃發展，電子產品也逐漸朝向多功能與高性能的趨勢。為了滿足半導體封裝件的高整合度（integration）及微型化（miniaturization）的封裝需求，以供更多主、被動元件及線路的載接，半導體封裝基板亦逐漸由雙層電路板演變成多層電路板（multi-layer board），俾於有限的空間下運用層間連接技術（interlayer connection）以擴大半導體封裝基板上可供利用的線路佈局面積，並能配合高線路密度之積體電路（integrated circuit）的使用需求，且降低封裝基板的厚度，而能使封裝件達到輕薄短小及提高電性功能之目的。With the booming electronics industry, electronic products are gradually moving toward versatility and high performance. In order to meet the requirements of high integration and miniaturization of semiconductor packages for more active and passive components and lines, semiconductor package substrates have gradually evolved from two-layer boards to multilayer circuits. Multi-layer board, which uses an interlayer connection to expand the available layout area on a semiconductor package substrate in a limited space, and can be combined with a high line density integrated circuit. The use requirements, and reduce the thickness of the package substrate, can make the package to be light and thin, and improve the electrical function.
習知技術中，封裝基板係由一核心板及對稱形成於其兩側之線路增層結構所構成，因使用核心板將導致導電路徑之長度及整體結構之厚度增加，難以滿足電子產品功能不斷提昇與體積不斷縮小的需求，遂發展出無核心層（coreless）結構之封裝基板，而能縮短導電路徑之長度及降低整體結構之厚度以符合高頻化與微小化的趨勢。In the prior art, the package substrate is composed of a core plate and a line build-up structure symmetrically formed on both sides thereof. The use of the core plate will increase the length of the conductive path and the thickness of the overall structure, and it is difficult to meet the functions of the electronic product. The need for improvement and shrinkage of volume has led to the development of a package substrate having a coreless structure, which can shorten the length of the conductive path and reduce the thickness of the overall structure to meet the trend of high frequency and miniaturization.
請參閱第1A至1H圖，係為習知無核心層之封裝基板暨封裝結構及其製法之剖視圖。Please refer to FIGS. 1A to 1H for a cross-sectional view of a conventional non-core layer package substrate and package structure and a method for fabricating the same.
如第1A圖所示，準備一承載件10。As shown in Fig. 1A, a carrier 10 is prepared.
如第1B圖所示，於該承載件10上形成複數第一電性接觸墊11。As shown in FIG. 1B, a plurality of first electrical contact pads 11 are formed on the carrier 10.
如第1C圖所示，於該承載件10上形成覆蓋該等第一電性接觸墊11的第一介電層12。As shown in FIG. 1C, a first dielectric layer 12 covering the first electrical contact pads 11 is formed on the carrier 10.
如第1D圖所示，藉由雷射燒灼以於該第一介電層12中形成複數連通該第一電性接觸墊11的盲孔120，並於各該盲孔120中形成導電盲孔13。As shown in FIG. 1D, a plurality of blind vias 120 that communicate with the first electrical contact pads 11 are formed in the first dielectric layer 12 by laser cauterization, and conductive vias are formed in each of the blind vias 120. 13.
如第1E圖所示，於該第一介電層12上形成連接該導電盲孔13的第一線路層14。As shown in FIG. 1E, a first wiring layer 14 connecting the conductive vias 13 is formed on the first dielectric layer 12.
如第1F圖所示，於該第一介電層12與第一線路層14上形成包括至少一相互堆疊之第二介電層151與第二線路層152的線路增層結構15，且最外層之該第二線路層152復具有複數第二電性接觸墊152a。As shown in FIG. 1F, a line build-up structure 15 including at least one second dielectric layer 151 and a second circuit layer 152 stacked on each other is formed on the first dielectric layer 12 and the first circuit layer 14, and the most The second circuit layer 152 of the outer layer has a plurality of second electrical contact pads 152a.
如第1G圖所示，移除該承載件10與該第一電性接觸墊11的部分厚度，俾使該第一電性接觸墊11凹陷於該第一介電層12表面，至此即完成一無核心層之封裝基板。As shown in FIG. 1G, a portion of the thickness of the carrier 10 and the first electrical contact pad 11 is removed, and the first electrical contact pad 11 is recessed on the surface of the first dielectric layer 12, thereby completing A package substrate without a core layer.
如第1H圖所示，於該第二電性接觸墊152a上接置半導體晶片16，並於該第一電性接觸墊11上接置焊球17，至此即完成一無核心層之封裝結構。As shown in FIG. 1H, the semiconductor wafer 16 is mounted on the second electrical contact pad 152a, and the solder ball 17 is mounted on the first electrical contact pad 11, thereby completing a package structure without a core layer. .
惟，習知無核心層之封裝基板係利用導電盲孔連通電性接觸墊與第一線路層，因該導電盲孔與第一線路層的接觸面積較小，且並未共同被介電層所包覆，造成彼此結合強度較弱，而易導致該結合處斷裂；又雷射製備盲孔的精度較差，且多盲孔的設計需考量誤差容忍度問題，進而提高製程難度。However, the conventional non-core layer package substrate uses conductive blind vias to connect the electrical contact pads to the first circuit layer because the conductive blind vias have a small contact area with the first circuit layer and are not collectively dielectric layers. The coating is weak, and the bonding strength is weak, which is easy to cause the joint to break. The precision of the blind hole prepared by the laser is poor, and the design of the multi-blind hole needs to consider the error tolerance problem, thereby improving the difficulty of the process.
因此，如何克服習知技術中之種種問題，實已成目前亟欲解決的課題。Therefore, how to overcome various problems in the prior art has become a problem that is currently being solved.
鑑於上述習知技術之封裝基板之結構強度及盲孔精度較差的缺失，本發明揭露一種無核心層之封裝基板，係包括：第一介電層，係具有相對之第一表面與第二表面，且該第一表面開設有複數介電層開孔；第一線路層，係嵌埋於該第一介電層中，其中，該介電層開孔外露出部分該第一線路層；複數第一電性接觸墊，係形成於各該介電層開孔中的該第一線路層上；線路增層結構，係形成於該第一介電層的第二表面上；以及導電盲孔，係形成於該第一介電層中，且電性連接該線路增層結構與第一線路層。In view of the lack of structural strength and blind hole precision of the packaged substrate of the prior art, the present invention discloses a package substrate having no core layer, comprising: a first dielectric layer having opposite first and second surfaces And the first surface is provided with a plurality of dielectric layer openings; the first circuit layer is embedded in the first dielectric layer, wherein the dielectric layer opening exposes a portion of the first circuit layer; a first electrical contact pad formed on the first circuit layer in each of the dielectric layer openings; a line build-up structure formed on the second surface of the first dielectric layer; and a conductive blind hole Formed in the first dielectric layer and electrically connected to the line build-up structure and the first circuit layer.
本發明復揭露一種無核心層之封裝基板之製法，係包括：於一承載件上形成第一阻層，該第一阻層具有複數外露該承載件的阻層開孔；於各該阻層開孔中形成第一電性接觸墊；於該第一阻層與第一電性接觸墊上形成第二阻層，該第二阻層具有複數外露該第一電性接觸墊與第一阻層的阻層開口區；於該阻層開口區中形成電性連接該第一電性接觸墊的第一線路層；移除該第一阻層與第二阻層；於該承載件上形成覆蓋該第一電性接觸墊與第一線路層的第一介電層；於該第一介電層上形成線路增層結構，並於該第一介電層中形成電性連接該線路增層結構與第一線路層的導電盲孔；以及移除該承載件。The invention discloses a method for manufacturing a package substrate without a core layer, comprising: forming a first resist layer on a carrier, the first resist layer having a plurality of barrier openings exposing the carrier; Forming a first electrical contact pad in the opening; forming a second resist layer on the first resistive layer and the first electrical contact pad, the second resistive layer having a plurality of exposed first electrical contact pads and a first resistive layer a barrier layer opening region; forming a first circuit layer electrically connected to the first electrical contact pad in the barrier layer opening region; removing the first barrier layer and the second barrier layer; forming a cover on the carrier The first electrical contact pad and the first dielectric layer of the first circuit layer; forming a line build-up structure on the first dielectric layer, and electrically connecting the line build-up layer in the first dielectric layer a conductive blind hole of the structure and the first circuit layer; and removing the carrier.
由上可知，本發明的無核心層之封裝基板係直接以第一線路層連接第一電性接觸墊，而非使用導電盲孔來連接該第一電性接觸墊，因此可減少習知雷射形成盲孔時的誤差容忍度問題，且可縮短該第一線路層與第一電性接觸墊之間的導電路徑；再者，本發明係以第一介電層包覆該第一電性接觸墊與第一線路層，所以可加強結構的強度。It can be seen that the package substrate of the coreless layer of the present invention directly connects the first electrical contact pads with the first circuit layer instead of using the conductive blind holes to connect the first electrical contact pads, thereby reducing the conventional lightning The problem of error tolerance when forming a blind hole, and shortening the conductive path between the first circuit layer and the first electrical contact pad; further, the present invention covers the first power with the first dielectric layer The contact pads are in contact with the first circuit layer so that the strength of the structure can be enhanced.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper" and "one" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship is changed or adjusted. Substantially changing the technical content is also considered to be within the scope of the invention.
請參閱第2A至2K圖，係為本發明之無核心層之封裝基板暨封裝結構及其製法的剖視圖。Please refer to FIGS. 2A to 2K , which are cross-sectional views showing a package substrate and a package structure without a core layer of the present invention and a manufacturing method thereof.
如第2A圖所示，準備一承載件20。As shown in Fig. 2A, a carrier 20 is prepared.
如第2B圖所示，於該承載件20上形成第一阻層21，該第一阻層21具有複數外露該承載件20的阻層開孔210。As shown in FIG. 2B, a first resist layer 21 is formed on the carrier 20, and the first resist layer 21 has a plurality of resistive openings 210 exposing the carrier 20.
如第2C圖所示，於各該阻層開孔210中形成第一電性接觸墊22。As shown in FIG. 2C, a first electrical contact pad 22 is formed in each of the barrier layer openings 210.
如第2D圖所示，於該第一阻層21與第一電性接觸墊22上形成第二阻層23，該第二阻層23具有複數外露該第一電性接觸墊22與第一阻層21的阻層開口區230。As shown in FIG. 2D, a second resist layer 23 is formed on the first resistive layer 21 and the first electrical contact pad 22, and the second resistive layer 23 has a plurality of exposed first electrical contact pads 22 and a first The resistive opening region 230 of the resist layer 21.
如第2E圖所示，於該阻層開口區230中形成電性連接該第一電性接觸墊22的第一線路層24。As shown in FIG. 2E, a first wiring layer 24 electrically connected to the first electrical contact pad 22 is formed in the barrier opening region 230.
如第2F圖所示，移除該第一阻層21與第二阻層23。As shown in FIG. 2F, the first resist layer 21 and the second resist layer 23 are removed.
如第2G圖所示，於該承載件20上形成覆蓋該第一電性接觸墊22與第一線路層24的第一介電層25。As shown in FIG. 2G, a first dielectric layer 25 covering the first electrical contact pad 22 and the first wiring layer 24 is formed on the carrier 20.
如第2H與2I圖所示，於該第一介電層25上形成電性連接該第一線路層24的線路增層結構，具體而言，先於該第一介電層25上形成第二線路層26，並於該第一介電層25中形成連接該第一線路層24與第二線路層26的第一導電盲孔27，然後，於該第一介電層25與第二線路層26上形成增層結構28，該增層結構28包括至少一第二介電層281、形成於該第二介電層281上的第三線路層282、及複數形成於該第二介電層281中並電性連接該第二線路層26與第三線路層282的第二導電盲孔283，且最外層之該第三線路層282具有複數第二電性接觸墊284，該第一電性接觸墊22凸出於該第一介電層25表面。As shown in FIGS. 2H and 2I, a line build-up structure electrically connecting the first circuit layer 24 is formed on the first dielectric layer 25, specifically, a first layer is formed on the first dielectric layer 25. a second circuit layer 26, and a first conductive via hole 27 connecting the first circuit layer 24 and the second circuit layer 26 is formed in the first dielectric layer 25, and then the first dielectric layer 25 and the second layer A build-up structure 28 is formed on the circuit layer 26, the build-up structure 28 includes at least a second dielectric layer 281, a third circuit layer 282 formed on the second dielectric layer 281, and a plurality of layers formed on the second dielectric layer The second conductive layer 283 of the second circuit layer 26 and the third circuit layer 282 is electrically connected to the second circuit layer 282, and the third circuit layer 282 of the outermost layer has a plurality of second electrical contact pads 284. An electrical contact pad 22 protrudes from the surface of the first dielectric layer 25.
如第2J圖所示，以例如化學蝕刻之方式移除該承載件20，並移除該第一電性接觸墊22的部分厚度，俾使該第一電性接觸墊22凹陷於該第一介電層25表面。As shown in FIG. 2J, the carrier 20 is removed by, for example, chemical etching, and a portion of the thickness of the first electrical contact pad 22 is removed, so that the first electrical contact pad 22 is recessed in the first The surface of the dielectric layer 25.
或者，如第2J’圖所示，係第2J圖之另一實施態樣，其主要的不同點在於該第二電性接觸墊284係齊平於第二介電層281表面。Alternatively, as shown in Fig. 2J', in another embodiment of Fig. 2J, the main difference is that the second electrical contact pad 284 is flush with the surface of the second dielectric layer 281.
或者，如第2J”圖所示，係第2J圖之又一實施態樣，其主要的不同點在於該第二電性接觸墊284係凹陷於第二介電層281表面，且該第二介電層281具有對應外露各該第二電性接觸墊284的介電層開孔2810。Or, as shown in FIG. 2J, which is another embodiment of FIG. 2J, the main difference is that the second electrical contact pad 284 is recessed on the surface of the second dielectric layer 281, and the second The dielectric layer 281 has a dielectric layer opening 2810 corresponding to each of the second electrical contact pads 284.
如第2K、2K’與2K”圖所示，分別係延續自第2J、2J’與2J”圖，於該第二電性接觸墊284上接置半導體晶片29，並於該半導體晶片29與增層結構28之間形成封裝膠體30，且於各該第一電性接觸墊22上接置焊球31。As shown in the 2K, 2K', and 2K" diagrams, the second semiconductor contact pads 284 are connected to the semiconductor chip 29, and the semiconductor wafer 29 is connected to the second electrical contact pads 284. The encapsulant 30 is formed between the build-up structures 28, and the solder balls 31 are attached to the first electrical contact pads 22.
本發明復提供一種無核心層之封裝基板，係包括：第一介電層25，係具有相對之第一表面25a與第二表面25b，且該第一表面25a開設有複數介電層開孔250；第一線路層24，係嵌埋於該第一介電層25中，其中，該介電層開孔250外露出部分該第一線路層24；複數第一電性接觸墊22，係形成於各該介電層開孔250中的該第一線路層24上；線路增層結構，係形成於該第一介電層25的第二表面25b上；以及第一導電盲孔27，係形成於該第一介電層25中，且電性連接該線路增層結構與第一線路層24。The present invention further provides a package substrate having no core layer, comprising: a first dielectric layer 25 having opposite first surface 25a and second surface 25b, and the first surface 25a is provided with a plurality of dielectric layer openings The first circuit layer 24 is embedded in the first dielectric layer 25, wherein the dielectric layer opening 250 exposes a portion of the first circuit layer 24; the plurality of first electrical contact pads 22 are Formed on the first circuit layer 24 in each of the dielectric layer openings 250; a line build-up structure is formed on the second surface 25b of the first dielectric layer 25; and a first conductive blind via 27, The first dielectric layer 25 is formed in the first dielectric layer 25 and electrically connected to the line build-up structure and the first circuit layer 24.
於前述之封裝基板中，該線路增層結構係包括至少一相互堆疊之第二介電層281與第二線路層，且最外層之該第二線路層復具有複數第二電性接觸墊284。In the foregoing package substrate, the circuit build-up structure includes at least one second dielectric layer 281 and a second circuit layer stacked on each other, and the second circuit layer of the outermost layer has a plurality of second electrical contact pads 284. .
於本發明的封裝基板中，該第二電性接觸墊284係凸出於、齊平於或凹陷於最外層的第二介電層281表面。In the package substrate of the present invention, the second electrical contact pad 284 is convex, flush or recessed on the surface of the second dielectric layer 281 of the outermost layer.
所述之無核心層之封裝基板，該第一電性接觸墊22係凹陷於該第一介電層25表面。The package substrate having no core layer, the first electrical contact pad 22 is recessed on the surface of the first dielectric layer 25.
綜上所述，本發明的無核心層之封裝基板係以第一線路層直接連接第一電性接觸墊，而非使用導電盲孔來連接該第一電性接觸墊，因此可減少習知雷射形成盲孔時的誤差容忍度問題，且可縮短導電路徑；再者，本發明係以第一介電層包覆該第一電性接觸墊與第一線路層，所以可提高整體結構的強度。In summary, the core-free package substrate of the present invention directly connects the first electrical contact pads with the first circuit layer instead of using the conductive blind holes to connect the first electrical contact pads, thereby reducing the conventional knowledge. The error tolerance problem when the laser forms a blind hole, and the conductive path can be shortened; further, the present invention covers the first electrical contact pad and the first circuit layer with the first dielectric layer, so that the overall structure can be improved Strength of.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
10,20‧‧‧承載件10,20‧‧‧Carrier
11,22‧‧‧第一電性接觸墊11,22‧‧‧First electrical contact pads
12,25‧‧‧第一介電層12,25‧‧‧First dielectric layer
25a‧‧‧第一表面25a‧‧‧ first surface
25b‧‧‧第二表面25b‧‧‧second surface
120‧‧‧盲孔120‧‧‧Blind hole
13‧‧‧導電盲孔13‧‧‧ Conductive blind holes
14,24‧‧‧第一線路層14,24‧‧‧First line layer
15‧‧‧線路增層結構15‧‧‧Line layering structure
151,281‧‧‧第二介電層151,281‧‧‧Second dielectric layer
152,26‧‧‧第二線路層152,26‧‧‧second circuit layer
152a,284‧‧‧第二電性接觸墊152a, 284‧‧‧Second electrical contact pads
16,29‧‧‧半導體晶片16,29‧‧‧Semiconductor wafer
17,31‧‧‧焊球17,31‧‧‧ solder balls
21‧‧‧第一阻層21‧‧‧First resistance layer
210‧‧‧阻層開孔210‧‧‧Resistance opening
23‧‧‧第二阻層23‧‧‧Second resistance layer
230‧‧‧阻層開口區230‧‧‧resistive open area
27‧‧‧第一導電盲孔27‧‧‧First conductive blind hole
28‧‧‧增層結構28‧‧‧Additional structure
282‧‧‧第三線路層282‧‧‧ third circuit layer
283‧‧‧第二導電盲孔283‧‧‧Second conductive blind hole
250,2810‧‧‧介電層開孔250, 2810‧‧‧ Dielectric layer opening
30‧‧‧封裝膠體30‧‧‧Package colloid
第1A至1H圖係為習知無核心層之封裝基板暨封裝結構及其製法之剖視圖；以及1A to 1H are cross-sectional views of a conventional non-core layer package substrate and package structure and a method of manufacturing the same;
第2A至2K圖係為本發明之無核心層之封裝基板暨封裝結構及其製法的剖視圖，其中，第2J’與2J”圖係第2J圖之其他實施態樣，第2K’與2K”圖係第2K圖之其他實施態樣。2A to 2K are cross-sectional views showing a package substrate and a package structure of the coreless layer of the present invention, and a method of manufacturing the same, wherein the 2J' and 2J" diagrams are other embodiments of the 2Jth diagram, 2K' and 2K" The figure is another embodiment of Figure 2K.
22‧‧‧第一電性接觸墊22‧‧‧First electrical contact pads
24‧‧‧第一線路層24‧‧‧First line layer
25‧‧‧第一介電層25‧‧‧First dielectric layer
25a‧‧‧第一表面25a‧‧‧ first surface
25b‧‧‧第二表面25b‧‧‧second surface
250‧‧‧介電層開孔250‧‧‧Dielectric layer opening
26‧‧‧第二線路層26‧‧‧Second circuit layer
27‧‧‧第一導電盲孔27‧‧‧First conductive blind hole
28‧‧‧增層結構28‧‧‧Additional structure
281‧‧‧第二介電層281‧‧‧Second dielectric layer
282‧‧‧第三線路層282‧‧‧ third circuit layer
283‧‧‧第二導電盲孔283‧‧‧Second conductive blind hole
284‧‧‧第二電性接觸墊284‧‧‧Second electrical contact pads
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100128439A TWI411362B (en) | 2011-08-09 | 2011-08-09 | Coreless package substrate and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100128439A TWI411362B (en) | 2011-08-09 | 2011-08-09 | Coreless package substrate and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| TW201309124A TW201309124A (en) | 2013-02-16 |
| TWI411362B true TWI411362B (en) | 2013-10-01 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201041465A (en) * | 2009-05-06 | 2010-11-16 | Phoenix Prec Technology Corp | Method of fabricating package substrate |
| TW201108367A (en) * | 2009-08-18 | 2011-03-01 | Unimicron Technology Corp | Coreless package substrate and method of forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201041465A (en) * | 2009-05-06 | 2010-11-16 | Phoenix Prec Technology Corp | Method of fabricating package substrate |
| TW201108367A (en) * | 2009-08-18 | 2011-03-01 | Unimicron Technology Corp | Coreless package substrate and method of forming the same |
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