TWI483316B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI483316B
TWI483316B TW097131279A TW97131279A TWI483316B TW I483316 B TWI483316 B TW I483316B TW 097131279 A TW097131279 A TW 097131279A TW 97131279 A TW97131279 A TW 97131279A TW I483316 B TWI483316 B TW I483316B
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Taiwan
Prior art keywords
wiring
semiconductor substrate
forming layer
layer
electrically connected
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TW097131279A
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English (en)
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TW200933756A (en
Inventor
山崎舜平
湯川幹央
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半導體能源研究所股份有限公司
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Publication of TW200933756A publication Critical patent/TW200933756A/zh
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Description

半導體裝置及其製造方法
本發明係有關一種具有經薄化之半導體基板的半導體裝置以及此種半導體裝置之製造方法。本發明特別有關一種具有穿透過經薄化之半導體基板的佈線的半導體裝置以及此種半導體裝置之製造方法。
在今天的社會生活之各種各樣的場合中，進行著利用電腦網路的資訊處理，且距離可以享受經由電腦網路來處理資訊之方便性的普遍存在社會(ubiquitous society)的實現越來越近。“普遍存在”來自拉丁語，且其意為“到處存在”，其已經被使用而具有可以隨時隨地將利用電腦的資訊處理自然融入於生活環境中而不需要意識到電腦的存在的意義。
實際上，可以藉由被歸類為可攜式電話裝置的可攜式電子裝置而利用作為通訊機構的電話通訊或電視廣播，並且可以藉由利用諸如IC標籤或IC卡之具有半導體晶片的類紙式或者卡式媒體來代替條碼和磁卡以供識別用。
順帶一提，為了將設有積體電路的半導體晶片(在下文中，也被稱為“IC晶片”或者“LSI晶片”等)自然組入於存在於人類生活空間中的各種各樣的事物中，需要使半導體晶片變薄。例如，已知有如下產品，其中，使IC晶片變薄到3μm至15μm的厚度，使得具有天線線圈、電容器等的IC標籤被嵌入於即將黏貼於紙等之物體中(參照專利檔案1)。
此外，由於半導體製造技術的進步，大型積體電路(LSI)的集成已經增高，而且對於在一個矽晶片上集成多個功能的系統LSI的需求已經增加。近年來，研究開發出層疊多個LSI晶片的三維(3D)LSI，以便對系統的更高精密度或複雜度做好準備。因為在一個封裝組件內設置多個LSIs，所以三維(3D)LSI也被稱為多晶片封裝組件(MCP)。作為MCP的實例，有以重疊方式而安裝快閃記憶體和靜態隨機存取記憶體(RAM)於其中的疊層MCP。
在疊層MCPs中，已知堆疊多個LSI晶片且利用打線接合法來進行連接的一種疊層MCP(例如，參照專利檔案2、3)。此外，作為交替堆疊多個矽晶片且使它們彼此耦接的結構，已知形成垂直互連體(interconnector)(經由電極)以層疊多個LSI晶片的疊層MCP(例如，參照專利檔案4)。
[專利檔案1]日本專利申請公開第2002-049901號公報
[專利檔案2]日本專利申請公開第Heill-204720號公報
[專利檔案3]日本專利申請公開第2005-228930號公報
[專利檔案4]日本專利申請公開第Heill-261001號公報
為了使半導體晶片變薄，已經使用如下技術：藉由使設有積體電路的矽晶圓的背面受到化學機械拋光(CMP)處理以使晶圓變成薄的層。
理想上，IC晶片的薄化被實施到確保IC晶片的各個元件之操作所需要的厚度之程度。
此外，至於MCPs，在對設有LSI的矽晶圓的背面進行CMP處理而使晶圓變成薄的層之後，這樣的晶圓被堆疊而形成多層。因此，為了在與現有同等尺寸之內層疊多個LSI晶片，需要使矽晶圓的厚度據以減薄。因此，理想上，IC晶片的薄化被實施到確保LSI晶片的各個元件之操作所需要的厚度之程度。
然而，因為CMP是在供應研磨材料的同時將晶圓按壓在拋光布上的加工技術，所以晶圓可以藉由CMP而被加工到具有約10μm的厚度；然而，一直難以使如12英寸晶圓那樣的較大直徑晶圓做成具有小於1μm的厚度之薄層。
鑒於上述，本發明之目的在於提供使諸如IC晶片和LSI晶片之半導體晶片做成更薄的技術。
此外，本發明之另一目的在於提供一種在以MCPs為典型的三維半導體積體電路中藉由使LSI晶片進一步薄化和層疊而可以提高LSI晶片之封裝(packing)密度的技術。
本發明之一樣態為：以離子來照射其表面上係設置有元件形成層且嵌入有電連接到元件形成層的第一佈線的半導體基板的背面來形成脆化層；沿著脆化層分離半導體基板的一部分以形成具有元件形成層以及第一佈線的半導體基板，且同時使第一佈線的一部分暴露出；層疊具有元件形成層以及第一佈線的半導體基板和設置有第二佈線的基板；以及使元件形成層和第二佈線電連接。
本發明之一樣態為一種半導體裝置，其包括：表面上設置有元件形成層的第一半導體基板；電連接到元件形成層且穿透過第一半導體基板的第一佈線；提供給第二基板的第二佈線。此外，第一佈線和第二佈線被電連接。
本發明之一樣態為一種半導體裝置，其包括：表面上設置有元件形成層的第一半導體基板；電連接到元件形成層且穿透過第一半導體基板的第一佈線；提供給第二基板的第二佈線。此外，第一佈線和第二佈線係經由藉由電鍍處理所形成的導電膜而被電連接。
本發明之一樣態為：藉由對其表面上係設置有元件形成層且嵌入有電連接到元件形成層的佈線的半導體基板的背面實施離子照射來形成脆化層，且沿著脆化層分離半導體基板的一部分以形成元件形成層以及具有佈線的半導體基板；因而，堆疊如此之元件形成層和半導體基板以形成多晶片。
藉由CMP等而對設有積體電路的半導體基板進行拋光，且藉由在半導體基板中形成脆化層，並分離半導體基板的一部分，以使半導體基板做成為薄的膜；因而，可以取得具有比以往更薄之諸如IC晶片的半導體晶片。
此外，藉由CMP等而對設有諸如LSI之積體電路的半導體基板進行拋光，且藉由在半導體基板中形成脆化層，並分離半導體基板的一部分，以使半導體基板做成為薄的膜，因而可以取得比以往更薄之諸如LSI晶片的半導體晶片。這種經薄化的LSI晶片被層疊，並經由穿透過半導體基板的佈線而被電連接；因而，可以取得具有改善之封裝密度的三維半導體積體電路。
下面，將參照附圖來說明本發明的實施例模式。注意，本發明並不局限於以下說明，且所屬技術領域的普通技術人員可以很容易地理解一個事實，就是其實施例模式和詳細內容在不違離本發明的精神及其範圍下可以被改變及修正為各種各樣的形式。因此，本發明不應該被解釋為其建構僅限定在以下所示的實施例模式所記載的內容中。在以下說明的本發明的結構中，在不同的附圖中共同使用表示相同部分的附圖標記。
[實施例模式1]
在本實施例模式中，參照附圖來說明諸如IC晶片或LSI晶片之半導體晶片，其具有一結構，該結構係藉由在使設置有元件形成層以及貫穿佈線的半導體基板做成薄的膜之後，分離該半導體基板的一部分所獲得到的。明確地說，將解說半導體晶片以及其製造方法，該半導體晶片具有一結構，該結構係藉由在使設置有元件形成層以及貫穿佈線的半導體基板做成薄的膜之後，分離該半導體基板的一部分，且藉以使貫穿佈線暴露出所獲得到的。
首先，在半導體基板100的表面之上設置元件形成層101、貫穿佈線102以及支撐基板110(參照圖1A)。
作為半導體基板100，可以使用矽、鍺等之單晶半導體基板或者矽、鍺等之多晶半導體基板。除此之外，還可以使用由諸如砷化鎵、磷化銦等化合物半導體所形成的單晶半導體基板或者多晶半導體基板作為半導體基板100。此外，作為半導體基板100，也可以使用具有晶格畸變的矽、在矽中添加有鍺的鍺化矽等所形成的半導體基板。具有晶格畸變的矽可以藉由形成矽於具有大於矽之晶格常數(lattice constant)的鍺化矽或者氮化矽來予以形成。
元件形成層101包含諸如電晶體、二極體、或電容器之元件及電連接到該等元件的佈線，而該等元件構成諸如LSI之積體電路。在此，顯示出在元件形成層101上設置電晶體103a和電晶體103b的實例。注意，係設置在元件形成層101上的電晶體103a和電晶體103b可具有各種各樣的結構，而並不局限於某種結構。
貫穿佈線102與元件形成層101的佈線電連接，並且貫穿佈線102的一部分係嵌入在半導體基板100中。貫穿佈線102係以單層或疊層的方式來予以設置，其含有選自鋁(Al)、鎢(W)、鈦(Ti)、鉭(Ta)、鉬(Mo)、鎳(Ni)、鉑(Pt)、銅(Cu)、金(Au)、銀(Ag)中的元素或者含有這些元素的任一者做為其主要成分的合金材料或化合物材料。此外，貫穿佈線102也可以用作LSI晶片或IC晶片中的貫穿電極。
支撐基板110係設置在元件形成層101的上方(在半導體基板100的相反一側上，且具有元件形成層101介於其間)，並且可以使用玻璃基板、石英基板、塑膠基板等。此外，支撐基板也可以由丙烯酸、聚醯亞胺、環氧樹脂等所構成。注意，不一定需要設置支撐基板110；然而，較佳設置支撐基板110，使得當對半導體基板100進行薄化處理等時，支撐基板110用作保護層。
接著，去除半導體基板100的一部分以使半導體基板100做成薄的膜(參照圖1B)。圖1B例示使半導體基板100做成薄的膜(藉由去除由虛線所包圍的部分)而形成半導體基板120的情況。例如，使半導體基板100的背面(在設置有元件形成層101的表面之相反側上)受到研磨處理、拋光處理或CMP處理，使得半導體基板100能夠被做成薄的膜。
在此，使半導體基板100變薄到不使貫穿佈線102暴露出的程度。較佳的是，使半導體基板120變薄到大於50nm且小於1000nm的厚度。
接著，如箭頭所示，以藉由電場而被加速的離子107來照射半導體基板120的背面(在設置有元件形成層101的表面之相反側上)，且在離半導體基板120的正面(設置有元件形成層101的表面)預定深度的區域中形成脆化層105(參照圖1C)。脆化層105係較佳使用離子摻雜法或離子植入法來予以形成。注意，離子植入法是指僅以具有藉由質量分離法所獲得到之比質量的離子來照射物體的技術，而離子摻雜法是指以藉由電場所加速之離子來照射物體而不進行質量分離的技術。能夠以導入離子時的加速電壓以及離子劑量來控制形成脆化層105的位置，並且脆化層105係形成在約為離子的平均穿透深度的深度處之區域中。注意，在本說明書中，“導入”離子是指以經加速之離子來照射半導體基板，而讓構成離子的元素包含在物體中的意思。脆化層105係設置在如下位置：即當沿著脆化層105來分離半導體基板120之時，使貫穿佈線102暴露出的位置。較佳的是，如下位置：當將離半導體基板120的表面的深度假設為L時，脆化層105係設置在使得L為大於50nm且小於1000nm、更佳為100nm到500nm的位置處。
作為離子107，可以使用氫離子、氦等之稀有氣體離子或者氟、氯等之鹵素離子。較佳的是，以一種離子或者由各自包含相同原子之不同質量的多種離子來照射半導體基板120：對選自氫、稀有氣體或鹵素中的源氣體等進行離子體激發來產生的。在實施以氫離子照射的情況下，在包含H+ 離子、H2 + 離子、以及H3 + 離子的同時，使H3 + 離子的比例做成比H+ 離子以及H2 + 離子高；因而，可以提高離子導入效率，並且可以縮短照射時間。
接著，利用脆化層105，半導體基板120被分成半導體基板120a和半導體基板120b(參照圖2A)。在此，進行熱處理，以便沿著脆化層105而將半導體基板120分成半導體基板120a和半導體基板120b。例如，熱處理係進行於範圍從300℃到550℃的溫度時；因而，使形成在脆化層105中的微小空洞的體積改變，並且半導體基板120沿著脆化層105而***，以便形成薄的半導體基板120a。注意，在本說明書中，“***”意指為了形成設置有元件形成層101的半導體基板120a而使半導體基板120b沿著脆化層105而分離。
注意，也可以在使半導體基板120分成半導體基板120a和半導體基板120b之前，在半導體基板120的背面側上設置支撐基板。當即將被分離的半導體基板120b是薄的情況下，可以設置支撐基板而和半導體基板120的背面相接觸，以便可以很容易地進行半導體基板120的分離。
經由上述步驟，可以取得具有如下結構之諸如IC晶片或LSI晶片的半導體晶片：即，貫穿佈線102穿透設置有元件形成層101的半導體基板120a且暴露出(參照圖2B)。
一般來說，當利用研磨處理、拋光處理或CMP處理來使基板變薄時，難以精確地控制該薄化，使得膜的厚度易於不規則，而且對能夠使基板做到多薄會有限制。然而，如本實施例模式所示，在使基板做成薄的膜之後，利用藉由離子的照射所形成的脆化層來進一步使半導體基板分離；因而，可以使基板的厚度相較於只進行研磨處理、拋光處理或CMP處理的情況係薄的。
[實施例模式2]
在本實施例模式中，將參照附圖來說明上述實施例模式1中所示之具有設置有貫穿佈線的IC晶片的半導體裝置。明確地說，將示出設置IC晶片於設有佈線的基板上，使得IC晶片的貫穿佈線係電連接到該佈線的情況。
在圖3A所示的半導體裝置中，上述實施例模式1中所示的IC晶片2130係藉由黏結而被設置在設置有佈線2152的內插板(interposer)2150上。在此，設置在多個IC晶片2130a至2130d中的元件形成層101與佈線2152係互相電連接。元件形成層101和佈線2152之間的連接係藉由使設置在IC晶片2130a至2130d各者中的貫穿佈線102與連接到佈線2152的連接端子2151電連接來予以做成(參照圖3B)。
此外，將參照圖4A和4B來說明經由導電材料來電連接貫穿佈線102和連接端子2151之情況的一個例子。
首先，在暴露出的貫穿佈線102上設置導電材料2126(參照圖4A)。導電材料2126可以藉由液滴噴射法、絲網印刷法等，透過選擇性地形成諸如銀膏、銅膏或焊料之材料來予以設置。
接著，使連接端子2151黏結到形成在貫穿佈線102上的導電材料2126，以使貫穿佈線102與連接端子2151電連接(參照圖4B)。藉由設置導電材料2126，可以減少貫穿佈線102和連接端子2151之間的連接不良。
注意，雖然圖4A和4B例示出在貫穿佈線102上設置導電材料2126的實例，但是也可以在連接端子2151上設置導電材料2126之後，藉由將貫穿佈線102黏結到導電材料2126，以使貫穿佈線102與連接端子2151互相電連接。
將參照圖5A和5B來說明貫穿佈線和連接端子之間的電連接的其他實例。圖5A和5B例示出利用電鍍處理而使貫穿佈線102與連接端子2151電連接的情況。
首先，將具有貫穿佈線102的IC晶片和具有連接端子2151的插板2150以保持間隔(間隙)的方式層疊(參照圖5A)。在此，利用球狀隔離物2125而在IC晶片和插板2150之間形成間隙2124。
設置間隙2124以使得即將在稍後進行的電鍍處理中，至少電鍍液可以進入於其中。此外，為了確保間隙2124，較佳以諸如密封材料之黏合樹脂來使IC晶片和插板2150互相黏結。注意，雖然在此使用球狀隔離物來形成間隙；但是，只要可以在IC晶片和插板2150之間形成間隙，就可以使用任何材料而不局限於球狀隔離物。
作為內插板2150，可以使用諸如有機聚合物或無機聚合物、陶瓷基板、玻璃基板、礬土(氧化鋁)基板、氮化鋁基板、金屬基板等材料。
此外，雖然圖5A例示出在互相重疊的貫穿佈線102和連接端子2151之間也設置間隔的情況；但是，也可以以彼此接觸的方式來設置貫穿佈線102和連接端子2151。
接著，藉由利用電鍍處理而在露出的貫穿佈線102和連接端子2151之間沉積以形成導電膜，藉以形成導電膜2127。進行電鍍處理直到導電膜2127和連接端子2151係經由貫穿佈線102而被電連接為止(參照圖5B)。電鍍處理可以利用銅(Cu)、鎳(Ni)、金(Au)、鉑(Pt)、銀(Ag)等來予以進行。利用電鍍處理而使貫穿佈線102和連接端子2151連接，因此，可以減少連接不良。
此外，將參照圖6來說明IC晶片封裝的一個結構例子。
圖6例示出將IC晶片2130安裝到底座2154並且設置散熱器2155以提高散熱效果的結構。設置散熱器2155以便覆蓋IC晶片2130，藉以除了防止IC晶片2130的加熱之外，還阻隔電磁波。此外，使貫穿佈線102的一部分與散熱薄片2153接觸，使得可以經由貫穿佈線102而將在IC晶片2130中所產生的熱排放到散熱器2155。因此，藉由有效率地散熱，可以提高IC晶片的可靠性。
IC晶片可以具有CPU、記憶體、網路處理電路、碟片處理電路、影像處理電路、音頻處理電路、電源電路、溫度感測器、濕度感測器、紅外線放射感測器等等的一個或多個功能。
如上所述，依據本實施例模式，藉由CMP等而使設有積體電路的半導體基板做成薄的膜，並且在半導體基板中形成脆化層，使得半導體基板的一部分被分離，以進一步使半導體基板變薄。因而，可以取得具有比以往更薄的IC晶片。
[實施例模式3]
在本實施例模式中，將參照附圖來說明具有LSI晶片的半導體裝置，其中，層疊有上述實施例模式1中所示的LSI晶片。
首先，準備第一LSI晶片(對應於圖2B所示的LSI晶片)和第二LSI晶片(對應於在圖1A中所示，沒有支撐基板110的LSI晶片)，該第一LSI晶片包含穿透設置有第一元件形成層101a的半導體基板120a且被暴露出的第一貫穿佈線102a，而第二LSI晶片包含係設置在半導體基板100之上的第二元件形成層101b以及第二貫穿佈線102b。此外，層疊第一LSI晶片和第二LSI晶片以形成疊層，以使第一貫穿佈線102a和第二貫穿佈線102b被電連接(參照圖7A)。
在此，使露出於第一半導體基板120a的背面側上的第一貫穿佈線102a經由在第二元件形成層101b的上方(在設置有半導體基板100的表面之相反側上)而與第二貫穿佈線102b電連接；因此，可以製造其中層疊有第一LSI晶片和第二LSI晶片的半導體裝置。
第一貫穿佈線102a和第二貫穿佈線102b係經由藉由形成清潔表面且進行大約在100℃到400℃的熱處理之表面活化接合而互相電連接。或者，也可以藉由形成清潔表面且在常溫下進行表面活化接合來使第一貫穿佈線102a和第二貫穿佈線102b互相電連接。第一貫穿佈線102a的表面係以當形成脆化層時所導入的氫來予以氫化，並且第二貫穿佈線102b的表面可以藉由電獎處理等而被氫化，使得該等表面幾乎不被氧化。在這種狀態下使第一貫穿佈線102a和第二貫穿佈線102b互相接觸，並且最好加熱於100℃到400℃；因此，氫被釋放出，而且可以形成接合。
作為另一方式，它們可以藉由使用各向異性導電薄膜(ACF)、各向異性導電膠(ACP)等之壓合(pressure bonding)而互相被電連接。或者，也可以使用諸如銀膏、銅膏或碳膏等的導電性黏合劑或焊料等以供連接用。
注意，在層疊第一LSI晶片和第二LSI晶片之後，藉由研磨處理、拋光處理或CMP處理來使半導體基板100做成薄的膜，疊層能夠被做成薄的膜(參照圖7B)。此外，除了研磨處理、拋光處理或CMP處理之外，對半導體基板100進行如實施例模式1中所示的分離處理，可以使疊層做成更薄。
此外，在藉由直接接觸而做成第一貫穿佈線102a和第二貫穿佈線102b之間的電連接之情況中，較佳使第一貫穿佈線102a和第二貫穿佈線102b彼此嚙合。例如，貫穿佈線的下側部分的寬度係小於貫穿佈線之上側部分的寬度，並且在貫穿佈線的頂面中設置凹部；因而，可以做成連接而使第一貫穿佈線102a和第二貫穿佈線102b彼此嚙合(參照圖11A和11B)。
因此，當做成連接而使貫穿佈線彼此嚙合時，可以防止連接不良。此外，可以縮短被層疊的第一LSI晶片和第二LSI晶片之間的間隙，因此可以使疊層做成薄的膜。注意，貫穿佈線的形狀並不局限於圖11A和11B中所示的結構。例如，可以在貫穿佈線的頂面處設置凸部，並且可以使該凸部穿透至另一貫穿佈線的底面，以做成電連接。
此外，將參照圖21A和21B來說明經由導電材料來使第一貫穿佈線102a和第二貫穿佈線102b互相電連接的情況的一個例子。
在此，首先，在露出的第一貫穿佈線102a上設置導電材料126(參照圖21A)。導電材料126可以藉由透過液滴噴射法、絲網印刷法以選擇性地形成諸如銀膏、銅膏、碳膏之材料或焊料等來予以設置。
接著，使第二貫穿佈線102b黏結到形成在第一貫穿佈線102b上的導電材料126，且藉以使第一貫穿佈線102a與第二貫穿佈線102b互相電連接(參照圖21B)。藉由設置導電材料126，可以減少第一貫穿佈線102a和第二貫穿佈線102b之間的連接不良。
注意，圖21A和21B例示出在第一貫穿佈線102a上設置導電材料126之情況的實例，替換地，也可以在第二貫穿佈線102b上設置導電材料126之後，使第一貫穿佈線102a黏結到導電材料126，以使第一貫穿佈線102a與第二貫穿佈線102b互相電連接。
此外，雖然圖7A和7B例示出製造具有其中層疊有兩個LSI晶片的疊層型LSI晶片的半導體裝置的情況，但是層疊在一起的LSI晶片之數目並不局限於兩個。
在層疊第一LSI晶片和第二LSI晶片之後(圖7A)，進行在實施例模式1中所示的步驟，以使第二LSI晶片的貫穿佈線暴露出，並層疊第三LSI晶片；因而，可以使三個LSI晶片層疊在一起。此外，當重複地進行這樣的步驟時，可以製造具有其中層疊有多個LSI晶片的結構的半導體裝置(參照圖8)。
圖8例示出包含具有n層(n≧2)的疊層型LSI晶片的半導體裝置。設置在第一個LSI晶片上的第一元件形成層1011至設置在第n個LSI晶片中的第n個元件形成層1019係以層疊的方式而被設置，並且該等元件形成層係經由第一貫穿佈線1021至第n貫穿佈線1029來予以電連接。
此外，可以在第一元件形成層1011至第n元件形成層1019上設置各自分別具有不同功能的電路。在此，顯示出如下情況：藉由設置記憶元件而使第二元件形成層1012用作為記憶電路，並且藉由設置CMOS電路而使第(n-1)個元件形成層1018用作為CPU(中央處理單元)。注意，在圖8中，第二元件形成層1012係與第二貫穿佈線1022電連接，並且第(n-1)元件形成層1018係與第(n-1)貫穿佈線1028電連接。
雖然圖8例示出在第一LSI晶片至第n個LSI晶片之各者上都設置貫穿佈線，使得第一元件形成層至第n元件形成層被電連接的情況，但是其並不局限於此，有一部分的元件形成層可以專門地僅彼此電連接。
例如，圖9例示出包含具有五層的疊層型LSI晶片的半導體裝置，其中設置在第一LSI晶片中的第一元件形成層1011至設置在第五LSI晶片中的第五元件形成層1015被層疊。在此，第二LSI晶片和第三LSI晶片係分別設置有第二貫穿佈線1022和第三貫穿佈線1023，使得第二元件形成層1012至第四元件形成層1014被電連接(參照圖9)。
注意，雖然在上述的說明中顯示出使露出於第一半導體基板120a的背面側上的第一貫穿佈線102a與露出於第二元件形成層101b的上方的第二貫穿佈線102b電連接的情況，但是其並不局限於此。例如，該層疊也可以具有使露出於半導體基板的背面側上的貫穿佈線彼此電連接的結構(參照圖10)。當做成這種連接時，即使在層疊多個LSI晶片的情況下，也可以應用多個組合；因而，可以增加設計自由度。
本實施例模式可以與實施例模式1中所示的結構或製造方法組合來予以實施。
[實施例模式4]
在本實施例模式中，將參照附圖來說明連接不同的LSI晶片之貫穿佈線的方法。明確地說，將說明利用電鍍處理來電連接貫穿佈線的情況。
首先，層疊具有第一貫穿佈線102a的第一LSI晶片和具有第二貫穿佈線102b的第二LSI晶片而具有間隔(間隙)於其間(參照圖22A)。在此，利用球狀隔離物125而在第一LSI晶片和第二LSI晶片之間形成間隙124。此外，較佳的是，層疊第一LSI晶片和第二LSI晶片以使第一貫穿佈線102a和第二貫穿佈線102b互相重疊。
設置間隙124以使在稍後即將進行的電鍍處理中，至少電鍍液可以進入於其中。此外，為了確保間隙124，最好以諸如密封材料之黏合樹脂來使第一LSI晶片和第二LSI晶片互相黏結。注意，雖然在此使用球狀隔離物來形成間隙，但是只要可以在第一LSI晶片和第二LSI晶片之間形成間隙，就能夠使用任何材料而不局限於球狀隔離物。
此外，雖然圖22A例示出其中也在互相重疊的第一貫穿佈線102a和第二實穿佈線102b之間設置間隔的情況，但是也可以以彼此接觸的方式來設置第一貫穿佈線102a和第二貫穿佈線102b。
接著，藉由透過電鍍處理而在露出的第一貫穿佈線102a和第二貫穿佈線102b之間沉積以形成導電膜，藉以形成導電膜127。實施電鍍處理直到導電膜127和第二貫穿佈線102b係經由第一貫穿佈線102a而互相電連接為止(參照圖22B)。電鍍處理可以利用銅(Cu)、鎳(Ni)、金(Au)、鉑(Pt)、銀(Ag)等來予以進行。
如本實施例模式中所示，當LSI晶片被層疊在一起時，利用電鍍處理而使不同的LSI晶片之間的貫穿佈線連接；因而，可以減少連接不良。
本實施例模式可以與實施例模式1至3中所示的結構或製造方法組合來予以實施。
[實施例模式5]
在本實施例模式中，將參照附圖來說明具有設置有貫穿佈線的LSI晶片的半導體裝置。明確地說，將顯示出設置半導體裝置而使得LSI晶片的貫穿佈線被電連接到設置有佈線的基板的情況。
在圖12A所示的半導體裝置中，上述實施例模式1中所示的LSI晶片130係藉由黏結而被設置於設有佈線152的基板150上。在此，設置在多個LSI晶片130a至130d中的元件形成層101與佈線152係互相電連接。元件形成層101和佈線152係經由各自被設置在LSI晶片130a至130d中的貫穿佈線102與連接到佈線152的連接端子151來予以電連接(參照圖12B)。
貫穿佈線102和連接端子151可以藉由直接接觸，或者藉由利用各向異性導電膜、各向異性導電膠等之壓合來予以電連接。或者，也可以藉由利用諸如銀膏、銅膏或碳膏之導電黏合劑；焊料等來做成連接。
此外，在圖12A所示的結構中，可以使用上述實施例模式3中所示之層疊有多個LSI晶片的層疊型LSI晶片作為LSI晶片130(參照圖13)。如上所述，將多個LSI晶片層疊而獲得到多層LSI晶片；因而，可以達成半導體裝置的更高的集成化和小型化。
多個LSI晶片各自可以用作為CPU、記憶體、網路處理電路、碟片處理電路、影像處理電路、音頻處理電路、電源電路、溫度感測器、濕度感測器、紅外線輻射感測器的其中一個或多個。
此外，當在基板150之上形成用作為天線的導電膜，並且使層疊的LSI晶片電連接到該天線時，層疊的LSI晶片可以被應用於能夠以非接觸的方式進行資料之發送及接收的半導體裝置(也被稱為RFID(射頻識別)標籤、ID標籤、IC標籤、無線標籤、或電子標籤)。
本實施例模式可以與實施例模式1、3及4中所示的結構或製造方法組合來予以實施。
[實施例模式6]
在本實施例模式中，將參照附圖來說明具有與上述實施例模式中所示之結構不同之具有層疊的LSI晶片的半導體裝置。明確地說，將說明在層疊LSI晶片之後設置貫穿佈線的情況。
首先，在半導體基板100的表面之上設置第一元件形成層101a以及支撐基板110(參照圖14A)。注意，在圖1A所示的結構中之貫穿佈線102係不包括在圖14A所示的結構中。
注意，雖然不一定需要設置支撐基板110，但是，因為當對半導體基板100進行薄化處理等時，支撐基板110用作為保護層，所以最好設置支撐基板110。
接著，去除半導體基板100的一部分以使半導體基板100更薄(參照圖14B)。圖14B例示出使半導體基板100更薄(藉由去除由虛線所包圍的區域)以形成半導體基板120的情況。例如，當對半導體基板100的背面進行研磨處理、拋光處理或CMP處理時，能夠使半導體基板100做成薄的膜。
在此，使半導體基板100更薄到用來分割第一元件形成層101a以及元件的埋入絕緣膜並未暴露出的程度。較佳的是，使半導體基板120變薄到1μm至30μm的厚度，更佳到5μm至15μm的厚度。
接著，如箭頭所示，以藉由電場所加速的離子107來照射半導體基板120的背面側，並且在離半導體基板120的表面預定深度的區域中形成脆化層105(參照圖14C)。能夠以導入離子時的加速電壓以及離子劑量來控制形成脆化層105的位置。脆化層105係設置在使元件形成層101側上的分離基板變薄到最薄的位置。較佳的是，當將離半導體基板120的表面的深度假設為L時，將脆化層105設置在使得L為大於10nm或小於1000nm、更佳為100nm到500nm的位置。
一般來說，當利用研磨處理、拋光處理或CMP處理來使基板變薄時，難以精確地控制該薄化，使得膜厚度容易不規則，並且對於基板能夠被做得多薄有限制。然而，如本實施例模式中所示，在基板做成薄的膜之後，利用藉由離子的照射所形成的脆化層而進一步分割半導體基板；因而，相較於只進行研磨處理、拋光處理或CMP處理的情況，可以使基板的厚度為薄。
接著，利用脆化層105而將半導體基板120分割成半導體基板120a和半導體基板120b(參照圖15A)。
注意，在將半導體基板120分割成半導體基板120a和半導體基板120b之前，可以在半導體基板120的背面側上設置支撐基板。當即將被分離的半導體基板120b係薄時，可以設置支撐基板而和半導體基板120的背面相接觸，使得半導體基板120可以很容易地被分割。
接著，將在圖15A中所取得的LSI晶片(在下文中，被稱為“第一LSI晶片”)與設有第二元件形成層101b的另一LSI晶片(在圖14A中，沒有支撐基板110的LSI晶片(在下文中，被稱為“第二LSI晶片”))層疊(參照圖15B)。可以用黏結樹脂等來使第一LSI晶片和第二LSI晶片互相貼合在一起。
接著，在去除支撐基板110之後，形成開口部111，且藉以使第一元件形成層101a的佈線以及第二元件形成層101b的佈線暴露出(參照圖16A)。在本實施例模式中，因為可以將第一LSI晶片的半導體基板120a設有小的厚度，所以能夠很容易地形成開口部111。
接著，在開口部111中形成貫穿佈線1032，且藉以使第一元件形成層101a和第二元件形成層101b互相電連接(參照圖16B)。
貫穿佈線1032係使用電鍍處理來予以形成。即使當開口部111由於LSI晶片的多層結構而係深時，也可以藉由電鍍處理來形成貫通佈線1032以填充開口部111的底部。注意，貫通佈線1032並不局限於電鍍處理，還可以藉由CVD法、濺射法、絲網印刷法、液滴噴射法等來予以形成。
經由上述步驟，可以製造包含具有兩層的層疊之LSI晶片的半導體裝置。
如本實施例模式中所示，在使基板做成薄的膜之後，利用藉由離子的照射所形成的脆化層來進一步分割半導體基板；因而，相較於只進行研磨處理、拋光處理或CMP處理的情況，可以使半導體基板的厚度係薄的。據此，即使在層疊多個LSI晶片的情況下，也可以抑制疊層的厚度的增加。此外，當疊層被形成到小的膜厚度時，可以很容易地形成開口部，而且可以使貫穿佈線的寬度係小的。
注意，當在形成貫穿佈線1032之前或之後使第二LSI晶片的半導體基板100做得更薄時，可以進一步使疊層的厚度更薄。
此外，雖然在上述說明中，在去除支撐基板110之後，從第一元件形成層101a的上方側形成開口部111而且設置貫穿佈線1032，但是其並不局限於此。例如，也可以從第二元件形成層101b的下方側形成開口部112而且可以設置貫穿佈線於其中。將參照圖17A和17B來說明該情況。
首先，藉由同樣地進行直到且包含圖15B所示的步驟，以藉由接合來層疊第一LSI晶片和第二LSI晶片。接著，使第二LSI晶片的半導體基板100變薄(參照圖17A)。此薄化可以藉由研磨處理、拋光處理或CMP處理來予以進行。此外，在進行研磨處理、拋光處理或CMP處理之後，使用藉由離子的照射所形成的脆化層來進行分離，可以使第二LSI晶片的半導體基板更進一步做得更薄。
接著，從經薄化之半導體基板120a的背面形成開口部112，且藉以使第二元件形成層101b的佈線以及第一元件形成層101a的佈線暴露出(參照圖17B)。在圖17A中，除了研磨處理、拋光處理或CMP處理以外，還進行分離的步驟，使得第二LSI晶片的半導體基板能夠被設有薄的厚度；因而，可以很容易地形成開口部112。
接著，在開口部112中形成貫穿佈線1042，且藉以使第一元件形成層101a和第二元件形成層101b電連接(參照圖18)。
如上所述，可以從第二元件形成層101b的下方側形成開口部112藉以設置貫穿佈線1042。此外，當以從第二LSI晶片的半導體基板120a露出的方式而設置貫穿佈線1042時，還可以將其他LSI晶片或設置有佈線的基板層疊於其上。
此外，當LSI晶片係設有多層結構時，在將設置有貫穿佈線的LSI晶片和沒有設置貫穿佈線的LSI晶片層疊之後，如上所述，藉由設置貫穿佈線，設置在多個LSI晶片中的元件形成層可以被電連接。
例如，將沒有設置貫穿佈線的第一LSI晶片、沒有設置貫穿佈線的第二LSI晶片、設置有貫穿佈線1033的第三LSI晶片、及設置有貫穿佈線1034的第四LSI晶片依次層疊(參照圖19)。然後，在形成穿透第一LSI晶片的第一元件形成層1011和第二LSI晶片的第二元件形成層1012的開口部之後，在該開口部中形成貫穿佈線1052，且藉以使第一元件形成層1011至第四元件形成層1014能夠電連接(參照圖20)。注意，在此，雖然四個LSI晶片被層疊，但是，LSI晶片的數目並不局限於此。
本實施例模式可以與實施例模式1及3至5中所示的結構或製造方法相組合來予以實施。
本說明書係根據2007年8月24日在日本專利局受理的日本專利申請編號2007-218891和日本專利申請編號2007-219086，且其整個內容被併入於本說明書中當做參考資料。
100．．．半導體基板
101．．．元件形成層
101a．．．第一元件形成層
101b．．．第二元件形成層
102．．．貫穿佈線
102a．．．第一貫穿佈線
102b．．．第二貫穿佈線
103a．．．電晶體
103b．．．電晶體
105．．．脆化層
107．．．離子
110．．．支撐基板
111．．．開口部
112．．．開口部
120．．．半導體基板
120a．．．半導體基板
120b．．．半導體基板
124．．．間隙
125．．．隔離物
126．．．導電材料
127．．．導電膜
130．．．LSI晶片
130a．．．LSI晶片
130b．．．LSI晶片
130c．．．LSI晶片
130d．．．LSI晶片
150．．．基板
151．．．連接端子
152．．．佈線
1011．．．第一元件形成層
1012．．．第二元件形成層
1013．．．第三元件形成層
1014．．．第四元件形成層
1015．．．第五元件形成層
1018．．．第(n-1)元件形成層
1019．．．第n元件形成層
1021．．．第一貫穿佈線
1022．．．第二貫穿佈線
1023．．．第三貫穿佈線
1028．．．第(n-1)貫穿佈線
1029．．．第n貫穿佈線
1032．．．貫穿佈線
1033．．．貫穿佈線
1034．．．貫穿佈線
1042．．．貫穿佈線
1052．．．貫穿佈線
2124．．．間隙
2125．．．隔離物
2126．．．導電材料
2127．．．導電膜
2130．．．IC晶片
2130a．．．IC晶片
2130b．．．IC晶片
2130c．．．IC晶片
2130d．．．IC晶片
2150．．．內插板
2151．．．連接端子
2152．．．佈線
2153．．．散熱薄片
2154．．．底座
2155．．．散熱器
圖1A至1C例示本發明的半導體晶片的製造方法的一個例子；
圖2A和2B例示本發明的半導體晶片的製造方法的一個例子；
圖3A和3B例示本發明的IC晶片的一個例子；
圖4A和4B例示以貫穿佈線的電連接的一個例子；
圖5A和5B例示以貫穿佈線的電連接的一個例子；
圖6例示IC晶片封裝組件的一個結構例子；
圖7A和7B例示包含本發明的LSI晶片的半導體裝置的製造方法的一個例子；
圖8例示包含本發明的LSI晶片的半導體裝置的一個例子；
圖9例示包含本發明的LSI晶片的半導體裝置的一個例子；
圖10例示以貫穿佈線的電連接的一個例子；
圖11A和11B例示以貫穿佈線的電連接的一個例子；
圖12A和12B例示包含本發明的LSI晶片的半導體裝置的一個例子；
圖13例示包含本發明的LSI晶片的半導體裝置的一個例子；
圖14A至14C例示包含本發明的LSI晶片的半導體裝置的製造方法的一個例子；
圖15A和15B例示包含本發明的LSI晶片的半導體裝置的製造方法的一個例子；
圖16A和16B例示包含本發明的LSI晶片的半導體裝置的製造方法的一個例子；
圖17A和17B例示包含本發明的LSI晶片的半導體裝置的製造方法的一個例子；
圖18是例包含本發明的LSI晶片的半導體裝置的製造方法的一個例子；
圖19例示包含本發明的LSI晶片的半導體裝置的製造方法的一個例子；
圖20例示包含本發明的LSI晶片的半導體裝置的製造方法的一個例子；
圖21A和21B例示以貫穿佈線的電連接的一個例子；
圖22A和22B例示以貫穿佈線的電連接的一個例子。
101．．．元件形成層
102．．．貫穿佈線
110．．．支撐基板
2150．．．內插板
2151．．．連接端子
2152．．．佈線

Claims (15)

  1. 一種半導體裝置的製造方法，包括如下步驟：製備第一半導體基板，該第一半導體基板係設置有元件形成層於正面上及電連接至該元件形成層的第一佈線；製備第二基板，該第二基板係設置有第二佈線；以離子來照射該第一半導體基板的背面，以便在離該第一半導體基板的該正面之預定深度中形成脆化層；沿著該脆化層而使該第一半導體基板的一部分分離出，且同時使該第一佈線的一部分暴露出；層疊該第一半導體基板和該第二基板，而使得該第一佈線的該部分面對該第二佈線；以及以導電材料而使該元件形成層和該第二佈線電連接，以使該第一佈線的該部分和該第二佈線相接合。
  2. 一種半導體裝置的製造方法，包括如下步驟：製備第一半導體基板，該第一半導體基板係設置有第一元件形成層於正面上及電連接至該第一元件形成層的第一佈線；製備第二半導體基板，該第二半導體基板係設置有第二元件形成層及電連接至該第二元件形成層的第二佈線；以離子來照射該第一半導體基板的背面，以便在離該第一半導體基板的該正面之預定深度中形成脆化層，沿著該脆化層而使該第一半導體基板的一部分分離出，且同時使該第一佈線的一部分暴露出；層疊該第一半導體基板和該第二半導體基板，而使得 該第一佈線的該部分面對該第二佈線；以及以導電材料而使該第一元件形成層和該第二元件形成層電連接，以使該第一佈線的該部分和該第二佈線相接合。
  3. 如申請專利範圍第1或2項所述的半導體裝置的製造方法，其中，該導電材料係使用銀膏、銅膏或焊料來予以形成。
  4. 一種半導體裝置的製造方法，包括如下步驟：製備第一半導體基板，該第一半導體基板係設置有元件形成層於正面上及電連接至該元件形成層的第一佈線；製備第二基板，該第二基板係設置有第二佈線；以離子來照射該第一半導體基板的背面，以便在離該第一半導體基板的該正面之預定深度中形成脆化層；沿著該脆化層而使該第一半導體基板的一部分分離出，且同時使該第一佈線的一部分暴露出；層疊該第一半導體基板和該第二基板，而使得該第一佈線的該部分面對該第二佈線；以及藉由電鍍處理而形成導電膜在該第一佈線的該部分與該第二佈線之間，以使該元件形成層和該第二佈線電連接。
  5. 一種半導體裝置的製造方法，包括如下步驟：製備第一半導體基板，該第一半導體基板係設置有第一元件形成層於正面上及電連接至該第一元件形成層的第 一佈線；製備第二半導體基板，該第二半導體基板係設置有第二元件形成層及電連接至該第二元件形成層的第二佈線；以離子來照射該第一半導體基板的背面，以便在離該第一半導體基板的該正面之預定深度中形成脆化層；沿著該脆化層而使該第一半導體基板的一部分分離出，且同時使該第一佈線的一部分暴露出；層疊該第一半導體基板和該第二半導體基板，而使得該第一佈線的該部分面對該第二佈線；以及藉由電鍍處理而形成導電膜在該第一佈線的該部分與該第二佈線之間，以使該第一元件形成層和該第二元件形成層電連接。
  6. 如申請專利範圍第4或5項所述的半導體裝置的製造方法，其中，該電鍍處理係使用銅、鎳、金、或者鉑來予以進行。
  7. 一種半導體裝置的製造方法，包括如下步驟：製備第一半導體基板，該第一半導體基板係設置有第一元件形成層於正面上及電連接至該第一元件形成層的第一佈線；製備第二半導體基板，該第二半導體基板係設置有第二元件形成層於正面上及電連接至該第二元件形成層的第二佈線；以離子來照射該第一半導體基板的背面，以便在離該 第一半導體基板的該正面之預定深度中形成第一脆化層；沿著該第一脆化層而使該第一半導體基板的一部分分離出，且同時使該第一佈線的一部分暴露出；層疊該第一半導體基板和該第二半導體基板，而使得該第一佈線的該部分面對該第二佈線；使該第一佈線的該部分和該第二佈線電連接；以離子來照射該第二半導體基板的背面，以便在離該第二半導體基板的該正面之預定深度中形成第二脆化層；以及沿著該第二脆化層而使該第二半導體基板的一部分分離出。
  8. 如申請專利範圍第7項所述的半導體裝置的製造方法，其中，使該第一佈線的該部分嚙合於設置在該第二佈線中的凹部中，以使該第一佈線的該部分和該第二佈線電連接。
  9. 如申請專利範圍第7項所述的半導體裝置的製造方法，其中，將設置在該第二佈線上的凸部穿透至該第一佈線的該部分，以使該第一佈線的該部分和該第二佈線電連接。
  10. 如申請專利範圍第7項所述的半導體裝置的製造方法，其中，藉由進行100℃到400℃的熱處理，以使該第 一佈線的該部分和該第二佈線互相電連接。
  11. 一種半導體裝置的製造方法，包括如下步驟：製備第一半導體基板，該第一半導體基板係設置有第一元件形成層於正面上及電連接至該第一元件形成層的第一佈線；製備第二半導體基板，該第二半導體基板係設置有第二元件形成層於正面上及電連接至該第二元件形成層的第二佈線；以離子來照射該第一半導體基板的背面，以便在離該第一半導體基板的該正面之預定深度中形成第一脆化層；沿著該第一脆化層而使該第一半導體基板的一部分分離出，且同時使該第一佈線的一部分暴露出；以離子來照射該第二半導體基板的背面，以便在離該第二半導體基板的該正面之預定深度中形成第二脆化層；沿著該第二脆化層而使該第二半導體基板的一部分分離出，且同時使該第二佈線的一部分暴露出；層疊該第一半導體基板和該第二半導體基板，而使得該第一佈線的該部分面對該第二佈線；以及使該第一佈線的該部分和該第二佈線的該部分電連接。
  12. 如申請專利範圍第11項所述的半導體裝置的製造方法，其中，藉由進行100℃到400℃的熱處理，以使該第一佈線的該部分和該第二佈線的該部分互相電連接。
  13. 如申請專利範圍第1,2,4,5,7及11項中任一項所述的半導體裝置的製造方法，其中，該等離子為氫離子、鹵素離子、或者稀有氣體離子。
  14. 如申請專利範圍第1,2,4,5,7及11項中任一項所述的半導體裝置的製造方法，其中，該等離子包括H+ 離子、H2 + 離子、以及H3 + 離子，並且該等H3 + 離子的比例比該等H+ 離子及該等H2 + 離子的比例更高。
  15. 如申請專利範圍第1,2,4,5,7及11項中任一項所述的半導體裝置的製造方法，其中，在以離子來照射該第一半導體基板之前，先對該第一半導體基板的該背面進行研磨處理、拋光處理或CMP處理。
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Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5142831B2 (ja) * 2007-06-14 2013-02-13 株式会社半導体エネルギー研究所 半導体装置及びその作製方法
EP2096115A1 (en) * 2008-02-26 2009-09-02 Nestec S.A. Oligosaccharide ingredient
US7846772B2 (en) * 2008-06-23 2010-12-07 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US7868442B2 (en) * 2008-06-30 2011-01-11 Headway Technologies, Inc. Layered chip package and method of manufacturing same
JP5331427B2 (ja) 2008-09-29 2013-10-30 株式会社日立製作所 半導体装置
US8518822B2 (en) * 2009-03-25 2013-08-27 Stats Chippac Ltd. Integrated circuit packaging system with multi-stacked flip chips and method of manufacture thereof
US7960282B2 (en) 2009-05-21 2011-06-14 Globalfoundries Singapore Pte. Ltd. Method of manufacture an integrated circuit system with through silicon via
US20110168785A1 (en) * 2010-01-14 2011-07-14 Rfmarq, Inc. System and Method To Embed A Wireless Communication Device Into Semiconductor Packages
US8541887B2 (en) 2010-09-03 2013-09-24 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
WO2012061304A1 (en) * 2010-11-02 2012-05-10 Georgia Tech Research Corporation Ultra-thin interposer assemblies with through vias
JP2012119532A (ja) 2010-12-01 2012-06-21 Seiko Epson Corp 薄膜トランジスタ形成用基板、半導体装置、電気装置
US8987728B2 (en) 2011-03-25 2015-03-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
CN105931967B (zh) 2011-04-27 2019-05-03 株式会社半导体能源研究所 半导体装置的制造方法
US8653639B2 (en) * 2011-06-09 2014-02-18 Headway Technologies, Inc. Layered chip package and method of manufacturing same
FR2979167B1 (fr) * 2011-08-19 2014-03-14 Soitec Silicon On Insulator Formation de structures semi-conductrices liées dans des processus d'intégration tridimensionnelle en utilisant des substrats récupérables
TWI640044B (zh) * 2011-08-09 2018-11-01 索尼半導體解決方案公司 在三度空間集積製程中使用可回收底材形成接合半導體構造之方法
US8617925B2 (en) 2011-08-09 2013-12-31 Soitec Methods of forming bonded semiconductor structures in 3D integration processes using recoverable substrates, and bonded semiconductor structures formed by such methods
FR2980037A1 (fr) * 2011-09-12 2013-03-15 St Microelectronics Crolles 2 Procede d'assemblage de circuits integres et structure integree tridimensionnelle correspondante
JP6157356B2 (ja) 2011-11-10 2017-07-05 シチズン時計株式会社 光集積デバイス
FR2990297A1 (fr) 2012-05-07 2013-11-08 St Microelectronics Crolles 2 Empilement de structures semi-conductrices et procede de fabrication correspondant
US9337182B2 (en) * 2012-12-28 2016-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method to integrate different function devices fabricated by different process technologies
KR102160786B1 (ko) * 2013-10-29 2020-09-28 삼성전자주식회사 반도체 패키지
JP2016012720A (ja) * 2014-06-03 2016-01-21 住友ベークライト株式会社 金属ベース実装基板および金属ベース実装基板実装部材
US10163871B2 (en) * 2015-10-02 2018-12-25 Qualcomm Incorporated Integrated device comprising embedded package on package (PoP) device
FR3044165B1 (fr) 2015-11-23 2018-03-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives Realisation d'interconnexions par recourbement d'elements conducteurs sous un dispositif microelectronique tel qu'une puce
US11373990B2 (en) 2016-02-29 2022-06-28 Semtech Corporation Semiconductor device and method of stacking semiconductor die for system-level ESD protection
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020017710A1 (en) * 2000-08-04 2002-02-14 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
US20040157410A1 (en) * 2003-01-16 2004-08-12 Seiko Epson Corporation Semiconductor device, semiconductor module, electronic equipment, method for manufacturing semiconductor device, and method for manufacturing semiconductor module

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5688719A (en) * 1996-06-07 1997-11-18 Taiwan Semiconductor Manufacturing Company Ltd Method for plasma hardening of patterned photoresist layers
US6191007B1 (en) * 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
JP3481444B2 (ja) * 1998-01-14 2003-12-22 シャープ株式会社 半導体装置及びその製造方法
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP3750444B2 (ja) * 1999-10-22 2006-03-01 セイコーエプソン株式会社 半導体装置の製造方法
JP2003007962A (ja) * 2001-06-19 2003-01-10 Toshiba Corp 半導体積層モジュール
FR2828762B1 (fr) * 2001-08-14 2003-12-05 Soitec Silicon On Insulator Procede d'obtention d'une couche mince d'un materiau semi-conducteur supportant au moins un composant et/ou circuit electronique
US7474002B2 (en) * 2001-10-30 2009-01-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having dielectric film having aperture portion
CN1505149A (zh) * 2002-12-02 2004-06-16 华泰电子股份有限公司 多芯片集成电路的立体封装装置
JP4554152B2 (ja) * 2002-12-19 2010-09-29 株式会社半導体エネルギー研究所 半導体チップの作製方法
JP4406300B2 (ja) * 2004-02-13 2010-01-27 株式会社東芝 半導体装置及びその製造方法
KR100618543B1 (ko) * 2004-06-15 2006-08-31 삼성전자주식회사 웨이퍼 레벨 적층 패키지용 칩 스케일 패키지 제조 방법
KR100570514B1 (ko) * 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100865365B1 (ko) * 2005-01-12 2008-10-24 샤프 가부시키가이샤 반도체 장치의 제조방법 및 반도체 장치
US7442631B2 (en) * 2005-02-10 2008-10-28 Semiconductor Energy Laboratory Co., Ltd. Doping method and method of manufacturing field effect transistor
US7863188B2 (en) * 2005-07-29 2011-01-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP4869664B2 (ja) * 2005-08-26 2012-02-08 本田技研工業株式会社 半導体装置の製造方法
TWI293499B (en) * 2006-01-25 2008-02-11 Advanced Semiconductor Eng Three dimensional package and method of making the same
CN101652867B (zh) * 2007-04-06 2012-08-08 株式会社半导体能源研究所 光伏器件及其制造方法
JP2009003436A (ja) * 2007-05-18 2009-01-08 Semiconductor Energy Lab Co Ltd 液晶表示装置
JP5142831B2 (ja) * 2007-06-14 2013-02-13 株式会社半導体エネルギー研究所 半導体装置及びその作製方法
US8102045B2 (en) * 2007-08-08 2012-01-24 Infineon Technologies Ag Integrated circuit with galvanically bonded heat sink

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020017710A1 (en) * 2000-08-04 2002-02-14 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
US20040157410A1 (en) * 2003-01-16 2004-08-12 Seiko Epson Corporation Semiconductor device, semiconductor module, electronic equipment, method for manufacturing semiconductor device, and method for manufacturing semiconductor module

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