TWI478245B

TWI478245B - Power mosfet with low rdson and fabrication method thereof

Info

Publication number: TWI478245B
Application number: TW100134815A
Authority: TW
Inventors: Yi Su; Daniel Ng; Anup Bhalla; Jun Lu
Original assignee: Alpha & Omega Semiconductor
Priority date: 2011-09-27
Filing date: 2011-09-27
Publication date: 2015-03-21
Also published as: TW201314787A

Description

一種低導通電阻的功率MOS電晶體裝置及其製備方法 Power MOS transistor device with low on-resistance and preparation method thereof

本發明一般涉及一種功率半導體裝置及其製備方法，更確切的說，本發明旨在提供一種減薄矽襯底來降低功率MOS電晶體導通電阻的方法及該方法所製備的功率MOS電晶體裝置。 The present invention generally relates to a power semiconductor device and a method of fabricating the same, and more particularly to a method for thinning a germanium substrate to reduce the on-resistance of a power MOS transistor and a power MOS transistor device prepared by the method .

對於功率電晶體而言，大的導通電阻RDSON將導致比較大的功耗，而我們所期望是盡可能的降低導通電阻從而減少裝置損耗。在一些導通電阻可以模擬計算的電晶體內，例如在0.8微米單元間隔的溝槽柵極MOS電晶體中，在10V電壓下一平方毫米裏的總導通電阻為4.1毫歐，而矽襯底的導通電阻就佔有2毫歐，襯底的導通電阻幾乎達到總通電阻的49%；如在4.5V電壓下一平方毫米裏的總導通電阻為5.7毫歐，矽襯底的導通電阻大致為2毫歐，襯底的導通電阻幾乎達到總通電阻的35%。由此可見，消除矽襯底可以在功率裝置中實現理想的低導通電阻。 For power transistors, the large on-resistance RDSON will result in relatively large power dissipation, and we expect to reduce the on-resistance as much as possible to reduce device losses. In some transistors whose on-resistance can be simulated, for example, in a 0.8 μm cell-spaced trench gate MOS transistor, the total on-resistance in a square millimeter at 10 V is 4.1 milliohms, while the 矽 substrate The on-resistance occupies 2 milliohms, and the on-resistance of the substrate is almost 49% of the total on-resistance; if the total on-resistance is 5.7 milliohms in the square millimeter of 4.5V, the on-resistance of the germanium substrate is approximately 2 In milliohms, the on-resistance of the substrate is almost 35% of the total on-resistance. It can be seen that eliminating the germanium substrate can achieve the desired low on-resistance in the power device.

矽襯底的刻蝕通常可以用標準工藝所採用的一些刻蝕方法。此外，電動化學刻蝕法同樣也可以對矽襯底進行刻蝕，主要原理是利用N型半導體基板和P型半導體基板的交界處所產生的PN結在反偏的條件下，對需要被刻蝕的半導體基板進行電化學腐蝕。例如附第1圖所示意出將結合在一起的N型半導體基板和P型半導體基板浸入刻蝕液中，在刻蝕液中裸露出需要被刻蝕的P型半導體基板，然後在N型半導體基板上連通陽極，而將陰極放置在刻蝕液中，同時刻蝕液中還可以放置參考電極作為參照，此刻蝕過程中，濕法刻蝕到達PN結時刻蝕停止，而且其刻蝕狀況可以通過測量電流ICE來監測。 The etching of the germanium substrate can usually be performed by standard processes. Some etching methods. In addition, the electro-chemical etching method can also etch the germanium substrate. The main principle is that the PN junction generated at the junction of the N-type semiconductor substrate and the P-type semiconductor substrate is reverse-biased and needs to be etched. The semiconductor substrate is subjected to electrochemical etching. For example, as shown in FIG. 1 , the N-type semiconductor substrate and the P-type semiconductor substrate combined together are immersed in an etching liquid, and a P-type semiconductor substrate to be etched is exposed in the etching liquid, and then the N-type semiconductor is exposed. The anode is connected to the substrate, and the cathode is placed in the etching liquid, and the reference electrode can also be placed in the etching liquid as a reference. During the etching process, the etching stops when the wet etching reaches the PN junction, and the etching condition can be Monitored by measuring current ICE.

專利號為US6111280的美國專利公開了一種在矽襯底中形成開口的氣體感測器，其目地是基於提高氣體感測器的氣體檢測靈敏度；專利號為US4618397的美國專利公開了一種在矽襯底中形成開口的壓力感測器，其主要是為了提高壓力感測器的壓力感受度；此外，專利號為US6927102 B2的美國專利公開了一種在矽襯底中形成開口的MOSFET裝置，主要是為了橫向降低功率MOSFET的寄生電容，此方法不會降低電阻。 U.S. Patent No. 6,111, 280, issued to U.S. Pat. A pressure sensor that forms an opening in the bottom, which is primarily intended to increase the pressure sensitivity of the pressure sensor; in addition, U.S. Patent No. 6,927,102 B2 discloses a MOSFET device for forming an opening in a ruthenium substrate, mainly In order to laterally reduce the parasitic capacitance of the power MOSFET, this method does not reduce the resistance.

鑒於上述問題，本發明提出了一種製備低導通電阻的功率MOS電晶體裝置的方法，在一襯底所支撐的外延層中形成有垂直MOS電晶體單元，外延層的底面構成垂直MOS電晶體單元的底部電極，且該襯底與外延層之間還設置有一層刻蝕阻擋層，該方法主要包括以下步驟：沉積一層底部鈍化層覆蓋在所述襯底的底面上；在底部鈍化層中形成一個或多個開口，利用底部鈍化層上的開口對襯底進行刻蝕，刻蝕停止在刻蝕阻擋層上，並通過該刻蝕過程形成襯底中的一個或多個凹槽；進一步對刻蝕阻擋層的暴露在凹槽中的區域進行刻蝕，刻蝕停止在外延層上，形成依次貫穿襯底和刻蝕阻擋層的一個或多個底部凹槽；於外延層的暴露在底部凹槽的頂部的區域內注入與外延層摻雜類型相同的摻雜物，形成外延層中位於底部凹槽的頂部的上方的重摻雜的底部電極接觸區；沉積一層金屬層覆蓋在所述襯底的底面上，該金屬層還同時覆蓋在所述底部凹槽的側壁和頂部上；其中，金屬層位於底部凹槽頂部的區域與所述底部電極接觸區保持接觸，並且所述金屬層用於構成功率MOS電晶體裝置的第一金屬電極。 In view of the above problems, the present invention provides a method of fabricating a low-on-resistance power MOS transistor device, supported by a substrate A vertical MOS transistor unit is formed in the extension layer, and a bottom surface of the epitaxial layer constitutes a bottom electrode of the vertical MOS transistor unit, and an etch barrier layer is further disposed between the substrate and the epitaxial layer. The method mainly includes the following steps: Depositing a bottom passivation layer overlying the bottom surface of the substrate; forming one or more openings in the bottom passivation layer, etching the substrate with an opening on the bottom passivation layer, and etching stops on the etch stop layer Forming one or more recesses in the substrate by the etching process; further etching the region of the etch barrier layer exposed in the recess, the etching stops on the epitaxial layer, forming a sequence through the substrate And etching one or more bottom recesses of the barrier layer; implanting a dopant of the same type as the epitaxial layer doping in a region of the epitaxial layer exposed at the top of the bottom trench to form a bottom recess in the epitaxial layer a heavily doped bottom electrode contact region above the top; a metal layer is deposited over the bottom surface of the substrate, the metal layer also overlying the sidewalls and top of the bottom trench; In the region of the metal layer and the bottom electrode contact region held in contact with the top of the bottom of the recess, and the metal layer is a metal electrode constituting a first MOS power transistor device.

上述的方法，對襯底進行刻蝕是利用濕法刻蝕或深反應摻雜物刻蝕實現的。上述的方法，對襯底進行濕法刻蝕所用到的刻蝕液為四甲基氫氧化銨溶液(TMAH)或氫氧化鉀溶液(KOH)或乙二胺鄰苯二酚溶液(EDP)。上述的方法，所述刻蝕阻擋層為一層掩埋二氧化矽層。上述的方法，對刻蝕阻擋層進行濕法刻蝕所用到的刻蝕液為緩衝氫氟酸溶液。上述的方法，所述襯底為輕摻雜N型襯底，所述外延層為輕摻雜N型外延層，所述垂直MOS電晶體單元為N型溝道的溝槽式MOS電晶體。上述的方法，所述襯底為輕摻雜P型襯底，所述外延層為輕摻雜P型外延層，所述垂直MOS電晶體單元為P型溝道的溝槽式MOS電晶體。 In the above method, etching the substrate is performed by wet etching or deep reactive dopant etching. In the above method, the etching solution used for wet etching the substrate is tetramethylammonium hydroxide solution (TMAH) or potassium hydroxide solution (KOH) or ethylenediamine catechol solution (EDP). In the above method, the etch barrier layer is a layer of buried ruthenium dioxide layer. In the above method, the etching solution used for wet etching the etch barrier layer is buffer hydrogen Fluoric acid solution. In the above method, the substrate is a lightly doped N-type substrate, the epitaxial layer is a lightly doped N-type epitaxial layer, and the vertical MOS transistor unit is an N-type channel trench MOS transistor. In the above method, the substrate is a lightly doped P-type substrate, the epitaxial layer is a lightly doped P-type epitaxial layer, and the vertical MOS transistor unit is a P-type trenched MOS transistor.

上述的方法，還包括以下步驟：在一基座的頂面上製備凸出於基座的頂面的數個金屬凸塊，金屬凸塊的數量與所述底部凹槽的數量保持一致，並且金屬凸塊的形貌與所述底部凹槽的槽體結構相適配；以及利用導電粘合材料將功率MOS電晶體裝置粘貼在基座的頂面，其中，任意一個金屬凸塊相對應的嵌入在一個底部凹槽中，並且導電粘合材料位於金屬層與基座之間，導電粘合材料還填充在底部凹槽的頂部與金屬凸塊之間及底部凹槽的側壁與金屬凸塊之間。 The above method further includes the steps of: preparing a plurality of metal bumps protruding from a top surface of the pedestal on a top surface of the susceptor, the number of the metal bumps being consistent with the number of the bottom recesses, and The topography of the metal bump is adapted to the groove structure of the bottom groove; and the power MOS transistor device is pasted on the top surface of the base by a conductive adhesive material, wherein any one of the metal bumps corresponds to Embedded in a bottom groove, and the conductive adhesive material is located between the metal layer and the base, and the conductive adhesive material is also filled between the top of the bottom groove and the metal bump and the sidewall of the bottom groove and the metal bump between.

上述的方法，在襯底所支撐的外延層中形成垂直MOS電晶體單元，包括以下步驟：在外延層中進行刻蝕形成多個第一類槽溝和至少一個第二類溝槽；在第一、第二類溝槽的側壁及底部覆蓋一層氧化物層並在第一、第二類槽溝內填充多晶矽；在外延層的位於第一類槽溝側壁周圍的區域中注入第一導電類型的摻雜物，形成從外延層的頂面向下延伸至外延層中的一個體區；以及在體區的位於第一類槽溝的較上部分的側壁周圍的區域中注入第二導電類型的摻雜物，形成從體區的頂面向下延伸至體區中的一個頂部電極摻雜區，使得任意一個第一類槽溝均依次貫穿所述頂部電極摻雜區和所述體區並延伸至位於體區下方的外延層中；沉積一絕緣介質層覆蓋在外延層上，且絕緣介質層同時還覆蓋在所述體區、頂部電極摻雜區以及第一類槽溝和第二類溝槽中所填充的多晶矽上；在所述絕緣介質層、頂部電極摻雜區、體區中進行刻蝕，形成依次貫穿緣介質層、頂部電極摻雜區並延伸至體區中的多個第一類通孔，以及形成至少一個貫穿緣介質層並接觸第二類溝槽中填充的多晶矽的第二類通孔；在第一類通孔的底部周圍的體區中注入重摻雜的第一導電類型的摻雜物，形成包圍第一類通孔的底部的接觸區；沉積一層勢壘材料層覆蓋在所述絕緣介質層上，勢壘材料層同時還覆蓋在第一、第二類通孔的底部及側壁上；在第一、第二類通孔中填充導電材料，並沉積一層金屬層覆蓋在位於絕緣介質層上方的勢壘材料層上，該金屬層同時還覆蓋在第一、第二類通孔中所填充的導電材料上並與之形成電接觸；對金屬層和位於絕緣介質層上方的勢壘材料層進行刻蝕，將金屬層分割成與第一類通孔中所填充的導電材料電性連接的第二金屬電極，金屬層還被分割成與第二類通孔中所填充的導電材料電性連接的第三金屬電極，覆蓋在絕緣介質層上方的勢壘材料層經刻蝕後的剩餘部分保留在第二、第三金屬電極的下方。 The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductive region in a region of the body region around a sidewall of the upper portion of the first type of trench a type of dopant forming a top electrode doped region extending from a top surface of the body region down into the body region such that any one of the first type of trenches sequentially penetrates the top electrode doped region and the body region And extending to the epitaxial layer below the body region; depositing an insulating dielectric layer overlying the epitaxial layer, and simultaneously covering the body region, the top electrode doped region, and the first type of trench and the second Etching on the polysilicon filled in the trench; etching in the dielectric dielectric layer, the top electrode doping region, and the body region to form a plurality of dielectric layers, a top electrode doped region, and a body region a first type of via hole, and a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; injecting heavily doped in the body region around the bottom of the first type of via hole a dopant of a first conductivity type forming a contact region surrounding a bottom of the first type of via hole; depositing a layer of barrier material overlying the dielectric dielectric layer, the barrier material layer simultaneously covering the first and the The bottom and side walls of the second type of through hole Filling the first and second types of via holes with a conductive material, and depositing a metal layer over the barrier material layer above the insulating dielectric layer, the metal layer also covering the first and second types of via holes And electrically contacting the filled conductive material; etching the metal layer and the barrier material layer above the insulating dielectric layer to divide the metal layer into electrical properties with the conductive material filled in the first type of via hole a second metal electrode connected, the metal layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, and the barrier material layer over the insulating dielectric layer is etched The remaining portion remains below the second and third metal electrodes.

上述的方法，在襯底所支撐的外延層中形成垂直MOS電晶體單元，包括以下步驟：在外延層中進行刻蝕形成多個第一類槽溝和至少一個第二類溝槽；在第一、第二類溝槽的側壁及底部覆蓋一層氧化物層並在第一、第二類槽溝內填充多晶矽；在外延層的位於第一類槽溝側壁周圍的區域中注入第一導電類型的摻雜物，形成從外延層的頂面向下延伸至外延層中的一個體區；以及在體區的位於每個第一類槽溝的較上部分的側壁周圍的區域中注入第二導電類型的摻雜物，形成體區中的多個頂部電極摻雜區，並且任意一個頂部電極摻雜區相對應的圍繞在一個第一類槽溝的較上部分的側壁的周圍，使得任意一個第一類槽溝均依次貫穿一個頂部電極摻雜區和所述體區並延伸至位於體區下方的外延層中；沉積一絕緣介質層覆蓋在外延層上，且絕緣介質層同時還覆蓋在所述體區、多個頂部電極摻雜區以及第一類槽溝和第二類溝槽中所填充的多晶矽上；在所述絕緣介質層中進行刻蝕，形成貫穿緣介質層的多個第一類通孔，以及形成至少一個貫穿緣介質層並接觸第二類溝槽中填充的多晶矽的第二類通孔；在體區的暴露在第一類通孔的底部的區域中注入重摻雜的第一導電類型的摻雜物，形成位於第一類通孔的底部的接觸區；沉積一層勢壘材料層覆蓋在所述絕緣介質層上，勢壘材料層同時還覆蓋在第一、第二類通孔的底部及側壁上；在第二類通孔中填充導電材料，並沉積一層金屬層覆蓋在位於絕緣介質層上方的勢壘材料層上且該金屬層的一部分還填充在第一類通孔中，該金屬層同時還覆蓋在第二類通孔中所填充的導電材料上並與之形成電接觸；對金屬層和位於絕緣介質層上方的勢壘材料層進行刻蝕，將金屬層分割成與第一類通孔中所填充的所述金屬層的一部分電性連接的第二金屬電極，金屬層還被分割成與第二類通孔中所填充的導電材料電性連接的第三金屬電極，覆蓋在絕緣介質層上方的勢壘材料層經刻蝕後的剩餘部分保留在第二、第三金屬電極的下方。 The above method forms a vertical in the epitaxial layer supported by the substrate The straight MOS transistor unit comprises the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; covering the sidewalls and the bottom of the first and second types of trenches with an oxidation layer And the first and second types of trenches are filled with polysilicon; the first conductivity type dopant is implanted in a region of the epitaxial layer around the sidewall of the first type of trench to form a lower extension from the top surface of the epitaxial layer And a body region in the epitaxial layer; and implanting a dopant of the second conductivity type in a region of the body region around the sidewall of the upper portion of each of the first type of trenches to form a plurality of top portions in the body region An electrode doped region, and any one of the top electrode doped regions is disposed around a sidewall of an upper portion of a first type of trench such that any one of the first type of trenches sequentially penetrates a top electrode doped region And extending the body region to an epitaxial layer located below the body region; depositing an insulating dielectric layer overlying the epitaxial layer, and simultaneously covering the body region, the plurality of top electrode doped regions, and the first a type of trench a polysilicon layer filled in the second type of trench; etching in the insulating dielectric layer to form a plurality of first type via holes penetrating the dielectric layer, and forming at least one through-edge dielectric layer and contacting the second type a second type of via hole filled with polysilicon in the trench; implanting a heavily doped first conductivity type dopant in a region of the body region exposed to the bottom of the first type of via hole to form a via hole in the first type a contact region at the bottom; a layer of barrier material is deposited over the insulating dielectric layer, and the barrier material layer also covers the bottom and sidewalls of the first and second types of vias; Filling the conductive material and depositing a layer of metal to cover the insulating layer a layer of barrier material above the layer and a portion of the layer of metal is also filled in the first type of via, which also covers and is in electrical contact with the conductive material filled in the via of the second type Etching the metal layer and the barrier material layer over the insulating dielectric layer to divide the metal layer into a second metal electrode electrically connected to a portion of the metal layer filled in the first type of via, metal The layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, and the remaining portion of the barrier material layer overlying the insulating dielectric layer is left in the second Below the three metal electrodes.

上述的方法，在沉積一層底部鈍化層覆蓋在襯底的底面上的同時，還沉積一層頂部鈍化層覆蓋在絕緣介質層上，頂部鈍化層同時將第二、第三金屬電極予以覆蓋；之後將覆蓋第二、第三金屬電極的部分頂部鈍化層移除，以在頂部鈍化層中將第二、第三金屬電極予以暴露。上述的方法，利用所注入的第一導電類型的摻雜物形成所述體區的同時，還在外延層中形成圍繞在體區周圍的保護環摻雜區，保護環摻雜區與體區的摻雜類型相同並與體區相互間隔開。上述的方法，利用注入的第二導電類型的摻雜物形成頂部電極摻雜區的同時，還在外延層中形成圍繞在保護環摻雜區周圍的通道阻斷摻雜區，通道阻斷摻雜區與頂部電極摻雜區的摻雜類型相同並與保護環摻雜區相互間隔開。 In the above method, while depositing a bottom passivation layer overlying the bottom surface of the substrate, a top passivation layer is deposited over the insulating dielectric layer, and the top passivation layer simultaneously covers the second and third metal electrodes; A portion of the top passivation layer covering the second and third metal electrodes is removed to expose the second and third metal electrodes in the top passivation layer. In the above method, the implanted first conductivity type dopant is used to form the body region, and a guard ring doping region surrounding the body region is formed in the epitaxial layer, and the guard ring doped region and the body region are formed. The doping types are the same and are spaced apart from the body regions. In the above method, while the implanted second conductivity type dopant is used to form the top electrode doped region, a channel blocking doping region surrounding the doped region of the guard ring is formed in the epitaxial layer, and the channel is blocked. The doping region has the same doping type as the top electrode doping region and is spaced apart from the guard ring doping region.

本發明還提供一種製備低導通電阻的功率MOS電晶體裝置的方法，在一襯底所支撐的外延層中形成有垂直MOS電晶體單元，其中，外延層的底面構成垂直MOS電晶體單元的底部電極，並且襯底與外延層的摻雜類型相反，該方法主要包括以下步驟：沉積一層底部鈍化層覆蓋在所述襯底的底面上；在底部鈍化層中形成一個或多個開口，並且襯底與外延層兩者的交界面所產生的PN結在反偏的條件下，利用底部鈍化層上的開口對襯底進行刻蝕，刻蝕停止在外延層上，並通過該刻蝕過程形成襯底中的一個或多個底部凹槽；於外延層的暴露在底部凹槽的頂部的區域內注入與外延層摻雜類型相同的摻雜物，形成外延層中位於底部凹槽的頂部的上方的重摻雜的底部電極接觸區；沉積一層金屬層覆蓋在所述襯底的底面上，該金屬層還同時覆蓋在所述底部凹槽的側壁和頂部上；其中，金屬層位於底部凹槽頂部的區域與所述底部電極接觸區保持接觸，並且所述金屬層用於構成所述功率MOS電晶體裝置的第一金屬電極。 The present invention also provides a method of fabricating a low-on-resistance power MOS transistor device in which a vertical MOS transistor unit is formed in an epitaxial layer supported by a substrate, wherein a bottom surface of the epitaxial layer constitutes a bottom portion of a vertical MOS transistor unit An electrode, and the substrate is opposite to the doping type of the epitaxial layer, the method mainly comprising the steps of: depositing a bottom passivation layer overlying the bottom surface of the substrate; forming one or more openings in the bottom passivation layer, and lining The PN junction generated at the interface between the bottom and the epitaxial layer is etched by the opening on the bottom passivation layer under the condition of reverse bias, and the etching stops on the epitaxial layer and is formed by the etching process. One or more bottom recesses in the substrate; implanting dopants of the same type as the epitaxial layer doping in a region of the epitaxial layer exposed at the top of the bottom trench to form a top of the bottom trench in the epitaxial layer a heavily doped bottom electrode contact region above; a metal layer is deposited over the bottom surface of the substrate, the metal layer also overlying the sidewall and top of the bottom trench Wherein the metal layer is located in a region of the bottom electrode contact region held in contact with the top of the bottom of the recess, and the metal layer is composed of a first metal electrode of the power MOS transistor device.

上述的方法，對襯底進行刻蝕是利用電化學刻蝕法實現的。上述的方法，對襯底進行電化學刻蝕法所用到的刻蝕液為四甲基氫氧化銨溶液(TMAH)或氫氧化鉀溶液(KOH)或乙二胺鄰苯二酚溶液(EDP)。上述的方法，所述襯底為輕摻雜P型襯底，所述外延層為輕摻雜N型外延層，所述垂直MOS電晶體單元為N型溝道的溝槽式MOS電晶體。上述的方法，所述襯底為輕摻雜N型襯底，所述外延層為輕摻雜P型外延層，所述垂直MOS電晶體單元為P型溝道的溝槽式MOS電晶體。 In the above method, etching the substrate is performed by electrochemical etching. In the above method, the etching solution used for the electrochemical etching of the substrate is tetramethylammonium hydroxide solution (TMAH) or potassium hydroxide solution (KOH) or ethylenediamine catechol solution (EDP). . In the above method, the substrate is a lightly doped P-type substrate, and the epitaxial layer is a lightly doped N-type epitaxial layer. The vertical MOS transistor unit is an N-channel trench MOS transistor. In the above method, the substrate is a lightly doped N-type substrate, the epitaxial layer is a lightly doped P-type epitaxial layer, and the vertical MOS transistor unit is a P-type trenched MOS transistor.

上述的方法，在襯底所支撐的外延層中形成垂直MOS電晶體單元，包括以下步驟：在外延層中進行刻蝕形成多個第一類槽溝和至少一個第二類溝槽；在第一、第二類溝槽的側壁及底部覆蓋一層氧化物層並在第一、第二類槽溝內填充多晶矽；在外延層的位於第一類槽溝側壁周圍的區域中注入第一導電類型的摻雜物，形成從外延層的頂面向下延伸至外延層中的一個體區；以及在體區的位於第一類槽溝的較上部分的側壁周圍的區域中注入第二導電類型的摻雜物，形成從體區的頂面向下延伸至體區中的一個頂部電極摻雜區，使得任意一個第一類槽溝均依次貫穿所述頂部電極摻雜區和所述體區並延伸至位於體區下方的外延層中；沉積一絕緣介質層覆蓋在外延層上，且絕緣介質層同時還覆蓋在所述體區、頂部電極摻雜區以及第一類槽溝和第二類溝槽中所填充的多晶矽上；在所述絕緣介質層、頂部電極摻雜區、體區中進行刻蝕，形成依次貫穿緣介質層、頂部電極摻雜區並延伸至體區中的多個第一類通孔，以及形成至少一個貫穿緣介質層並接觸第二類溝槽中填充的多晶矽的第二類通孔；在第一類通孔的底部周圍的體區中注入重摻雜的第一導電類型的摻雜物，形成包圍第一類通孔的底部的接觸區；沉積一層勢壘材料層覆蓋在所述絕緣介質層上，勢壘材料層同時還覆蓋在第一、第二類通孔的底部及側壁上；在第一、第二類通孔中填充導電材料，並沉積一層金屬層覆蓋在位於絕緣介質層上方的勢壘材料層上，該金屬層同時還覆蓋在第一、第二類通孔中所填充的導電材料上並與之形成電接觸；對金屬層和位於絕緣介質層上方的勢壘材料層進行刻蝕，將金屬層分割成與第一類通孔中所填充的導電材料電性連接的第二金屬電極，金屬層還被分割成與第二類通孔中所填充的導電材料電性連接的第三金屬電極，覆蓋在絕緣介質層上方的勢壘材料層經刻蝕後的剩餘部分保留在第二、第三金屬電極的下方。 The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductivity type in a region of the body region around the sidewall of the upper portion of the first type of trench a dopant extending from a top surface of the body region to a lower portion of the body region a top electrode doped region, such that any one of the first type of trenches sequentially penetrates the top electrode doped region and the body region and extends to an epitaxial layer located below the body region; depositing an insulating dielectric layer overlying the epitaxial layer a layer, and an insulating dielectric layer simultaneously covering the body region, the top electrode doped region, and the polysilicon filled in the first type of trench and the second type of trench; the insulating dielectric layer and the top electrode are doped Etching in the impurity region and the body region to form a plurality of first type via holes sequentially penetrating the edge dielectric layer, the top electrode doped region and extending into the body region, and forming at least one through-edge dielectric layer and contacting the second type a second type of via hole filled in the trench; implanting a heavily doped first conductivity type dopant in the body region around the bottom of the first type of via hole to form a bottom surrounding the first type of via hole a contact region; a layer of barrier material is deposited over the insulating dielectric layer, and the barrier material layer is also covered on the bottom and sidewalls of the first and second types of via holes; in the first and second types of via holes Fill the conductive material and deposit a layer of gold The layer is covered on the barrier material layer above the insulating dielectric layer, and the metal layer also covers and electrically contacts the conductive material filled in the first and second types of via holes; the metal layer and the insulating layer The barrier material layer above the dielectric layer is etched to divide the metal layer into a second metal electrode electrically connected to the conductive material filled in the first type of via hole, and the metal layer is further divided into the second type of via hole. The third metal electrode electrically connected to the conductive material filled in the insulating material layer and the remaining portion of the barrier material layer over the insulating dielectric layer remains under the second and third metal electrodes.

上述的方法，在襯底所支撐的外延層中形成垂直MOS電晶體單元，包括以下步驟：在外延層中進行刻蝕形成多個第一類槽溝和至少一個第二類溝槽；在第一、第二類溝槽的側壁及底部覆蓋一層氧化物層並在第一、第二類槽溝內填充多晶矽；在外延層的位於第一類槽溝側壁周圍的區域中注入第一導電類型的摻雜物，形成從外延層的頂面向下延伸至外延層中的一個體區；以及在體區的位於每個第一類槽溝的較上部分的側壁周圍的區域中注入第二導電類型的摻雜物，形成體區中的多個頂部電極摻雜區，並且任意一個頂部電極摻雜區相對應的圍繞在一個第一類槽溝的較上部分的側壁的周圍，使得任意一個第一類槽溝均依次貫穿一個頂部電極摻雜區和所述體區並延伸至位於體區下方的外延層中；沉積一絕緣介質層覆蓋在外延層上，且絕緣介質層同時還覆蓋在所述體區、多個頂部電極摻雜區以及第一類槽溝和第二類溝槽中所填充的多晶矽上；在所述絕緣介質層中進行刻蝕，形成貫穿緣介質層的多個第一類通孔，以及形成至少一個貫穿緣介質層並接觸第二類溝槽中填充的多晶矽的第二類通孔；在體區的暴露在第一類通孔的底部的區域中注入重摻雜的第一導電類型的摻雜物，形成位於第一類通孔的底部的接觸區；沉積一層勢壘材料層覆蓋在所述絕緣介質層上，勢壘材料層同時還覆蓋在第一、第二類通孔的底部及側壁上；在第二類通孔中填充導電材料，並沉積一層金屬層覆蓋在位於絕緣介質層上方的勢壘材料層上且該金屬層的一部分還填充在第一類通孔中，該金屬層同時還覆蓋在第二類通孔中所填充的導電材料上並與之形成電接觸；對金屬層和位於絕緣介質層上方的勢壘材料層進行刻蝕，將金屬層分割成與第一類通孔中所填充的所述金屬層的一部分電性連接的第二金屬電極，金屬層還被分割成與第二類通孔中所填充的導電材料電性連接的第三金屬電極，覆蓋在絕緣介質層上方的勢壘材料層經刻蝕後的剩餘部分保留在第二、第三金屬電極的下方。 The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductive region in a region of the body region around a sidewall of the upper portion of each of the first type of trenches a type of dopant forming a plurality of top electrode doped regions in the body region, and any one of the top electrode doped regions surrounding the sidewall of the upper portion of a first type of trench, such that any one The first type of trenches sequentially penetrate through a top electrode doped region and the body region and extend into an epitaxial layer located below the body region; an insulating dielectric layer is deposited over the epitaxial layer, and the insulating dielectric layer is also covered at the same time. Place a body region, a plurality of top electrode doped regions, and a polysilicon layer filled in the first type of trenches and the second type of trenches; etching in the insulating dielectric layer to form a plurality of first through dielectric layers a via-like hole, and a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; implanting a heavily doped region in a region of the body region exposed to the bottom of the first type of via hole a dopant of a first conductivity type forming a contact region at a bottom of the first type of via hole; depositing a layer of barrier material overlying the dielectric dielectric layer, the barrier material layer simultaneously covering the first and the The bottom of the second type of through hole and the side wall; The hole is filled with a conductive material, and a metal layer is deposited over the barrier material layer above the insulating dielectric layer and a portion of the metal layer is also filled in the first type of via hole, and the metal layer is also covered in the second type And electrically contacting the conductive material filled in the via hole; etching the metal layer and the barrier material layer above the insulating dielectric layer to divide the metal layer into the filled area of the first type of via hole a second metal electrode electrically connected to a portion of the metal layer, the metal layer being further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, covering the barrier above the insulating dielectric layer The remaining portion of the material layer after etching remains below the second and third metal electrodes.

上述的方法，在沉積一層底部鈍化層覆蓋在襯底的底面上的同時，還沉積一層頂部鈍化層覆蓋在絕緣介質層上，頂部鈍化層同時將第二、第三金屬電極予以覆蓋；之後將覆蓋第二、第三金屬電極的部分頂部鈍化層移除，以在頂部鈍化層中將第二、第三金屬電極予以暴露。上述的方法，利用所注入的第一導電類型的摻雜物形成所述體區的同時，還在外延層中形成圍繞在體區周圍的保護環摻雜區，保護環摻雜區與體區的摻雜類型相同並與體區相互間隔開。上述的方法，利用所述注入的第二導電類型的摻雜物形成頂部電極摻雜區的同時，還在外延層中形成圍繞在保護環摻雜區周圍的通道阻斷摻雜區，通道阻斷摻雜區與頂部電極摻雜區的摻雜類型相同並與保護環摻雜區相互間隔開。 In the above method, while depositing a bottom passivation layer overlying the bottom surface of the substrate, a top passivation layer is deposited over the insulating dielectric layer, and the top passivation layer simultaneously covers the second and third metal electrodes; A portion of the top passivation layer covering the second and third metal electrodes is removed to expose the second and third metal electrodes in the top passivation layer. In the above method, the implanted first conductivity type dopant is used to form the body region, and a guard ring doping region surrounding the body region is formed in the epitaxial layer, and the guard ring doped region and the body region are formed. The doping types are the same and are spaced apart from the body regions. In the above method, the implanted second conductivity type dopant is used to form the top electrode doped region, and a channel blocking doping region around the doped region of the guard ring is formed in the epitaxial layer. The doping type of the broken doping region and the top electrode doping region are the same and interact with the doping region of the guard ring Interspersed.

本發明提供一種製備低導通電阻的功率MOS電晶體裝置的方法，在一襯底所支撐的外延層中形成有垂直MOS電晶體單元，襯底的底面構成垂直MOS電晶體單元的底部電極，該襯底與外延層之間還設置有一層由掩埋重摻雜層所構成的刻蝕阻擋層，且該方法主要包括以下步驟：沉積一層底部鈍化層覆蓋在所述襯底的底面上；在底部鈍化層中形成一個或多個開口，利用底部鈍化層上的開口對襯底進行刻蝕，刻蝕停止在由掩埋重摻雜層所構成的刻蝕阻擋層上，並通過該刻蝕過程形成襯底中的一個或多個底部凹槽；沉積一層金屬層覆蓋在所述襯底的底面上，該金屬層還同時覆蓋在所述底部凹槽的側壁和頂部上；其中，金屬層位於底部凹槽頂部的區域與所述掩埋重摻雜層保持接觸，並且所述金屬層用於構成功率MOS電晶體裝置的第一金屬電極。 The present invention provides a method of fabricating a low-on-resistance power MOS transistor device in which a vertical MOS transistor unit is formed in an epitaxial layer supported by a substrate, and a bottom surface of the substrate constitutes a bottom electrode of a vertical MOS transistor unit. An etch stop layer composed of a buried heavily doped layer is further disposed between the substrate and the epitaxial layer, and the method mainly comprises the steps of: depositing a bottom passivation layer overlying the bottom surface of the substrate; at the bottom Forming one or more openings in the passivation layer, etching the substrate by using an opening on the bottom passivation layer, stopping on the etch stop layer formed by the buried heavily doped layer, and forming through the etching process One or more bottom grooves in the substrate; a metal layer is deposited over the bottom surface of the substrate, the metal layer also covering the sidewalls and the top of the bottom groove; wherein the metal layer is at the bottom A region at the top of the recess remains in contact with the buried heavily doped layer and the metal layer is used to form a first metal electrode of the power MOS transistor device.

上述的方法，對襯底進行刻蝕是利用濕法刻蝕或深反應摻雜物刻蝕實現的。上述的方法，對襯底進行濕法刻蝕所用到的刻蝕液為四甲基氫氧化銨溶液(TMAH)或氫氧化鉀溶液(KOH)或乙二胺鄰苯二酚溶液(EDP)。上述的方法，所述襯底為輕摻雜P型襯底，所述外延層為輕摻雜P型外延層，所述垂直MOS電晶體單元為P型溝道的溝槽式MOS電晶體。上述的方法，所述掩埋重摻雜層為P型的重摻雜層，且該P型重摻雜層的摻雜濃度超過1e19/cm3。 In the above method, etching the substrate is performed by wet etching or deep reactive dopant etching. In the above method, the etching solution used for wet etching the substrate is tetramethylammonium hydroxide solution (TMAH) or potassium hydroxide solution (KOH) or ethylenediamine catechol solution (EDP). In the above method, the substrate is a lightly doped P-type substrate, the epitaxial layer is a lightly doped P-type epitaxial layer, and the vertical MOS transistor unit is a P-type trenched MOS transistor. In the above method, the buried heavily doped layer is a P-type heavily doped The impurity layer, and the doping concentration of the P-type heavily doped layer exceeds 1e19/cm3.

上述的方法，在襯底所支撐的外延層中形成垂直MOS電晶體單元，包括以下步驟：在外延層中進行刻蝕形成多個第一類槽溝和至少一個第二類溝槽；在第一、第二類溝槽的側壁及底部覆蓋一層氧化物層並在第一、第二類槽溝內填充多晶矽；在外延層的位於第一類槽溝側壁周圍的區域中注入第一導電類型的摻雜物，形成從外延層的頂面向下延伸至外延層中的一個體區；以及在體區的位於第一類槽溝的較上部分的側壁周圍的區域中注入第二導電類型的摻雜物，形成從體區的頂面向下延伸至體區中的一個頂部電極摻雜區，使得任意一個第一類槽溝均依次貫穿所述頂部電極摻雜區和所述體區並延伸至位於體區下方的外延層中；沉積一絕緣介質層覆蓋在外延層上，且絕緣介質層同時還覆蓋在所述體區、頂部電極摻雜區以及第一類槽溝和第二類溝槽中所填充的多晶矽上；在所述絕緣介質層、頂部電極摻雜區、體區中進行刻蝕，形成依次貫穿緣介質層、頂部電極摻雜區並延伸至體區中的多個第一類通孔，以及形成至少一個貫穿緣介質層並接觸第二類溝槽中填充的多晶矽的第二類通孔；在第一類通孔的底部周圍的體區中注入重摻雜的第一導電類型的摻雜物，形成包圍第一類通孔的底部的接觸區；沉積一層勢壘材料層覆蓋在所述絕緣介質層上，勢壘材料層同時還覆蓋在第一、第二類通孔的底部及側壁上；在第一、第二類通孔中填充導電材料，並沉積一層金屬層覆蓋在位於絕緣介質層上方的勢壘材料層上，該金屬層同時還覆蓋在第一、第二類通孔中所填充的導電材料上並與之形成電接觸；對金屬層和位於絕緣介質層上方的勢壘材料層進行刻蝕，將金屬層分割成與第一類通孔中所填充的導電材料電性連接的第二金屬電極，金屬層還被分割成與第二類通孔中所填充的導電材料電性連接的第三金屬電極，覆蓋在絕緣介質層上方的勢壘材料層經刻蝕後的剩餘部分保留在第二、第三金屬電極的下方。 The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductivity type in a region of the body region around the sidewall of the upper portion of the first type of trench The dopant is formed to extend from a top surface of the body region to a top electrode doped region in the body region such that any one of the first type of trenches sequentially penetrates the top electrode doped region and the body region and extends To the epitaxial layer below the body region; depositing an insulating dielectric layer overlying the epitaxial layer, and insulating the dielectric layer The magnetic layer also covers the bulk region, the top electrode doped region, and the polysilicon filled in the first type of trench and the second type of trench; the insulating dielectric layer, the top electrode doped region, and the body region Etching, forming a plurality of first type vias sequentially penetrating the edge dielectric layer, the top electrode doped region and extending into the body region, and forming at least one through-edge dielectric layer and contacting the second type of trench filling a second type of via hole of the polysilicon; implanting a heavily doped first conductivity type dopant in the body region around the bottom of the first type of via hole to form a contact region surrounding the bottom of the first type of via hole; depositing a layer a barrier material layer covering the insulating dielectric layer, the barrier material layer also covering the bottom and sidewalls of the first and second types of via holes; filling the first and second types of via holes with a conductive material, and Depositing a metal layer over the barrier material layer above the insulating dielectric layer, the metal layer also covering and electrically contacting the conductive material filled in the first and second types of via holes; And the potential above the dielectric layer The material layer is etched to divide the metal layer into a second metal electrode electrically connected to the conductive material filled in the first type of via hole, and the metal layer is further divided into the conductive material filled in the second type of via hole. The electrically connected third metal electrode, the remaining portion of the barrier material layer overlying the insulating dielectric layer is left under the second and third metal electrodes.

上述的方法，在襯底所支撐的外延層中形成垂直MOS電晶體單元，包括以下步驟：在外延層中進行刻蝕形成多個第一類槽溝和至少一個第二類溝槽；在第一、第二類溝槽的側壁及底部覆蓋一層氧化物層並在第一、第二類槽溝內填充多晶矽；在外延層的位於第一類槽溝側壁周圍的區域中注入第一導電類型的摻雜物，形成從外延層的頂面向下延伸至外延層中的一個體區；以及在體區的位於每個第一類槽溝的較上部分的側壁周圍的區域中注入第二導電類型的摻雜物，形成體區中的多個頂部電極摻雜區，並且任意一個頂部電極摻雜區相對應的圍繞在一個第一類槽溝的較上部分的側壁的周圍，使得任意一個第一類槽溝均依次貫穿一個頂部電極摻雜區和所述體區並延伸至位於體區下方的外延層中；沉積一絕緣介質層覆蓋在外延層上，且絕緣介質層同時還覆蓋在所述體區、多個頂部電極摻雜區以及第一類槽溝和第二類溝槽中所填充的多晶矽上；在所述絕緣介質層中進行刻蝕，形成貫穿緣介質層的多個第一類通孔，以及形成至少一個貫穿緣介質層並接觸第二類溝槽中填充的多晶矽的第二類通孔；在體區的暴露在第一類通孔的底部的區域中注入重摻雜的第一導電類型的摻雜物，形成位於第一類通孔的底部的接觸區；沉積一層勢壘材料層覆蓋在所述絕緣介質層上，勢壘材料層同時還覆蓋在第一、第二類通孔的底部及側壁上；在第二類通孔中填充導電材料，並沉積一層金屬層覆蓋在位於絕緣介質層上方的勢壘材料層上且該金屬層的一部分還填充在第一類通孔中，該金屬層同時還覆蓋在第二類通孔中所填充的導電材料上並與之形成電接觸；對金屬層和位於絕緣介質層上方的勢壘材料層進行刻蝕，將金屬層分割成與第一類通孔中所填充的所述金屬層的一部分電性連接的第二金屬電極，金屬層還被分割成與第二類通孔中所填充的導電材料電性連接的第三金屬電極，覆蓋在絕緣介質層上方的勢壘材料層經刻蝕後的剩餘部分保留在第二、第三金屬電極的下方。 The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; First, the first The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the doping of the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench Forming a body region extending from a top surface of the epitaxial layer to the epitaxial layer; and implanting a second conductivity type in the region of the body region around the sidewall of the upper portion of each of the first type of trenches a plurality of top electrode doped regions in the body region, and any one of the top electrode doped regions surrounding the sidewall of the upper portion of the first type of trenches, such that any one of the first classes The trenches are sequentially penetrated through a top electrode doped region and the body region and extend into the epitaxial layer below the body region; an insulating dielectric layer is deposited over the epitaxial layer, and the insulating dielectric layer also covers the body a region, a plurality of top electrode doped regions, and a polysilicon layer filled in the first type of trench and the second type of trench; etching in the insulating dielectric layer to form a plurality of first types of penetrating dielectric layers Through hole, and Forming at least one second type of via hole penetrating through the edge dielectric layer and contacting the polysilicon filled in the second type of trench; implanting the heavily doped first conductivity type in a region of the body region exposed to the bottom of the first type of via hole The dopant forms a contact region at the bottom of the first type of via; a layer of barrier material is deposited over the dielectric layer, and the barrier material layer also covers the first and second types of vias a bottom layer and a sidewall; filling a conductive material in the second type of via hole, and depositing a metal layer over the barrier material layer over the insulating dielectric layer and filling a portion of the metal layer in the first type of via hole The metal layer is also covered by filling in the second type of through hole And electrically contacting the conductive material; etching the metal layer and the barrier material layer over the insulating dielectric layer to divide the metal layer into a portion of the metal layer filled in the first type of via The electrically connected second metal electrode is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, and the barrier material layer overlying the insulating dielectric layer is etched The remaining portion remains below the second and third metal electrodes.

上述的方法，在沉積一層底部鈍化層覆蓋在襯底的底面上的同時，還沉積一層頂部鈍化層覆蓋在絕緣介質層上，頂部鈍化層同時將第二、第三金屬電極予以覆蓋；之後將覆蓋第二、第三金屬電極的部分頂部鈍化層移除，以在頂部鈍化層中將第二、第三金屬電極予以暴露。上述的方法，利用所注入的第一導電類型的摻雜物形成所述體區的同時，還在外延層中形成圍繞在體區周圍的保護環摻雜區，保護環摻雜區與體區的摻雜類型相同並與體區相互間隔開。上述的方法，利用所述注入的第二導電類型的摻雜物形成頂部電極摻雜區的同時，還在外延層中形成圍繞在保護環摻雜區周圍的通道阻斷摻雜區，通道阻斷摻雜區與頂部電極摻雜區的摻雜類型相同並與保護環摻雜區相互間隔開。 In the above method, while depositing a bottom passivation layer overlying the bottom surface of the substrate, a top passivation layer is deposited over the insulating dielectric layer, and the top passivation layer simultaneously covers the second and third metal electrodes; A portion of the top passivation layer covering the second and third metal electrodes is removed to expose the second and third metal electrodes in the top passivation layer. In the above method, the implanted first conductivity type dopant is used to form the body region, and a guard ring doping region surrounding the body region is formed in the epitaxial layer, and the guard ring doped region and the body region are formed. The doping types are the same and are spaced apart from the body regions. In the above method, the implanted second conductivity type dopant is used to form the top electrode doped region, and a channel blocking doping region around the doped region of the guard ring is formed in the epitaxial layer. The doped region and the top electrode doped region have the same doping type and are spaced apart from the guard ring doped region.

本發明提供一種製備低導通電阻的功率MOS電晶體裝置的方法，在一襯底所支撐的外延層中形成有垂直MOS電晶體單元，襯底的底面構成垂直MOS電晶體單元的底部電極，該方法主要包括以下步驟：沉積一層底部鈍化層覆蓋在所述襯底的底面上；在底部鈍化層中形成一個或多個開口，利用底部鈍化層上的開口對襯底進行刻蝕，刻蝕停止在襯底中，並通過該刻蝕過程形成襯底中的一個或多個底部凹槽；沉積一層金屬層覆蓋在所述襯底的底面上，該金屬層還同時覆蓋在所述底部凹槽的側壁和頂部上；其中，所述金屬層用於構成功率MOS電晶體裝置的第一金屬電極。 The invention provides a method for preparing a low-on-resistance power MOS transistor device, which is formed in an epitaxial layer supported by a substrate a straight MOS transistor unit, the bottom surface of the substrate constitutes a bottom electrode of the vertical MOS transistor unit, the method mainly comprising the steps of: depositing a bottom passivation layer overlying the bottom surface of the substrate; forming one or a plurality of openings, etching the substrate with an opening on the bottom passivation layer, etching stops in the substrate, and forming one or more bottom grooves in the substrate by the etching process; depositing a metal layer to cover On the bottom surface of the substrate, the metal layer also covers both the sidewalls and the top of the bottom recess; wherein the metal layer is used to form the first metal electrode of the power MOS transistor device.

上述的方法，對襯底進行刻蝕是利用濕法刻蝕或深反應摻雜物刻蝕實現的。上述的方法，對襯底進行濕法刻蝕所用到的刻蝕液為四甲基氫氧化銨溶液(TMAH)或氫氧化鉀溶液(KOH)或乙二胺鄰苯二酚溶液(EDP)。上述的方法，所述襯底為重摻雜P型襯底，所述外延層為輕摻雜P型外延層，所述垂直MOS電晶體單元為P型溝道的溝槽式MOS電晶體。上述的方法，所述襯底為重摻雜N型襯底，所述外延層為輕摻雜N型外延層，所述垂直MOS電晶體單元為N型溝道的溝槽式MOS電晶體。上述的方法，在對襯底進行刻蝕的過程中，所形成的底部凹槽的頂部與外延層的頂面之間的距離保持在10um至20um之間。 In the above method, etching the substrate is performed by wet etching or deep reactive dopant etching. In the above method, the etching solution used for wet etching the substrate is tetramethylammonium hydroxide solution (TMAH) or potassium hydroxide solution (KOH) or ethylenediamine catechol solution (EDP). In the above method, the substrate is a heavily doped P-type substrate, the epitaxial layer is a lightly doped P-type epitaxial layer, and the vertical MOS transistor unit is a P-type trenched MOS transistor. In the above method, the substrate is a heavily doped N-type substrate, the epitaxial layer is a lightly doped N-type epitaxial layer, and the vertical MOS transistor unit is an N-type channel trench MOS transistor. In the above method, the distance between the top of the formed bottom groove and the top surface of the epitaxial layer is maintained between 10 um and 20 um during the etching of the substrate.

上述的方法，還包括以下步驟：在一基座的頂面上製備凸出於基座的頂面的數個金屬凸塊，金屬凸塊的數量與所述底部凹槽的數量保持一致，並且金屬凸塊的形貌與所述底部凹槽的槽體結構相適配；以及利用導電粘合材料將功率MOS電晶體裝置粘貼在基座的頂面，其中，任意一個金屬凸塊相對應的嵌入在一個底部凹槽中，並且導電粘合材料位於金屬層與基座之間，導電粘合材料還填充在底部凹槽的頂部與金屬凸塊之間及底部凹槽的側壁與金屬凸塊之間。 The above method further comprises the steps of: preparing a plurality of metal bumps protruding from the top surface of the pedestal on the top surface of the pedestal, the metal bumps The number is consistent with the number of the bottom grooves, and the topography of the metal bumps is adapted to the groove structure of the bottom groove; and the power MOS transistor device is pasted on the pedestal by a conductive adhesive material a top surface, wherein any one of the metal bumps is correspondingly embedded in a bottom recess, and the conductive adhesive material is located between the metal layer and the base, and the conductive adhesive material is further filled on the top of the bottom recess and the metal bump Between the side walls of the block and the bottom groove and the metal bump.

上述的方法，在襯底所支撐的外延層中形成垂直MOS電晶體單元，包括以下步驟：在外延層中進行刻蝕形成多個第一類槽溝和至少一個第二類溝槽；在第一、第二類溝槽的側壁及底部覆蓋一層氧化物層並在第一、第二類槽溝內填充多晶矽；在外延層的位於第一類槽溝側壁周圍的區域中注入第一導電類型的摻雜物，形成從外延層的頂面向下延伸至外延層中的一個體區；以及在體區的位於第一類槽溝的較上部分的側壁周圍的區域中注入第二導電類型的摻雜物，形成從體區的頂面向下延伸至體區中的一個頂部電極摻雜區，使得任意一個第一類槽溝均依次貫穿所述頂部電極摻雜區和所述體區並延伸至位於體區下方的外延層中；沉積一絕緣介質層覆蓋在外延層上，且絕緣介質層同時還覆蓋在所述體區、頂部電極摻雜區以及第一類槽溝和第二類溝槽中所填充的多晶矽上；在所述絕緣介質層、頂部電極摻雜區、體區中進行刻蝕，形成依次貫穿緣介質層、頂部電極摻雜區並延伸至體區中的多個第一類通孔，以及形成至少一個貫穿緣介質層並接觸第二類溝槽中填充的多晶矽的第二類通孔；在第一類通孔的底部周圍的體區中注入重摻雜的第一導電類型的摻雜物，形成包圍第一類通孔的底部的接觸區；沉積一層勢壘材料層覆蓋在所述絕緣介質層上，勢壘材料層同時還覆蓋在第一、第二類通孔的底部及側壁上；在第一、第二類通孔中填充導電材料，並沉積一層金屬層覆蓋在位於絕緣介質層上方的勢壘材料層上，該金屬層同時還覆蓋在第一、第二類通孔中所填充的導電材料上並與之形成電接觸；對金屬層和位於絕緣介質層上方的勢壘材料層進行刻蝕，將金屬層分割成與第一類通孔中所填充的導電材料電性連接的第二金屬電極，金屬層還被分割成與第二類通孔中所填充的導電材料電性連接的第三金屬電極，覆蓋在絕緣介質層上方的勢壘材料層經刻蝕後的剩餘部分保留在第二、第三金屬電極的下方。 The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductivity type in a region of the body region around the sidewall of the upper portion of the first type of trench The dopant is formed to extend from a top surface of the body region to a top electrode doped region in the body region such that any one of the first type of trenches sequentially penetrates the top electrode doped region and the body region and extends Up to an epitaxial layer below the body region; depositing an insulating dielectric layer overlying the epitaxial layer, and simultaneously covering the body region, the top electrode doped region, and the first type of trench and the second type of trench Filled in the slot On silicon; etching the insulating dielectric layer, the top electrode doped region, the body region is formed sequentially through the edge a dielectric layer, a top electrode doped region and extending to the plurality of first type of via holes in the body region, and a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; A heavily doped first conductivity type dopant is implanted into the body region around the bottom of the first type of via to form a contact region surrounding the bottom of the first type of via; a layer of barrier material is deposited over the insulating layer On the dielectric layer, the barrier material layer is also covered on the bottom and sidewalls of the first and second types of via holes; the first and second types of via holes are filled with a conductive material, and a metal layer is deposited over the insulating medium. On the barrier material layer above the layer, the metal layer also covers and is in electrical contact with the conductive material filled in the first and second types of via holes; the metal layer and the barrier above the insulating dielectric layer The material layer is etched to divide the metal layer into a second metal electrode electrically connected to the conductive material filled in the first type of via hole, and the metal layer is further divided into the conductive material filled in the second type of via hole. Electrically connected third metal Electrode, the insulating dielectric layer overlies the remaining portion of the barrier material layer is etched to remain below the second, the third metal electrode.

上述的方法，在襯底所支撐的外延層中形成垂直MOS電晶體單元，包括以下步驟：在外延層中進行刻蝕形成多個第一類槽溝和至少一個第二類溝槽；在第一、第二類溝槽的側壁及底部覆蓋一層氧化物層並在第一、第二類槽溝內填充多晶矽；在外延層的位於第一類槽溝側壁周圍的區域中注入第一導電類型的摻雜物，形成從外延層的頂面向下延伸至外延層中的一個體區；以及在體區的位於每個第一類槽溝的較上部分的側壁周圍的區域中注入第二導電類型的摻雜物，形成體區中的多個頂部電極摻雜區，並且任意一個頂部電極摻雜區相對應的圍繞在一個第一類槽溝的較上部分的側壁的周圍，使得任意一個第一類槽溝均依次貫穿一個頂部電極摻雜區和所述體區並延伸至位於體區下方的外延層中；沉積一絕緣介質層覆蓋在外延層上，且絕緣介質層同時還覆蓋在所述體區、多個頂部電極摻雜區以及第一類槽溝和第二類溝槽中所填充的多晶矽上；在所述絕緣介質層中進行刻蝕，形成貫穿緣介質層的多個第一類通孔，以及形成至少一個貫穿緣介質層並接觸第二類溝槽中填充的多晶矽的第二類通孔；在體區的暴露在第一類通孔的底部的區域中注入重摻雜的第一導電類型的摻雜物，形成位於第一類通孔的底部的接觸區；沉積一層勢壘材料層覆蓋在所述絕緣介質層上，勢壘材料層同時還覆蓋在第一、第二類通孔的底部及側壁上；在第二類通孔中填充導電材料，並沉積一層金屬層覆蓋在位於絕緣介質層上方的勢壘材料層上且該金屬層的一部分還填充在第一類通孔中，該金屬層同時還覆蓋在第二類通孔中所填充的導電材料上並與之形成電接觸；對金屬層和位於絕緣介質層上方的勢壘材料層進行刻蝕，將金屬層分割成與第一類通孔中所填充的所述金屬層的一部分電性連接的第二金屬電極，金屬層還被分割成與第二類通孔中所填充的導電材料電性連接的第三金屬電極，覆蓋在絕緣介質層上方的勢壘材料層經刻蝕後的剩餘部分保留在第二、第三金屬電極的下方。 The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench Dopant formed from the epitaxial layer The top surface extends downward to a body region in the epitaxial layer; and a dopant of the second conductivity type is implanted in a region of the body region around the sidewall of the upper portion of each of the first type of trenches to form a body region a plurality of top electrode doped regions, and any one of the top electrode doped regions surrounding the sidewall of the upper portion of a first type of trench such that any one of the first type of trenches sequentially passes through a top An electrode doped region and the body region extend to an epitaxial layer located below the body region; an insulating dielectric layer is deposited over the epitaxial layer, and the insulating dielectric layer also covers the body region and the plurality of top electrodes are doped a hetero region and a polysilicon filled in the first type of trench and the second type of trench; etching in the insulating dielectric layer to form a plurality of first type via holes penetrating the dielectric layer, and forming at least one a second type of via hole penetrating the edge dielectric layer and contacting the polysilicon filled in the second type of trench; implanting a doped first conductivity type doping in a region of the body region exposed to the bottom of the first type of via hole Object, formed in the first a contact region at the bottom of the via-like hole; a layer of barrier material is deposited over the insulating dielectric layer, and the barrier material layer also covers the bottom and sidewalls of the first and second types of via holes; The via hole is filled with a conductive material, and a metal layer is deposited over the barrier material layer above the insulating dielectric layer and a portion of the metal layer is further filled in the first type of via hole, and the metal layer is also covered in the second layer. And electrically contacting the conductive material filled in the via hole; etching the metal layer and the barrier material layer above the insulating dielectric layer to divide the metal layer into filling with the first type of via hole a second gold electrically connected to a portion of the metal layer a metal electrode, the metal layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, and the remaining portion of the barrier material layer overlying the insulating dielectric layer is retained in the Below the second and third metal electrodes.

上述的方法，其特徵在於，在沉積一層底部鈍化層覆蓋在襯底的底面上的同時，還沉積一層頂部鈍化層覆蓋在絕緣介質層上，頂部鈍化層同時將第二、第三金屬電極予以覆蓋；之後將覆蓋第二、第三金屬電極的部分頂部鈍化層移除，以在頂部鈍化層中將第二、第三金屬電極予以暴露。上述的方法，利用所注入的第一導電類型的摻雜物形成所述體區的同時，還在外延層中形成圍繞在體區周圍的保護環摻雜區，保護環摻雜區與體區的摻雜類型相同並與體區相互間隔開。上述的方法，利用所述注入的第二導電類型的摻雜物形成頂部電極摻雜區的同時，還在外延層中形成圍繞在保護環摻雜區周圍的通道阻斷摻雜區，通道阻斷摻雜區與頂部電極摻雜區的摻雜類型相同並與保護環摻雜區相互間隔開。 The above method is characterized in that, while depositing a bottom passivation layer overlying the bottom surface of the substrate, a top passivation layer is deposited over the insulating dielectric layer, and the top passivation layer simultaneously applies the second and third metal electrodes Covering; then removing a portion of the top passivation layer overlying the second and third metal electrodes to expose the second and third metal electrodes in the top passivation layer. In the above method, the implanted first conductivity type dopant is used to form the body region, and a guard ring doping region surrounding the body region is formed in the epitaxial layer, and the guard ring doped region and the body region are formed. The doping types are the same and are spaced apart from the body regions. In the above method, the implanted second conductivity type dopant is used to form the top electrode doped region, and a channel blocking doping region around the doped region of the guard ring is formed in the epitaxial layer. The doped region and the top electrode doped region have the same doping type and are spaced apart from the guard ring doped region.

本發明提供一種製備低導通電阻的功率MOS電晶體裝置的方法，在一襯底所支撐的外延層中形成有垂直MOS電晶體單元，襯底的底面構成垂直MOS電晶體單元的底部電極，該方法主要包括以下步驟：沉積一層底部鈍化層覆蓋在所述襯底的底面上；在底部鈍化層中形成一個或多個開口，利用底部鈍化層上的開口對襯底進行刻蝕，刻蝕停止在襯底中，並通過該刻蝕過程形成襯底中的一個或多個底部通孔；在所述底部通孔的側壁和頂部沉積一層勢壘材料層之後再在所述底部通孔中填充導電材料；再沉積一層金屬層覆蓋在所述襯底的底面上，該金屬層還同時與所述底部通孔中所填充的導電材料保持電性接觸；其中，所述金屬層用於構成功率MOS電晶體裝置的第一金屬電極。 The present invention provides a method of fabricating a low-on-resistance power MOS transistor device in which a vertical MOS transistor unit is formed in an epitaxial layer supported by a substrate, and a bottom surface of the substrate constitutes a bottom electrode of a vertical MOS transistor unit. The method mainly comprises the steps of: depositing a layer of bottom passivation layer overlying the bottom surface of the substrate; forming a layer in the bottom passivation layer Or a plurality of openings, etching the substrate with an opening on the bottom passivation layer, etching stops in the substrate, and forming one or more bottom vias in the substrate by the etching process; at the bottom Depositing a layer of barrier material on the sidewall and top of the via hole and then filling the bottom via hole with a conductive material; depositing a metal layer overlying the bottom surface of the substrate, the metal layer also simultaneously communicating with the bottom layer The electrically conductive material filled in the aperture remains in electrical contact; wherein the metallic layer is used to form a first metal electrode of the power MOS transistor device.

上述的方法，對襯底進行刻蝕是利用幹法刻蝕或鐳射刻蝕實現的。上述的方法，所述襯底為重摻雜P型襯底，所述外延層為輕摻雜P型外延層，所述垂直MOS電晶體單元為P型溝道的溝槽式MOS電晶體。上述的方法，所述襯底為重摻雜N型襯底，所述外延層為輕摻雜N型外延層，所述垂直MOS電晶體單元為N型溝道的溝槽式MOS電晶體。上述的方法，在對襯底進行刻蝕的過程中，所形成的底部通孔的頂部與外延層的頂面之間的距離保持在5um至20um之間。 In the above method, etching the substrate is performed by dry etching or laser etching. In the above method, the substrate is a heavily doped P-type substrate, the epitaxial layer is a lightly doped P-type epitaxial layer, and the vertical MOS transistor unit is a P-type trenched MOS transistor. In the above method, the substrate is a heavily doped N-type substrate, the epitaxial layer is a lightly doped N-type epitaxial layer, and the vertical MOS transistor unit is an N-type channel trench MOS transistor. In the above method, the distance between the top of the formed bottom via and the top surface of the epitaxial layer is maintained between 5 um and 20 um during the etching of the substrate.

上述的方法，在襯底所支撐的外延層中形成垂直MOS電晶體單元，包括以下步驟：在外延層中進行刻蝕形成多個第一類槽溝和至少一個第二類溝槽；在第一、第二類溝槽的側壁及底部覆蓋一層氧化物層並在第一、第二類槽溝內填充多晶矽；在外延層的位於第一類槽溝側壁周圍的區域中注入第一導電類型的摻雜物，形成從外延層的頂面向下延伸至外延層中的一個體區；以及在體區的位於第一類槽溝的較上部分的側壁周圍的區域中注入第二導電類型的摻雜物，形成從體區的頂面向下延伸至體區中的一個頂部電極摻雜區，使得任意一個第一類槽溝均依次貫穿所述頂部電極摻雜區和所述體區並延伸至位於體區下方的外延層中；沉積一絕緣介質層覆蓋在外延層上，且絕緣介質層同時還覆蓋在所述體區、頂部電極摻雜區以及第一類槽溝和第二類溝槽中所填充的多晶矽上；在所述絕緣介質層、頂部電極摻雜區、體區中進行刻蝕，形成依次貫穿緣介質層、頂部電極摻雜區並延伸至體區中的多個第一類通孔，以及形成至少一個貫穿緣介質層並接觸第二類溝槽中填充的多晶矽的第二類通孔；在第一類通孔的底部周圍的體區中注入重摻雜的第一導電類型的摻雜物，形成包圍第一類通孔的底部的接觸區；沉積一層勢壘材料層覆蓋在所述絕緣介質層上，勢壘材料層同時還覆蓋在第一、第二類通孔的底部及側壁上；在第一、第二類通孔中填充導電材料，並沉積一層金屬層覆蓋在位於絕緣介質層上方的勢壘材料層上，該金屬層同時還覆蓋在第一、第二類通孔中所填充的導電材料上並與之形成電接觸；對金屬層和位於絕緣介質層上方的勢壘材料層進行刻蝕，將金屬層分割成與第一類通孔中所填充的導電材料電性連接的第二金屬電極，金屬層還被分割成與第二類通孔中所填充的導電材料電性連接的第三金屬電極，覆蓋在絕緣介質層上方的勢壘材料層經刻蝕後的剩餘部分保留在第二、第三金屬電極的下方。 The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; and the epitaxial layer is located on the sidewall of the first type of trench Injecting a dopant of a first conductivity type into a surrounding region to form a body region extending from a top surface of the epitaxial layer to an epitaxial layer; and surrounding a sidewall of the upper portion of the body region of the first type of trench Injecting a dopant of a second conductivity type into a region extending from a top surface of the body region to a top electrode doped region in the body region such that any one of the first type of trenches sequentially penetrates the top electrode The impurity region and the body region extend into the epitaxial layer located below the body region; depositing an insulating dielectric layer over the epitaxial layer, and simultaneously covering the body region, the top electrode doped region, and the first a type of trench and a polysilicon layer filled in the second type of trench; etching in the insulating dielectric layer, the top electrode doping region, and the body region, forming a dielectric layer and a top electrode doping region in sequence Extending a plurality of first type of vias in the body region, and forming a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; around the bottom of the first type of via Heavy doping in the body region a dopant of a first conductivity type forming a contact region surrounding a bottom of the first type of via hole; depositing a layer of barrier material overlying the dielectric dielectric layer, the barrier material layer simultaneously covering the first and second regions The bottom and side walls of the through-hole are filled with a conductive material in the first and second types of via holes, and a metal layer is deposited over the barrier material layer above the insulating dielectric layer, and the metal layer is also covered 1. The conductive material filled in the second type of via hole is electrically contacted with the metal material; and the metal layer and the barrier material layer above the insulating dielectric layer are etched to divide the metal layer into the first type of via hole. a second metal electrically connected to the electrically conductive material filled in a metal layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, and the remaining portion of the barrier material layer overlying the insulating dielectric layer is left in the 2. Below the third metal electrode.

上述的方法，在襯底所支撐的外延層中形成垂直MOS電晶體單元，包括以下步驟：在外延層中進行刻蝕形成多個第一類槽溝和至少一個第二類溝槽；在第一、第二類溝槽的側壁及底部覆蓋一層氧化物層並在第一、第二類槽溝內填充多晶矽；在外延層的位於第一類槽溝側壁周圍的區域中注入第一導電類型的摻雜物，形成從外延層的頂面向下延伸至外延層中的一個體區；以及在體區的位於每個第一類槽溝的較上部分的側壁周圍的區域中注入第二導電類型的摻雜物，形成體區中的多個頂部電極摻雜區，並且任意一個頂部電極摻雜區相對應的圍繞在一個第一類槽溝的較上部分的側壁的周圍，使得任意一個第一類槽溝均依次貫穿一個頂部電極摻雜區和所述體區並延伸至位於體區下方的外延層中；沉積一絕緣介質層覆蓋在外延層上，且絕緣介質層同時還覆蓋在所述體區、多個頂部電極摻雜區以及第一類槽溝和第二類溝槽中所填充的多晶矽上；在所述絕緣介質層中進行刻蝕，形成貫穿緣介質層的多個第一類通孔，以及形成至少一個貫穿緣介質層並接觸第二類溝槽中填充的多晶矽的第二類通孔；在體區的暴露在第一類通孔的底部的區域中注入重摻雜的第一導電類型的摻雜物，形成位於第一類通孔的底部的接觸區；沉積一層勢壘材料層覆蓋在所述絕緣介質層上，勢壘材料層同時還覆蓋在第一、第二類通孔的底部及側壁上；在第二類通孔中填充導電材料，並沉積一層金屬層覆蓋在位於絕緣介質層上方的勢壘材料層上且該金屬層的一部分還填充在第一類通孔中，該金屬層同時還覆蓋在第二類通孔中所填充的導電材料上並與之形成電接觸；對金屬層和位於絕緣介質層上方的勢壘材料層進行刻蝕，將金屬層分割成與第一類通孔中所填充的所述金屬層的一部分電性連接的第二金屬電極，金屬層還被分割成與第二類通孔中所填充的導電材料電性連接的第三金屬電極，覆蓋在絕緣介質層上方的勢壘材料層經刻蝕後的剩餘部分保留在第二、第三金屬電極的下方。 The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductive region in a region of the body region around a sidewall of the upper portion of each of the first type of trenches a type of dopant forming a plurality of top electrode doped regions in the body region, and any one of the top electrode doped regions surrounding the sidewall of the upper portion of a first type of trench, such that any one The first type of trenches sequentially penetrate through a top electrode doped region and the body region and extend into an epitaxial layer located below the body region; an insulating dielectric layer is deposited over the epitaxial layer, and the insulating dielectric layer is also covered at the same time. Place a body region, a plurality of top electrode doped regions, and a polysilicon layer filled in the first type of trenches and the second type of trenches; etching in the insulating dielectric layer to form a plurality of first through dielectric layers a via-like hole, and a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; exposure in the body region Depositing a heavily doped first conductivity type dopant in a region at the bottom of the first type of via to form a contact region at the bottom of the first type of via; depositing a layer of barrier material overlying the insulating dielectric On the layer, the barrier material layer also covers the bottom and sidewalls of the first and second types of via holes; the second type of via holes are filled with a conductive material, and a metal layer is deposited to cover the potential above the insulating dielectric layer. And a portion of the metal layer is further filled in the first type of via hole, the metal layer also covering and electrically contacting the conductive material filled in the second type of via hole; The barrier material layer located above the insulating dielectric layer is etched to divide the metal layer into a second metal electrode electrically connected to a portion of the metal layer filled in the first type of via hole, and the metal layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, and the remaining portion of the barrier material layer overlying the insulating dielectric layer is left under the second and third metal electrodes .

上述的方法，在沉積一層底部鈍化層覆蓋在襯底的底面上的同時，還沉積一層頂部鈍化層覆蓋在絕緣介質層上，頂部鈍化層同時將第二、第三金屬電極予以覆蓋；之後將覆蓋第二、第三金屬電極的部分頂部鈍化層移除，以在頂部鈍化層中將第二、第三金屬電極予以暴露。上述的方法，利用所注入的第一導電類型的摻雜物形成所述體區的同時，還在外延層中形成圍繞在體區周圍的保護環摻雜區，保護環摻雜區與體區的摻雜類型相同並與體區相互間隔開。上述的方法，利用所述注入的第二導電類型的摻雜物形成頂部電極摻雜區的同時，還在外延層中形成圍繞在保護環摻雜區周圍的通道阻斷摻雜區，通道阻斷摻雜區與頂部電極摻雜區的摻雜類型相同並與保護環摻雜區相互間隔開。本發明所提供的一種低導通電阻的功率MOS電晶體裝置，是利用上述方法所製備的。 In the above method, while depositing a bottom passivation layer overlying the bottom surface of the substrate, a top passivation layer is deposited over the insulating dielectric layer, and the top passivation layer simultaneously covers the second and third metal electrodes; A portion of the top passivation layer covering the second and third metal electrodes is removed to expose the second and third metal electrodes in the top passivation layer. In the above method, the implanted first conductivity type dopant is used to form the body region, and a guard ring doping region surrounding the body region is formed in the epitaxial layer, and the guard ring doped region and the body region are formed. The doping type is the same and interacts with the body region Interspersed. In the above method, the implanted second conductivity type dopant is used to form the top electrode doped region, and a channel blocking doping region around the doped region of the guard ring is formed in the epitaxial layer. The doped region and the top electrode doped region have the same doping type and are spaced apart from the guard ring doped region. A low on-resistance power MOS transistor device provided by the present invention is prepared by the above method.

本領域的技術人員閱讀以下較佳實施例的詳細說明，並參照附圖之後，本發明的這些和其他方面的優勢無疑將顯而易見。 These and other advantages of the present invention will no doubt become apparent to those skilled in the <RTIgt;

100、100’‧‧‧晶圓 100, 100' ‧ ‧ wafer

100A、100”A‧‧‧MOS電晶體裝置 100A, 100” A‧‧‧MOS transistor device

101‧‧‧外延層 101‧‧‧ Epilayer

101’、101”‧‧‧槽溝 101’, 101”‧‧‧ trench

102、102’‧‧‧氧化物層 102, 102'‧‧‧ oxide layer

103‧‧‧犧牲氧化層 103‧‧‧Sacrificial oxide layer

104、604‧‧‧柵氧化物層 104, 604‧‧‧ gate oxide layer

105’、105”‧‧‧柵多晶矽 105', 105" ‧‧‧Gate Polysilicon

107、107a、607、607a‧‧‧體區 107, 107a, 607, 607a‧‧‧ body area

108、108a、108’a、608‧‧‧頂部電極摻雜區 108, 108a, 108'a, 608‧‧‧ top electrode doped area

109‧‧‧絕緣介質層 109‧‧‧Insulation medium layer

110、110’、110a、110-1、110a-1‧‧‧通孔 110, 110', 110a, 110-1, 110a-1‧‧‧ through holes

111‧‧‧導電材料 111‧‧‧Electrical materials

112、612‧‧‧勢壘材料層 112, 612‧‧‧ barrier material layer

112’a、112’b‧‧‧剩餘部分 112’a, 112’b‧‧‧ remaining

113A、113A-1‧‧‧第二金屬電極 113A, 113A-1‧‧‧ second metal electrode

113B、113B-1‧‧‧第三金屬電極 113B, 113B-1‧‧‧ third metal electrode

114a、114’a‧‧‧頂部鈍化層 114a, 114’a‧‧‧ top passivation layer

114b、114’b‧‧‧底部鈍化層 114b, 114’b‧‧‧ bottom passivation layer

115、115’‧‧‧底部凹槽 115, 115'‧‧‧ bottom groove

116‧‧‧電極接觸區 116‧‧‧Electrode contact zone

117‧‧‧金屬層(底部金屬層) 117‧‧‧metal layer (bottom metal layer)

120、120’‧‧‧刻蝕阻擋層 120, 120'‧‧‧ etch barrier

125‧‧‧襯底 125‧‧‧Substrate

200‧‧‧功率MOS電晶體裝置 200‧‧‧Power MOS transistor device

300、400‧‧‧基座 300, 400‧‧‧ base

201、301、401‧‧‧頂面 201, 301, 401‧‧‧ top

202‧‧‧底面 202‧‧‧ bottom

302‧‧‧源極引線基座 302‧‧‧Source lead pedestal

303‧‧‧柵極引線基座 303‧‧‧Gate lead pedestal

315‧‧‧金屬凸塊 315‧‧‧Metal bumps

320‧‧‧導電粘合材料 320‧‧‧ Conductive bonding materials

605‧‧‧多晶矽柵極 605‧‧‧Polysilicon gate

613A‧‧‧金屬層 613A‧‧‧ metal layer

參考所附附圖，以更加充分的描述本發明的實施例。然而，所附附圖僅用於說明和闡述，並不構成對本發明範圍的限制。 Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention.

第1圖是背景技術中利用電動化學刻蝕法刻蝕矽基板的示意圖。 Fig. 1 is a schematic view of a ruthenium substrate etched by electro-chemical etching in the background art.

第2A圖是在襯底和外延層之間設置一層刻蝕阻擋層的示意圖。 Figure 2A is a schematic illustration of an etch stop layer disposed between the substrate and the epitaxial layer.

第2B圖是直接在襯底上生成外延層的示意圖。 Figure 2B is a schematic illustration of the formation of an epitaxial layer directly on a substrate.

第2C圖是在襯底和外延層之間利用摻雜物進行重摻雜形成一層掩埋層，並利用該掩埋層作為刻蝕阻擋層的示意圖。 2C is a schematic diagram of forming a buried layer by heavily doping with a dopant between the substrate and the epitaxial layer, and using the buried layer as an etch barrier.

第3A-3S圖是在外延層中形成功率裝置以及在襯底中形成底部凹槽的方法流程圖。 3A-3S is a flow chart of a method of forming a power device in an epitaxial layer and forming a bottom recess in the substrate.

第4A-4D圖是利用襯底和外延層之間形成的PN結作為刻蝕阻擋層的示意圖。 4A-4D is a schematic diagram of utilizing a PN junction formed between a substrate and an epitaxial layer as an etch barrier.

第5A-5D圖是利用襯底和外延層之間的重摻雜的掩埋層作為刻蝕阻擋層的示意圖。 5A-5D is a schematic illustration of the use of a heavily doped buried layer between the substrate and the epitaxial layer as an etch stop.

第6圖是直接在襯底中形成底部通孔並在底部通孔中填充金屬材料的示意圖。 Figure 6 is a schematic illustration of forming a bottom via directly in the substrate and filling the bottom via with a metal material.

第7圖是不利用任何刻蝕阻擋層而直接在襯底中形成底部凹槽的結構示意圖。 Figure 7 is a schematic illustration of the formation of a bottom recess directly in the substrate without the use of any etch stop.

第8A-8E圖是在外延層中形成另一種溝槽式垂直功率裝置的方法流程圖。 8A-8E is a flow chart of a method of forming another trench vertical power device in an epitaxial layer.

第9A圖是在襯底中形成多個底部凹槽的結構示意圖。 Figure 9A is a schematic view showing the structure of forming a plurality of bottom grooves in the substrate.

第9B圖是與襯底中的底部凹槽相適配的引線框架/基座的結構示意圖。 Figure 9B is a schematic view of the structure of the lead frame/base adapted to the bottom recess in the substrate.

第10圖是功率MOS電晶體粘貼在有金屬凸塊的基座上的截面示意圖。 Figure 10 is a schematic cross-sectional view of a power MOS transistor attached to a pedestal with metal bumps.

第11圖是功率MOS電晶體粘貼在沒有金屬凸塊的基座上的截面示意圖。 Figure 11 is a schematic cross-sectional view of a power MOS transistor adhered to a pedestal without metal bumps.

第12圖是在VDMOS的襯底中形成底部凹槽的結構示意圖。 Figure 12 is a schematic view showing the structure of forming a bottom groove in a substrate of a VDMOS.

實施方式一： Embodiment 1:

參見第2A圖所示，在晶圓100中，襯底125與外延層101之間設置有一層刻蝕阻擋層120，這類晶圓通常稱之為絕緣矽SOI(silicon on insulator)晶圓。而在第2B圖中所示的晶圓100'中，外延層101是直接生長在襯底125上。另外，在第2C-1至2C-2圖中所示出晶圓100"中，先在襯底125的頂面植入一層重摻雜物以形成的一層掩埋重摻雜層120"，之後再在襯底125上生長外延層101，例如從輕摻雜的P-型襯底125的頂面注入一層重摻雜的P+型掩埋重摻雜層120"，再在襯底125上生長輕摻雜的P-型外延層101，這樣襯底125與外延層101之間就存在一層重摻雜物的掩埋重摻雜層120"。 Referring to FIG. 2A, in the wafer 100, an etch stop layer 120 is disposed between the substrate 125 and the epitaxial layer 101. Such a wafer is commonly referred to as a silicon on insulator (SOI) wafer. In the wafer 100' shown in FIG. 2B, the epitaxial layer 101 is grown directly on the substrate 125. In addition, in the wafer 100" shown in the second C-1 to 2C-2, a layer of heavily doped layer 120" is implanted on the top surface of the substrate 125 to form a buried heavily doped layer 120". An epitaxial layer 101 is grown on the substrate 125, for example, by implanting a heavily doped P+ type buried heavily doped layer 120" from the top surface of the lightly doped P-type substrate 125, and then growing lightly on the substrate 125. The doped P-type epitaxial layer 101 is such that there is a heavily doped buried heavily doped layer 120" between the substrate 125 and the epitaxial layer 101.

現以SOI晶圓為例對本案進行說明。第3A圖中，先生成一層氧化物層102(如LTO低溫氧化物)覆蓋在外延層101上，並在氧化物層102上塗覆一層光阻115，利用光刻工藝形成在光阻115中的多個開口115'對氧化物層102進行刻蝕，從而形成氧化物層102中的多個開口102'，並利用氧化物層102作為硬掩模對外延層101進行刻蝕，形成外延層101中的多個第一類槽溝101'和至少一個第二類溝槽101"，為了獲得較為圓滑的溝槽底部以提高電學特性，通常是先進行各項異性刻蝕再實施小部分的濕法刻蝕，之後移除該氧化物層102，如第3B-2圖C所示。在第3C圖中，由於形成溝槽過程的幹法刻蝕過程中造成對溝槽壁的物理損傷以及一些其他形式的表面缺陷，需要移除溝槽壁表面的一層有缺陷的矽，通常是採用比較迅速且熱預算小的濕氧進行犧牲氧化工藝，從而生成一層犧牲氧化層103覆蓋在外延層101的頂面，同時犧牲氧化層103還覆蓋在第一類槽溝101'和第二類溝槽101"的側壁及底部，之後實施犧牲氧化層103蝕刻。如第3D圖所示，然後進行通常為高溫幹氧條件下的柵氧工藝生長一層柵氧化物層104，柵氧化物層104覆蓋在第一類槽溝101'和第二類溝槽101"的側壁及底部並還覆蓋在外延層101的頂面。如第3E-3F圖所示，先進行LPCVD澱積多晶矽層105覆蓋在柵氧化物層104上，此過程中底部及側壁附有柵氧化物層104的第一類槽溝101'和第二類溝槽101"中均填充有多晶矽層105，多晶矽層105可以選擇原位摻雜或澱積之後再適度摻雜，然後對多晶矽層105進行回蝕，僅保留分別位於第一類槽溝101'中的柵多晶矽105'和第二類溝槽101"中的柵極流道多晶矽105"(或稱之為柵極通道多晶矽)，其實第一類槽溝101'和第二類溝槽101"是連通的，故柵多晶矽105'和柵極流道多晶矽105"也是電性導通的。如第3G圖所示，覆蓋在外延層101的頂面的柵氧化物層104蝕刻之後進行遮罩氧化，形成的遮罩氧化層106覆蓋在在外延層101的頂面和覆蓋在柵多晶矽105'和柵極流道多晶矽105"上。如第3H圖所示，在外延層101的位於第一類槽101'溝側壁周圍的區域中注入第一導電類型的摻雜物並伴隨著退火擴散，從而形成從外延層101的頂面向下延伸至外延層101中的一個體區107(結深通常在0.6至0.7微米之間)，並使用同一離子注入掩模，同時還利用第一導電類型的摻雜物在外延層101中形成圍繞在體區107周圍的保護環摻雜區(Guard ring)107a，保護環摻雜區107a與體區107的摻雜類型相同並與體區107相互間隔開。如第3I圖所示，在體區107的位於第一類槽溝101'的較上部分的側壁周圍的區域中注入第二導電類型(與第一導電類型的摻雜類型相反)的摻雜物並伴隨著退火擴散，從而形成從體區107的頂面向下延伸至體區107中的一個頂部電極摻雜區108(結深通常在0.25微米左右)，使得任意一個第一類槽溝101'均依次貫穿頂部電極摻雜區108和體區107並延伸至外延層101位於體區107下方的區域中，其中，形成頂部電極摻雜區108的同時，使用同一離子注入掩模，還利用第二導電類型的摻雜物在外延層107中形成圍繞在保護環摻雜區107a周圍的通道阻斷摻雜區(Channel stop)108a，通道阻斷摻雜區108a與頂部電極摻雜區108的摻雜類型相同並與保護環摻雜區107a相互間隔開。 The case is described by taking SOI wafer as an example. In FIG. 3A, an oxide layer 102 (such as LTO low temperature oxide) is overlaid on the epitaxial layer 101, and a photoresist 115 is coated on the oxide layer 102, which is formed in the photoresist 115 by a photolithography process. The plurality of openings 115' etch the oxide layer 102 to form a plurality of openings 102' in the oxide layer 102, and etch the epitaxial layer 101 using the oxide layer 102 as a hard mask to form the epitaxial layer 101. The plurality of first type trenches 101' and the at least one second type of trenches 101" are generally wetted by anisotropic etching to obtain a small portion of the trenches in order to obtain a relatively smooth trench bottom. Etching, then removing the oxide layer 102, as shown in Figure 3B-2, Figure C. In Figure 3C, the physical damage to the trench walls is caused by the dry etching process that forms the trench process and Some other forms of surface defects that need to be moved In addition to a defective defect in the surface of the trench wall, a sacrificial oxidation process is usually performed using a relatively fast and low thermal budget wet oxygen, thereby forming a sacrificial oxide layer 103 overlying the top surface of the epitaxial layer 101 while sacrificing the oxide layer 103. The sidewalls and the bottom of the first type of trench 101' and the second type of trench 101" are also covered, and then the sacrificial oxide layer 103 is etched. As shown in FIG. 3D, the gate oxide is usually performed under high temperature dry oxygen conditions. A gate oxide layer 104 is grown by the process, and the gate oxide layer 104 covers the sidewalls and bottom of the first type of trench 101' and the second type of trench 101" and also covers the top surface of the epitaxial layer 101. As shown in FIG. 3E-3F, the LPCVD deposition polysilicon layer 105 is first overlaid on the gate oxide layer 104, and the first type of trench 101' and the second side of the gate oxide layer 104 are attached to the bottom and sidewalls. Each of the trenches 101" is filled with a polysilicon layer 105. The polysilicon layer 105 can be selectively doped or deposited after being doped, and then the polysilicon layer 105 is etched back, leaving only the first type of trenches 101. The gate channel polysilicon 105' in the 'gate and the channel runner polysilicon 105" (or gate channel polysilicon) in the second type of trench 101", in fact, the first type of trench 101' and the second type of trench 101 "It is connected, so the gate polysilicon 105' and the gate runner polysilicon 105" are also electrically conductive. As shown in Fig. 3G, the gate oxide layer 104 covering the top surface of the epitaxial layer 101 is etched and then masked. Oxidation, a mask oxide layer 106 is formed overlying the top surface of epitaxial layer 101 and overlying gate polysilicon 105' and gate runner polysilicon 105". As shown in FIG. 3H, a dopant of the first conductivity type is implanted in a region of the epitaxial layer 101 around the sidewall of the trench of the first type of trench 101' and is accompanied by annealing diffusion, thereby forming a top surface from the top of the epitaxial layer 101. Extending to one of the body regions 107 in the epitaxial layer 101 (the junction depth is typically between 0.6 and 0.7 microns) and The same ion implantation mask is used, while a guard ring doping region 107a surrounding the body region 107 is formed in the epitaxial layer 101 by using the dopant of the first conductivity type, and the guard ring doping region 107a and the body are protected. The doping types of the regions 107 are the same and are spaced apart from the body regions 107. As shown in FIG. 3I, a doping of a second conductivity type (opposite to the doping type of the first conductivity type) is implanted in a region of the body region 107 around the sidewall of the upper portion of the first type of trench 101'. The material is accompanied by annealing diffusion to form a top electrode doped region 108 extending from the top surface of the body region 107 to the body region 107 (the junction depth is typically around 0.25 microns), such that any of the first type of trenches 101 'Equipped sequentially through the top electrode doping region 108 and the body region 107 and extending to a region of the epitaxial layer 101 below the body region 107, wherein the same electrode implantation mask 108 is formed while using the same ion implantation mask, The second conductivity type dopant forms a channel stop doping region 108a around the guard ring doping region 107a in the epitaxial layer 107, the channel blocking doping region 108a and the top electrode doping region 108 The doping types are the same and are spaced apart from the guard ring doping region 107a.

如第3J圖所示，剝離遮罩氧化層106之後，沉積一絕緣介質層109覆蓋在外延層上，絕緣介質層通常是低溫氧化物/含硼酸的矽玻璃(LTO/BPSG)的雙鈍化層，且絕緣介質層109同時還覆蓋在體區107、保護環摻雜區107a、頂部電極摻雜區108、通道阻斷摻雜區108a以及第一類槽溝101'中填充的柵多晶矽105'和第二類溝槽101"中填充的柵極流道多晶矽105"上。然後如第3K圖所示，利用掩模116中的多個開口116'，在絕緣介質層109、頂部電極摻雜區108、體區107中進行刻蝕，形成依次貫穿絕緣介質層109、頂部電極摻雜區108並延伸至體區107中的多個第一類通孔110，以及形成至少一個貫穿緣介質層109並接觸第二類溝槽101"中填充的柵極流道多晶矽105"的第二類通孔110'，而從頂部電極摻雜區108的頂面算起，第一類通孔110的深度通常在0.25至0.4微米之間。如第3L圖所示，在體區107的位於第一類通孔110的底部的周圍的區域中注入重摻雜的第一導電類型的摻雜物，形成包圍第一類通孔110的底部的接觸區110a。如第3M圖所示，沉積一層具良好導電性能的勢壘材料層112(例如Ti/TiN)覆蓋在所述絕緣介質層109上，勢壘材料層112同時還覆蓋在第一類通孔110、第二類通孔110'各自的底部及側壁上；然後在底部及側壁附有勢壘材料層112的第一類通孔110、第二類通孔110'中填充導電材料(例如鎢W)111，並沉積一層金屬層113覆蓋在勢壘材料層112的位於絕緣介質層109上方的區域上，該金屬層113同時還覆蓋在分別填充在第一類通孔110和第二類通孔110'中的導電材料111上並與導電材料111形成電接觸。如第3N圖所示，同時對金屬層113和勢壘材料層112的位於絕緣介質層109上方的區域進行刻蝕，將金屬層113分割成與第一類通孔110中所填充的導電材料111電性連接的第二金屬電極113A，此過程中金屬層113還被分割成與第二類通孔110'中所填充的導電材料111電性連接的第三金屬電極113B，勢壘材料層112覆蓋在絕緣介質層109上方的區域經刻蝕後的剩餘部分112'a和112'b分別保留在第二金屬電極113A和第三金屬電極113B的下方。如第3O圖所示，PECVD沉積一層底部鈍化層114b覆蓋在襯底125的底面上，及沉積一層頂部鈍化層114a覆蓋在絕緣介質層109上，頂部鈍化層114a同時將第二金屬電極113A和第三金屬電極113B予以覆蓋，鈍化層通常為二氧化矽或氮化矽。如第3P圖所示，在底部鈍化層114b中形成一個開口114'b或多個未示出的開口，從而將底部鈍化層114b作為掩模並利用底部鈍化層114b上的開口114'b對襯底125進行刻蝕，並通過該刻蝕過程相對應的形成襯底125中的一個凹槽115或多個未示出的凹槽，刻蝕停止在刻蝕阻擋層120上。其中，襯底125的刻蝕可為濕法刻蝕或深反應摻雜物刻蝕，而濕法刻蝕用到的刻蝕液通常為四甲基氫氧化銨溶液(TMAH)或氫氧化鉀溶液(KOH)或乙二胺鄰苯二酚溶液(EDP)，由於TMAH相容CMOS的濕法刻蝕並且不含鹼金屬離子，而EDP具有腐蝕性和潛在的致癌性的不利因素，另外，KOH刻蝕液中K+是一種可移動的離子電荷源，會對裝置的電性特徵(例如開啟電壓)有負面影響，所以本發明優選TMAH作為刻蝕劑。 As shown in FIG. 3J, after the mask oxide layer 106 is stripped, an insulating dielectric layer 109 is deposited over the epitaxial layer, which is typically a double passivation layer of a low temperature oxide/boric acid-containing bismuth glass (LTO/BPSG). And the insulating dielectric layer 109 also covers the gate polysilicon 105' filled in the body region 107, the guard ring doping region 107a, the top electrode doping region 108, the channel blocking doping region 108a, and the first type of trench 101'. And the second type of trench 101" is filled in the gate runner polysilicon 105". Then, as shown in FIG. 3K, using a plurality of openings 116' in the mask 116, the insulating dielectric layer 109, the top is electrically Etching is performed in the electrode doped region 108 and the body region 107 to form a plurality of first type via holes 110 that sequentially penetrate the insulating dielectric layer 109, the top electrode doped region 108, and extend into the body region 107, and form at least one through The edge dielectric layer 109 is in contact with the second type of via hole 110' of the gate runner polysilicon 105" filled in the second type of trench 101", and the first type of pass is calculated from the top surface of the top electrode doping region 108. The depth of the holes 110 is typically between 0.25 and 0.4 microns. As shown in FIG. 3L, a heavily doped first conductivity type dopant is implanted in a region of the body region 107 around the bottom of the first type of via 110 to form a bottom surrounding the first type of via 110. Contact area 110a. As shown in FIG. 3M, a barrier material layer 112 (eg, Ti/TiN) having a good electrical conductivity is deposited over the insulating dielectric layer 109, and the barrier material layer 112 also covers the first via 110. The second type of through holes 110' are respectively on the bottom and the side walls; then the first type of through holes 110 and the second type of through holes 110' with the barrier material layer 112 attached to the bottom and the side walls are filled with a conductive material (for example, tungsten W And a metal layer 113 is deposited over the region of the barrier material layer 112 above the insulating dielectric layer 109, and the metal layer 113 is also covered in the first type of via hole 110 and the second type of via hole, respectively. The conductive material 111 in 110' is in electrical contact with the conductive material 111. As shown in FIG. 3N, the regions of the metal layer 113 and the barrier material layer 112 above the insulating dielectric layer 109 are simultaneously etched to divide the metal layer 113 into conductive materials filled in the first type of vias 110. 111 electrically connected second metal electrode 113A, in this process, the metal layer 113 is further divided into a third metal electrode 113B electrically connected to the conductive material 111 filled in the second type of via hole 110', the barrier material layer 112 covers the area above the insulating dielectric layer 109 after etching The remaining portions 112'a and 112'b remain below the second metal electrode 113A and the third metal electrode 113B, respectively. As shown in FIG. 3O, PECVD deposits a bottom passivation layer 114b overlying the bottom surface of the substrate 125, and deposits a top passivation layer 114a overlying the dielectric dielectric layer 109. The top passivation layer 114a simultaneously exposes the second metal electrode 113A and The third metal electrode 113B is covered, and the passivation layer is usually hafnium oxide or tantalum nitride. As shown in FIG. 3P, an opening 114'b or a plurality of openings, not shown, are formed in the bottom passivation layer 114b, thereby using the bottom passivation layer 114b as a mask and utilizing the opening 114'b on the bottom passivation layer 114b. The substrate 125 is etched, and a recess 115 or a plurality of recesses not shown in the substrate 125 are formed by the etching process, and etching is stopped on the etch barrier layer 120. The etching of the substrate 125 may be wet etching or deep reactive dopant etching, and the etching solution used for wet etching is usually tetramethylammonium hydroxide solution (TMAH) or potassium hydroxide. Solution (KOH) or ethylenediamine catechol solution (EDP), due to TMAH compatible CMOS wet etching and no alkali metal ions, and EDP has corrosive and potential carcinogenic disadvantages, in addition, K+ in the KOH etchant is a mobile source of ionic charge that negatively affects the electrical characteristics of the device (e.g., turn-on voltage), so TMAH is preferred as an etchant in the present invention.

如第3Q圖所示，進一步對通常為二氧化矽的刻蝕阻擋層120的暴露在凹槽115中的區域(例如虛線所框定的區域120’)進行刻蝕，其刻蝕可用緩衝氫氟酸溶液，並且刻蝕停止在外延層101上，由此形成依次貫穿襯底125和刻蝕阻擋層120的一個或多個底部凹槽115’。如第3R圖所示，於外延層101的暴露在底部凹槽115’的頂部的區域內注入與外延層101摻雜類型相同的摻雜物，形成外延層101中位於底部凹槽115’的頂部的上方的重摻雜的底部電極接觸區116，然後移去底部鈍化層114b，之後將覆蓋第二金屬電極113A、第三金屬電極113B的部分頂部鈍化層114a移除，可以在合適的時機選擇將頂部鈍化層114a覆蓋在第二金屬電極113A上的區域(例如114a-1)移除，將頂部鈍化層114a覆蓋在和第三金屬電極113B上的區域(例如114a-2)移除，以在頂部鈍化層中114a將第二金屬電極113A、第三金屬電極113B予以暴露。如第3S圖所示，沉積一層金屬層(底部金屬層)117覆蓋在襯125底的底面上，該金屬層117還同時覆蓋在底部凹槽115’的側壁和頂部上，其中，金屬層117位於底部凹槽115’的頂部的區域與重摻雜的底部電極接觸區116保持良好的歐姆接觸，並且金屬層117用於構成功率MOS電晶體裝置100A的第一金屬電極。如第3S圖所示，在MOS電晶體裝置100A中，垂直MOS電晶體單元為溝槽式MOS電晶體，第一類槽溝101’中所填充的柵多晶矽105’構成垂直MOS電晶體單元的柵極，溝道形成在體區107中，受柵多晶矽105’控制的電流從頂部電極摻雜區108經體區107流向外延層101的底面(或相反)，所以稱外延層101的底面構成垂直MOS電晶體單元的底部電極(如漏極)，而相應的頂部電極摻雜區108一般構成垂直MOS電晶體單元的頂部電極(如源極)。其中，第一類通孔110中填充的導電材料111提供頂部電極摻雜區108與第二金屬電極113A之間的電接觸，同時還提供源區-體區之間的電接觸，所以第二金屬電極113A構成MOS電晶體裝置100A的源極電極；第二類通孔110’中填充的導電材料111提供柵極流道多晶矽105”與第三金屬電極113B之間的電接觸，由於第三金屬電極113B與任意一個柵多晶矽105’都是電性導通的，所以第三金屬電極113B構成功率MOS電晶體裝置100A的柵極電極，而由金屬層117所構成的第一金屬電極則為功率MOS電晶體裝置100A的漏極電極。例如，如果襯底125為輕摻雜N型襯底，外延層101為輕摻雜N型外延層，前述第一導電類型的摻雜物可為P型的離子，第二導電類型的摻雜物可為N型的離子，則垂直MOS電晶體單元為N型溝道的溝槽式MOS電晶體；如果襯底125為輕摻雜P型襯底，外延層為輕摻雜P型外延層，前述第一導電類型的摻雜物可為N型的離子，第二導電類型的摻雜物可為P型的離子，則垂直MOS電晶體單元為P型溝道的溝槽式MOS電晶體。 As shown in FIG. 3Q, the region of the etch barrier layer 120, which is typically cerium oxide, exposed in the recess 115 (eg, the region 120' enclosed by the dashed line) is further etched, and the etch can be buffered with hydrogen fluoride. The acid solution is etched and the etch stops on the epitaxial layer 101, thereby forming one or more bottom recesses 115' that extend through the substrate 125 and the etch stop layer 120 in sequence. As shown in FIG. 3R, in the region of the epitaxial layer 101 exposed at the top of the bottom recess 115' A dopant of the same type as that of the epitaxial layer 101 is implanted in the domain to form a heavily doped bottom electrode contact region 116 in the epitaxial layer 101 above the top of the bottom trench 115', and then the bottom passivation layer 114b is removed. Then, the partial top passivation layer 114a covering the second metal electrode 113A and the third metal electrode 113B is removed, and the region where the top passivation layer 114a is covered on the second metal electrode 113A (for example, 114a-1) may be selected at an appropriate timing. To remove, the region where the top passivation layer 114a is overlaid on the third metal electrode 113B (for example, 114a-2) is removed to expose the second metal electrode 113A and the third metal electrode 113B in the top passivation layer 114a. As shown in FIG. 3S, a metal layer (bottom metal layer) 117 is deposited over the bottom surface of the bottom of the liner 125. The metal layer 117 also covers the sidewalls and top of the bottom recess 115', wherein the metal layer 117 The region at the top of the bottom recess 115' maintains good ohmic contact with the heavily doped bottom electrode contact region 116, and the metal layer 117 is used to form the first metal electrode of the power MOS transistor device 100A. As shown in FIG. 3S, in the MOS transistor device 100A, the vertical MOS transistor unit is a trench MOS transistor, and the gate polysilicon 105' filled in the first type of trench 101' constitutes a vertical MOS transistor unit. The gate, the channel is formed in the body region 107, and the current controlled by the gate polysilicon 105' flows from the top electrode doping region 108 to the bottom surface (or vice versa) of the epitaxial layer 101 via the body region 107, so that the bottom surface of the epitaxial layer 101 is formed. The bottom electrode (e.g., the drain) of the vertical MOS transistor unit, and the corresponding top electrode doped region 108 generally constitutes the top electrode (e.g., source) of the vertical MOS transistor unit. Wherein, the conductive material 111 filled in the first type of via hole 110 provides electrical contact between the top electrode doped region 108 and the second metal electrode 113A, The electrical contact between the source region and the body region, so that the second metal electrode 113A constitutes the source electrode of the MOS transistor device 100A; the conductive material 111 filled in the second type of via hole 110' provides the gate runner polysilicon 105" The electrical contact with the third metal electrode 113B, since the third metal electrode 113B and any one of the gate polysilicon 105' are electrically connected, the third metal electrode 113B constitutes the gate electrode of the power MOS transistor device 100A, The first metal electrode composed of the metal layer 117 is the drain electrode of the power MOS transistor device 100A. For example, if the substrate 125 is a lightly doped N-type substrate, the epitaxial layer 101 is a lightly doped N-type epitaxial layer. The layer, the first conductivity type dopant may be a P type ion, the second conductivity type dopant may be an N type ion, and the vertical MOS transistor unit is an N type channel trench MOS a crystal; if the substrate 125 is a lightly doped P-type substrate, the epitaxial layer is a lightly doped P-type epitaxial layer, the aforementioned first conductivity type dopant may be an N-type ion, and the second conductivity type dopant It can be a P-type ion, and the vertical MOS transistor unit is a P-type channel. Trough MOS transistor.

實施方式二： Embodiment 2:

參見第2B圖及第4A-4D圖所示，在晶圓100，中，外延層101是直接生長在襯底125上，若是前述製備垂直MOS電晶體單元是在晶圓100’中實施的，那麼在外延層101中製備垂直MOS電晶體單元與實施方式一中的流程並無差異，所以襯底125所支撐的外延層101中形成有相同的垂直MOS電晶體單元。只不過此時要求襯底125與外延層101的摻雜類型相反，主要原因是利用襯底125與外延層101兩者的交界面所產生的PN結作為刻蝕襯底125 時的刻蝕阻擋層。如第4A圖所示，在沉積一層底部鈍化層114b覆蓋在襯底125的底面上，在底部鈍化層114b中形成一個開口114’b或多個未示出的開口(為了簡潔起見，只示意出了一個開口)。如第4B圖所示，襯底125與外延層101兩者的交界面所產生的PN結在反偏的條件下，利用底部鈍化層114b上的開口114’b對襯底125進行刻蝕，主要是電化學腐蝕，電化學刻蝕法所用到的濕法刻蝕液主要為四甲基氫氧化銨溶液(TMAH)或氫氧化鉀溶液(KOH)，刻蝕到達PN結時刻蝕反應停止，此時刻蝕精度經過調整可認為刻蝕大致停止在外延層101上，從而通過該刻蝕過程形成襯底125中的一個底部凹槽115’或多個未示意出的底部凹槽。如第4C圖所示，然後於外延層101的暴露在底部凹槽115’的頂部的區域內注入與外延層101摻雜類型相同的摻雜物，此摻雜過程為重摻雜過程，以形成外延層101中位於底部凹槽115’的頂部的上方的底部電極接觸區116。如第4D圖所示，沉積一層金屬層(底部金屬層)117覆蓋在襯底125的底面上，該金屬層117還同時覆蓋在底部凹槽115’的側壁和頂部上。其中，金屬層117位於底部凹槽115’的頂部的區域與底部電極接觸區116保持良好的歐姆接觸，並且由金屬層117所構成的第一金屬電極為功率MOS電晶體裝置100’A的漏極電極，第二金屬電極113A構成功率MOS電晶體裝置100’A的源極電極，第三金屬電極113B構成功率MOS電晶體裝置100’A的柵極電極。其中，如果襯底125為輕摻雜P型襯底，外延層101為輕摻雜N型外延層，前述第一導電類型的摻雜物可為P型的離子，第二導電類型的摻雜物可為N型的離子，則垂直MOS電晶體單元為N型溝道的溝槽式MOS電晶體。如果襯底125為輕摻雜N型襯底，外延層101為輕摻雜P型外延層，前述第一導電類型的摻雜物可為N型的離子，第二導電類型的摻雜物可為P型的離子，則垂直MOS電晶體單元為P型溝道的溝槽式MOS電晶體。 Referring to FIG. 2B and FIG. 4A-4D, in the wafer 100, the epitaxial layer 101 is directly grown on the substrate 125. If the foregoing vertical MOS transistor unit is fabricated in the wafer 100', Then, the preparation of the vertical MOS transistor unit in the epitaxial layer 101 is not different from the flow in the first embodiment, so that the same vertical MOS transistor unit is formed in the epitaxial layer 101 supported by the substrate 125. However, the doping type of the substrate 125 and the epitaxial layer 101 are required to be opposite at this time. The main reason is that the PN junction generated by the interface between the substrate 125 and the epitaxial layer 101 is used as the etched substrate 125. Time etch barrier. As shown in FIG. 4A, a bottom passivation layer 114b is deposited over the bottom surface of the substrate 125, and an opening 114'b or a plurality of openings (not shown) are formed in the bottom passivation layer 114b (for the sake of brevity, only An opening is indicated). As shown in FIG. 4B, the PN junction generated by the interface between the substrate 125 and the epitaxial layer 101 is etched by the opening 114'b on the bottom passivation layer 114b under reverse bias conditions. Mainly electrochemical corrosion, the wet etching solution used in the electrochemical etching method is mainly tetramethylammonium hydroxide solution (TMAH) or potassium hydroxide solution (KOH), and the etching reaction stops when the etching reaches the PN junction. At this time, the etching precision is adjusted to be considered to substantially stop on the epitaxial layer 101, thereby forming a bottom recess 115' or a plurality of unillustrated bottom recesses in the substrate 125 by the etching process. As shown in FIG. 4C, a dopant of the same type as that of the epitaxial layer 101 is implanted in a region of the epitaxial layer 101 exposed at the top of the bottom recess 115'. This doping process is a heavily doped process to form A bottom electrode contact region 116 in the epitaxial layer 101 above the top of the bottom recess 115'. As shown in Fig. 4D, a metal layer (bottom metal layer) 117 is deposited overlying the bottom surface of the substrate 125, which also covers the sidewalls and top of the bottom recess 115'. Wherein, the region of the metal layer 117 located at the top of the bottom recess 115' maintains good ohmic contact with the bottom electrode contact region 116, and the first metal electrode composed of the metal layer 117 is the drain of the power MOS transistor device 100'A. The pole electrode, the second metal electrode 113A constitutes the source electrode of the power MOS transistor device 100'A, and the third metal electrode 113B constitutes the gate electrode of the power MOS transistor device 100'A. Wherein, if the substrate 125 is a lightly doped P-type substrate, the epitaxial layer 101 is lightly doped N-type In the extension layer, the dopant of the first conductivity type may be a P-type ion, the dopant of the second conductivity type may be an N-type ion, and the vertical MOS transistor unit is an N-channel trench MOS Transistor. If the substrate 125 is a lightly doped N-type substrate, the epitaxial layer 101 is a lightly doped P-type epitaxial layer, the aforementioned first conductivity type dopant may be an N-type ion, and the second conductivity type dopant may be In the case of a P-type ion, the vertical MOS transistor unit is a P-channel trench MOS transistor.

實施方式三： Embodiment 3:

參見第2C-1至2C-2圖及第5A-5D圖所示，在晶圓100”中，外延層101雖然是生長在襯底125上，但是之前先在襯底125的頂面植入一層重摻雜物以形成的一層掩埋重摻雜層120”，所以認為外延層101和襯底125之間間隔了一層掩埋重摻雜層120”。若是前述製備垂直MOS電晶體單元是在晶圓100”中實施的，那麼在第5A圖所示的外延層101中製備垂直MOS電晶體單元與實施方式一中的流程並無差異。此時主要是利用掩埋重摻雜層120”作為刻蝕襯底125時的刻蝕阻擋層。一種可選方式是，從輕摻雜的P-型襯底125的頂面注入一層重摻雜的P+型掩埋重摻雜層120”，例如重摻雜的硼摻雜層，其摻雜濃度超過1e19/cm3。再在襯底125上生長輕摻雜的P-型外延層101。須注意的是，由於外延層101、掩埋重摻雜層120”和襯底125的摻雜類型相同，則受柵多晶矽105’控制的電流可以從頂部電極摻雜區108經體區107流向外延層101的底面並繼續流向襯底的底面(或相反)，所以稱襯底125的底面構成垂直MOS電晶體單元的底部電極(如漏極)。如第5B圖所示，沉積一層底部鈍化層114b覆蓋在襯底125的底面上，在底部鈍化層114b中形成一個開口114’b或多個未示出的開口，利用底部鈍化層114b上的開口114’b對襯底125進行刻蝕，刻蝕停止在由掩埋重摻雜層120”所構成的刻蝕阻擋層上，並通過該刻蝕過程形成襯底125中的一個底部凹槽115’或多個未示出的底部凹槽，如第5C圖所示。再如第5D圖所示，沉積一層金屬層(底部金屬層)117覆蓋在襯底125的底面上，該金屬層117還同時覆蓋在底部凹槽115’的側壁和頂部上，其中，金屬層117位於底部凹槽115’的頂部的區域與掩埋重摻雜層120”保持良好的歐姆接觸，並且由金屬層117所構成的第一金屬電極為功率MOS電晶體裝置100”A的漏極電極，第二金屬電極113A構成功率MOS電晶體裝置100”A的源極電極，第三金屬電極113B構成功率MOS電晶體裝置100”A的柵極電極。前述第一導電類型的摻雜物可為N型的離子，第二導電類型的摻雜物可為P型的離子，則此時垂直MOS電晶體單元為P型溝道的溝槽式MOS電晶體。 Referring to FIGS. 2C-1 to 2C-2 and 5A-5D, in the wafer 100", the epitaxial layer 101 is grown on the substrate 125 but previously implanted on the top surface of the substrate 125. A layer of heavily doped material is formed to bury the heavily doped layer 120", so that a layer of buried heavily doped layer 120" is considered to be interposed between the epitaxial layer 101 and the substrate 125. If the foregoing preparation of the vertical MOS transistor unit is in the crystal In the case of the circle 100", the preparation of the vertical MOS transistor unit in the epitaxial layer 101 shown in FIG. 5A is not different from the flow in the first embodiment. At this time, the heavily doped layer 120" is mainly used as an etch barrier when etching the substrate 125. Alternatively, a heavily doped layer is implanted from the top surface of the lightly doped P-type substrate 125. The P+ type buried heavily doped layer 120", such as a heavily doped boron doped layer, has a doping concentration in excess of 1e19/cm3. A lightly doped P-type epitaxial layer 101 is then grown on the substrate 125. It should be noted that since the doping type of the epitaxial layer 101, the buried heavily doped layer 120" and the substrate 125 are the same, the current controlled by the gate polysilicon 105' can flow from the top electrode doping region 108 to the epitaxial region 107. The bottom surface of layer 101 continues to flow to the bottom surface of the substrate (or vice versa), so the bottom surface of substrate 125 is referred to A bottom electrode (such as a drain) that constitutes a vertical MOS transistor unit. As shown in FIG. 5B, a bottom passivation layer 114b is deposited over the bottom surface of the substrate 125, and an opening 114'b or a plurality of openings, not shown, are formed in the bottom passivation layer 114b, using the bottom passivation layer 114b. The opening 114'b etches the substrate 125, the etch stops on the etch stop layer formed by the buried heavily doped layer 120", and a bottom recess 115 in the substrate 125 is formed by the etching process. 'Or a plurality of bottom grooves not shown, as shown in Fig. 5C. As shown in Fig. 5D, a metal layer (bottom metal layer) 117 is deposited over the bottom surface of the substrate 125, the metal layer 117. It also covers both the sidewalls and the top of the bottom recess 115', wherein the region of the metal layer 117 at the top of the bottom recess 115' maintains good ohmic contact with the buried heavily doped layer 120" and is covered by the metal layer 117. The first metal electrode is a drain electrode of the power MOS transistor device 100"A, the second metal electrode 113A constitutes a source electrode of the power MOS transistor device 100"A, and the third metal electrode 113B constitutes a power MOS transistor device. 100"A gate electrode. The first guide Type dopant may be an N-type ion, trench MOS transistor of the second conductivity type dopant may be a P-type ions, at this time, the vertical MOS transistor is a P-type channel unit.

實施方式四： Embodiment 4:

參見第2B圖及第6圖所示，在晶圓100'中，外延層101是直接生長在襯底125上，若是前述製備垂直MOS電晶體單元是在晶圓100'中實施的，那麼在外延層101中製備垂直MOS電晶體單元與實施方式一中的流程並無差異，所以襯底125所支撐的外延層101中形成有相同的垂直MOS電晶體單元。此時襯底125與外延層101的摻雜類型相同，但襯底125為重摻雜而外延層101為輕摻雜。由於外延層101和襯底125的摻雜類型相同，則受柵多晶矽105'控制的電流可以從頂部電極摻雜區108經體區107流向外延層101的底面並繼續流向襯底的底面(或相反)，所以認為襯底125的底面構成垂直MOS電晶體單元的底部電極(如漏極)。可以沉積一層底部鈍化層(未示出)覆蓋在襯底125的底面上，並在底部鈍化層中形成一個或多個開口，利用底部鈍化層上的開口對襯底125進行刻蝕，刻蝕停止在襯底125中，並通過該刻蝕過程形成襯底125中的一個或多個底部通孔118，此時底部通孔118的形成可利用幹法刻蝕或鐳射刻蝕等刻蝕手段，而且必須保障底部通孔118的頂部距離外延層101還有一段距離，通常在對襯底進行刻蝕的過程中進行時間或他刻蝕因素控制，以使得所形成的底部通孔118的頂部與外延層101的頂面之間的距離X1保持在5um至20um之間。在底部通孔118的側壁和頂部沉積一層勢壘材料層(如Ti/TiN，未示出)之後，再在側壁和頂部襯墊有勢壘材料層的底部通孔118中進行化學氣相沉積而填充導電材料(如鎢)119，再沉積一層金屬層(底部金屬層)117覆蓋在襯底125的底面上，該金屬層117還同時與底部通孔118中所填充的導電材料119保持電性接觸，其中，由金屬層117所構成的第一金屬電極為功率MOS電晶體裝置100'B的漏極電極，第二金屬電極113A構成功率MOS電晶體裝置100'B的源極電極，第三金屬電極113B構成功率MOS電晶體裝置100'B的柵極電極。此時如果襯底125為重摻雜N型襯底，外延層101為輕摻雜N型外延層，前述第一導電類型的摻雜物可為P型的離子，第二導電類型的摻雜物可為N型的離子，則垂直MOS電晶體單元為N型溝道的溝槽式MOS電晶體。如果襯底125為重摻雜P型襯底，外延層101為輕摻雜P型外延層，前述第一導電類型的摻雜物可為N型的離子，第二導電類型的摻雜物可為P型的離子，則垂直MOS電晶體單元為P型溝道的溝槽式MOS電晶體。 Referring to FIGS. 2B and 6 , in the wafer 100 ′, the epitaxial layer 101 is directly grown on the substrate 125 . If the foregoing prepared vertical MOS transistor unit is implemented in the wafer 100 ′, then The vertical MOS transistor unit prepared in the epitaxial layer 101 is not different from the flow in the first embodiment, so that the epitaxial layer 101 supported by the substrate 125 is formed in the same manner. Vertical MOS transistor unit. At this time, the doping type of the substrate 125 and the epitaxial layer 101 are the same, but the substrate 125 is heavily doped and the epitaxial layer 101 is lightly doped. Since the doping type of the epitaxial layer 101 and the substrate 125 are the same, the current controlled by the gate polysilicon 105' can flow from the top electrode doping region 108 through the body region 107 to the bottom surface of the epitaxial layer 101 and continue to flow to the bottom surface of the substrate (or Conversely, it is considered that the bottom surface of the substrate 125 constitutes the bottom electrode (e.g., the drain) of the vertical MOS transistor unit. A bottom passivation layer (not shown) may be deposited over the bottom surface of the substrate 125, and one or more openings may be formed in the bottom passivation layer, and the substrate 125 may be etched and etched using an opening in the bottom passivation layer. Stopping in the substrate 125 and forming one or more bottom vias 118 in the substrate 125 by the etching process. At this time, the bottom vias 118 can be formed by etching such as dry etching or laser etching. And it must be ensured that the top of the bottom via 118 is still some distance away from the epitaxial layer 101, usually during the etching of the substrate, or by the etching factor, so that the top of the bottom via 118 is formed. The distance X1 from the top surface of the epitaxial layer 101 is maintained between 5 um and 20 um. After depositing a layer of barrier material (such as Ti/TiN, not shown) on the sidewalls and top of the bottom via 118, chemical vapor deposition is performed in the sidewall vias 118 of the sidewall and top pad with barrier material layers. A conductive material (such as tungsten) 119 is filled, and a metal layer (bottom metal layer) 117 is deposited on the bottom surface of the substrate 125. The metal layer 117 is also electrically insulated from the conductive material 119 filled in the bottom via 118. Sexual contact, wherein the first metal electrode composed of the metal layer 117 is the drain electrode of the power MOS transistor device 100'B, and the second metal electrode 113A constitutes the source electrode of the power MOS transistor device 100'B, The trimetal electrode 113B constitutes the gate electrode of the power MOS transistor device 100'B. At this time, if the substrate 125 is a heavily doped N-type substrate, the epitaxial layer 101 is a lightly doped N-type epitaxial layer, and the dopant of the first conductivity type may be a P-type ion, and the second conductivity type dopant The N-type ion may be an N-channel trench MOS transistor. If the substrate 125 is a heavily doped P-type substrate, the epitaxial layer 101 is a lightly doped P-type epitaxial layer, the aforementioned first conductivity type dopant may be an N-type ion, and the second conductivity type dopant may be For the P-type ions, the vertical MOS transistor unit is a P-channel trench MOS transistor.

實施方式五： Embodiment 5:

此實施方式與實施方式四的相同點在於，均是針對第2B圖所示的晶圓100'而採取的製備方法，均是在襯底125所支撐的外延層101中形成有垂直MOS電晶體單元，且襯底125與外延層101的摻雜類型相同，但襯底125為重摻雜而外延層101為輕摻雜。此實施例中，先沉積一層底部鈍化層(未示出)覆蓋在襯底125的底面上，再在底部鈍化層中形成一個或多個開口(未示出)，並利用底部鈍化層上的開口對襯底125進行濕法刻蝕，刻蝕停止在襯底125中，並通過該刻蝕過程形成襯底125中的一個底部凹槽115'或多個底部凹槽115'，一般情況下可調整刻蝕時間或其他刻蝕因素，而使得底部凹槽115'的頂部與外延層101的頂面之間的距離X2保持在10um至20um之間。之後沉積一層金屬層(底部金屬層)117覆蓋在襯底125的底面上，該金屬層117還同時覆蓋在底部凹槽115'的側壁和頂部上，其中，由金屬層117所構成的第一金屬電極為功率MOS電晶體裝置100"B的漏極電極，第二金屬電極113A構成功率MOS電晶體裝置100"B的源極電極，第三金屬電極113B構成功率MOS電晶體裝置100"B的柵極電極。此時如果襯底125為重摻雜N型襯底，外延層101為輕摻雜N型外延層，前述第一導電類型的摻雜物可為P型的離子，第二導電類型的摻雜物可為N型的離子，則垂直MOS電晶體單元為N型溝道的溝槽式MOS電晶體。如果襯底125為重摻雜P型襯底，外延層101為輕摻雜P型外延層，前述第一導電類型的摻雜物可為N型的離子，第二導電類型的摻雜物可為P型的離子，則垂直MOS電晶體單元為P型溝道的溝槽式MOS電晶體。 This embodiment is the same as the fourth embodiment in that it is a preparation method for the wafer 100' shown in FIG. 2B, in which a vertical MOS transistor is formed in the epitaxial layer 101 supported by the substrate 125. The cell, and the doping type of the substrate 125 and the epitaxial layer 101 are the same, but the substrate 125 is heavily doped and the epitaxial layer 101 is lightly doped. In this embodiment, a bottom passivation layer (not shown) is first deposited over the bottom surface of the substrate 125, and one or more openings (not shown) are formed in the bottom passivation layer, and the bottom passivation layer is utilized. The opening is wet etched on the substrate 125, the etching is stopped in the substrate 125, and a bottom recess 115' or a plurality of bottom recesses 115' in the substrate 125 are formed by the etching process. The etching time or other etching factor can be adjusted such that the distance X2 between the top of the bottom recess 115' and the top surface of the epitaxial layer 101 is maintained between 10 um and 20 um. A metal layer (bottom metal layer) 117 is then deposited over the bottom surface of the substrate 125, which also covers the sidewalls of the bottom recess 115'. And the top portion, wherein the first metal electrode composed of the metal layer 117 is the drain electrode of the power MOS transistor device 100"B, and the second metal electrode 113A constitutes the source electrode of the power MOS transistor device 100"B, The third metal electrode 113B constitutes the gate electrode of the power MOS transistor device 100"B. At this time, if the substrate 125 is a heavily doped N-type substrate, the epitaxial layer 101 is a lightly doped N-type epitaxial layer, the aforementioned first conductivity type The dopant may be a P-type ion, the second conductivity type dopant may be an N-type ion, and the vertical MOS transistor unit is an N-channel trench MOS transistor. If the substrate 125 is heavy The P-type substrate is doped, the epitaxial layer 101 is a lightly doped P-type epitaxial layer, the dopant of the first conductivity type may be an N-type ion, and the dopant of the second conductivity type may be a P-type ion. Then, the vertical MOS transistor unit is a P-channel trench MOS transistor.

以上各實施例均是在體區107的位於第一類槽溝101'的較上部分的側壁周圍的區域中注入摻雜物，形成從體區107的頂面向下延伸至體區107中的一個頂部電極摻雜區108，通常這種垂直MOS電晶體單元的結構模式可以稱之為TC-MOS(Trench touch MOSFET)裝置。為了進一步闡明本發明的更為廣泛的適應範圍，依然用SOI晶圓100為例進行說明。第8A-8E圖展示了垂直MOS電晶體作為傳統Trench DMOS裝置的降低通態電阻的方法，其與第3A-3S圖的製備方式大致上一致，二者差異在於，只是在體區107的位於每個第一類槽溝101'的較上部分的側壁周圍的區域中注入第二導電類型的摻雜物，形成體區107中的多個頂部電極摻雜區108'，並且任意一個頂部電極摻雜區108'相對應的圍繞在一個第一類槽溝101'的較上部分的側壁的周圍，使得任意一個第一類槽溝101'均依次貫穿一個頂部電極摻雜區108'和體區107並延伸至外延層101位於體區107下方的區域中，如第8A圖所示。然後如第8B圖所示，沉積一絕緣介質層109覆蓋在外延層101上，絕緣介質層109同時還覆蓋在體區107、多個頂部電極摻雜區108'，以及覆蓋在第一類槽溝101'中所填充的柵多晶矽105'和第二類溝槽101"中所填充的柵極流道多晶矽105"上。然後如第8C圖所示，在絕緣介質層109中進行刻蝕，形成貫穿緣介質層109的多個第一類通孔110-1，以及形成至少一個貫穿緣介質層109並接觸第二類溝槽101"中填充的多晶矽(即柵極流道多晶矽105")的第二類通孔110'-1，並在體區107的暴露在第一類通孔110-1的底部的區域中注入重摻雜的第一導電類型的摻雜物，形成位於第一類通孔110-1的底部的接觸區110a-1，如第8D圖所示。再沉積一層勢壘材料層(未示出)112覆蓋在絕緣介質層109上，勢壘材料層112同時還覆蓋在第一類通孔110-1、第二類通孔110'-1各自的底部及側壁上。再在第二類通孔110'-1中填充導電材料(如鎢)111，並沉積一層金屬層(未示出)113覆蓋在勢壘材料層112位於絕緣介質層109上方的區域上，且該金屬層113的一部分113A-2還填充在第一類通孔110-1中，該金屬層113同時還覆蓋在第二類通孔110'-1中所填充的導電材料111上並與之形成電接觸。對金屬層113和勢壘材料層112位於絕緣介質層109上方的區域進行刻蝕，將金屬層113進行分割以形成第二金屬電極113A-1和第三金屬電極113B-1，第二金屬電極113A-1與金屬層113填充在第一類通孔110-1中的那一部分113A-2電性連接，第三金屬電極113B-1與第二類通孔110'-1中所填充的導電材料111電性連接，勢壘材料層112覆蓋在絕緣介質層109上方的區域經刻蝕後的剩餘部分112'a、112'b分別保留在第二金屬電極113A-1、第三金屬電極113B-1的下方。金屬層113填充在第一類通孔110-1中的那一部分113A-2構成互連接頭，將頂部電極摻雜區108'與體區107短接，重摻雜的接觸區110a-1與體區107的摻雜類型相同，並促進金屬層113填充在第一類通孔110-1中的部分113A-2與體區107的歐姆接觸。第8E圖中的底部凹槽115'的製備流程與第3O圖至第3S圖的方法或與其他前文所提供的方法並無差別。該製備垂直MOS電晶體單元和底部凹槽的方法，除了可以應用第2A圖所示的晶圓100以外，第2B、2C-2圖中所示的晶圓100'、100"也均適用，並且製備底部凹槽的方式也可以隨之進行適應性修正。由於前述內容已經充分揭露應對不同的晶圓(也即應對不同的刻蝕阻擋層)而可以對製備底部凹槽的方法進行調整，所以本案不再針對Trench DMOS而重複贅述底部凹槽的製備方法。 Each of the above embodiments injects dopants into the region of the body region 107 around the sidewall of the upper portion of the first type of trench 101', forming a region extending downward from the top surface of the body region 107 into the body region 107. A top electrode doped region 108, generally the structural mode of such a vertical MOS transistor unit can be referred to as a TC-MOS (Trench touch MOSFET) device. In order to further clarify the broader scope of the present invention, the SOI wafer 100 is still described as an example. 8A-8E shows a vertical MOS transistor as a method for reducing the on-resistance of a conventional Trench DMOS device, which is substantially identical to the preparation method of the 3A-3S diagram, and the difference is that it is located only in the body region 107. A dopant of a second conductivity type is implanted into a region around a sidewall of the upper portion of each of the first type of trenches 101' to form a plurality of top electrode doped regions 108' in the body region 107, and any one of the top electrodes Doped region 108' corresponds Surrounding the sidewall of the upper portion of a first type of trench 101' such that any one of the first type of trenches 101' sequentially penetrates through a top electrode doped region 108' and body region 107 and extends to the epitaxial layer 101 is located in the area below the body area 107 as shown in Fig. 8A. Then, as shown in FIG. 8B, an insulating dielectric layer 109 is deposited over the epitaxial layer 101. The insulating dielectric layer 109 also covers the body region 107, the plurality of top electrode doped regions 108', and the first type of trenches. The gate polysilicon 105' filled in the trench 101' and the gate runner polysilicon 105" filled in the trench 101" of the second type. Then, as shown in FIG. 8C, etching is performed in the insulating dielectric layer 109 to form a plurality of first-type via holes 110-1 penetrating the edge dielectric layer 109, and at least one through-edge dielectric layer 109 is formed and in contact with the second type. The second type of via hole 110'-1 of the polysilicon (ie, the gate runner polysilicon 105" filled in the trench 101" is in the region of the body region 107 exposed at the bottom of the first type via 110-1 A heavily doped dopant of the first conductivity type is implanted to form a contact region 110a-1 at the bottom of the first type of via 110-1, as shown in FIG. 8D. A layer of barrier material (not shown) 112 is deposited over the insulating dielectric layer 109. The barrier material layer 112 also covers the first via 110-1 and the second via 110'-1. On the bottom and on the side walls. Further, a conductive material (such as tungsten) 111 is filled in the second type of via hole 110'-1, and a metal layer (not shown) 113 is deposited over the region of the barrier material layer 112 above the insulating dielectric layer 109, and A portion 113A-2 of the metal layer 113 is also filled in the first type of via hole 110-1, and the metal layer 113 also covers the conductive material 111 filled in the second type of via hole 110'-1 and is Electrical contact is formed. The metal layer 113 and the region of the barrier material layer 112 above the insulating dielectric layer 109 are etched, and the metal layer 113 is divided to form The second metal electrode 113A-1 and the third metal electrode 113B-1 are electrically connected to the portion 113A-2 of the metal layer 113 filled in the first type of via hole 110-1, and the third The metal electrode 113B-1 is electrically connected to the conductive material 111 filled in the second type of via hole 110'-1, and the barrier material layer 112 covers the remaining portion 112'a after etching in the region above the insulating dielectric layer 109. The 112'b remains below the second metal electrode 113A-1 and the third metal electrode 113B-1, respectively. The portion 113A-2 of the metal layer 113 filled in the first type of via hole 110-1 constitutes an interconnection joint, and the top electrode doping region 108' is shorted to the body region 107, and the heavily doped contact region 110a-1 is The doping type of the body region 107 is the same, and promotes the ohmic contact of the portion 113A-2 of the metal layer 113 filled in the first type of via hole 110-1 with the body region 107. The preparation process of the bottom groove 115' in Fig. 8E is not different from the method of Figs. 3O to 3S or other methods previously provided. The method of preparing the vertical MOS transistor unit and the bottom recess, in addition to the wafer 100 shown in FIG. 2A, the wafers 100', 100" shown in FIGS. 2B and 2C-2 are also applicable. Moreover, the manner of preparing the bottom groove can also be adaptively corrected. Since the foregoing has fully revealed that the method of preparing the bottom groove can be adjusted to cope with different wafers (that is, to deal with different etch barrier layers), Therefore, in this case, the preparation method of the bottom groove is not repeated for the Trench DMOS.

如第9A圖所示的功率MOS電晶體裝置200，此時原本鑄造連接在一起並共同位於一個晶圓上的大量功率MOS電晶體裝置200被從晶圓上切割分離下來而形成單獨的晶片，在其襯底125(未示意出)中形成有一個或多個底部凹槽115'後，作為一種選擇方式，該多個底部凹槽115' 中的所有底部凹槽115'共同組合在一起構成一個矩陣。底部凹槽115'位於功率MOS電晶體裝置200的底面202的一側，值得注意的是，金屬層117並未在第9A圖中示意出來。而其由金屬層117所構成的第一金屬電極為功率MOS電晶體裝置200的漏極電極，第二金屬電極構成MOS電晶體裝置200的源極電極，第三金屬電極構成功率MOS電晶體裝置200的柵極電極，第二金屬電極、第三金屬電極均位於功率MOS電晶體裝置200的頂面201的一側。為了降低MOS的通態電阻，還可以在如第9B圖所示的基座300的頂面301上製備凸出於基座300的頂面301的數個金屬凸塊315，金屬凸塊315的數量與底部凹槽115'的數量保持一致，並且金屬凸塊315的形貌與底部凹槽115'的槽體結構相適配。例如假定金屬凸塊315為四棱臺，則底部凹槽115'的槽體結構為四棱臺式的空腔並且其空腔體積以適合金屬凸塊315剛好嵌入為佳；金屬凸塊315的形貌還可以為其他類型如正方體、長方體、圓柱、圓臺等，此時要求底部凹槽115'的槽體結構(腔體形貌)隨之變化。其次，利用導電粘合材料320(如導電銀漿或焊錫膏等)將功率MOS電晶體裝置200粘貼在基座300的頂面301，其中，任意一個金屬凸塊315相對應的嵌入在一個底部凹槽115'中，並且導電粘合材料320位於金屬層117與基座301之間，導電粘合材料320還填充在底部凹槽115'的頂部與金屬凸塊315之間，及導電粘合材料320填充在底部凹槽115'的側壁與金屬凸塊315之間，如第10圖所示的功率MOS電晶體裝置200與基座300完成粘帖後二者的橫截面示意圖。第9B圖中基座300附近所設置的源極引線基座302可以通過額外的金屬導線或金屬片/帶等用於與第二金屬電極進行電性連接，從而作為功率MOS電晶體裝置200的源極引腳；基座300附近所設置的柵極引線基座303可以通過額外的金屬導線或金屬片/帶等用於與第三金屬電極進行電性連接，從而作為功率MOS電晶體裝置200的柵極引腳；較寬的基座300則可直接作為功率MOS電晶體裝置200的漏極引腳和散熱盤。必須提出的是，為了增強功率MOS電晶體裝置200和基座300之間的粘附能力，減少二者之間的導電粘合材料320中的氣泡等空洞，以避免功率MOS電晶體裝置200從基座300上脫離，可以在抽取真空的環境下將功率MOS電晶體裝置200粘貼在基座300的頂面301上。在另一種實施方案中，如第11圖所示，甚至於可以直接將功率MOS電晶體裝置200粘貼在基座400的頂面401上，注意此時在基座400的頂面401上並未設置任何類似金屬凸塊之類的突起物，而是將導電粘合材料320塗覆在基座400的頂面401上，並直接將功率MOS電晶體裝置200粘貼在基座400上後，導電粘合材料320不僅位於金屬層117(未示出)與基座301之間，並且部分導電粘合材料320還填充在底部凹槽115'中，同樣，為了減少底部凹槽115'中的氣泡(Void)量，此粘貼過程同樣也可以在真空的環境下進行。可見，與底部凹槽115'相適配的該基座300、400或類似的引線框架均能提供較好的低電阻封裝模型。 The power MOS transistor device 200 shown in FIG. 9A, in which a large number of power MOS transistor devices 200 originally connected together and co-located on one wafer are cut and separated from the wafer to form a separate wafer. After forming one or more bottom recesses 115' in its substrate 125 (not shown), as an alternative, the plurality of bottom recesses 115' All of the bottom grooves 115' in the group are combined to form a matrix. The bottom recess 115' is located on one side of the bottom surface 202 of the power MOS transistor device 200. It is noted that the metal layer 117 is not illustrated in FIG. 9A. The first metal electrode composed of the metal layer 117 is the drain electrode of the power MOS transistor device 200, the second metal electrode constitutes the source electrode of the MOS transistor device 200, and the third metal electrode constitutes the power MOS transistor device. The gate electrode of 200, the second metal electrode, and the third metal electrode are all located on one side of the top surface 201 of the power MOS transistor device 200. In order to reduce the on-resistance of the MOS, a plurality of metal bumps 315 protruding from the top surface 301 of the susceptor 300 may be prepared on the top surface 301 of the susceptor 300 as shown in FIG. 9B, the metal bumps 315 The number is consistent with the number of bottom recesses 115' and the topography of the metal bumps 315 is adapted to the slot structure of the bottom recess 115'. For example, assuming that the metal bump 315 is a quadrangular prism, the groove structure of the bottom groove 115' is a quadrangular cavity and the cavity volume thereof is preferably embedded in the metal bump 315; the metal bump 315 is preferably The topography may also be other types such as a cube, a cuboid, a cylinder, a truncated cone, etc., in which case the groove structure (cavity topography) of the bottom groove 115' is required to vary. Next, the power MOS transistor device 200 is pasted on the top surface 301 of the susceptor 300 by using a conductive bonding material 320 (such as a conductive silver paste or solder paste, etc.), wherein any one of the metal bumps 315 is correspondingly embedded in a bottom portion. In the recess 115', and the conductive adhesive material 320 is located between the metal layer 117 and the susceptor 301, the conductive adhesive material 320 is also filled between the top of the bottom recess 115' and the metal bump 315, and conductive bonding The material 320 is filled between the sidewall of the bottom recess 115' and the metal bump 315. As shown in FIG. 10, the power MOS transistor device 200 and the susceptor 300 are pasted together. Schematic diagram of the section. The source lead pedestal 302 disposed near the susceptor 300 in FIG. 9B may be electrically connected to the second metal electrode through an additional metal wire or a metal piece/band or the like, thereby serving as the power MOS transistor device 200. The source lead; the gate lead pedestal 303 disposed near the susceptor 300 can be electrically connected to the third metal electrode through an additional metal wire or a metal piece/band or the like, thereby serving as the power MOS transistor device 200. The gate pin; the wider pedestal 300 can be directly used as the drain pin and the heat sink of the power MOS transistor device 200. It has to be mentioned that in order to enhance the adhesion between the power MOS transistor device 200 and the susceptor 300, voids such as bubbles in the conductive bonding material 320 between the two are reduced to avoid the power MOS transistor device 200 from The susceptor 300 is detached, and the power MOS transistor device 200 can be attached to the top surface 301 of the susceptor 300 in a vacuum-extracting environment. In another embodiment, as shown in FIG. 11, even the power MOS transistor device 200 can be directly pasted on the top surface 401 of the susceptor 400, noting that it is not present on the top surface 401 of the susceptor 400. Any protrusions like metal bumps are provided, but the conductive bonding material 320 is coated on the top surface 401 of the susceptor 400, and the power MOS transistor device 200 is directly pasted on the susceptor 400, and is electrically conductive. The adhesive material 320 is not only located between the metal layer 117 (not shown) and the susceptor 301, and a portion of the conductive adhesive material 320 is also filled in the bottom recess 115', as well as to reduce air bubbles in the bottom recess 115'. (Void) amount, this pasting process can also be carried out under vacuum. It can be seen that the pedestal 300, 400 or similar lead frame that fits the bottom recess 115' provides a better low resistance package model.

以上內容，均是以溝槽式柵極的垂直MOS電晶體裝置為例進行敍述說明，其實，平面柵極的垂直MOS電晶體裝置同樣適用，例如垂直雙擴散MOSFET(VDMOS)裝置。參見第12圖，在襯底125所支撐的外延層101中形成有垂直MOS電晶體單元，只不過垂直MOS電晶體單元的柵極是平面的而非溝槽式的，具體而言，位於外延層101中且在外延層101的頂面附近形成有VDMOS的體區607，以及外延層101中還形成有從體區607的頂面延伸至體區607中的頂部電極摻雜區(即源極區)608，並且體區607包圍在頂部電極摻雜區608的周圍。柵氧化層604設置在多晶矽柵極605下方，體區607的位於柵氧化層604和多晶矽柵極605下方的區域607a，並且該區域607a位於頂部電極摻雜區608與外延層101之間，從而區域607a構成VDMOS裝置的電流通道，電流從頂部電極摻雜區608經體區607橫向流動後垂直流向外延層101的底面，所以仍然可以認為外延層101的底面構成垂直MOS電晶體單元的底部電極(漏極)。勢壘材料層612和金屬層613A提供頂部電極摻雜區608和體區607之間的短路。刻蝕阻擋層120設置在外延層101與襯底125之間，形成了依次貫穿襯底125和刻蝕阻擋層120的一個底部凹槽115'或多個未示意出的底部凹槽。於外延層101的暴露在底部凹槽115'的頂部的區域內注入與外延層101摻雜類型相同的摻雜物，形成外延層101中位於底部凹槽115'的頂部的上方的重摻雜的底部電極接觸區116，金屬層(底部金屬層)117覆蓋在襯底125的底面上，金屬層117還同時覆蓋在底部凹槽115'的側壁和頂部上，金屬層117位於底部凹槽 115'頂部的區域與底部電極接觸區116保持接觸，並且金屬層117用於構成VDMOS裝置的第一金屬電極(漏極)，此時金屬層613A為第二金屬電極(源極電極)，而未示意出的並與多晶矽柵極605連接的金屬層構成第三金屬電極(柵極電極)。由於前述內容已經充分揭露應對不同的晶圓(也即應對不同的刻蝕阻擋層)而可以對製備底部凹槽的方法進行調整，所以本案不再針對VDMOS而重複贅述底部凹槽的製備方法。 The above content is a vertical MOS transistor with a trench gate The bulk device is described as an example. In fact, a vertical gate MOS transistor device of a planar gate is also applicable, such as a vertical double diffused MOSFET (VDMOS) device. Referring to FIG. 12, a vertical MOS transistor unit is formed in the epitaxial layer 101 supported by the substrate 125, except that the gate of the vertical MOS transistor unit is planar rather than trench type, specifically, epitaxial A body region 607 of the VDMOS is formed in the layer 101 and near the top surface of the epitaxial layer 101, and a top electrode doped region (ie, a source) extending from the top surface of the body region 607 to the body region 607 is also formed in the epitaxial layer 101. The polar region 608, and the body region 607 is surrounded by the top electrode doping region 608. A gate oxide layer 604 is disposed under the polysilicon gate 605, a region 607a of the body region 607 under the gate oxide layer 604 and the polysilicon gate 605, and the region 607a is located between the top electrode doping region 608 and the epitaxial layer 101, thereby The region 607a constitutes a current path of the VDMOS device. The current flows laterally from the top electrode doping region 608 through the body region 607 and then flows vertically to the bottom surface of the epitaxial layer 101. Therefore, it can be considered that the bottom surface of the epitaxial layer 101 constitutes the bottom electrode of the vertical MOS transistor unit. (drain). Barrier material layer 612 and metal layer 613A provide a short between top electrode doped region 608 and body region 607. The etch stop layer 120 is disposed between the epitaxial layer 101 and the substrate 125 to form a bottom recess 115' or a plurality of unillustrated bottom recesses that sequentially penetrate the substrate 125 and the etch stop layer 120. A dopant of the same type as that of the epitaxial layer 101 is implanted in a region of the epitaxial layer 101 exposed at the top of the bottom recess 115' to form a heavily doped layer in the epitaxial layer 101 above the top of the bottom recess 115'. The bottom electrode contact region 116, the metal layer (bottom metal layer) 117 covers the bottom surface of the substrate 125, the metal layer 117 also covers the sidewall and the top of the bottom recess 115', and the metal layer 117 is located at the bottom recess. The area at the top of 115' is in contact with the bottom electrode contact region 116, and the metal layer 117 is used to constitute the first metal electrode (drain) of the VDMOS device, at which time the metal layer 613A is the second metal electrode (source electrode), and A metal layer not shown and connected to the polysilicon gate 605 constitutes a third metal electrode (gate electrode). Since the foregoing has sufficiently revealed that the method of preparing the bottom groove can be adjusted to cope with different wafers (that is, to deal with different etch barrier layers), the method of preparing the bottom groove is not repeated for the VDMOS in this case.

儘管本申請並未單獨額外的對以上各種裝置結構進行詳細描述，但是由以上所羅列的方法所製備的半導體裝置的結構模式已經較為明瞭，而且通讀本申請內容，其裝置結構也全然體現在方法當中，所以本申請不再對裝置結構進行贅述。然而必須明確的是，本發明所要保護的低導通電阻的功率MOS電晶體裝置，是利用以上各方法所製備的。 Although the present application does not separately describe the above various device structures in detail, the structural mode of the semiconductor device prepared by the above-listed method is already clear, and the device structure is fully embodied in the method. In this regard, the description of the device structure will not be repeated in this application. However, it must be clarified that the low on-resistance power MOS transistor device to be protected by the present invention is prepared by the above methods.

通過說明和附圖，給出了具體實施方式的特定結構的典型實施例，例如，本案是以頂源底漏的垂直MOS電晶體進行闡述，基於本發明精神，晶片還可作其他類型的轉換，譬如將垂直MOS電晶體替換成頂漏底源的垂直MOS電晶體同樣是可行的。所以，儘管上述發明提出了現有的較佳實施例，然而，這些內容並不作為侷限。 Exemplary embodiments of a specific structure of a specific embodiment are given by way of illustration and the accompanying drawings. For example, the present invention is illustrated by a vertical MOS transistor with a top-source drain, and the wafer can be used for other types of conversions based on the spirit of the present invention. For example, a vertical MOS transistor in which a vertical MOS transistor is replaced with a top-drain bottom source is also feasible. Therefore, although the above invention proposes a prior preferred embodiment, these are not intended to be limiting.

對於本領域的技術人員而言，閱讀上述說明後，各種變化和修正無疑將顯而易見。因此，所附的申請專利範圍應看作是涵蓋本發明的真實意圖和範圍的全部變化和修正。在申請專利範圍內任何和所有等價的範圍與內容，都應認為仍屬本發明的意圖和範圍內。 Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Therefore, the scope of the appended claims should be construed as covering all changes in the true meaning and scope of the invention. And correction. Any and all equivalent ranges and contents within the scope of the claims are considered to be within the spirit and scope of the invention.

100A‧‧‧MOS電晶體裝置 100A‧‧‧MOS transistor device

101‧‧‧外延層 101‧‧‧ Epilayer

101’‧‧‧槽溝 101’‧‧‧ Groove

105’‧‧‧柵多晶矽 105'‧‧‧Gate Polysilicon

107‧‧‧體區 107‧‧‧ Body area

108‧‧‧頂部電極摻雜區 108‧‧‧Top electrode doped area

110、110’‧‧‧通孔 110, 110’‧‧‧ Through Hole

111‧‧‧導電材料 111‧‧‧Electrical materials

112‧‧‧勢壘材料層 112‧‧‧ barrier material layer

113A‧‧‧第二金屬電極 113A‧‧‧Second metal electrode

113B‧‧‧第三金屬電極 113B‧‧‧ Third metal electrode

115’‧‧‧底部凹槽 115’‧‧‧ bottom groove

116‧‧‧電極接觸區 116‧‧‧Electrode contact zone

125‧‧‧襯底 125‧‧‧Substrate

Claims

一種製備低導通電阻的垂直功率MOS電晶體裝置的方法，在一襯底所支撐的外延層中形成有垂直MOS電晶體單元，外延層的底面構成垂直MOS電晶體單元的底部電極，其中，該方法主要包括以下步驟：沉積一層底部鈍化層覆蓋在所述襯底的底面上；在底部鈍化層中形成一個或多個開口，利用底部鈍化層上的開口對襯底進行刻蝕，並通過該刻蝕過程形成貫穿襯底的一個或多個底部凹槽，暴露出所述外延層的一個底面；從所述襯底的底面注入與外延層摻雜類型相同的摻雜物，形成外延層底部對應於凹槽的重摻雜區；沉積一層金屬層覆蓋在所述襯底的底面上，該金屬層還同時覆蓋在所述底部凹槽的側壁和頂部上；其中，所述金屬層用於構成所述垂直功率MOS電晶體裝置的底部金屬電極；在一基座的頂面上製備凸出於基座的頂面的數個金屬凸塊，金屬凸塊的數量與所述底部凹槽的數量保持一致，並且金屬凸塊的形貌與所述底部凹槽的槽體結構相適配；以及利用導電粘合材料將功率電晶體裝置粘貼在基座的頂面，其中，任意一個金屬凸塊相對應的嵌入在一個底部凹槽中，並且導電粘合材料位於金屬層與基座之間，導電粘合材料還填充在底部凹槽的頂部與金屬凸塊之間及底部凹槽的側壁與金屬凸塊之間。 A method for preparing a low-on-resistance vertical power MOS transistor device, wherein a vertical MOS transistor unit is formed in an epitaxial layer supported by a substrate, and a bottom surface of the epitaxial layer constitutes a bottom electrode of a vertical MOS transistor unit, wherein The method mainly comprises the steps of: depositing a bottom passivation layer overlying the bottom surface of the substrate; forming one or more openings in the bottom passivation layer, etching the substrate with an opening on the bottom passivation layer, and passing the Etching process forming one or more bottom recesses through the substrate to expose a bottom surface of the epitaxial layer; implanting dopants of the same type as the epitaxial layer doping from the bottom surface of the substrate to form an epitaxial layer bottom Corresponding to the heavily doped region of the recess; depositing a metal layer overlying the bottom surface of the substrate, the metal layer also covering both the sidewall and the top of the bottom recess; wherein the metal layer is used for Forming a bottom metal electrode of the vertical power MOS transistor device; preparing a plurality of metal bumps protruding from a top surface of the pedestal on a top surface of the pedestal, the number of metal bumps and The number of bottom grooves is kept uniform, and the topography of the metal bumps is adapted to the groove structure of the bottom groove; and the power transistor device is pasted on the top surface of the base by using a conductive adhesive material, wherein Any one of the metal bumps is correspondingly embedded in a bottom recess, and the conductive adhesive material is located between the metal layer and the base, and the conductive adhesive material is further filled between the top of the bottom recess and the metal bump and Bottom concave Between the sidewall of the slot and the metal bump.

如申請專利範圍第1項所述的方法，其中，襯底與外延層都是輕摻雜。 The method of claim 1, wherein the substrate and the epitaxial layer are both lightly doped.

如申請專利範圍第2項所述的方法，其中，對襯底進行刻蝕是利用濕法刻蝕或深反應摻雜物刻蝕實現的。 The method of claim 2, wherein etching the substrate is performed by wet etching or deep reactive dopant etching.

如申請專利範圍第3項所述的方法，其中，對襯底進行濕法刻蝕所用到的刻蝕液為四甲基氫氧化銨溶液(TMAH)或氫氧化鉀溶液(KOH)或乙二胺鄰苯二酚溶液(EDP)。 The method of claim 3, wherein the etching solution used for wet etching the substrate is tetramethylammonium hydroxide solution (TMAH) or potassium hydroxide solution (KOH) or ethylene. Amine catechol solution (EDP).

如申請專利範圍第1項所述的方法，其中，在對襯底進行刻蝕的過程中，所形成的底部凹槽的頂部與外延層的頂面之間的距離保持在10um至20um之間。 The method of claim 1, wherein the distance between the top of the formed bottom groove and the top surface of the epitaxial layer is maintained between 10 um and 20 um during etching of the substrate. .

如申請專利範圍第2項所述的方法，其中，襯底與外延層的摻雜類型相反，在底部鈍化層中形成一個或多個開口，並且襯底與外延層兩者的交界面所產生的PN結在反偏的條件下，利用底部鈍化層上的開口對襯底利用電化學刻蝕法進行刻蝕，刻蝕停止在外延層上，並通過該刻蝕過程形成襯底中的一個或多個底部凹槽。 The method of claim 2, wherein the substrate is opposite to the doping type of the epitaxial layer, one or more openings are formed in the bottom passivation layer, and an interface between the substrate and the epitaxial layer is generated. The PN junction is etched by electrochemical etching using an opening on the bottom passivation layer under reverse bias conditions, etching is stopped on the epitaxial layer, and one of the substrates is formed by the etching process. Or multiple bottom grooves.

如申請專利範圍第1項所述的方法，其中，該襯底與外延層之間還設置有一層刻蝕阻擋層，利用底部鈍化層上的開口對襯底進行刻蝕，刻蝕停止在刻蝕阻擋層上，並通過該刻蝕過程形成襯底中的一個或多個凹槽；進一步對刻蝕阻擋層的暴露在凹槽中的區域進行刻蝕，刻蝕停止在外延層上，形成依次貫穿襯底和刻蝕阻擋層的一個或多個底部凹槽。 The method of claim 1, wherein an etching barrier layer is further disposed between the substrate and the epitaxial layer, and the substrate is etched by using an opening on the bottom passivation layer, and the etching is stopped. Etching the barrier layer and forming one or more recesses in the substrate by the etching process; further etching the region of the etch barrier layer exposed in the recess, and etching stops on the epitaxial layer to form Through the substrate and etch block One or more bottom grooves of the layer.

如申請專利範圍第7項所述的方法，其中，所述刻蝕阻擋層為一層掩埋二氧化矽層。 The method of claim 7, wherein the etch barrier layer is a layer of buried ruthenium dioxide layer.

如申請專利範圍第8項所述的方法，其特徵在於，對刻蝕阻擋層進行濕法刻蝕所用到的刻蝕液為緩衝氫氟酸溶液。 The method of claim 8, wherein the etching solution used for wet etching the etch barrier layer is a buffered hydrofluoric acid solution.

如申請專利範圍第8項所述的方法，其中，所述襯底與外延層的摻雜類型相同。 The method of claim 8, wherein the substrate and the epitaxial layer are of the same doping type.

一種製備低導通電阻的垂直功率MOS電晶體裝置的方法，在一襯底所支撐的外延層中形成有垂直MOS電晶體單元，外延層的底面構成垂直MOS電晶體單元的底部電極，其中，該方法主要包括以下步驟：沉積一層底部鈍化層覆蓋在所述襯底的底面上；在底部鈍化層中形成一個或多個開口，利用底部鈍化層上的開口對襯底進行刻蝕，並通過該刻蝕過程形成貫穿襯底的一個或多個底部凹槽，暴露出所述外延層的一個底面；從所述襯底的底面注入與外延層摻雜類型相同的摻雜物，形成外延層底部對應於凹槽的重摻雜區；沉積一層金屬層覆蓋在所述襯底的底面上，該金屬層還同時覆蓋在所述底部凹槽的側壁和頂部上；其中，所述金屬層用於構成所述垂直功率MOS電晶體裝置的底部金屬電極；在沉積一層底部鈍化層覆蓋在襯底的底面上的同時，還沉積一層頂部鈍化層將頂部金屬電極予以覆蓋；之後將覆蓋頂部金屬電極的部分頂部鈍化層移除，以在頂部鈍化層中將頂部金屬電極予以暴露。 A method for preparing a low-on-resistance vertical power MOS transistor device, wherein a vertical MOS transistor unit is formed in an epitaxial layer supported by a substrate, and a bottom surface of the epitaxial layer constitutes a bottom electrode of a vertical MOS transistor unit, wherein The method mainly comprises the steps of: depositing a bottom passivation layer overlying the bottom surface of the substrate; forming one or more openings in the bottom passivation layer, etching the substrate with an opening on the bottom passivation layer, and passing the Etching process forming one or more bottom recesses through the substrate to expose a bottom surface of the epitaxial layer; implanting dopants of the same type as the epitaxial layer doping from the bottom surface of the substrate to form an epitaxial layer bottom Corresponding to the heavily doped region of the recess; depositing a metal layer overlying the bottom surface of the substrate, the metal layer also covering both the sidewall and the top of the bottom recess; wherein the metal layer is used for Forming a bottom metal electrode of the vertical power MOS transistor device; while depositing a bottom passivation layer overlying the bottom surface of the substrate, A top passivation layer is also deposited to cover the top metal electrode; a portion of the top passivation layer overlying the top metal electrode is then removed to expose the top metal electrode in the top passivation layer.

一種製備低導通電阻的垂直功率電晶體裝置的方法，在一襯底所支撐的外延層中形成有垂直電晶體單元，其中，該方法主要包括以下步驟：在一個輕摻雜的襯底上形成一個輕摻雜的外延層；在所述的外延層中形成垂直電晶體單元；沉積一層底部鈍化層覆蓋在所述襯底的底面上；在底部鈍化層中形成一個或多個開口，利用底部鈍化層上的開口對襯底進行刻蝕，並通過該刻蝕過程形成貫穿襯底的一個或多個底部凹槽，暴露出所述外延層的一個底面；沉積一層金屬層覆蓋在所述襯底的底面上，該金屬層還同時覆蓋在所述底部凹槽的側壁和頂部上；其中，所述金屬層用於構成所述垂直功率電晶體裝置的底部金屬電極；在沉積一層底部鈍化層覆蓋在襯底的底面上的同時，還沉積一層頂部鈍化層將頂部金屬電極予以覆蓋；之後將覆蓋頂部金屬電極的部分頂部鈍化層移除，以在頂部鈍化層中將頂部金屬電極予以暴露。 A method of fabricating a low-on-resistance vertical power transistor device, wherein a vertical transistor unit is formed in an epitaxial layer supported by a substrate, wherein the method mainly comprises the steps of: forming on a lightly doped substrate a lightly doped epitaxial layer; forming a vertical transistor unit in the epitaxial layer; depositing a bottom passivation layer overlying the bottom surface of the substrate; forming one or more openings in the bottom passivation layer, utilizing the bottom An opening on the passivation layer etches the substrate and forms one or more bottom recesses through the substrate through the etching process to expose a bottom surface of the epitaxial layer; depositing a metal layer over the lining On the bottom surface of the bottom, the metal layer also covers both the sidewall and the top of the bottom recess; wherein the metal layer is used to form the bottom metal electrode of the vertical power transistor device; and a bottom passivation layer is deposited While covering the bottom surface of the substrate, a top passivation layer is deposited to cover the top metal electrode; then the top portion of the top metal electrode is covered bluntly Layer is removed, so as to be exposed on the top in the top of the passivation layer is a metal electrode.

如申請專利範圍第12項所述的方法，其中，襯底與外延層的摻雜類型相反，在底部鈍化層中形成一個或多個開口，並且襯底與外延層兩者的交界面所產生的PN結在反偏的條件下，利用底部鈍化層上的開口對襯底利用電化學刻蝕法進行刻蝕，刻蝕停止在外延層上，並通過該刻蝕過程形成襯底中的一個或多個底部凹槽；從所述襯底的底面注入與外延層摻雜類型相同的摻雜物，形成外延層底部對應於凹槽的重摻雜區。 The method of claim 12, wherein the substrate is opposite to the doping type of the epitaxial layer, one or more openings are formed in the bottom passivation layer, and an interface between the substrate and the epitaxial layer is generated. PN junction Under reverse bias conditions, the substrate is etched by electrochemical etching using an opening in the bottom passivation layer, etching is stopped on the epitaxial layer, and one or more of the substrates are formed by the etching process. a bottom recess; implanting a dopant of the same type as the epitaxial layer doping from the bottom surface of the substrate to form a heavily doped region at the bottom of the epitaxial layer corresponding to the recess.

如申請專利範圍第12項所述的方法，其中，所述襯底與外延層的摻雜類型相同，該襯底與外延層之間還設置有一層刻蝕阻擋層，利用底部鈍化層上的開口對襯底進行刻蝕，刻蝕停止在刻蝕阻擋層上，並通過該刻蝕過程形成襯底中的一個或多個凹槽；進一步對刻蝕阻擋層的暴露在凹槽中的區域進行刻蝕，刻蝕停止在外延層上，形成依次貫穿襯底和刻蝕阻擋層的一個或多個底部凹槽；從所述襯底的底面注入與外延層摻雜類型相同的摻雜物，形成外延層底部對應於凹槽的重摻雜區。 The method of claim 12, wherein the substrate and the epitaxial layer have the same doping type, and an etch barrier layer is disposed between the substrate and the epitaxial layer, using the bottom passivation layer The opening etches the substrate, the etching stops on the etch barrier layer, and one or more recesses in the substrate are formed by the etching process; further exposing the etch barrier layer to the area exposed in the recess Etching, etching stops on the epitaxial layer, forming one or more bottom recesses sequentially penetrating through the substrate and the etch stop layer; implanting dopants of the same type as the epitaxial layer doping from the bottom surface of the substrate Forming a heavily doped region at the bottom of the epitaxial layer corresponding to the recess.

如申請專利範圍第12項所述的方法，其中，該襯底與外延層之間還設置有一層由掩埋重摻雜層所構成的刻蝕阻擋層。 The method of claim 12, wherein an etching barrier layer composed of a buried heavily doped layer is further disposed between the substrate and the epitaxial layer.

如申請專利範圍第15項所述的方法，其中，所述外延層為輕摻雜P型外延層，所述垂直MOS電晶體單元為P型溝道的溝槽式MOS電晶體。 The method of claim 15, wherein the epitaxial layer is a lightly doped P-type epitaxial layer, and the vertical MOS transistor unit is a P-type trenched MOS transistor.

如申請專利範圍第15項所述的方法，其中，所述掩埋重摻雜層為P型的重摻雜層，且該P型重摻雜層的摻雜濃度超過1e19/cm3。 The method of claim 15, wherein the buried heavily doped layer is a P-type heavily doped layer, and the P-type heavily doped layer has a doping concentration of more than 1e19/cm3.

一種低導通電阻的垂直功率電晶體裝置的封裝，包括安裝在一基座上的一個半導體晶片，其中，所述的半導體晶片包括：形成在一襯底所支撐的第一導電類型的外延層中的垂直電晶體單元，所述的襯底包括從底面貫穿襯底的一個或多個底部凹槽，暴露出所述外延層的一個底面；覆蓋在所述襯底的底面上的一層金屬層，該金屬層還同時覆蓋在所述底部凹槽的側壁和所述暴露出的外延層的底面上；其中，所述金屬層用於構成所述垂直功率電晶體裝置的底部金屬電極；其中，所述的基座的頂面上包含凸出於基座的頂面的數個金屬凸塊，金屬凸塊的數量與所述底部凹槽的數量保持一致，並且金屬凸塊的形貌與所述底部凹槽的槽體結構相適配；以及利用導電粘合材料將功率電晶體裝置粘貼在基座的頂面，其中，任意一個金屬凸塊相對應的嵌入在一個底部凹槽中，並且導電粘合材料位於金屬層與基座之間，導電粘合材料還填充在底部凹槽的頂部與金屬凸塊之間及底部凹槽的側壁與金屬凸塊之間。 A package of a low on-resistance vertical power transistor device comprising a semiconductor wafer mounted on a susceptor, wherein the semiconductor wafer comprises: formed in an epitaxial layer of a first conductivity type supported by a substrate a vertical transistor unit, the substrate comprising one or more bottom recesses extending through the substrate from the bottom surface to expose a bottom surface of the epitaxial layer; a metal layer overlying the bottom surface of the substrate, The metal layer also covers both the sidewall of the bottom recess and the bottom surface of the exposed epitaxial layer; wherein the metal layer is used to form a bottom metal electrode of the vertical power transistor device; The top surface of the pedestal includes a plurality of metal bumps protruding from the top surface of the pedestal, the number of metal bumps is consistent with the number of the bottom recesses, and the topography of the metal bumps is The groove structure of the bottom groove is adapted; and the power transistor device is pasted on the top surface of the base by using a conductive adhesive material, wherein any one of the metal bumps is correspondingly embedded in a bottom groove And the conductive bonding material is located between the metal layer and the base, the conductive bonding material is also filled between the side walls and the bottom of the groove and the metal bump between the top and bottom of the groove of the metal bumps.

如申請專利範圍第18項所述的低導通電阻的垂直功率電晶體裝置的封裝，其中，所述襯底與外延層的摻雜類型相反，在所述襯底與外延層兩者的交界面形成PN結。 The package of a low-on-resistance vertical power transistor device according to claim 18, wherein the substrate is opposite to the doping type of the epitaxial layer at an interface between the substrate and the epitaxial layer A PN junction is formed.

如申請專利範圍第19項所述的低導通電阻的垂直功率電晶體裝置的封裝，其中，所述襯底為輕摻雜。 Vertical of low on-resistance as described in claim 19 A package for a power transistor device, wherein the substrate is lightly doped.

如申請專利範圍第18項所述的低導通電阻的垂直功率電晶體裝置的封裝，其中，該襯底與外延層之間還設置有一層掩埋二氧化矽刻蝕阻擋層，所述的底部凹槽貫穿掩埋二氧化矽刻蝕阻擋層。 The package of the low-on-resistance vertical power transistor device of claim 18, wherein a buried cerium oxide etch barrier layer is disposed between the substrate and the epitaxial layer, the bottom concave portion The trench penetrates the buried cerium oxide etch barrier layer.

一種低導通電阻的垂直功率電晶體裝置的封裝，包括安裝在一基座上的一個半導體晶片，其中，所述的半導體晶片包括：形成在一襯底所支撐的第一導電類型的外延層中的垂直電晶體單元，所述的襯底包括從底面貫穿襯底的一個或多個底部凹槽，暴露出所述外延層的一個底面；覆蓋在所述襯底的底面上的一層金屬層，該金屬層還同時覆蓋在所述底部凹槽的側壁和所述暴露出的外延層的底面上；其中，所述金屬層用於構成所述垂直功率電晶體裝置的底部金屬電極所述的基座包含一個平整的頂面，利用導電粘合材料將功率電晶體裝置粘貼在基座的頂面，其中，所述的底部凹槽還填充與所述的基座不同材料的導電材料。 A package of a low on-resistance vertical power transistor device comprising a semiconductor wafer mounted on a susceptor, wherein the semiconductor wafer comprises: formed in an epitaxial layer of a first conductivity type supported by a substrate a vertical transistor unit, the substrate comprising one or more bottom recesses extending through the substrate from the bottom surface to expose a bottom surface of the epitaxial layer; a metal layer overlying the bottom surface of the substrate, The metal layer also covers both the sidewall of the bottom recess and the bottom surface of the exposed epitaxial layer; wherein the metal layer is used to form the base of the bottom metal electrode of the vertical power transistor device The seat includes a flat top surface, and the power transistor device is adhered to the top surface of the base by a conductive adhesive material, wherein the bottom groove further fills a conductive material of a different material from the base.