TWI416726B - Power mosfet device with an added tungsten spacer in its contact hole and the manufacturing method - Google Patents
Power mosfet device with an added tungsten spacer in its contact hole and the manufacturing method Download PDFInfo
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本發明屬於半導體晶片製造領域，尤其涉及一種在接觸孔中設置鎢間隔層的功率MOSFET(金屬氧化物半導體場效應電晶體)裝置及其製造方法。 The invention belongs to the field of semiconductor wafer manufacturing, and in particular to a power MOSFET (metal oxide semiconductor field effect transistor) device in which a tungsten spacer layer is disposed in a contact hole and a manufacturing method thereof.
如第1圖所示，為現有技術中的功率MOSFET裝置的結構示意圖，該MOSFET裝置具有一作為漏極的底部基底1’；在該底部基底1’之上形成有體區域2’。在該體區域2’中開設有若干貫穿該體區域2’並延伸至底部基底1’中一定深度的溝槽，在所述的溝槽中設置溝槽閘極3’，並且在該溝槽中還設置有沿溝槽側壁和底部形成的較薄閘極絕緣層31’，其用於將溝槽閘極3’與底部基底1’以及體區域2’絕緣隔離。在所述的體區域2’中且圍繞每個溝槽的頂部部分，形成有源極區域4’。在該體區域2’、源極區域4’及溝槽的頂部表面上還依次沉積有低溫氧化層5’和硼磷矽玻璃層6’。 As shown in Fig. 1, it is a schematic structural view of a prior art power MOSFET device having a bottom substrate 1' as a drain; a body region 2' is formed on the bottom substrate 1'. A plurality of grooves extending through the body region 2' and extending to a certain depth in the bottom substrate 1' are formed in the body region 2', and a trench gate 3' is disposed in the trench, and the trench is provided in the trench There is also provided a thinner gate insulating layer 31' formed along the sidewalls and bottom of the trench for isolating the trench gate 3' from the bottom substrate 1' and the body region 2'. In the body region 2' and around the top portion of each trench, a source region 4' is formed. A low temperature oxide layer 5' and a borophosphonium glass layer 6' are sequentially deposited on the body region 2', the source region 4', and the top surface of the trench.
對所述的低溫氧化層5’及硼磷矽玻璃層6’進行刻蝕，從而在其中貫穿開設有若干接觸孔7’；其中一部分接觸孔形成在體區域2’及源極區域4’上，而另一部分形成在溝槽閘極3’上(圖中未示出)。在該硼磷矽玻璃層6’的頂部表面上及各個接觸孔7’內沉積有鋁金屬層10’。 The low temperature oxide layer 5' and the borophosphosilicate glass layer 6' are etched so as to have a plurality of contact holes 7' formed therethrough; a part of the contact holes are formed on the body region 2' and the source region 4' And another portion is formed on the trench gate 3' (not shown). An aluminum metal layer 10' is deposited on the top surface of the borophosphon glass layer 6' and in each of the contact holes 7'.
在上述的功率MOSFET裝置中，由於矽在鋁材料中有一定 的固溶度，所以當沉積在接觸孔7’中的鋁金屬層10’直接和設置在其下方的體區域2’以及源極區域4’接觸時，或者當接觸孔7’中的鋁金屬層10’直接和設置在其下方的溝槽閘極3’接觸時，體區域2’以及源極區域4’中的矽，或者是溝槽閘極3’中的矽將擴散至鋁金屬層10’中溶解，從而造成鋁穿刺現象。所述的鋁穿刺現象會導致整個半導體裝置Idss漏電短路，影響產品的合格率。 In the above power MOSFET device, since germanium is fixed in the aluminum material Solid solubility, so when the aluminum metal layer 10' deposited in the contact hole 7' is directly in contact with the body region 2' and the source region 4' disposed therebelow, or when the aluminum metal in the contact hole 7' When the layer 10' is in direct contact with the trench gate 3' disposed under it, the germanium in the body region 2' and the source region 4', or the germanium in the trench gate 3' will diffuse to the aluminum metal layer. Dissolved in 10', causing aluminum puncture. The aluminum puncture phenomenon causes a leakage short circuit of the entire semiconductor device Ids, which affects the yield of the product.
所以，為了避免發生所提到的鋁穿刺現象，在目前的功率MOSFET裝置的製造工藝中，通常使用Ti/TiN(鈦/氮化鈦)來形成阻擋層以避免矽和鋁的直接接觸。如第1圖所示，即在硼磷矽玻璃層6’的頂部表面上及接觸孔7’的內表面上首先沉積Ti/TiN阻擋層8’，再在該Ti/TiN阻擋層8’的基礎上，沉積鋁金屬層10’以填充接觸孔7’，從而避免上述提到的矽和鋁直接接觸的情況。如第2圖所示，該方法的具體工藝步驟為：首先，在低溫氧化層5’及硼磷矽玻璃層6’中進行刻蝕以在其中貫穿形成若干接觸孔7’，該若干接觸孔分別形成在體區域2’及源極區域4’上，或者形成在溝槽閘極3’上。接著在硼磷矽玻璃層6’的頂部表面上及接觸孔7’的內表面上沉積Ti/TiN阻擋層8’。隨後在該Ti/TiN阻擋層8’上沉積正面鋁金屬層10’，並對該正面鋁金屬層10’進行光刻。最後對所述的鋁金屬層10’以及Ti/TiN阻擋層8’進行刻蝕。從而通過利用該Ti/TiN阻擋層8’來避免因矽和鋁的直接接觸而導致的鋁穿刺現象。 Therefore, in order to avoid the occurrence of the aluminum puncture phenomenon mentioned, in the current manufacturing process of the power MOSFET device, Ti/TiN (titanium/titanium nitride) is usually used to form the barrier layer to avoid direct contact between the crucible and the aluminum. As shown in FIG. 1, a Ti/TiN barrier layer 8' is first deposited on the top surface of the borophosphorus glass layer 6' and on the inner surface of the contact hole 7', and then on the Ti/TiN barrier layer 8'. In addition, the aluminum metal layer 10' is deposited to fill the contact holes 7', thereby avoiding the above-mentioned case where the tantalum and aluminum are in direct contact. As shown in FIG. 2, the specific process steps of the method are as follows: first, etching is performed in the low temperature oxide layer 5' and the borophosphonium glass layer 6' to form a plurality of contact holes 7' therethrough, the plurality of contact holes Formed on the body region 2' and the source region 4', respectively, or formed on the trench gate 3'. Next, a Ti/TiN barrier layer 8' is deposited on the top surface of the borophosphon glass layer 6' and on the inner surface of the contact hole 7'. A front aluminum metal layer 10' is then deposited on the Ti/TiN barrier layer 8', and the front aluminum metal layer 10' is photolithographically patterned. Finally, the aluminum metal layer 10' and the Ti/TiN barrier layer 8' are etched. Thereby, the aluminum puncture phenomenon due to the direct contact of the crucible and the aluminum is avoided by utilizing the Ti/TiN barrier layer 8'.
但是，由此工藝而會導致的另一個問題是，如果在接觸孔7’的底部角落有凹坑產生，則Ti/TiN阻擋層8’會因無法做到很好的臺階覆蓋以防止矽和鋁的直接接觸，在該接觸孔7’的底部角落71’處仍然會發生鋁穿刺的現象。 However, another problem caused by this process is that if pits are formed at the bottom corners of the contact holes 7', the Ti/TiN barrier layer 8' may be prevented from being well covered by a step to prevent the enthalpy. In the direct contact of aluminum, aluminum puncture still occurs at the bottom corner 71' of the contact hole 7'.
由於目前先進的半導體製造技術可以通過減小裝置的外形尺寸，來提高半導體裝置的集成度；例如，一些目前所使用的MOSFET中的晶胞節距尺寸(wall-to-wall pitch size)大約為1微米，從而導致接 觸孔的尺寸較小，以及導致源極區域/體區域的深度較淺。由此，Ti/TiN阻擋層較差的臺階覆蓋性將會導致更多的由於接觸孔底部角落存在凹坑而發生的鋁穿刺現象。所以在目前的半導體製造領域內，所述的鋁穿刺現象已經成為影響半導體產品品質的一個極為嚴重的問題。 Since the current advanced semiconductor manufacturing technology can improve the integration of semiconductor devices by reducing the external dimensions of the device; for example, some of the currently used MOSFETs have a wall-to-wall pitch size of approximately 1 micron, resulting in connection The size of the contact hole is small and the depth of the source area/body area is shallow. Thus, the poor step coverage of the Ti/TiN barrier layer will result in more aluminum punctures due to the presence of pits in the bottom corners of the contact holes. Therefore, in the current field of semiconductor manufacturing, the phenomenon of aluminum puncture has become an extremely serious problem affecting the quality of semiconductor products.
因此，需要提供一種功率MOSFET裝置的結構，以防止在接觸孔底部角落發生鋁穿刺現象。 Therefore, it is desirable to provide a structure of a power MOSFET device to prevent aluminum puncture in the bottom corner of the contact hole.
本發明的目的在於提供一種新型的功率MOSFET裝置及其製造方法，其在接觸孔中設置鎢間隔層以完全克服鋁穿刺的問題，從而有效防止半導體裝置因Idss漏電短路而失效，保證產品的合格率。 The object of the present invention is to provide a novel power MOSFET device and a manufacturing method thereof, which are provided with a tungsten spacer layer in a contact hole to completely overcome the problem of aluminum puncture, thereby effectively preventing the semiconductor device from failing due to Idss leakage short circuit, and ensuring product qualification. rate.
為達上述目的，本發明提供一種接觸孔中具有鎢間隔層的功率MOSFET裝置，其包含：設置在底部基底上的體區域；形成於所述體區域和底部基底中的溝槽內的溝槽閘極；形成在體區域的頂部部分，且圍繞溝槽閘極的源極區域；形成在所述溝槽閘極和源極區域頂部表面上的介電層；若干在介電層中貫穿開設的接觸孔，在所述介電層的頂部表面和所述接觸孔的側壁和底部表面上形成阻擋層；設置在所述接觸孔的底部角落處的阻擋層之上的鎢間隔層；設置在所述鎢間隔層和阻擋層上的、且填充接觸孔的鋁金屬層，其延伸至所述介電層的頂部表面形成接觸金屬層。 To achieve the above object, the present invention provides a power MOSFET device having a tungsten spacer layer in a contact hole, comprising: a body region disposed on a bottom substrate; a trench formed in the trench in the body region and the bottom substrate a gate electrode; a source region formed at a top portion of the body region and surrounding the trench gate; a dielectric layer formed on a top surface of the gate gate and source regions; and a plurality of openings extending through the dielectric layer a contact hole, a barrier layer formed on a top surface of the dielectric layer and sidewalls and a bottom surface of the contact hole; a tungsten spacer layer disposed over the barrier layer at a bottom corner of the contact hole; An aluminum metal layer on the tungsten spacer layer and the barrier layer and filling the contact hole extends to a top surface of the dielectric layer to form a contact metal layer.
所述鋁金屬層中含有銅或其他元素。 The aluminum metal layer contains copper or other elements.
進一步，所述的功率MOSFET裝置包含一閘極流道區域，其包含一閘極流道溝槽；所述的閘極流道溝槽與溝槽閘極同時形成且結構相同，但比溝槽閘極更寬且更深。 Further, the power MOSFET device includes a gate runner region including a gate runner trench; the gate runner trench is formed simultaneously with the trench gate and has the same structure but a specific trench The gate is wider and deeper.
所述的一接觸孔形成在閘極流道區域，該接觸孔可以設置在閘極流道溝槽的頂部表面，也可以設置在閘極流道溝槽的內部，即該接觸孔的底部延伸至閘極流道溝槽內。 The contact hole is formed in the gate flow channel region, and the contact hole may be disposed on the top surface of the gate flow channel groove, or may be disposed inside the gate flow channel groove, that is, the bottom of the contact hole extends To the gate channel trench.
所述的另一部分接觸孔形成在與閘極流道區域緊鄰的晶胞區域。當體區域的上部未被源極區域完全覆蓋時，即體區域延伸至半導體上表面時，該接觸孔可以設置在體區域的頂部表面；也可以設置在體區域的內部，即該接觸孔的底部延伸至該體區域內；也可以設置在體區域和源極區域的頂部表面。當體區域的上部被源極區域完全覆蓋時，可以將該接觸孔穿過源極區域使其底部延伸至體區域內部。 The other portion of the contact hole is formed in a cell region immediately adjacent to the gate runner region. When the upper portion of the body region is not completely covered by the source region, that is, when the body region extends to the upper surface of the semiconductor, the contact hole may be disposed on the top surface of the body region; or may be disposed inside the body region, that is, the contact hole The bottom portion extends into the body region; it may also be disposed on the top surface of the body region and the source region. When the upper portion of the body region is completely covered by the source region, the contact hole may be passed through the source region such that the bottom portion thereof extends to the inside of the body region.
所述的鎢間隔層呈側壁狀，其覆蓋位於接觸孔側壁底部部分的阻擋層，以及覆蓋位於接觸孔底部表面兩側部分的阻擋層，以覆蓋接觸孔的底部角落；而接觸孔底部表面中間部分的阻擋層顯露出來與金屬層直接接觸。 The tungsten spacer layer has a sidewall shape covering a barrier layer at a bottom portion of the sidewall of the contact hole, and a barrier layer covering portions on both sides of the bottom surface of the contact hole to cover a bottom corner of the contact hole; and a bottom surface of the contact hole A portion of the barrier layer is exposed to be in direct contact with the metal layer.
所述的鎢間隔層呈塞狀，其覆蓋位於接觸孔側壁下部部分的阻擋層，以及覆蓋位於接觸孔整個底部表面的阻擋層，以覆蓋接觸孔的底部角落和底部表面。 The tungsten spacer layer is plug-shaped, covering a barrier layer located at a lower portion of the sidewall of the contact hole, and covering a barrier layer on the entire bottom surface of the contact hole to cover the bottom corner and the bottom surface of the contact hole.
在所述的溝槽中還設置有沿溝槽側壁和底部形成的薄閘極絕緣層，其位於溝槽閘極與體區域、源極區域以及底部基底之間。 A thin gate insulating layer formed along the sidewalls and the bottom of the trench is also disposed in the trench, and is located between the trench gate and the body region, the source region, and the bottom substrate.
所述的介電層包含依次沉積在體區域、溝槽閘極和源極區域頂部表面上的低溫氧化層和硼磷矽玻璃層。 The dielectric layer includes a low temperature oxide layer and a borophosphophosphorus glass layer which are sequentially deposited on the top surface of the body region, the trench gate and the source region.
所述的阻擋層是Ti/TiN阻擋層。 The barrier layer is a Ti/TiN barrier layer.
本發明還提供一種接觸孔中具有鎢間隔層的功率MOSFET裝置的製造方法，具體包含以下步驟：a.在底部基底上形成一體區域層；b.在體區域和底部基底中形成溝槽閘極；c.在溝槽閘極以及體區域上沉積形成介電層； d.在所述的體區域的頂部部分，且圍繞溝槽閘極形成源極區域；e.在所述的介電層中通過刻蝕形成貫穿該介電層的若干接觸孔，並在該介電層頂部表面上及接觸孔的側壁和底部表面上沉積生成阻擋層；f.在接觸孔中的阻擋層上生成鎢間隔層；g.在所述的阻擋層以及鎢間隔層上沉積生成鋁金屬層，並對其進行光刻；h.刻蝕鋁金屬層及阻擋層，形成源極接觸金屬層和閘極接觸金屬層。 The present invention also provides a method of fabricating a power MOSFET device having a tungsten spacer layer in a contact hole, specifically comprising the steps of: a. forming an integral region layer on the bottom substrate; b. forming a trench gate in the body region and the bottom substrate ;c. depositing a dielectric layer on the trench gate and the body region; d. forming a source region around the trench gate at a top portion of the body region; e. forming a plurality of contact holes through the dielectric layer by etching in the dielectric layer, and Depositing a barrier layer on the top surface of the dielectric layer and on the sidewalls and the bottom surface of the contact hole; f. forming a tungsten spacer layer on the barrier layer in the contact hole; g. depositing on the barrier layer and the tungsten spacer layer An aluminum metal layer is lithographically patterned; h. an aluminum metal layer and a barrier layer are etched to form a source contact metal layer and a gate contact metal layer.
進一步，在進行步驟b的同時還形成閘極流道區域，其包含一閘極流道溝槽；所述的閘極流道溝槽與溝槽閘極同時形成且結構相同，但比溝槽閘極更寬且更深。 Further, while performing step b, a gate runner region is formed, which includes a gate runner trench; the gate runner trench is formed simultaneously with the trench gate and has the same structure but a specific trench The gate is wider and deeper.
在所述的步驟e中形成的接觸孔，其中一接觸孔形成在閘極流道區域，該接觸孔可以設置在閘極流道溝槽的頂部表面，也可以設置在閘極流道溝槽的內部，即該接觸孔的底部延伸至閘極流道溝槽內。 a contact hole formed in the step e, wherein a contact hole is formed in the gate flow channel region, and the contact hole may be disposed on the top surface of the gate flow channel groove or may be disposed in the gate flow channel groove The inside of the contact hole extends into the gate channel trench.
在所述的步驟e中形成的接觸孔，其中另一部分形成在與閘極流道區域緊鄰的晶胞區域。當體區域的上部未被源極區域完全覆蓋時，即體區域延伸至半導體上表面時，該接觸孔可以設置在體區域的頂部表面；也可以設置在體區域的內部，即該接觸孔的底部延伸至該體區域內；也可以設置在體區域和源極區域的頂部表面。當體區域的上部被源極區域完全覆蓋時，可以將該接觸孔穿過源極區域使其底部延伸至體區域內部。 The contact hole formed in the step e described above, the other portion of which is formed in the cell region immediately adjacent to the gate flow path region. When the upper portion of the body region is not completely covered by the source region, that is, when the body region extends to the upper surface of the semiconductor, the contact hole may be disposed on the top surface of the body region; or may be disposed inside the body region, that is, the contact hole The bottom portion extends into the body region; it may also be disposed on the top surface of the body region and the source region. When the upper portion of the body region is completely covered by the source region, the contact hole may be passed through the source region such that the bottom portion thereof extends to the inside of the body region.
進一步，所述的步驟f具體包含以下步驟：f1.在接觸孔中的阻擋層上沉積生成鎢層，該鎢層填滿接觸孔並高於接觸孔孔口； f2.對鎢層進行回蝕刻至阻擋層表面，即將高於接觸孔孔口的鎢層蝕刻掉；f3.繼續對鎢層進行過刻，在接觸孔中的底部角落處的阻擋層上形成鎢間隔層。 Further, the step f includes the following steps: f1. depositing a tungsten layer on the barrier layer in the contact hole, the tungsten layer filling the contact hole and higher than the contact hole; F2. etching back the tungsten layer to the surface of the barrier layer, that is, etching away the tungsten layer higher than the contact hole; f3. continuing to engrave the tungsten layer, forming tungsten on the barrier layer at the bottom corner in the contact hole Spacer layer.
所述的步驟f1中，使用化學氣相沉積的方法在接觸孔中的阻擋層上沉積生成鎢層。 In the step f1, a tungsten layer is deposited on the barrier layer in the contact hole by chemical vapor deposition.
所述的步驟f3中形成的鎢間隔層可呈側壁狀，其覆蓋位於接觸孔側壁底部部分的阻擋層，以及覆蓋位於接觸孔底部表面兩側部分的阻擋層，以覆蓋接觸孔的底部角落，而接觸孔底部表面中間部分的阻擋層顯露出來與金屬層直接接觸。 The tungsten spacer layer formed in the step f3 may have a sidewall shape covering a barrier layer located at a bottom portion of the sidewall of the contact hole, and a barrier layer covering portions on both sides of the bottom surface of the contact hole to cover a bottom corner of the contact hole. The barrier layer in the middle portion of the bottom surface of the contact hole is exposed to be in direct contact with the metal layer.
所述的步驟f3中形成的鎢間隔層可呈V形塞狀，其覆蓋位於接觸孔側壁下部部分的阻擋層，以及覆蓋位於接觸孔整個底部表面的阻擋層，以覆蓋接觸孔的底部角落和底部表面。 The tungsten spacer layer formed in the step f3 may have a V-shaped plug shape covering the barrier layer located at a lower portion of the sidewall of the contact hole, and covering a barrier layer located on the entire bottom surface of the contact hole to cover the bottom corner of the contact hole and Bottom surface.
所述的步驟b具體包含以下步驟：b1.在體區域內通過刻蝕開設若干貫穿該體區域並延伸至底部基底中一定深度的溝槽；b2.沿溝槽的側壁和底部形成閘極絕緣層；b3.在溝槽內形成溝槽閘極；所述的閘極絕緣層位於該溝槽閘極和體區域以及底部基底之間；所述的步驟c中，包含依次沉積低溫氧化物層和硼磷矽玻璃層的步驟。 The step b specifically includes the following steps: b1. opening a plurality of trenches extending through the body region and extending to a certain depth in the bottom substrate by etching in the body region; b2 forming gate insulation along the sidewalls and the bottom of the trench a layer; a trench gate is formed in the trench; the gate insulating layer is located between the trench gate and the body region and the bottom substrate; and the step c includes sequentially depositing a low temperature oxide layer And the step of the borophosphorus glass layer.
所述的步驟d中，該源極區域與溝槽閘極之間還設有閘極絕緣層。 In the step d, a gate insulating layer is further disposed between the source region and the trench gate.
所述的步驟e中形成的阻擋層是Ti/TiN阻擋層。 The barrier layer formed in the step e is a Ti/TiN barrier layer.
所述的步驟f和步驟g之間進一步包含在鎢間隔層上形成第二阻擋層的步驟。 The step f and the step g further comprise the step of forming a second barrier layer on the tungsten spacer layer.
所述的步驟g中形成的鋁金屬層含有銅或其他元素。 The aluminum metal layer formed in the step g contains copper or other elements.
本發明的優點在於：在功率MOSFET裝置的接觸孔的底部角落位置處添加了鎢間隔層，可以有效地防止由於Ti/TiN阻擋層不具有良好的臺階覆蓋性，使矽和鋁直接接觸，造成鋁穿刺的問題，進一步更有效的避免了Idss漏電短路，保證了半導體矽片的產品品質。 The invention has the advantages that a tungsten spacer layer is added at a bottom corner position of the contact hole of the power MOSFET device, which can effectively prevent the Ti/TiN barrier layer from having a good step coverage, so that the tantalum and the aluminum are in direct contact, resulting in The problem of aluminum puncture further avoids the Idss leakage short circuit and ensures the product quality of the semiconductor chip.
1’‧‧‧底部基底 1'‧‧‧ bottom base
1‧‧‧N+底部基底 1‧‧‧N + bottom substrate
2’‧‧‧體區域 2’‧‧‧ Body area
2‧‧‧P-體區域 2‧‧‧P-body area
3、3’‧‧‧溝槽閘極 3, 3'‧‧‧ trench gate
4’‧‧‧源極區域 4’‧‧‧ Source Area
4‧‧‧N+源極區域 4‧‧‧N + source area
5、5’‧‧‧低溫氧化層 5, 5'‧‧‧ Low temperature oxide layer
6、6’‧‧‧硼磷矽玻璃層 6, 6'‧‧‧ Boron Phosphate Glass Layer
8、8’‧‧‧Ti/TiN阻擋層 8, 8'‧‧‧Ti/TiN barrier layer
9‧‧‧鎢間隔層 9‧‧‧Tungsten spacer
10、10’‧‧‧鋁金屬層 10, 10'‧‧‧ aluminum metal layer
11‧‧‧N-外延層 11‧‧‧N - epitaxial layer
30‧‧‧閘極流道溝槽 30‧‧‧gate runner channel trench
31‧‧‧閘極絕緣層 31‧‧‧ gate insulation
40‧‧‧區域P+ 40‧‧‧Regional P+
71、72、7’、711、721‧‧‧接觸孔 71, 72, 7', 711, 721‧ ‧ contact holes
71’‧‧‧底部角落 71’‧‧‧ bottom corner
第1圖為現有技術中在接觸孔中使用Ti/TiN阻擋層來避免鋁穿刺的功率MOSFET裝置的示意圖；第2圖為現有技術中在功率MOSFET裝置的接觸孔中沉積Ti/TiN阻擋層的流程圖；第3圖為本發明所提供的接觸孔中具有鎢間隔層的的功率MOSFET裝置的一種實施例的剖視圖；第4圖為本發明所提供的接觸孔中具有鎢間隔層的的功率MOSFET裝置的另一種實施例的剖視圖；第5圖為本發明所提供的在功率MOSFET裝置的接觸孔中沉積鎢間隔層的流程圖；第6A-6E圖為本發明中在接觸孔中沉積鎢間隔層的各步驟示意圖。 1 is a schematic diagram of a prior art power MOSFET device using a Ti/TiN barrier layer in a contact hole to avoid aluminum puncture; FIG. 2 is a prior art deposition of a Ti/TiN barrier layer in a contact hole of a power MOSFET device. FIG. 3 is a cross-sectional view showing an embodiment of a power MOSFET device having a tungsten spacer layer in a contact hole according to the present invention; and FIG. 4 is a diagram showing power of a tungsten spacer layer in a contact hole provided by the present invention. A cross-sectional view of another embodiment of a MOSFET device; FIG. 5 is a flow chart of depositing a tungsten spacer layer in a contact hole of a power MOSFET device according to the present invention; and FIGS. 6A-6E are views showing deposition of tungsten in a contact hole in the present invention. Schematic diagram of each step of the spacer layer.
以下結合第3圖、第4圖、第5圖和第6A-6E圖，通過若干實施例詳細說明本發明的具體實施方式。 Specific embodiments of the present invention will be described in detail below with reference to Figures 3, 4, 5, and 6A-6E.
如第3圖所示，是本發明所述的接觸孔中具有鎢側壁的功率MOSFET裝置的一種實施例的剖視圖。該功率MOSFET裝置是N溝道半導體裝置，其包含一作為漏極的高摻雜的N+底部基底1，在該N+底部基底1上生長有一N-外延層11；在該N-外延層11之上形成有P-體 區域2。在該P-體區域2中開設有若干貫穿該P-體區域2並延伸至N-外延層11中一定深度的溝槽，在所述的溝槽中填充諸如多晶矽的導電材料以形成溝槽閘極3，並且在該溝槽中還設置有沿溝槽側壁和底部形成的較薄的閘極絕緣層31，該閘極絕緣層31通常為一氧化物層，其用於將溝槽閘極3與N-外延層11以及P-體區域2絕緣隔離。在所述的P-體區域2的頂部部分，圍繞每個溝槽形成有N+源極區域4，該N+源極區域4與溝槽閘極3之間被所述的閘極絕緣層31絕緣隔離。在所述的P-體區域2、N+源極區域4及溝槽閘極3的頂部表面上還沉積有由低溫氧化層5和硼磷矽玻璃層6構成的介電層，該介電層用於隔絕溝槽閘極3，避免其與P-體區域2以及N+源極區域4接觸。該功率MOSFET裝置進一步還包含一閘極流道(gate runner)區域，其包含一閘極流道溝槽30；該閘極流道溝槽30與溝槽閘極3同時形成且結構相同，但也可以比溝槽閘極3更寬因而也更深。 As shown in FIG. 3, a cross-sectional view of one embodiment of a power MOSFET device having a tungsten sidewall in the contact hole of the present invention. The N-channel power MOSFET device is a semiconductor device comprising a highly doped drain of a N + base substrate 1, the N + 1 grown on a base substrate N - epitaxial layer 11; the N - epitaxial layer A P-body region 2 is formed on top of 11. A plurality of trenches penetrating the P-body region 2 and extending to a certain depth in the N − epitaxial layer 11 are formed in the P-body region 2, and the trench is filled with a conductive material such as polysilicon to form a trench. a gate 3, and a thinner gate insulating layer 31 formed along the sidewalls and the bottom of the trench is also disposed in the trench, and the gate insulating layer 31 is usually an oxide layer for the trench gate electrode 3 and N - 2 insulating spacer 11 and the P- epitaxial layer bulk region. In the top portion of the P-body region 2, an N + source region 4 is formed around each trench, and the gate insulating layer is interposed between the N + source region 4 and the trench gate 3. 31 insulation isolation. A dielectric layer composed of a low temperature oxide layer 5 and a borophosphosilicate glass layer 6 is deposited on the top surface of the P-body region 2, the N + source region 4, and the trench gate 3, and the dielectric layer is deposited. The layer is used to isolate the trench gate 3 from contact with the P-body region 2 and the N + source region 4. The power MOSFET device further includes a gate runner region including a gate runner trench 30; the gate runner trench 30 is formed simultaneously with the trench gate 3 and has the same structure, but It can also be wider and thus deeper than the trench gate 3.
在所述的介電層，也就是低溫氧化層5和硼磷矽玻璃層6中貫穿開設若干接觸孔，其中一部分接觸孔71形成在晶胞(cell)區域。因P-體區域延伸至半導體上表面，其可僅僅形成在P-體區域2的頂部表面上，並可選擇性地設置接觸注入區域P+40以減低P-體區域2與金屬層之間的接觸電阻；而另一接觸孔72則形成在閘極流道(gate runner)區域，即形成在閘極流道溝槽30的頂部表面上。接觸孔71或72也可適當地延伸至P-體區域或閘極流道溝槽30內(如第4圖)。 A plurality of contact holes are formed in the dielectric layer, that is, the low temperature oxide layer 5 and the borophosphosilicate glass layer 6, and a part of the contact holes 71 are formed in a cell region. Since the P-body region extends to the upper surface of the semiconductor, it may be formed only on the top surface of the P-body region 2, and the contact injection region P+40 may be selectively disposed to reduce the P-body region 2 and the metal layer. The contact resistance 72 is formed in the gate runner region, that is, on the top surface of the gate runner trench 30. Contact holes 71 or 72 may also suitably extend into the P-body region or gate runner trench 30 (as in Figure 4).
在所述的硼磷矽玻璃層6的頂部表面上及各個接觸孔71和72的內表面上(也就是沿各個接觸孔的側壁和底部表面)設置有Ti/TiN阻擋層8；在所述的各個接觸孔71和72的底部角落處的Ti/TiN阻擋層8之上，還設置有鎢間隔層9；在該鎢間隔層9與Ti/TiN阻擋層8上設置有鋁金屬層10，其填充接觸孔71和72大部分的空間，並延伸至所述介電層的頂部表面以形成源極/體區接觸金屬層和閘極接觸金屬層。其中，所述的鋁金屬層10可含有銅或其他元素。 a Ti/TiN barrier layer 8 is disposed on the top surface of the borophosphon glass layer 6 and on the inner surfaces of the respective contact holes 71 and 72 (that is, along the sidewalls and the bottom surface of each contact hole); Above the Ti/TiN barrier layer 8 at the bottom corners of each of the contact holes 71 and 72, a tungsten spacer layer 9 is further disposed; an aluminum metal layer 10 is disposed on the tungsten spacer layer 9 and the Ti/TiN barrier layer 8 It fills most of the space of contact holes 71 and 72 and extends to the top surface of the dielectric layer to form a source/body contact metal layer and a gate contact metal layer. Wherein, the aluminum metal layer 10 may contain copper or other elements.
進一步，當所述的接觸孔71和72的形狀較寬較淺時，所述的形成在其底部角落處Ti/TiN阻擋層8之上的鎢間隔層9呈側壁狀(如第6C圖所示)，即該鎢間隔層9覆蓋位於接觸孔71和72的側壁底部部分的Ti/TiN阻擋層8，以及覆蓋位於接觸孔71和72的底部表面兩側部分的Ti/TiN阻擋層8，最終僅僅覆蓋接觸孔71和72的兩個底部角落，使接觸孔底部表面中間部分的Ti/TiN阻擋層8顯露出來。鋁金屬層10填充接觸孔底部側壁狀鎢間隔層之間的區域並直接接觸顯露的接觸孔底部表面中間部分的Ti/TiN阻擋層8。鋁金屬層10同時填充接觸孔鎢間隔層上方的區域並延伸至所述介電層的頂部表面以形成源極/體區接觸金屬層和閘極接觸金屬層。 Further, when the shape of the contact holes 71 and 72 is wider and shallower, the tungsten spacer layer 9 formed on the Ti/TiN barrier layer 8 at the bottom corner thereof has a sidewall shape (as shown in FIG. 6C). That is, the tungsten spacer layer 9 covers the Ti/TiN barrier layer 8 at the bottom portion of the sidewalls of the contact holes 71 and 72, and the Ti/TiN barrier layer 8 covering the both side portions of the bottom surfaces of the contact holes 71 and 72, Finally, only the two bottom corners of the contact holes 71 and 72 are covered, so that the Ti/TiN barrier layer 8 in the middle portion of the bottom surface of the contact hole is exposed. The aluminum metal layer 10 fills the area between the sidewall-shaped tungsten spacer layers at the bottom of the contact hole and directly contacts the Ti/TiN barrier layer 8 in the middle portion of the bottom surface of the exposed contact hole. The aluminum metal layer 10 simultaneously fills a region above the contact hole tungsten spacer layer and extends to the top surface of the dielectric layer to form a source/body contact metal layer and a gate contact metal layer.
由於鋁金屬層和Ti/TiN阻擋層之間比較鋁金屬層和鎢間隔層之間有較好的接觸，一般地說鎢間隔層所覆蓋的阻擋層越小越好。但當所述的接觸孔71和72的形狀較窄較深時，接觸孔底部的鎢間隔層可能不易全部除去，此時形成在其底部角落處Ti/TiN阻擋層8之上的鎢間隔層9呈V形塞狀(如第6D圖所示)，即該鎢間隔層9覆蓋位於接觸孔71和72的側壁下部部分的Ti/TiN阻擋層8，以及覆蓋位於接觸孔71和72的整個底部表面Ti/TiN阻擋層8，最終覆蓋了接觸孔71和72的兩個底部角落和整個底部表面。鋁金屬層10填充接觸孔底部V形塞狀鎢間隔層之間的V形區域；鋁金屬層10同時填充接觸孔鎢間隔層上方的區域並接觸覆蓋接觸孔71和72的側壁頂部部分的Ti/TiN阻擋層8，並延伸至所述介電層的頂部表面以形成源極/體區接觸金屬層和閘極接觸金屬層。另一可選方案可在塞狀鎢間隔層和鋁金屬層10之間再夾設一第二Ti/TiN阻擋層以改進鋁金屬層10和鎢間隔層之間的接觸。在此情況下，塞狀鎢間隔層可不拘於V形，比如方形或U形。 Since the aluminum metal layer and the Ti/TiN barrier layer have better contact between the aluminum metal layer and the tungsten spacer layer, generally speaking, the barrier layer covered by the tungsten spacer layer is as small as possible. However, when the shape of the contact holes 71 and 72 is narrower and deeper, the tungsten spacer layer at the bottom of the contact hole may not be completely removed, and a tungsten spacer layer formed on the Ti/TiN barrier layer 8 at the bottom corner thereof is formed at this time. 9 is in the shape of a V-shaped plug (as shown in Fig. 6D), that is, the tungsten spacer layer 9 covers the Ti/TiN barrier layer 8 located at the lower portion of the side walls of the contact holes 71 and 72, and covers the entire contact holes 71 and 72. The bottom surface Ti/TiN barrier layer 8 eventually covers the two bottom corners of the contact holes 71 and 72 and the entire bottom surface. The aluminum metal layer 10 fills the V-shaped region between the V-shaped plug-like tungsten spacer layers at the bottom of the contact hole; the aluminum metal layer 10 simultaneously fills the region above the contact hole tungsten spacer layer and contacts the Ti covering the top portion of the sidewall of the contact holes 71 and 72 /TiN barrier layer 8 and extending to the top surface of the dielectric layer to form a source/body contact metal layer and a gate contact metal layer. Alternatively, a second Ti/TiN barrier layer may be interposed between the plug tungsten spacer layer and the aluminum metal layer 10 to improve contact between the aluminum metal layer 10 and the tungsten spacer layer. In this case, the plug tungsten spacer layer may be of a V shape, such as a square or a U shape.
如第4圖所示，是本發明所述的接觸孔中具有鎢側壁的功率MOSFET裝置的另一種實施例的剖視圖。該實施例中的MOSFET裝置結構與第3圖所示的MOSFET裝置結構相類似，唯一的區別在於：第3 圖中的接觸孔71和72是形成在矽表面的，即接觸孔71的底部表面剛好位於P-體區域2，或者P-體區域2及N+源極區域4的頂部表面上，而接觸孔72的底部表面則剛好位於溝槽閘極3的頂部表面上。在本實施例中，接觸孔是形成在矽裏面的，又稱為溝槽接觸孔。如第4圖所示，P-體區域被上層源極區域完全覆蓋，為達成晶胞區域源極和P-體區之間的良好電接觸，接觸孔711可穿過源極區域使其底部延伸至P-體區域2中的一定深度處，並可選擇性地設置接觸注入區域P+40；而形成在閘極流道溝槽的接觸孔721的底部延伸至閘極流道溝槽30中的一定深度處。在如第4圖所示的深入至矽內部的溝槽接觸孔結構中，與第3圖所示的實施例一致，在該接觸孔中依次沉積設置Ti/TiN阻擋層8，在接觸孔底部角落處的Ti/TiN阻擋層8上形成鎢間隔層9，以及用以形成源極/體區接觸區域和閘極接觸區域的鋁金屬層10。所述的鋁金屬層10可含有銅或其他元素。 As shown in Fig. 4, a cross-sectional view of another embodiment of a power MOSFET device having a tungsten sidewall in the contact hole of the present invention. The structure of the MOSFET device in this embodiment is similar to that of the MOSFET device shown in Fig. 3, the only difference being that the contact holes 71 and 72 in Fig. 3 are formed on the surface of the crucible, that is, the bottom surface of the contact hole 71. It is located just on the top surface of the P-body region 2, or the P-body region 2 and the N + source region 4, and the bottom surface of the contact hole 72 is located just on the top surface of the trench gate 3. In this embodiment, the contact hole is formed in the crucible, which is also referred to as a trench contact hole. As shown in FIG. 4, the P-body region is completely covered by the upper source region. To achieve good electrical contact between the cell region source and the P-body region, the contact hole 711 can pass through the source region to the bottom. Extending to a certain depth in the P-body region 2, and selectively providing a contact injection region P+40; and forming a bottom portion of the contact hole 721 of the gate runner trench extending to the gate runner trench 30 At a certain depth in the middle. In the trench contact hole structure deep into the crucible as shown in FIG. 4, in accordance with the embodiment shown in FIG. 3, a Ti/TiN barrier layer 8 is sequentially deposited in the contact hole at the bottom of the contact hole. A tungsten spacer layer 9 is formed on the Ti/TiN barrier layer 8 at the corner, and an aluminum metal layer 10 for forming a source/body contact region and a gate contact region. The aluminum metal layer 10 may contain copper or other elements.
其中，當所述的接觸孔711和721的形狀較寬較淺時，所述的形成在其底部角落處Ti/TiN阻擋層8之上的鎢間隔層9呈側壁狀(如第6C圖所示)，即該鎢間隔層9覆蓋位於接觸孔711和721的側壁底部部分的Ti/TiN阻擋層8，以及覆蓋位於接觸孔711和721的底部表面兩側部分的Ti/TiN阻擋層8，最終僅僅覆蓋接觸孔711和721的兩個底部角落使接觸孔底部表面中間部分的Ti/TiN阻擋層8顯露出來。鋁金屬層10填充接觸孔底部側壁狀鎢間隔層之間的區域並直接接觸顯露的接觸孔底部表面中間部分的Ti/TiN阻擋層8；鋁金屬層10同時填充接觸孔鎢間隔層上方的區域並延伸至所述介電層的頂部表面以形成源極/體區接觸金屬層和閘極接觸金屬層。 Wherein, when the shape of the contact holes 711 and 721 is wider and shallower, the tungsten spacer layer 9 formed on the Ti/TiN barrier layer 8 at the bottom corner thereof has a sidewall shape (as shown in FIG. 6C). That is, the tungsten spacer layer 9 covers the Ti/TiN barrier layer 8 at the bottom portion of the sidewalls of the contact holes 711 and 721, and the Ti/TiN barrier layer 8 covering the both side portions of the bottom surfaces of the contact holes 711 and 721, Finally, only the two bottom corners of the contact holes 711 and 721 are covered to expose the Ti/TiN barrier layer 8 in the middle portion of the bottom surface of the contact hole. The aluminum metal layer 10 fills a region between the sidewall-shaped tungsten spacer layers at the bottom of the contact hole and directly contacts the Ti/TiN barrier layer 8 in the middle portion of the bottom surface of the exposed contact hole; the aluminum metal layer 10 simultaneously fills the region above the tungsten spacer layer of the contact hole And extending to a top surface of the dielectric layer to form a source/body contact metal layer and a gate contact metal layer.
而當所述的接觸孔711和721的形狀較窄較深時，所述的形成在其底部角落處Ti/TiN阻擋層8之上的鎢間隔層9呈V形塞狀(如第6D圖所示)，即該鎢間隔層9覆蓋位於接觸孔711和721的側壁下部部分的Ti/TiN阻擋層8，以及覆蓋位於接觸孔711和721的整個底部 表面Ti/TiN阻擋層8，最終覆蓋了接觸孔711和721的兩個底部角落和整個底部表面。鋁金屬層10填充接觸孔底部V形塞狀鎢間隔層之間的V形區域；鋁金屬層10同時填充接觸孔鎢間隔層上方的區域並接觸覆蓋接觸孔711和721的側壁頂部部分的Ti/TiN阻擋層8，並延伸至所述介電層的頂部表面以形成源極/體區接觸金屬層和閘極接觸金屬層。另一可選方案可在塞狀鎢間隔層和鋁金屬層10之間夾設一第二Ti/TiN阻擋層以改進鋁金屬層和鎢間隔層之間的接觸。在此情況下，塞狀鎢間隔層可不拘於V形，比如方形(如第6E圖所示)或U形(如第6B圖所示)。 When the shape of the contact holes 711 and 721 is narrower and deeper, the tungsten spacer layer 9 formed on the bottom corner of the Ti/TiN barrier layer 8 has a V-shaped plug shape (as shown in FIG. 6D). As shown, the tungsten spacer layer 9 covers the Ti/TiN barrier layer 8 located at the lower portion of the sidewall of the contact holes 711 and 721, and covers the entire bottom of the contact holes 711 and 721. The surface Ti/TiN barrier layer 8 eventually covers the two bottom corners and the entire bottom surface of the contact holes 711 and 721. The aluminum metal layer 10 fills the V-shaped region between the V-shaped plug-like tungsten spacer layers at the bottom of the contact hole; the aluminum metal layer 10 simultaneously fills the region above the contact hole tungsten spacer layer and contacts the Ti covering the top portion of the sidewall of the contact holes 711 and 721 /TiN barrier layer 8 and extending to the top surface of the dielectric layer to form a source/body contact metal layer and a gate contact metal layer. Alternatively, a second Ti/TiN barrier layer may be interposed between the plug tungsten spacer layer and the aluminum metal layer 10 to improve contact between the aluminum metal layer and the tungsten spacer layer. In this case, the plug tungsten spacer layer may be of a V shape, such as a square shape (as shown in Fig. 6E) or a U shape (as shown in Fig. 6B).
以下詳細說明上述實施例中所提供的N溝道功率MOSFET裝置的具體製造工藝步驟。首先，在高摻雜的N+底部基底1上通過生長一N-外延層11。接著，在N-外延層11的頂部部分通過P-離子注入和擴散形成P-體區域2，例如可通過將硼離子以20至100KeV的能量被注入到N-外延層11中，注入劑量約為3×1012至1×1014，以此形成P-體區域2，且所形成的P-體區域2的深度較淺。隨後在該P-體區域2的表面上形成一由二氧化矽構成的溝槽掩模，並以非等向性(anisotropically)蝕刻在穿過該溝槽掩模以及P-體區域2後將N-外延層11蝕刻至預設深度，形成若干溝槽。沿溝槽的側壁和底部，通過標準的犧牲氧化層生長和蝕刻工序，形成通常由氧化物構成的閘極絕緣層31。隨後在溝槽內的剩餘空間中以及二氧化矽溝槽掩模上沉積N+摻雜多晶矽以形成溝槽閘極3。再對二氧化矽溝槽掩模上的N+摻雜多晶矽進行回蝕刻，並剝離該溝槽掩模。在溝槽閘極3以及P-體區域2上依次沉積低溫氧化層5和硼磷矽玻璃層6，其作為介電層將溝槽閘極3隔離絕緣。作為一種可選擇的技術方案，所述的P-體區域2也可以在此時生成。隨後，在所述的P-體區域2的頂部部分形成有N+源極區域4(如第4圖)，或利用源極掩模通過離子注入，圍繞溝槽內的閘極絕緣層31形成有N+源極區域4(如第3圖)。 The specific manufacturing process steps of the N-channel power MOSFET device provided in the above embodiment will be described in detail below. First, on a highly doped N + substrate 1 by growing a bottom N - epitaxial layer 11. Next, the N - epitaxial layer 11 of the top portion of P- body region is formed by ion implantation and diffusion P- 2, for example by boron ions are implanted at an energy of 20 to N to 100KeV - the epitaxial layer 11, the implantation dose of about It is 3 × 10 12 to 1 × 10 14 , thereby forming the P-body region 2, and the formed P-body region 2 has a shallow depth. A trench mask made of ruthenium dioxide is then formed on the surface of the P-body region 2, and anisotropically etched after passing through the trench mask and the P-body region 2 The N- epitaxial layer 11 is etched to a predetermined depth to form a plurality of trenches. A gate insulating layer 31, typically composed of an oxide, is formed along the sidewalls and bottom of the trench by standard sacrificial oxide growth and etching processes. An N + doped polysilicon is then deposited in the remaining space within the trench and on the ceria trench mask to form trench gate 3. The N + -doped polysilicon on the ceria trench mask is etched back and the trench mask is stripped. A low temperature oxide layer 5 and a borophosphonium glass layer 6 are sequentially deposited on the trench gate 3 and the P-body region 2, which insulates the trench gate 3 as a dielectric layer. As an alternative technical solution, the P-body region 2 can also be generated at this time. Subsequently, an N + source region 4 is formed at the top portion of the P-body region 2 (as shown in FIG. 4), or formed by ion implantation around the gate insulating layer 31 in the trench by using a source mask. There is an N+ source region 4 (as in Figure 3).
如第5圖所示，隨後進一步在該功率MOSFET裝置的接觸孔中生成鎢間隔層，具體步驟是：在所述的低溫氧化層5及硼磷矽玻璃層6中通過刻蝕貫穿生成若干接觸孔。其中若干接觸孔是形成在晶胞區域的。當P-體區域延伸至半導體上表面時，其可僅僅形成在P-體區域2的表面上(如第3圖中所示的接觸孔71)；當P-體區域被上層源極區域完全複蓋時，接觸孔可穿過源極區域使其底部延伸至P-體區域2內(如第4圖中所示的接觸孔711)。另外還有一個接觸孔是形成在閘極流道區域的，即其形成在溝槽閘極3的表面上(如第3圖中所示的接觸孔72)，或者其底部延伸至溝槽閘極3內(如第4圖中所示的接觸孔721)。 As shown in FIG. 5, a tungsten spacer layer is further formed in the contact hole of the power MOSFET device. The specific step is: forming a plurality of contacts through the etching through the low temperature oxide layer 5 and the borophosphonium glass layer 6. hole. Several of the contact holes are formed in the cell region. When the P-body region extends to the upper surface of the semiconductor, it may be formed only on the surface of the P-body region 2 (such as the contact hole 71 shown in FIG. 3); when the P-body region is completely covered by the upper source region When covered, the contact hole may pass through the source region such that its bottom extends into the P-body region 2 (such as the contact hole 711 shown in FIG. 4). Further, a contact hole is formed in the gate flow path region, that is, it is formed on the surface of the trench gate 3 (such as the contact hole 72 shown in FIG. 3), or the bottom portion thereof extends to the trench gate. Inside the pole 3 (such as the contact hole 721 shown in Fig. 4).
隨後，在所述硼磷矽玻璃6的頂部表面上及接觸孔的側壁和底部表面上沉積生成Ti/TiN阻擋層8。一可選項接觸注入區域P+40可在沉積生成Ti/TiN阻擋層8之前或之後由接觸孔注入生成。接著，如第6A圖所示，使用化學氣相沉積(CVD)的方法，在接觸孔中的Ti/TiN阻擋層8上沉積生成鎢層，該鎢層將接觸孔填充接觸孔並高於接觸孔孔口一定厚度，該厚度根據接觸孔的實際高度具體設置；本實施例中，大約為6000A。如第6B圖所示，再對鎢層進行回蝕刻至Ti/TiN阻擋層8的表面，即將高於接觸孔孔口的鎢層蝕刻掉。如第6C圖所示，進一步對鎢層過刻一段時間，避免Ti/TiN阻擋層8表面還殘留有鎢層，並形成呈側壁狀的鎢間隔層9；即該鎢側壁覆蓋位於接觸孔側壁底部部分的Ti/TiN阻擋層8，以及覆蓋位於接觸孔底部表面兩側部分的Ti/TiN阻擋層8，最終僅僅覆蓋接觸孔的兩個底部角落，使接觸孔底部表面中間部分的Ti/TiN阻擋層8顯露出來以便與後道工序沉積生成的正面鋁金屬層10直接接觸。鋁金屬層10可含有銅或其他元素。 Subsequently, a Ti/TiN barrier layer 8 is deposited on the top surface of the borophosphon glass 6 and on the sidewalls and bottom surface of the contact hole. An optional contact implant region P+40 can be generated by contact hole injection before or after deposition to form the Ti/TiN barrier layer 8. Next, as shown in FIG. 6A, a tungsten layer is deposited on the Ti/TiN barrier layer 8 in the contact hole by a chemical vapor deposition (CVD) method, and the tungsten layer fills the contact hole with the contact hole and is higher than the contact The orifice opening has a thickness which is specifically set according to the actual height of the contact hole; in this embodiment, it is about 6000A. As shown in Fig. 6B, the tungsten layer is etched back to the surface of the Ti/TiN barrier layer 8, i.e., the tungsten layer above the contact hole opening is etched away. As shown in FIG. 6C, the tungsten layer is further etched for a period of time to prevent the tungsten layer from remaining on the surface of the Ti/TiN barrier layer 8 and to form a tungsten spacer layer 9 having a sidewall shape; that is, the tungsten sidewall cover is located on the sidewall of the contact hole. a Ti/TiN barrier layer 8 at the bottom portion, and a Ti/TiN barrier layer 8 covering portions on both sides of the bottom surface of the contact hole, and finally covering only the two bottom corners of the contact hole, so that the Ti/TiN in the middle portion of the bottom surface of the contact hole The barrier layer 8 is exposed to be in direct contact with the front aluminum metal layer 10 deposited by the subsequent process. The aluminum metal layer 10 may contain copper or other elements.
特別的，當接觸孔寬度較窄時，所述的對鎢層進行過刻的步驟將不會把接觸孔底部中心的鎢刻蝕掉，如第6D圖所示，由此形成呈V形塞狀的鎢間隔層9；即其覆蓋位於接觸孔側壁下部部分的Ti/TiN阻 擋層8，以及覆蓋位於接觸孔的整個底部表面的Ti/TiN阻擋層8，最終覆蓋了接觸孔的兩個底部角落和整個底部表面。另一可選方案可在如第6A圖所示步驟完成後，用CMP(化學機械平坦化)方法形成一方形塞狀鎢間隔層(如第6E圖所示)或用蝕刻方法形成一U形塞狀鎢間隔層(如第6B圖所示)，再沉積生成一第二Ti/TiN阻擋層，此時如第6C圖或如第6D圖所示的對鎢層進行過刻的步驟則成為可選項而可免去。這樣，塞狀鎢間隔層上有一第二Ti/TiN阻擋層以改進該鎢間隔層與鋁金屬層的接觸。 In particular, when the contact hole width is narrow, the step of etching the tungsten layer will not etch away the tungsten at the center of the bottom of the contact hole, as shown in FIG. 6D, thereby forming a V-shaped plug. Tungsten spacer layer 9; that is, it covers the Ti/TiN resistance at the lower portion of the sidewall of the contact hole The barrier layer 8, and the Ti/TiN barrier layer 8 covering the entire bottom surface of the contact hole, ultimately covers the two bottom corners of the contact hole and the entire bottom surface. Alternatively, after the step shown in FIG. 6A is completed, a square plug tungsten spacer layer (as shown in FIG. 6E) may be formed by CMP (Chemical Mechanical Planarization) or a U-shaped method may be formed by etching. a plug-like tungsten spacer layer (as shown in FIG. 6B) is redeposited to form a second Ti/TiN barrier layer, and the step of etching the tungsten layer as shown in FIG. 6C or as shown in FIG. 6D becomes Optional and can be removed. Thus, the plug tungsten spacer layer has a second Ti/TiN barrier layer to improve contact of the tungsten spacer layer with the aluminum metal layer.
最後，在所述的Ti/TiN阻擋層以及鎢間隔層9上沉積生成正面鋁金屬層10，使其填充接觸孔並延伸至所述介電層的頂部表面，然後對該鋁金屬層10進行光刻；鋁金屬層10可含有銅或其他元素。在刻蝕正面鋁金屬層10及Ti/TiN阻擋層8的步驟完成之後，鋁金屬層10在晶胞區域形成源極接觸金屬層，在閘極流道區域形成閘極接觸金屬層。其餘可按標準程式完成整個功率MOSFET裝置的製造。 Finally, a front aluminum metal layer 10 is deposited on the Ti/TiN barrier layer and the tungsten spacer layer 9 to fill the contact hole and extend to the top surface of the dielectric layer, and then the aluminum metal layer 10 is performed. Photolithography; the aluminum metal layer 10 may contain copper or other elements. After the step of etching the front aluminum metal layer 10 and the Ti/TiN barrier layer 8 is completed, the aluminum metal layer 10 forms a source contact metal layer in the cell region and a gate contact metal layer in the gate channel region. The rest can be manufactured in a standard program for the entire power MOSFET device.
上述本發明的各個實施例所提供的功率MOSFET裝置結構中，雖然對於閘極流道區域的接觸孔來說，其由於開設在溝槽閘極(溝槽多晶矽)上，所以當其底部角落區域處的鋁金屬層和溝槽閘極中的多晶矽接觸發生鋁穿刺現象後，由於在溝槽閘極和P-體區域、N+源極區域以及N-外延層之間還設置有閘極絕緣層(柵氧化物層)，所以即使發生了鋁穿刺，也將不會輕易導致Idss漏電短路。所以，絕大部分的因Idss漏電短路而失效的MOSFET裝置都是由開設在晶胞區域(即P-體區域上，或者P-體區域及N+源極區域上)的接觸孔底部所發生的鋁穿刺而導致的。但是為了更進一步的提高裝置的安全性，保證裝置的品質，在本發明中，對分別開設在晶胞區域和閘極流道區域的接觸孔，均在其底部角落處的Ti/TiN阻擋層與鋁金屬層之間設置了鎢間隔層，以有效隔絕矽、鋁接觸所引發的鋁穿刺現象。 In the above structure of the power MOSFET device provided by the various embodiments of the present invention, although the contact hole of the gate runner region is opened on the trench gate (trench polysilicon), the bottom corner region thereof After the aluminum metal layer and the polysilicon in the trench gate contact the aluminum puncture phenomenon, the gate insulation is also provided between the trench gate and the P-body region, the N + source region and the N − epitaxial layer. The layer (gate oxide layer), so even if aluminum puncture occurs, Idss leakage short circuit will not easily occur. Therefore, most of the MOSFET devices that fail due to Idss leakage short circuit are generated by the bottom of the contact hole opened in the cell region (ie, the P-body region, or the P-body region and the N + source region). Caused by the aluminum puncture. However, in order to further improve the safety of the device and ensure the quality of the device, in the present invention, the contact holes respectively opened in the cell region and the gate runner region are Ti/TiN barrier layers at the bottom corners thereof. A tungsten spacer layer is disposed between the aluminum metal layer to effectively isolate the aluminum puncture phenomenon caused by the contact of the tantalum and aluminum.
綜上所述，由於本發明在接觸孔的底部角落處設置了所述的 鎢間隔層，當接觸孔的底部角落處形成有凹坑，或Ti/TiN阻擋層不具有良好的臺階覆蓋性時，由於還有這層鎢間隔層作為保護層，可有效避免正面的鋁金屬層通過角落處與接觸孔下方的體區域或源極區域接觸，以及避免鋁金屬層通過角落處與接觸孔下方的溝槽閘極接觸，從而避免發生因鋁和矽的接觸引發的鋁穿刺現象所導致的功率MOSFET裝置的Idss漏電短路的情況發生。因此，本發明尤其適用於目前結構和製造工藝較先進的功率MOSFET裝置，該裝置為了在具有高集成度(也就是裝置本身封裝尺寸較小)的基礎上擴大半導體區域的使用效率，其具有較淺的源極區域和體區域，並且其接觸孔的深度和寬度的比值較高(即接觸孔相對比較深且比較窄)。 In summary, since the present invention is provided at the bottom corner of the contact hole In the tungsten spacer layer, when the bottom corner of the contact hole is formed with a pit, or the Ti/TiN barrier layer does not have good step coverage, since the tungsten spacer layer is also used as a protective layer, the front aluminum metal can be effectively avoided. The layer contacts the body region or the source region under the contact hole through the corner, and prevents the aluminum metal layer from contacting the groove gate under the contact hole through the corner, thereby avoiding the aluminum puncture phenomenon caused by the contact between the aluminum and the crucible. The resulting Idss leakage short circuit of the power MOSFET device occurs. Therefore, the present invention is particularly applicable to a power MOSFET device having a relatively advanced structure and manufacturing process, and the device has an efficiency of expanding a semiconductor region on the basis of high integration (that is, a package size of the device itself). The shallow source region and the body region have a higher ratio of depth to width of the contact hole (i.e., the contact hole is relatively deep and narrow).
由於本發明有效解決了功率MOSFET裝置中存在的鋁穿刺現象，故產品品質合格率得到了明顯的提高，基本可達到99.9%。 Since the invention effectively solves the aluminum puncture phenomenon existing in the power MOSFET device, the product quality pass rate is obviously improved, and the basic can reach 99.9%.
需要說明的是，本發明不僅如所提供的實施例中涉及的適用於並製造N溝道功率MOSFET裝置，其同樣可適用於並製造P溝道的功率MOSFET裝置，這對本領域內的技術人員是顯而易見的。由於半導體材料的相反極性(例如P型和N型)區別主要在於使用極性不同的摻雜物，所以只要採用與上述實施例中相反極性的半導體層和摻雜物之後，就可適用於P溝道功率MOSFET裝置。 It should be noted that the present invention is applicable not only to the N-channel power MOSFET device as applied to and in the embodiments provided, but is also applicable to and fabrication of a P-channel power MOSFET device, which will be apparent to those skilled in the art. It is obvious. Since the opposite polarity (for example, P-type and N-type) of the semiconductor material is mainly due to the use of dopants having different polarities, it can be applied to the P-channel as long as the semiconductor layer and the dopant having the opposite polarity to those in the above embodiment are used. Channel power MOSFET device.
儘管本發明的內容已經通過上述優選實施例作了詳細介紹，但應當認識到上述的描述不應被認為是對本發明的限制。在本領域技術人員閱讀了上述內容後，對於本發明的多種修改和替代都將是顯而易見的。因此，本發明的保護範圍應由所附的權利要求來限定。 Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the foregoing description should not be construed as limiting. Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be defined by the appended claims.
1‧‧‧N+底部基底 1‧‧‧N + bottom substrate
2‧‧‧P-體區域 2‧‧‧P-body area
3‧‧‧溝槽閘極 3‧‧‧ trench gate
4‧‧‧N+源極區域 4‧‧‧N + source area
5‧‧‧低溫氧化層 5‧‧‧Low temperature oxide layer
6‧‧‧硼磷矽玻璃層 6‧‧‧Boron phosphate glass layer
8‧‧‧Ti/TiN阻擋層 8‧‧‧Ti/TiN barrier layer
9‧‧‧鎢間隔層 9‧‧‧Tungsten spacer
10‧‧‧鋁金屬層 10‧‧‧Aluminum metal layer
11‧‧‧N-外延層 11‧‧‧N - epitaxial layer
30‧‧‧閘極流道溝槽 30‧‧‧gate runner channel trench
31‧‧‧閘極絕緣層 31‧‧‧ gate insulation
40‧‧‧區域P+ 40‧‧‧Regional P+
71、72‧‧‧接觸孔 71, 72‧‧‧ contact holes
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| US20060027862A1 (en) * | 2003-08-04 | 2006-02-09 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US20060043495A1 (en) * | 2002-07-19 | 2006-03-02 | Renesas Technology Corp. | Semiconductor device |
| US20060157779A1 (en) * | 2005-01-20 | 2006-07-20 | Tsuyoshi Kachi | Semiconductor device and manufacturing method of the same |
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| US20060043495A1 (en) * | 2002-07-19 | 2006-03-02 | Renesas Technology Corp. | Semiconductor device |
| US20060027862A1 (en) * | 2003-08-04 | 2006-02-09 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US20050104093A1 (en) * | 2003-11-17 | 2005-05-19 | Kenichi Yoshimochi | Semiconductor device and method for fabricating the same |
| US20060157779A1 (en) * | 2005-01-20 | 2006-07-20 | Tsuyoshi Kachi | Semiconductor device and manufacturing method of the same |
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