TWI475610B - Electrode construction and substrate processing device - Google Patents
Electrode construction and substrate processing device Download PDFInfo
- Publication number
- TWI475610B TWI475610B TW098109962A TW98109962A TWI475610B TW I475610 B TWI475610 B TW I475610B TW 098109962 A TW098109962 A TW 098109962A TW 98109962 A TW98109962 A TW 98109962A TW I475610 B TWI475610 B TW I475610B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- electrode
- wafer
- peripheral portion
- processing
- Prior art date
Links
- 238000012545 processing Methods 0.000 title claims description 106
- 239000000758 substrate Substances 0.000 title claims description 75
- 238000010276 construction Methods 0.000 title 1
- 230000002093 peripheral effect Effects 0.000 claims description 50
- 238000009832 plasma treatment Methods 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 description 75
- 239000007789 gas Substances 0.000 description 30
- 238000000034 method Methods 0.000 description 17
- 238000001020 plasma etching Methods 0.000 description 15
- 238000005530 etching Methods 0.000 description 14
- 150000001768 cations Chemical class 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 7
- 239000003507 refrigerant Substances 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 239000000470 constituent Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000001179 sorption measurement Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 1
- 239000000498 cooling water Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000013022 venting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32137—Radio frequency generated discharge controlling of the discharge by modulation of energy
- H01J37/32155—Frequency modulation
- H01J37/32165—Plural frequencies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
- H01J37/32541—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Description
本發明係關於電極構造及基板處理裝置，尤其關於被配置在基板處理裝置之處理室內連接直流電源之電極構造。The present invention relates to an electrode structure and a substrate processing apparatus, and more particularly to an electrode structure in which a DC power source is connected to a processing chamber disposed in a substrate processing apparatus.
對當作基板之晶圓施予電漿處理之基板處理裝置具備收容晶圓之處理室，和配置在該處理室內而載置晶圓之載置台，和對處理室內之處理空間供給處理氣體之噴淋頭。該基板處理裝置係在載置台連接高頻電源，載置台對處理空間施加高頻電力，被供給至處理空間之處理氣體藉由高頻電力被激發而成為電漿(陽離子或電子)。A substrate processing apparatus for applying a plasma treatment to a wafer as a substrate includes a processing chamber for accommodating a wafer, a mounting table on which the wafer is placed in the processing chamber, and a processing gas for processing a processing space in the processing chamber. Sprinkler. In the substrate processing apparatus, a high-frequency power source is connected to the mounting table, and the mounting table applies high-frequency power to the processing space, and the processing gas supplied to the processing space is excited by the high-frequency power to become a plasma (cation or electron).
因處理空間中之電漿分佈對晶圓之電漿處理之結果造成大影響，故以積極性控制電漿分佈為佳，對應此為了控制電漿分佈尤其係電子密度分佈，執行對噴淋頭施加直流電壓。Since the plasma distribution in the processing space has a great influence on the plasma processing result of the wafer, it is preferable to actively control the plasma distribution, and correspondingly to control the plasma distribution, especially the electron density distribution, the application to the shower head is performed. DC voltage.
於對噴淋頭施加直流電壓之時，於噴淋頭之構成構件即係露出於處理空間之圓板狀之天井電極板連接直流電源。在此，當對噴淋頭施加負之直流電壓之時，該噴淋頭只引入電漿中之陽離子。直流電壓因與高頻電壓不同，電位不經時間變化，故陽離子持續地被引入噴淋頭。再者，被引入噴淋頭之陽離子自該噴淋頭之構成原子釋放出二次電子。其結果，在與處理空間之噴淋頭相向之部分，電子密 度提高(例如，參照專利文獻1)。When a DC voltage is applied to the shower head, the constituent members of the shower head are connected to the DC electrode of the disk-shaped patio electrode plate exposed in the processing space. Here, when a negative DC voltage is applied to the showerhead, the showerhead only introduces cations in the plasma. Since the DC voltage is different from the high-frequency voltage, the potential does not change with time, so the cation is continuously introduced into the shower head. Furthermore, the cation introduced into the shower head releases secondary electrons from the constituent atoms of the shower head. As a result, in the portion facing the shower head of the processing space, the electronic secret The degree is improved (for example, refer to Patent Document 1).
〔專利文獻1〕日本特開2006-270019號公報[Patent Document 1] Japanese Patent Laid-Open Publication No. 2006-270019
但是，電子密度分佈受到處理室之形狀等之影響，在處理空間中有成為不均勻之情形，但於以一片導電板構成天井電極板之時，即使對天井電極板施加直流電壓，因僅有與噴淋頭相向之處理空間中之所有部份之電子密度提高，故無法解除電子密度分佈不均勻之情形。其結果，在與處理空間中之晶圓周緣部相向之部分，電子密度降低，於蝕刻處理之時，則有晶圓之周緣部中之蝕刻率低於晶圓之中心部的問題。However, the electron density distribution is affected by the shape of the processing chamber, etc., and it is uneven in the processing space. However, when a patio electrode plate is formed by a single conductive plate, even if a DC voltage is applied to the patio electrode plate, only The electron density of all the portions in the processing space facing the shower head is increased, so that the uneven distribution of electron density cannot be resolved. As a result, the electron density decreases in a portion facing the peripheral edge portion of the wafer in the processing space, and at the time of the etching process, the etching rate in the peripheral portion of the wafer is lower than the center portion of the wafer.
本發明之目的係提供可在與處理空間中之基板之周緣部相向的部份使電子密度充分提高之電極構造及基板處理裝置。An object of the present invention is to provide an electrode structure and a substrate processing apparatus which can sufficiently increase the electron density in a portion facing a peripheral portion of a substrate in a processing space.
為了達成上述目的，本發明之電極構造，係屬於被配置在對基板施予電漿處理之基板處理裝置所具備之處理室內，與在該處理室內被配置在載置台之上述基板相向的電極構造，其特徵為：具備與上述基板之中心部相向之內側電極，和與上述基板之周緣部相向之外側電極，上述內側電極連接第1直流電源，並且上述外 側電極連接第2直流電源，上述外側電極具有與上述基板平行之第1面，和對該第1面傾斜之第2面。In order to achieve the above object, the electrode structure of the present invention belongs to an electrode structure disposed in a processing chamber provided in a substrate processing apparatus for applying a plasma treatment to a substrate, and facing the substrate disposed on the mounting table in the processing chamber. The inner electrode facing the central portion of the substrate and the outer electrode facing the peripheral portion of the substrate, wherein the inner electrode is connected to the first direct current power source, and the outer electrode is external The side electrode is connected to the second DC power source, and the outer electrode has a first surface parallel to the substrate and a second surface inclined to the first surface.
上述電極構造中，上述第1面及上述第2面指向上述基板之周緣部。In the above electrode structure, the first surface and the second surface are directed to a peripheral portion of the substrate.
為了達成上述目的，本發明之基板處理裝置，係屬於對基板施予電漿處理之基板處理裝置，其特徵為：具備收容上述基板之處理室，和被配置在上述處理室內載置上述基板之載置台，和被配置在上述處理室內並且與被載置在上述載置台之上述基板相向之電極構造，上述電極構造具備與上述基板之中心部相向之內側電極，和與上述基板之周緣部相向之外側電極，上述內側電極連接第1直流電源，並且上述外側電極連接第2直流電源，上述外側電極具有與上述基板平行之第1面，和對該第1面傾斜之第2面。In order to achieve the above object, a substrate processing apparatus according to the present invention is a substrate processing apparatus for applying a plasma treatment to a substrate, comprising: a processing chamber for accommodating the substrate; and a substrate disposed in the processing chamber. a mounting structure, and an electrode structure disposed in the processing chamber and facing the substrate placed on the mounting table, wherein the electrode structure includes an inner electrode facing the central portion of the substrate and facing a peripheral portion of the substrate The outer electrode is connected to the first direct current power source, and the outer electrode is connected to the second direct current power source, and the outer electrode has a first surface parallel to the substrate and a second surface inclined to the first surface.
若藉由本發明之電極構造及基板處理裝置時，在與基板之周緣部相向之外側電極連接第2直流電源而被施加直流電壓。當在外側電極施加直流電壓之時，該外側電極引入電漿中之陽離子而釋放出二次電子。其結果，可以在與處理空間中之基板之周緣部相向之部分提高電子密度。再者，連接第2直流電源之外側電極具有與基板平行之第1面，和 對該第1面傾斜之第2面，二次電子自第1面及第2面釋放出。第2面因對第1面傾斜，故在與處理空間中之基板之周緣部相向之部分，自第2面釋放出之二次電子與自第1面釋放出之二次電子重疊。其結果，可以在與處理空間中之基板之周緣部相向之部分充分提高電子密度。According to the electrode structure and the substrate processing apparatus of the present invention, a DC voltage is applied to the second DC power source connected to the side electrode opposite to the peripheral portion of the substrate. When a direct current voltage is applied to the outer electrode, the outer electrode introduces a cation in the plasma to release secondary electrons. As a result, the electron density can be increased in a portion facing the peripheral portion of the substrate in the processing space. Furthermore, the second electrode connected to the second direct current power source has a first surface parallel to the substrate, and The second electron is released from the first surface and the second surface on the second surface on which the first surface is inclined. Since the second surface is inclined with respect to the first surface, the secondary electrons emitted from the second surface overlap with the secondary electrons released from the first surface in a portion facing the peripheral portion of the substrate in the processing space. As a result, the electron density can be sufficiently increased in a portion facing the peripheral portion of the substrate in the processing space.
上述電極構造中，因第1面及第2面指向基板之周緣部，故自第1面釋放出之二次電子及自第2面釋放出之二次電子在基板之周緣部之正上方重疊。其結果，可以在基板之周緣部之正上方確實且充分提高電子密度。In the electrode structure, since the first surface and the second surface are directed to the peripheral edge portion of the substrate, the secondary electrons released from the first surface and the secondary electrons released from the second surface overlap directly above the peripheral portion of the substrate. . As a result, the electron density can be surely and sufficiently increased directly above the peripheral portion of the substrate.
以下，針對本發明之實施型態，一面參照圖面一面予以說明。Hereinafter, the embodiment of the present invention will be described with reference to the drawings.
第1圖為概略性表示本實施型態所涉及之基板處理裝置之構成的剖面圖，第2圖為概略性表示第1圖中之上部電極之外側電極附近之構成之放大剖面圖。該基板處理裝置係構成對當作基板之半導體晶圓使用電漿施予RIE(Reactive Ion Etching)處理。1 is a cross-sectional view schematically showing a configuration of a substrate processing apparatus according to the present embodiment, and FIG. 2 is an enlarged cross-sectional view schematically showing a configuration in the vicinity of an electrode on the outer side of the upper electrode in FIG. This substrate processing apparatus is configured to apply a RIE (Reactive Ion Etching) process to a semiconductor wafer as a substrate.
在第1圖及第2圖中，基板處理裝置10係具備有圓筒形狀之處理室11、被配置在該處理室11內，當作載置例如直徑為300mm之半導體晶圓(以下，單稱為「晶圓」)W之載置台的圓柱狀之承受器12。In the first and second figures, the substrate processing apparatus 10 includes a cylindrical processing chamber 11 and is disposed in the processing chamber 11 to mount, for example, a semiconductor wafer having a diameter of 300 mm (hereinafter, A cylindrical susceptor 12 called a "wafer" W mounting table.
在基板處理裝置10中，藉由處理室11之內側壁和承受器12之側面，形成將後述之處理空間S之氣體排出處理室11外之流路而發揮功能之排氣流路13。在該排氣流路13之途中，配置排氣板(排氣環)14。In the substrate processing apparatus 10, the inner side wall of the processing chamber 11 and the side surface of the susceptor 12 form an exhaust gas flow path 13 that functions as a flow path outside the gas discharge processing chamber 11 of the processing space S to be described later. An exhaust plate (exhaust ring) 14 is disposed in the middle of the exhaust flow path 13.
排氣板14為具有多數貫通孔之板狀構件，當作將處理室11分隔成上部和下部之分隔板而發揮功能。在藉由排氣板14而分隔之處理室11之上部(以下稱為「反應室」)15如後述般產生電漿。再者，在處理室11之下部(以下，稱為「排氣室(歧管)」)16連接排出處理室11內之氣體的排氣管17、18。排氣板14捕捉或反射產生於反應室15之電漿而防止朝歧管16洩漏。The exhaust plate 14 is a plate-like member having a plurality of through holes, and functions as a partition plate that partitions the processing chamber 11 into upper and lower portions. The upper portion of the processing chamber 11 (hereinafter referred to as "reaction chamber") 15 partitioned by the exhaust plate 14 generates plasma as will be described later. Further, the lower portion of the processing chamber 11 (hereinafter referred to as "exhaust chamber (manifold)") 16 is connected to the exhaust pipes 17, 18 which discharge the gas in the processing chamber 11. The venting plate 14 captures or reflects the plasma generated in the reaction chamber 15 to prevent leakage toward the manifold 16.
排氣管17連接TMP(Turbo Molecular Pump)(無圖示)，排氣管18連接DP(Dry Pump)(無圖示)，該些泵將處理室11內予以抽真空而減壓。具體而言，DP係將處理室11內從大氣壓減壓至中真空狀態(例如，1.3×10Pa(0.1Torr)以下)，TMP與DP合作將處理室11內減壓至低於中真空狀態之壓力的高真空狀態(例如，1.3×10-3 Pa(1.0×10-5 Torr)以下)。並且，處理室11內之壓力藉由APC閥(無圖示)被控制。The exhaust pipe 17 is connected to a TMP (Turbo Molecular Pump) (not shown), and the exhaust pipe 18 is connected to a DP (Dry Pump) (not shown), and the pumps are evacuated in the processing chamber 11 to be depressurized. Specifically, the DP system decompresses the inside of the processing chamber 11 from atmospheric pressure to a medium vacuum state (for example, 1.3×10 Pa (0.1 Torr) or less), and the TMP cooperates with the DP to decompress the inside of the processing chamber 11 to a state lower than the medium vacuum state. A high vacuum state of pressure (for example, 1.3 × 10 -3 Pa (1.0 × 10 -5 Torr) or less). Further, the pressure in the processing chamber 11 is controlled by an APC valve (not shown).
在處理室11內之承受器12，經第1整合器21及第2整合器22各連接第1高頻電源19及第2高頻電源20，第1高頻電源19對承受器12施加比較高之頻率例如60MHz之高頻電力，第2高頻電源20對承受器12施加比較低之頻率例如2MHz之高頻電力。依此，承受器12當作對該承受器12及後述噴淋頭30之間之處理空間S施加高頻電力之下部電極而發揮功能。The first high-frequency power source 19 and the second high-frequency power source 20 are connected to the susceptor 12 in the processing chamber 11 via the first integrator 21 and the second integrator 22, and the first high-frequency power source 19 compares the susceptor 12. The high frequency power is, for example, 60 MHz high frequency power, and the second high frequency power source 20 applies a relatively low frequency, for example, 2 MHz high frequency power to the susceptor 12. Accordingly, the susceptor 12 functions as a lower-frequency electrode for applying high-frequency power to the processing space S between the susceptor 12 and the shower head 30 to be described later.
再者，在承受器12上設置有在內部具有靜電電極板23之由圓板狀絕緣性構件所構成之靜電夾具24。當在承受器12載置晶圓W之時，該晶圓W則被配置在靜電夾具24上。再者，在該靜電夾具24中，於靜電電極板23電性連接有直流電源25。當對靜電電極板23施加正的直流電壓時，則在晶圓W中之靜電夾具24側之面(以下，稱為「背面」)產生負電位，在靜電電極板23及晶圓W之背面之間產生電位差，因該電位差引起之庫倫力或強生拉別克(Johnsen-Rahbek)力，晶圓W被吸附保持於靜電夾具24。Further, the susceptor 12 is provided with an electrostatic chuck 24 composed of a disk-shaped insulating member having an electrostatic electrode plate 23 therein. When the wafer W is placed on the susceptor 12, the wafer W is placed on the electrostatic chuck 24. Further, in the electrostatic chuck 24, a DC power source 25 is electrically connected to the electrostatic electrode plate 23. When a positive DC voltage is applied to the electrostatic electrode plate 23, a negative potential is generated on the surface of the wafer W on the side of the electrostatic chuck 24 (hereinafter referred to as "back surface"), and is on the back side of the electrostatic electrode plate 23 and the wafer W. A potential difference is generated between the wafers W by the Coulomb force or the Johnsonsen-Rahbek force caused by the potential difference, and the wafer W is adsorbed and held by the electrostatic chuck 24.
再者，在承受器12上，以包圍被吸附保持之晶圓W之方式，載置圓環狀之聚焦環26。聚焦環26係由導電性構件，例如由矽所構成，使電漿朝向晶圓W之表面收束，提高RIE處理之效率。Further, an annular focus ring 26 is placed on the susceptor 12 so as to surround the wafer W that is adsorbed and held. The focus ring 26 is made of a conductive member, for example, made of tantalum, and the plasma is condensed toward the surface of the wafer W, thereby improving the efficiency of the RIE process.
再者，在承受器12之內部設置有例如延伸於圓周方向之環狀冷媒室27。在該冷媒室27自冷卻單元(無圖示)經冷媒用配管28循環供給低溫之冷媒例如冷卻水或油脂液(Galden：註冊商標)。藉由該低溫之冷媒而被冷卻之承受器12，經靜電夾具24冷卻晶圓W及聚焦環26。Further, an annular refrigerant chamber 27 extending in the circumferential direction is provided inside the susceptor 12, for example. In the refrigerant chamber 27, a low-temperature refrigerant such as cooling water or a grease liquid (Galden: registered trademark) is circulated and supplied from a cooling unit (not shown) through a refrigerant pipe 28. The susceptor 12 cooled by the low-temperature refrigerant cools the wafer W and the focus ring 26 via the electrostatic chuck 24.
在靜電夾具24之上面中吸附保持晶圓W之部分(以下，稱為「吸附面」)，開口多數傳熱氣體供給孔29。該些多數傳熱氣體供給孔29係經傳熱氣體供給孔29而將當作傳熱氣體之氦(He)氣體供給至吸附面及晶圓W之背面之間隙。被供給至吸附面及晶圓W之背面之間隙的氦氣體係有效果地將晶圓W之熱傳達至靜電夾具24。A portion of the upper surface of the electrostatic chuck 24 that holds and holds the wafer W (hereinafter referred to as "adsorption surface") is opened, and a plurality of heat transfer gas supply holes 29 are opened. The plurality of heat transfer gas supply holes 29 are supplied through a heat transfer gas supply hole 29 to supply a helium (He) gas as a heat transfer gas to a gap between the adsorption surface and the back surface of the wafer W. The helium gas system supplied to the gap between the adsorption surface and the back surface of the wafer W effectively transfers the heat of the wafer W to the electrostatic chuck 24.
在處理室11之天井部設置有噴淋頭30。該噴淋頭30具有露出於處理空間S而與被載置在承受器12之晶圓W(以下，稱為「載置晶圓W」)相向之上部電極31(電極構造)，和由絕緣性構件所構成之絕緣板32，和經該絕緣板32垂釣支撐上部電極31之電極垂釣支撐體33，依照上部電極31、絕緣板32及電極垂釣支撐體33之順序被重疊。A shower head 30 is provided on the patio portion of the processing chamber 11. The shower head 30 has an upper surface electrode 31 (electrode structure) that is exposed to the processing space S and is opposed to the wafer W (hereinafter referred to as "mounting wafer W") placed on the susceptor 12, and is insulated. The insulating plate 32 composed of the member and the electrode fishing support 33 for supporting the upper electrode 31 via the insulating plate 32 are overlapped in the order of the upper electrode 31, the insulating plate 32, and the electrode fishing support 33.
電極垂釣支撐體33在內部具有緩衝室39。緩衝室39為圓柱狀之空間，藉由圓環狀之密封材，例如O型環40被區分成內側緩衝室39a和外側緩衝室39b。The electrode fishing support 33 has a buffer chamber 39 inside. The buffer chamber 39 has a cylindrical space, and is divided into an inner buffer chamber 39a and an outer buffer chamber 39b by an annular seal member such as an O-ring 40.
在內側緩衝室39a連接有處理氣體導入管41，在外側緩衝室39b連接有處理氣體導入管42，處理氣體導入管41、42各對內側緩衝室39a及外側緩衝室39b導入處理氣體。The processing gas introduction pipe 41 is connected to the inner buffer chamber 39a, the processing gas introduction pipe 42 is connected to the outer buffer chamber 39b, and the processing gas is introduced into the inner buffer chamber 39a and the outer buffer chamber 39b of the processing gas introduction pipes 41 and 42.
處理氣體導入管41、42因各具有流量控制器(MFC)(無圖示)，故被導入至內側緩衝室39a及外側緩衝室39b之處理氣體之流量各獨立性被控制。再者，緩衝室39經電極垂釣支撐體33之氣體孔43、絕緣板32之氣體孔44及上部電極31之氣體孔36而與處理空間S連通，被導入至內側緩衝室39a或外側緩衝室39b之處理氣體被供給至處理空間S。此時，藉由調整被導入至內側緩衝室39a及外側緩衝室39b之處理氣體之流量，控制處理空間S中之處理氣體之分佈。Since the process gas introduction pipes 41 and 42 each have a flow rate controller (MFC) (not shown), the flow rates of the process gases introduced into the inner buffer chamber 39a and the outer buffer chamber 39b are controlled independently. Further, the buffer chamber 39 is communicated with the processing space S via the gas hole 43 of the electrode fishing support 33, the gas hole 44 of the insulating plate 32, and the gas hole 36 of the upper electrode 31, and is introduced into the inner buffer chamber 39a or the outer buffer chamber. The processing gas of 39b is supplied to the processing space S. At this time, the distribution of the processing gas in the processing space S is controlled by adjusting the flow rate of the processing gas introduced into the inner buffer chamber 39a and the outer buffer chamber 39b.
在該基板處理裝置10中，於對載置晶圓W施予RIE處理之時，噴淋頭30將處理氣體供給至處理空間S，第1高頻電源19經承受器12對處理空間S施加60MHz之高頻電力，並且第2高頻電源20對承受器12施加2MHz之高頻電力。此時，處理氣體藉由60MHz之高頻電力而被激發成為電漿。再者，2MHz之高頻電力在承受器12中產生偏壓電壓，故電漿中之陽離子或電子被引入至載置晶圓W表面，該載置晶圓W被施予RIE處理。In the substrate processing apparatus 10, when the RIE process is performed on the mounted wafer W, the shower head 30 supplies the processing gas to the processing space S, and the first high-frequency power source 19 applies the processing space S via the susceptor 12. The high frequency power of 60 MHz is applied, and the second high frequency power source 20 applies high frequency power of 2 MHz to the susceptor 12. At this time, the processing gas is excited into a plasma by high frequency power of 60 MHz. Further, since the high frequency power of 2 MHz generates a bias voltage in the susceptor 12, cations or electrons in the plasma are introduced to the surface of the mounting wafer W, and the mounted wafer W is subjected to RIE processing.
再者，為了在處理空間中部分性控制電子密度分佈，開發有將上部電極分割成與晶圓之中心部相向之內側電極，和與晶圓之周緣部相向之外側電極，對內側電極及外側電極之各個獨立施加負極性之直流電壓的方法已被開發。在該方法中，對外側電極施加與內側電極值不同之直流電壓而獨立控制在處理空間中與外側電極相向之部分之電子密度，和與內側電極相向之部分之電子密度。Further, in order to partially control the electron density distribution in the processing space, an inner electrode that divides the upper electrode into a central portion of the wafer and an outer electrode that faces the peripheral portion of the wafer, the inner electrode and the outer side are developed. A method of independently applying a DC voltage of a negative polarity to each of the electrodes has been developed. In this method, a direct current voltage different from the inner electrode value is applied to the outer electrode to independently control the electron density of the portion facing the outer electrode in the processing space and the electron density of the portion facing the inner electrode.
關於該方法，本發明人等發現當透過RIE處理之實驗使外側電極中朝向處理空間之相向面的表面積(以下，稱為「外側電極表面積」)增加時，與處理空間中之外側電極之相向面相向之部分(以下稱為「外側電極相向部份」)之電子密度提高，其結果提高晶圓之周緣部中之蝕刻率(參照第3圖)。In the present inventors, the present inventors have found that when the surface of the outer electrode facing the opposing surface of the processing space (hereinafter referred to as "outer electrode surface area") is increased by an experiment by RIE treatment, it faces the outer electrode in the processing space. The electron density of the surface facing portion (hereinafter referred to as the "outer electrode facing portion") is increased, and as a result, the etching rate in the peripheral portion of the wafer is increased (see Fig. 3).
再者，本發明人等發現當使施加於外側電極之直流電壓之值增加時，依然提高外側電極相向部分之電子密度，其結果提高晶圓之周緣部中之蝕刻率。具體而言，確認出當施加於內側電極之直流電壓之絕對值維持在300V之狀態，直接將施加於外側電極之直流電壓之絕對值從300V上升至900V之時，晶圓之周緣部中之蝕刻率提高大約7%(參照第4圖)。Furthermore, the inventors of the present invention have found that when the value of the DC voltage applied to the outer electrode is increased, the electron density of the opposing portion of the outer electrode is also increased, and as a result, the etching rate in the peripheral portion of the wafer is increased. Specifically, it is confirmed that when the absolute value of the DC voltage applied to the inner electrode is maintained at 300 V, and the absolute value of the DC voltage applied to the outer electrode is directly increased from 300 V to 900 V, the peripheral portion of the wafer The etching rate is increased by about 7% (refer to Fig. 4).
但是，在通常之基板處理裝置中，在外側電極之周邊因存在其他處理室構成構件，故難以將外側電極表面積增加至給定值以上之情形為多。再者，也難以從直流電源之性能等之制約提高施加於外側電極之直流電源之值至給定值以上之情形為多。即是，通常難以使處理空間中與晶圓之周緣部相向之部分充分提高電子密度。However, in a conventional substrate processing apparatus, since other processing chamber constituent members exist around the outer electrode, it is difficult to increase the surface area of the outer electrode to a predetermined value or more. Further, it is difficult to increase the value of the DC power supply applied to the external electrode to a predetermined value or more from the viewpoint of the performance of the DC power supply or the like. That is, it is generally difficult to sufficiently increase the electron density in a portion of the processing space that faces the peripheral portion of the wafer.
在基板處理裝置10中，對應此上部電極31具有與載置晶圓W之中心部相向之內側電極34，和包圍該內側電極34並且與載置晶圓W之周緣部相向之外側電極35，外側電極35具有與載置晶圓W平行之第1二次電子釋放面35a(第1面)，及對該第1二次電子釋放面35a朝向載置晶圓W傾斜之第2二次電子釋放面35b(第2面)。第1二次電子釋放面35a及外側電極35b各指向載置晶圓W之周緣部。In the substrate processing apparatus 10, the upper electrode 31 has an inner electrode 34 that faces the center portion on which the wafer W is placed, and an outer electrode 35 that surrounds the inner electrode 34 and faces the peripheral edge portion of the wafer W. The outer electrode 35 has a first secondary electron emission surface 35a (first surface) parallel to the mounting wafer W, and a second secondary electron that is inclined toward the first wafer discharge surface 35a toward the mounting wafer W. Release surface 35b (second surface). Each of the first secondary electron emission surface 35a and the outer electrode 35b is directed to the peripheral portion of the wafer W.
在此，內側電極34具有例如由直徑為300mm之圓板狀構件所構成，貫通於厚度方向之多數氣體孔36。外側電極35係由外徑為380mm且內徑為300mm之圓環狀構件所構成。內側電極34及外側電極35係由導電性或半導電性材料例如單晶矽所構成。Here, the inner electrode 34 has, for example, a disk-shaped member having a diameter of 300 mm, and penetrates a plurality of gas holes 36 in the thickness direction. The outer electrode 35 is composed of an annular member having an outer diameter of 380 mm and an inner diameter of 300 mm. The inner electrode 34 and the outer electrode 35 are made of a conductive or semiconductive material such as single crystal germanium.
再者，在上部電極31中，於內側電極34連接有第1直流電源37，於外側電極35連接有第2直流電源38，內側電極34及外側電極35各獨立被施加直流電壓。Further, in the upper electrode 31, the first DC power source 37 is connected to the inner electrode 34, the second DC power source 38 is connected to the outer electrode 35, and the DC voltage is independently applied to the inner electrode 34 and the outer electrode 35.
在基板處理裝置10中，於RIE處理之期間，第1直流電源37及第2直流電源38對上部電極31之內側電極34及外側電極35施加負的直流電壓。此時，於內側電極34或外側電極35被引入處理空間S之電漿中之陽離子。被引入之陽離子對內側電極34或外側電極35中之構成原子中之電子賦予能量，當所賦予之能量超過給定值之時，構成原子中之電子則當作二次電子自內側電極34之表面或外側電極35之第1二次電子釋放面35a及第2二次電子釋放面35b被釋放出。In the substrate processing apparatus 10, the first DC power source 37 and the second DC power source 38 apply a negative DC voltage to the inner electrode 34 and the outer electrode 35 of the upper electrode 31 during the RIE process. At this time, the inner electrode 34 or the outer electrode 35 is introduced into the cation in the plasma of the processing space S. The introduced cation imparts energy to the electrons in the constituent atoms in the inner electrode 34 or the outer electrode 35. When the energy imparted exceeds a given value, the electrons constituting the atom are regarded as secondary electrons from the inner electrode 34. The first secondary electron emission surface 35a and the second secondary electron emission surface 35b of the surface or outer electrode 35 are released.
內側電極34如上述般，為圓板狀構件，因僅與載置晶圓W平行之表面露出於處理空間S，故自該表面所釋放出之二次電子從載置晶圓W之中心部到周緣部幾乎均勻分佈。其結果，RIE處理在整個載置晶圓W全面被促進。As described above, the inner electrode 34 is a disk-shaped member, and since only the surface parallel to the wafer W is exposed to the processing space S, the secondary electrons released from the surface are placed from the center of the wafer W. It is almost evenly distributed to the peripheral edge. As a result, the RIE process is fully promoted throughout the placement of the wafer W.
外側電極35之第1二次電子釋放面35a及第2二次電子釋放面35b如上述般，因任一者皆指向載置晶圓W之周緣部，故自第1二次電子釋放面35a及自第2二次電子釋放面35b所釋放出之二次電子在載置晶圓W之周緣部之正上方重疊。其結果，可以在載置晶圓W之周緣部之正上方充分提高電子密度，並在晶圓W之周緣部促進RIE處理。As described above, the first secondary electron emission surface 35a and the second secondary electron emission surface 35b of the outer electrode 35 are directed to the peripheral portion of the wafer W, and thus the first secondary electron emission surface 35a is provided. The secondary electrons released from the second secondary electron emission surface 35b overlap directly above the peripheral portion of the wafer W. As a result, the electron density can be sufficiently increased just above the peripheral portion on which the wafer W is placed, and the RIE process can be promoted at the peripheral portion of the wafer W.
並且，上述基板處理裝置10之各構成零件之動作係由基板處理裝置10所具備之控制部(無圖示)之CPU控制。Further, the operation of each component of the substrate processing apparatus 10 is controlled by a CPU of a control unit (not shown) included in the substrate processing apparatus 10.
若藉由本實施型態所涉及之當作電極構造的上部電極31時，在與載置晶圓W之周緣部相向之外側電極35連接第2直流電源38而被施加直流電壓。當在外側電極35施加直流電壓之時，該外側電極35引入電漿中之陽離子而釋放出二次電子。其結果，可以在與處理空間S中之載置晶圓W之周緣部之正上方提高電子密度。再者，連接第2直流電源38之外側電極35具有與載置晶圓W平行之第1二次電子釋放面35a，和對該第1二次電子釋放面35a朝向載置晶圓W傾斜之第2二次電子釋放面35b，二次電子自第1二次電子釋放面35a及第2二次電子釋放面35b釋放出。第1二次電子釋放面35a及第2二次電子釋放面35b因指向載置晶圓W之周緣部，故可以在載置晶圓W之周緣部之正上方充分提高電子密度，可以在載置晶圓W之周緣部促進RIE處理。When the upper electrode 31 having the electrode structure according to the present embodiment is used, the DC power source 38 is connected to the side electrode 35 facing the peripheral edge portion of the wafer W, and a DC voltage is applied thereto. When a direct current voltage is applied to the outer electrode 35, the outer electrode 35 introduces a cation in the plasma to release secondary electrons. As a result, the electron density can be increased directly above the peripheral portion of the wafer W placed in the processing space S. Further, the external electrode 35 connected to the second DC power source 38 has a first secondary electron emission surface 35a parallel to the mounting wafer W, and the first secondary electron emission surface 35a is inclined toward the mounting wafer W. The second secondary electron emission surface 35b emits secondary electrons from the first secondary electron emission surface 35a and the second secondary electron emission surface 35b. Since the first secondary electron emission surface 35a and the second secondary electron emission surface 35b are directed to the peripheral portion of the wafer W, the electron density can be sufficiently increased directly above the peripheral portion of the wafer W to be placed. The peripheral portion of the wafer W is placed to facilitate the RIE process.
在上述上部電極31中，因不用增加外側電極35中之朝晶圓W之相向面的面積，可以在載置晶圓W之周緣部之正上方充分提高電子密度，故不需要增大外側電極35。其結果，可以刪減高價之單晶矽之使用量，進而可以降低上部電極31之製造成本。In the upper electrode 31, since the area of the opposing surface of the wafer W facing the wafer W is not increased, the electron density can be sufficiently increased directly above the peripheral portion on which the wafer W is placed, so that it is not necessary to increase the outer electrode. 35. As a result, the amount of use of the high-priced single crystal germanium can be reduced, and the manufacturing cost of the upper electrode 31 can be reduced.
再者，在上述上部電極31中，不僅第1二次電子釋放面35a，第2二次電子釋放面35b雖然也指向載置晶圓W之周緣部，但是第2二次電子釋放面35b即使不指向載置晶圓W之周緣部亦可，例如第2二次電子釋放面35b即使對第1二次電子釋放面35a垂直亦可。即使於此時，因在處理空間S中與載置晶圓W之周緣部相向之部分，重疊所釋放出之二次電子，故可以在與載置晶圓W之周緣部相向之部分充分提高電子密度。Further, in the upper electrode 31, not only the first secondary electron emission surface 35a but also the second secondary electron emission surface 35b is directed to the peripheral portion of the wafer W, but the second secondary electron emission surface 35b The second secondary electron emission surface 35b may be perpendicular to the first secondary electron emission surface 35a, for example, without being directed to the peripheral portion of the wafer W. Even at this time, since the secondary electrons released are overlapped in the portion facing the peripheral portion of the wafer W in the processing space S, the portion facing the peripheral portion of the wafer W can be sufficiently improved. Electronic density.
又，第2二次電子釋放面35b不須要為平面，即使為指向載置晶圓W之周緣部的拋物面亦可。此時，可以將二次電子從第2二次電子釋放面35b朝向載置晶圓W之周緣部集中性釋放出，進而可以更充分提高載置晶圓W之周緣部之正上方之電子密度。Further, the second secondary electron emission surface 35b does not need to be a flat surface, and may be a paraboloid that faces the peripheral portion of the wafer W. In this case, the secondary electrons can be collectively released from the second secondary electron emission surface 35b toward the peripheral portion of the mounting wafer W, and the electron density directly above the peripheral portion of the wafer W can be more sufficiently increased. .
並且，在上述本實施之型態中，施予蝕刻處理之基板雖然為半導體晶圓W，但是並不限定於施予蝕刻處理之基板，即使為例如LCD(Liquid Crystal Display)或FPD(Flat Panel Display)等之玻璃基板亦可。Further, in the above-described embodiment, the substrate to which the etching treatment is applied is the semiconductor wafer W, but is not limited to the substrate to which the etching treatment is applied, and is, for example, an LCD (Liquid Crystal Display) or an FPD (Flat Panel). A glass substrate such as Display) is also available.
接著，針對本發明之實施例予以說明。Next, an embodiment of the present invention will be described.
首先，本發明人在基板處理裝置10中對載置晶圓W施予RIE處理，測量該RIE處理中之載置晶圓W之周緣部之蝕刻率，將其結果在第5圖之曲線圖中以「●」表示。First, the inventors of the present invention applied RIE processing to the substrate W in the substrate processing apparatus 10, and measured the etching rate of the peripheral portion of the wafer W placed in the RIE process, and the result is shown in the graph of FIG. It is indicated by "●".
比較例1、2Comparative example 1, 2
接著，本發明人準備僅具有與載置晶圓W平行之表面，且互相該表面面積不同之兩個外側電極，以代替外側電極35。然後，在基板處理裝置10將外側電極35與所準備之各外側電極替換，對載置晶圓W施予RIE處理，測量該RIE處理中之載置晶圓W之周緣部之蝕刻率，將其結果在第5圖之曲線圖中以「◆」表示。Next, the inventors prepared to have only two outer electrodes which are different from the surface on which the wafer W is placed and which have different surface areas from each other instead of the outer electrode 35. Then, the substrate processing apparatus 10 replaces the outer electrode 35 with each of the prepared outer electrodes, and performs an RIE process on the mounted wafer W to measure the etching rate of the peripheral portion of the wafer W to be placed in the RIE process. The result is indicated by "◆" in the graph of Fig. 5.
第5圖之曲線圖之橫軸表示外側電極之表面積。在此，外側電極之表面積相當於實施例1中之第1二次電子釋放面35a及第2二次電子釋放面35b之面積之合計值或比較例1、2中與載置晶圓W平行之表面的面積。再者，在第5圖之曲線圖中，橫軸表示將比較例1之外側電極之表面積設為1之時之實施例1或各比較例之外側電極之表面積，縱軸為將比較例1之蝕刻率設為1之時之實施例1或各比較例之蝕刻率。藉由第5圖之曲線圖，可知比起增加外側面積之表面積，藉由設置對第1二次電子釋放面35a傾斜之第2二次電子釋放面35b則可以有效率充分提高載置晶圓W之周緣部正上方之電子密度，可以在載置晶圓W之周緣部促進RIE處理。The horizontal axis of the graph of Fig. 5 indicates the surface area of the outer electrode. Here, the surface area of the outer electrode corresponds to the total value of the areas of the first secondary electron emission surface 35a and the second secondary electron emission surface 35b in the first embodiment or the parallel to the mounting wafer W in the comparative examples 1 and 2. The area of the surface. In the graph of Fig. 5, the horizontal axis represents the surface area of the external electrode of Example 1 or Comparative Example when the surface area of the external electrode of Comparative Example 1 is set to 1, and the vertical axis is Comparative Example 1. The etching rate of Example 1 or each comparative example when the etching rate was set to 1. According to the graph of Fig. 5, it can be seen that the placement of the wafer can be sufficiently improved by providing the second secondary electron emission surface 35b inclined to the first secondary electron emission surface 35a as compared with the surface area for increasing the outer area. The electron density directly above the peripheral portion of W can facilitate the RIE process on the peripheral portion of the wafer W.
W．．．晶圓W. . . Wafer
10．．．基板處理裝置10. . . Substrate processing device
11．．．處理室11. . . Processing room
12．．．承受器12. . . Receptor
31．．．上部電極31. . . Upper electrode
34．．．內側電極34. . . Inner electrode
35．．．外側電極35. . . Outer electrode
35a．．．第1二次電子釋放面35a. . . First secondary electron release surface
35b．．．第2二次電子釋放面35b. . . Second secondary electron release surface
37．．．第1直流電源37. . . 1st DC power supply
38．．．第2直流電源38. . . 2nd DC power supply
第1圖為概略性表示本發明之實施型態所涉及之基板處理裝置之構成的剖面圖。Fig. 1 is a cross-sectional view schematically showing the configuration of a substrate processing apparatus according to an embodiment of the present invention.
第2圖為概略表示第1圖中之上部電極之外側電極附近之構成的放大剖面圖。Fig. 2 is an enlarged cross-sectional view schematically showing the configuration of the vicinity of the outer electrode of the upper electrode in Fig. 1.
第3圖為表示外側電極中之外側電極表面積和晶圓之周緣部中之蝕刻率之關係曲線圖。Fig. 3 is a graph showing the relationship between the surface area of the outer side electrode and the etching rate in the peripheral portion of the wafer in the outer electrode.
第4圖為表示使施加至外側電極之直流電壓之值增加之時之蝕刻率上升率之曲線圖。Fig. 4 is a graph showing the rate of increase in the etching rate when the value of the DC voltage applied to the outer electrode is increased.
第5圖為表示本發明之實施例1、以及比較例1、2中之外側電極表面積和晶圓之周緣部中之蝕刻率之關係曲線圖。Fig. 5 is a graph showing the relationship between the surface area of the outer side electrode and the etching rate in the peripheral portion of the wafer in Example 1 and Comparative Examples 1 and 2 of the present invention.
12．．．承受器12. . . Receptor
23．．．靜電電極板twenty three. . . Electrostatic electrode plate
24．．．靜電夾具twenty four. . . Static fixture
26．．．聚焦環26. . . Focus ring
31．．．上部電極31. . . Upper electrode
32．．．絕緣板32. . . Insulation board
33．．．電極垂釣支撐體33. . . Electrode fishing support
34．．．內側電極34. . . Inner electrode
35．．．外側電極35. . . Outer electrode
35a．．．第1二次電子釋放面35a. . . First secondary electron release surface
35b．．．第2二次電子釋放面35b. . . Second secondary electron release surface
36．．．氣體孔36. . . Gas hole
37．．．第1直流電源37. . . 1st DC power supply
38．．．第2直流電源38. . . 2nd DC power supply
39．．．緩衝室39. . . Buffer chamber
39a．．．內側緩衝室39a. . . Inner buffer chamber
39b．．．外側緩衝室39b. . . Outer buffer chamber
40．．．O型環40. . . O-ring
42．．．處理氣體導入管42. . . Process gas introduction tube
43．．．氣體孔43. . . Gas hole
44．．．氣體孔44. . . Gas hole
Claims (4)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008083046A JP5348919B2 (en) | 2008-03-27 | 2008-03-27 | Electrode structure and substrate processing apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201001530A TW201001530A (en) | 2010-01-01 |
| TWI475610B true TWI475610B (en) | 2015-03-01 |
Family
ID=41115344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW098109962A TWI475610B (en) | 2008-03-27 | 2009-03-26 | Electrode construction and substrate processing device |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20090242133A1 (en) |
| JP (1) | JP5348919B2 (en) |
| KR (1) | KR20110131157A (en) |
| CN (1) | CN101546700B (en) |
| TW (1) | TWI475610B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5102706B2 (en) * | 2008-06-23 | 2012-12-19 | 東京エレクトロン株式会社 | Baffle plate and substrate processing apparatus |
| CN101740298B (en) * | 2008-11-07 | 2012-07-25 | 东京毅力科创株式会社 | Plasma processing apparatus and constituent part thereof |
| US20110206833A1 (en) * | 2010-02-22 | 2011-08-25 | Lam Research Corporation | Extension electrode of plasma bevel etching apparatus and method of manufacture thereof |
| US9543123B2 (en) | 2011-03-31 | 2017-01-10 | Tokyo Electronics Limited | Plasma processing apparatus and plasma generation antenna |
| JP2015053384A (en) * | 2013-09-06 | 2015-03-19 | 東京エレクトロン株式会社 | Plasma processing method and plasma processing device |
| JP6339866B2 (en) * | 2014-06-05 | 2018-06-06 | 東京エレクトロン株式会社 | Plasma processing apparatus and cleaning method |
| US20160289827A1 (en) * | 2015-03-31 | 2016-10-06 | Lam Research Corporation | Plasma processing systems and structures having sloped confinement rings |
| KR101938306B1 (en) | 2016-04-18 | 2019-01-14 | 최상준 | Controlling Method for Apparatus for Dry Etching |
| US10242845B2 (en) * | 2017-01-17 | 2019-03-26 | Lam Research Corporation | Near-substrate supplemental plasma density generation with low bias voltage within inductively coupled plasma processing chamber |
| KR102568084B1 (en) * | 2020-06-02 | 2023-08-21 | 세메스 주식회사 | Apparatus and method for treating substrate |
| JP2022068583A (en) | 2020-10-22 | 2022-05-10 | 東京エレクトロン株式会社 | Plasma processing apparatus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060037701A1 (en) * | 2004-06-21 | 2006-02-23 | Tokyo Electron Limited | Plasma processing apparatus and method |
| US20060219363A1 (en) * | 2005-03-31 | 2006-10-05 | Naoki Matsumoto | Capacitive coupling plasma processing apparatus and method for using the same |
| US20070187038A1 (en) * | 2006-02-13 | 2007-08-16 | Daxing Ren | Sealed elastomer bonded Si electrodes and the like for reduced particle contamination in dielectric etch |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5472565A (en) * | 1993-11-17 | 1995-12-05 | Lam Research Corporation | Topology induced plasma enhancement for etched uniformity improvement |
| TW299559B (en) * | 1994-04-20 | 1997-03-01 | Tokyo Electron Co Ltd | |
| JP3814176B2 (en) * | 2001-10-02 | 2006-08-23 | キヤノンアネルバ株式会社 | Plasma processing equipment |
| US7988816B2 (en) * | 2004-06-21 | 2011-08-02 | Tokyo Electron Limited | Plasma processing apparatus and method |
| JP4672456B2 (en) * | 2004-06-21 | 2011-04-20 | 東京エレクトロン株式会社 | Plasma processing equipment |
| JP4704088B2 (en) * | 2005-03-31 | 2011-06-15 | 東京エレクトロン株式会社 | Plasma processing equipment |
| US7829469B2 (en) * | 2006-12-11 | 2010-11-09 | Tokyo Electron Limited | Method and system for uniformity control in ballistic electron beam enhanced plasma processing system |
| JP5231038B2 (en) * | 2008-02-18 | 2013-07-10 | 東京エレクトロン株式会社 | Plasma processing apparatus, plasma processing method, and storage medium |
| JP2009239012A (en) * | 2008-03-27 | 2009-10-15 | Tokyo Electron Ltd | Plasma processing device and method of plasma etching |
-
2008
- 2008-03-27 JP JP2008083046A patent/JP5348919B2/en active Active
-
2009
- 2009-03-19 US US12/407,109 patent/US20090242133A1/en not_active Abandoned
- 2009-03-20 CN CN2009101294603A patent/CN101546700B/en active Active
- 2009-03-26 TW TW098109962A patent/TWI475610B/en active
-
2011
- 2011-10-26 KR KR1020110109965A patent/KR20110131157A/en not_active Application Discontinuation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060037701A1 (en) * | 2004-06-21 | 2006-02-23 | Tokyo Electron Limited | Plasma processing apparatus and method |
| US20060219363A1 (en) * | 2005-03-31 | 2006-10-05 | Naoki Matsumoto | Capacitive coupling plasma processing apparatus and method for using the same |
| US20070187038A1 (en) * | 2006-02-13 | 2007-08-16 | Daxing Ren | Sealed elastomer bonded Si electrodes and the like for reduced particle contamination in dielectric etch |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20110131157A (en) | 2011-12-06 |
| CN101546700B (en) | 2011-04-13 |
| US20090242133A1 (en) | 2009-10-01 |
| JP5348919B2 (en) | 2013-11-20 |
| CN101546700A (en) | 2009-09-30 |
| TW201001530A (en) | 2010-01-01 |
| JP2009239014A (en) | 2009-10-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI475610B (en) | Electrode construction and substrate processing device | |
| JP5759718B2 (en) | Plasma processing equipment | |
| TWI553729B (en) | Plasma processing method | |
| JP5702968B2 (en) | Plasma processing apparatus and plasma control method | |
| TW201923948A (en) | Substrate support with electrically floating power supply | |
| US8414705B2 (en) | Seal mechanism, seal trench, seal member, and substrate processing apparatus | |
| TWI478203B (en) | A plasma processing device and its constituent parts | |
| JP6552346B2 (en) | Substrate processing equipment | |
| JP2009212340A (en) | Electrode unit, substrate treatment apparatus, and temperature control method for electrode unit | |
| US9011635B2 (en) | Plasma processing apparatus | |
| JP2010016021A (en) | Plasma processing apparatus | |
| JPH08264515A (en) | Plasma treatment device, processing device and etching device | |
| KR101432375B1 (en) | Substrate loading system, substrate treatment apparatus, electrostatic chuck and substrate cooling method | |
| US20080236746A1 (en) | Substrate processing apparatus and substrate mounting stage on which focus ring is mounted | |
| US8104428B2 (en) | Plasma processing apparatus | |
| KR101898079B1 (en) | Plasma processing apparatus | |
| KR20080005116A (en) | Heat transfer structure and substrate processing apparatus | |
| JP7209515B2 (en) | Substrate holding mechanism and deposition equipment | |
| KR100889433B1 (en) | Plasma processing apparatus | |
| TWI698928B (en) | Plasma processing method | |
| KR101117922B1 (en) | Electrode structure and substrate processing apparatus | |
| US20070221332A1 (en) | Plasma processing apparatus | |
| JP6298293B2 (en) | Substrate processing apparatus, shutter mechanism, and plasma processing apparatus | |
| JP2004006813A (en) | Electrostatic chuck susceptor and substrate processor | |
| JP6541355B2 (en) | Cooling structure and parallel plate etching apparatus |