TWI462243B - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

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TWI462243B
TWI462243B TW102141593A TW102141593A TWI462243B TW I462243 B TWI462243 B TW I462243B TW 102141593 A TW102141593 A TW 102141593A TW 102141593 A TW102141593 A TW 102141593A TW I462243 B TWI462243 B TW I462243B
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Taiwan
Prior art keywords
alloy
semiconductor structure
layer
bump
electroplated
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TW102141593A
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English (en)
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TW201436136A (zh
Inventor
Shih Jye Cheng
Tung Bao Lu
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Chipmos Technologies Inc
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Description

半導體結構及其製造方法
本發明係關於一種半導體結構及其製造方法。
隨著電子工業之近期進展，正開發具有高效能之電子組件，且因此存在對於小型化及高密度封裝之需求。因此，必須更密集地封裝用於將IC連接至主機板之內插物。封裝之高緊密化可歸因於IC之I/O的數目之增大，且亦已使得用於與內插物進行連接的方法更為有效。
愈發普及的內插物技術中的一者為覆晶結合。矽積體電路(IC)裝置之製造處理流程中的覆晶裝配由若干事實驅動。第一，當與習知線結合互連技術相關的寄生電感減小時，半導體裝置之電效能可得以改良。第二，較之於線結合，覆晶裝配在晶片與封裝之間提供較高互連密度。第三，較之於線結合，覆晶裝配消耗較少矽「佔據面積」，且因此有助於節省矽區域且降低裝置成本。及第四，當使用並行群式結合技術而非連續個別結合步驟時，可降低製造成本。
為了減小內插物的大小及其間距，已努力用金屬凸塊替換先前在覆晶結合中之基於焊料的互連球，尤其是努力藉由經修改的線球技術來產生金屬凸塊。通常，在半導體晶片之接觸襯墊之鋁層上產生金屬凸塊。隨後，使用焊料將晶片附接至基板。該等金屬凸塊用於針對LCD、記憶體、微處理器及微波RFIC之應用的倒裝晶片封裝。
10‧‧‧銀合金凸塊結構
20‧‧‧銀合金凸塊結構
30‧‧‧膜上晶片(COF)半導體結構
40‧‧‧多層凸塊結構
50‧‧‧膜上晶片(COF)半導體結構
60‧‧‧玻璃上晶片(COG)半導體結構
70‧‧‧玻璃上晶片(COG)半導體結構
80‧‧‧玻璃上晶片(COG)半導體結構
100‧‧‧容器
100A‧‧‧入口
100B‧‧‧出口
101‧‧‧銀合金凸塊本體
101A‧‧‧側壁
101B‧‧‧頂表面
102‧‧‧導電襯墊
103‧‧‧鈍化層
104‧‧‧凸塊下金屬化(UBM)層
105‧‧‧晶種層
107‧‧‧金屬層
109‧‧‧第一遮罩層
109A‧‧‧開口
110‧‧‧第二遮罩層
111‧‧‧陽極
112‧‧‧陰極
113‧‧‧電鍍浴
115‧‧‧無電極鍍敷浴
200‧‧‧容器
201‧‧‧熱板
301‧‧‧可撓性膜
301A‧‧‧第一表面
301B‧‧‧第二表面
302‧‧‧導電層
303‧‧‧點框
304‧‧‧底部填充材料
305‧‧‧阻焊劑圖案
306‧‧‧焊料層
307‧‧‧點框
308‧‧‧焊料層
401‧‧‧玻璃基板
401A‧‧‧第一表面
402‧‧‧導電跡線
406‧‧‧各向異性導電膜(ACF)
406A‧‧‧塑膠球體
當結合附圖閱讀時，可自以下詳細描述最佳地理解本發明之態樣。應強調，根據工業中之標準實務，各種特徵不按比例繪製。實際上，為了論述之清楚起見，可任意增大或減小各種特徵之尺寸。
圖1為根據本發明之一些實施例的銀合金凸塊結構之橫截面圖；圖2為根據本發明之一些實施例的粒徑分散曲線；圖3為根據本發明之一些實施例的銀合金凸塊結構之橫截面圖；圖4為根據本發明之一些實施例的具有銀合金凸塊結構之膜上晶片(COF)半導體結構之橫截面圖；圖5為根據本發明之一些實施例的展示於圖4中之接頭部分之放大視圖；圖6為根據本發明之一些實施例的多層凸塊結構之橫截面圖；圖7為根據本發明之一些實施例的具有多層凸塊結構之膜上晶片(COF)半導體結構之橫截面圖；圖8為根據本發明之一些實施例的展示於圖7中之接頭部分之放大視圖；圖9為根據本發明之一些實施例的具有銀合金凸塊結構之玻璃上晶片(COG)半導體結構之橫截面圖；圖10為根據本發明之一些實施例的具有多層凸塊結構之玻璃上晶片(COG)半導體結構之橫截面圖；圖11為根據本發明之一些實施例的具有多層凸塊結構之玻璃上晶片(COG)半導體結構之橫截面圖；及圖12至圖25展示根據本發明之一些實施例的製造銀合金凸塊結構及多層凸塊結構之操作。
在以下詳細描述中，列出了若干特定細節以便提供對本發明之 全面瞭解。然而，熟習此項技術者應瞭解，本發明可在無該等特定細節的情況下實施。在其他情形中，未對熟知方法、程序、組件及電路進行詳細描述，以免混淆本發明。應理解，以下揭示內容提供用於建構各種實施例之不同特徵的許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本發明。當然，此等僅為實例，而並不意欲為限制性的。
下文詳細論述實施例之製作及使用。然而，應瞭解，本發明提供可在廣泛多種特定內容脈絡中體現的許多適用的發明性概念。所論述之特定實施例僅為說明製作及使用本發明之特定方式，而並不限制本發明之範疇。
在半導體封裝之金屬凸塊技術當中，金凸塊由於與此項技術中之材料特性及處理技術之類似性而最為風行。然而，高材料成本、較差結合可靠性及諸如低電導率及低熱導率之不令人滿意的材料特性仍為待解決之問題。製造金屬凸塊之替代成本節省方法係藉由產生多層凸塊，例如，Cu(底部層)、Ni(中間層)及Au(頂部層)凸塊。此方法節省金屬凸塊之金材料消耗，但銅底部層易受氧化及腐蝕，且因此產生可靠性憂慮。
當藉由回焊已沈積在襯墊上之焊料而將金凸塊接合至基板襯墊時，形成數個金/錫金屬間物(intermetallics)。因為金在熔融焊料中之高溶解率，具有金凸塊之焊料接頭在一次回焊之後具有大體積分率之金屬間化合物(其中AuSn4 為主要相)，其使接頭大大變脆。在兩次或兩次以上回焊(對於裝配疊層封裝產品通常為需要的)之後，金凸塊可能完全耗盡且轉化成金/錫金屬間化合物。由於此等化合物及金屬間物與晶片側上之鋁襯墊之直接接觸的脆性，接頭經常由於在凸塊/晶片界面處開裂而通不過諸如機械墜落測試之可靠性測試。
銀凸塊的成本為金凸塊之二十分之一，且銀凸塊在本文中論述 之三種金屬(Au、Cu、Ag)中具有最高電導率及最高熱導率。此外，銀凸塊之退火溫度低於金凸塊之退火溫度，因此大大減少鈍化裂痕之風險。就將銀凸塊接合至基板之焊料而言，在高於共晶溫度之溫度下，銀/錫界面表現出優於金/錫界面之結合特性的結合特性。在本發明之一些實施例中，銀合金用於銀凸塊以避免銀針、銀遷移、純銀所固有的氧化及硫化問題。
本發明之一些實施例提供一種具有銀合金凸塊之半導體結構。銀合金凸塊可為具有0.005至0.25原子%之非銀元件之二元合金或三元合金。在一些實施例中，因為銀合金凸塊係藉由電鍍而形成，因此觀測到均一的粒徑分佈，且可藉由量測粒徑分佈之標準差而量化該粒徑分佈。
本發明之一些實施例提供一種具有含有銀之多層合金凸塊之半導體結構。該多層合金凸塊包括具有0.005至0.25原子%之非銀元件的二元合金或三元合金。在一些實施例中，至少包括Au及Cu之額外金屬層定位在該二元合金或三元合金上方。在一些實施例中，該額外金屬層覆蓋該二元合金或三元合金之側壁。在一些實施例中，因為該多層合金凸塊係藉由電鍍而形成，因此觀測到均一粒徑分佈，且可藉由量測粒徑分佈之標準差而量化該粒徑分佈。
本發明之一些實施例提供一種包括經電鍍銀合金凸塊之膠帶自動結合(TAB)半導體結構。在一些實施例中，膜上晶片(COF)結構包括在薄膜上之銀合金凸塊與導電銅線之間的銀/錫界面。在一些實施例中，額外金屬層定位在該COF結構中之經電鍍銀合金凸塊上方。在一些實施例中，該額外金屬層覆蓋該COF結構中之該經電鍍銀合金凸塊之側壁。
本發明之一些實施例提供一種包括經電鍍Ag1-x Yx 合金凸塊之玻璃上晶片(COG)結構，該經電鍍Ag1-x Yx 合金凸塊將半導體晶片電耦接 至導電層。在一些實施例中，該經電鍍Ag1-x Yx 合金凸塊之Y包括Pd及Au中之至少一者。在一些實施例中，額外金屬層定位在該COG結構中之經電鍍銀合金凸塊上方。在一些實施例中，該額外金屬層覆蓋該COG結構中之該經電鍍銀合金凸塊之側壁。
本發明之一些實施例提供一種在一半導體結構中之經電鍍銀合金凸塊。在一些實施例中，由本文中所描述的經電鍍銀合金凸塊製成之銀合金薄膜具有自約250W/(mK)至約450W/(mK)之熱導率。在其他實施例中，該經電鍍銀合金凸塊具有自約35(Ωm)-1 至約(Ωm)-1 之電導率。
定義
在描述及主張本發明時，將根據下文所闡述的定義使用以下術語。
如本文所使用，「平均粒徑」係藉由諸如X射線繞射(XRD)、電子束散射型式(EBSP)、穿透電子顯微術(TEM)或掃描電子顯微術(SEM)之任何習知粒徑量測技術而量測。樣本之經預處理橫截面平面經製備用於本發明中所論述之粒徑量測。圖1展示銀合金凸塊結構10之橫截面，其中銀合金凸塊本體101連接至導電襯墊102，且銀合金凸塊本體101及導電襯墊102兩者皆定位在裝置100上。銀合金凸塊結構10之縱向方向平行於Y方向。換言之，縱向方向係指垂直於容納銀合金凸塊本體101及導電襯墊102之表面的方向。經受本文中所論述之量測中之任一者的橫截面平面為穿經銀合金凸塊本體101、具有垂直於該縱向方向之平面法線的任何平面。
如本文所使用，用於平均粒徑量測之「電子束散射型式(EBSP)」由電腦分析程式(例如，TSL OIM分析)加以輔助。電腦分析程式之設定包括但不限於15度之晶界錯向、等於或大於0.1之CI值，及至少為5測試點之極小粒徑。在一些實施例中，EBSP量測之平均粒 徑係藉由對至少在橫截面平面之三個不同測試位置上的粒徑求平均而獲得。在每一測試位置量測一預定區域。預定區域根據不同實施例之特徵而變化。每一測試位置距鄰近測試位置至少1mm遠。在一些實施例中，一個測試位置中之每一量測點之間的間隔為至少5μm。在一些實施例中，在20kV之加速電壓及100倍至500倍之放大率下觀測經受EBSP量測之所製備樣本。在一些實施例中，所製備樣本定位在70度之傾斜角處。
如本文所使用，用於平均粒徑量測之「穿透電子顯微術(TEM)或掃描電子顯微術(SEM)」係由影像分析程式(例如，CLEMEX Vision PE)加以輔助。在一些實施例中，TEM或SEM量測之平均粒徑係藉由對橫截面平面之至少三個不同測試位置上的粒徑求平均而獲得。在每一測試位置中量測一預定區域。該預定區域根據不同實施例之特徵而變化。每一測試位置距鄰近測試位置至少1mm遠。在一些實施例中，一個測試位置中之每一量測點之間的間隔為至少5μm。在一些實施例中，在約5kV至約20kV之加速電壓及100倍至500倍之放大率下觀測經受TEM或SEM量測之所製備樣本。
如本文所使用，銀合金凸塊之「粒徑分佈之標準差」係指使用本文中所論述之影像分析程式獲得之統計結果。在獲得粒徑分佈之分散曲線之後，一個標準差被定義為自均值粒徑(期望值)偏離之粒徑，其中粒徑在所偏離粒徑與均值粒徑之間的晶粒之數目占到晶粒之總數目的34%。
圖1為銀合金凸塊結構10之橫截面，其中銀合金凸塊本體101連接至導電襯墊102。銀合金凸塊本體101及導電襯墊102定位在裝置100上。在一些實施例中，裝置100包括但不限於諸如記憶體、電晶體、二極體(PN或PIN接面)、積體電路或可變電抗器之主動裝置。在其他實施例中，裝置100包括諸如電阻器、電容器或電感器之被動裝置。 如圖1中所示，僅展示銀合金凸塊本體101之微觀結構。銀合金凸塊本體101之橫截面係藉由沿縱向方向(Y方向)切割銀合金凸塊結構10而製備，且獲得XY表面。使用電子顯微鏡，在橫截面平面上識別銀合金凸塊本體101之晶粒結構，且在本文中所論述之影像分析軟體之幫助下，可獲得粒徑分佈之統計資訊。
參看圖1，晶粒101A之一區域用直線劃出陰影。銀合金凸塊本體101中所示的SEM圖像係取自本文中所描述的銀合金凸塊本體101之真實橫截面平面。在一些實施例中，因為銀合金凸塊本體101係藉由電鍍操作而形成，因此粒徑分佈相當均一，且未觀測到如螺柱凸塊(未圖示)中之受熱影響區(HAZ)的受熱影響區。HAZ由於以下事實而產生粒徑之突變：晶粒生長程序經受局部高溫。通常，粒徑在HAZ中明顯地增大。在本發明之一些實施例中，可在銀合金凸塊本體101之晶粒中識別出子晶粒結構。舉例而言，在晶粒101A中，可以如下方式看到子晶粒域：可識別出藉由域邊界分離的晶粒101A內之若干區。
在一些實施例中，銀合金凸塊本體101包括Ag1-x Yx 合金。Ag1-x Yx 合金中之物質Y包括以任意權重百分比與銀形成完成固溶體之金屬。在一些實施例中，可藉由觀察二元相圖而識別物質Y。二元相圖中形成透鏡形狀之液相線及固相線指示在兩種金屬組分之任何組成下的固溶體之完全混合。舉例而言，在本發明之一些實施例中，物質Y為金、鈀，或其組合。在一些實施例中，物質Y在Ag1-x Yx 合金中之含量介於約0.005至0.25原子%之間。
如圖1中所示，銀合金凸塊本體101之粒徑形成圖2中之分散曲線。在一些實施例中，圖2中之分散曲線係經由諸如但不限於CLEMEX Vision PE之影像分析軟體程式而獲得。在圖2中，該分散曲線之X軸指示粒徑，而該分散曲線之Y軸展示經正規化之晶粒數目。本發明中之粒徑計算係藉由電腦分析程式(例如，TSL OIM分析)加以 輔助。在一些實施例中，電腦分析程式將晶粒之面積轉換為具有相同面積之假設圓，且此假設圓之直徑被界定為按一長度單位(通常為微米)之粒徑。然而，粒徑計算不限於上述操作。在其他實施例中，平均粒徑係藉由在本文中所描述的銀合金凸塊結構之橫截面平面之TEM圖像或SEM圖像上繪製對角線，並將該對角線之長度除以該對角線所遇到之晶粒的數目而獲得。任何粒徑量測操作為適當的，只要其藉由電腦軟體加以輔助或其係以一致且系統化之方式進行即可。
在繪出如圖2中所示的分散曲線之後，可將標準差量測為銀合金凸塊本體101之微觀結構之形態特徵。在一些實施例中，該分散曲線具有近鐘形狀(eschewed bell shape)，其最大值較接近於該分散曲線之右端。在一些實施例中，粒徑之均值或期望值由分散曲線之最大值表示。如圖2中所示，均值M對應於粒徑A，其在一些實施例中在約0.7μm至約0.8μm之範圍內。離開均值M至正方向一個標準差(+1σ)對應於粒徑C，其在一些實施例中在約1.0μm至約1.1μm之範圍內。離開平均值M至負方向一個標準差(-1σ)對應於粒徑B，其在一些實施例中在約0.4μm至約0.5μm之範圍內。在一些實施例中，一個標準差被定義為自均值M偏離之粒徑，且其中粒徑在所偏離粒徑B或C與均值M之間的晶粒之數目占到晶粒之總數目的34%。注意，獲自實際粒徑量測之分散曲線並不必須關於均值M對稱，且因此，在一些實施例中，離開均值M至粒徑C處之正方向一個標準差(+1σ)與均值M之間的差異未必與在粒徑B處在負方向上離開均值M一個標準差(-1σ)與均值M之間的差異相同。
在本發明之一些實施例中，粒徑C與粒徑A之間的差異約自0.2μm至約0.4μm。在其他實施例中，粒徑B與粒徑A之間的差異約自0.2μm至約0.4μm。藉由利用本發明中所論述之電鍍操作，銀合金凸塊本體101之粒徑表現出均一分佈，且離開均值M(至正或負方向)一個標準 差之間的差異可量化為在0.2μm至約0.4μm之範圍內。
參看圖3，展示銀合金凸塊結構20之橫截面。與圖1中之銀合金凸塊結構10相比，銀合金凸塊結構20進一步包括凸塊下金屬化(UBM)層104及晶種層105。在一些實施例中，晶種層105含有銀或銀合金，且係藉由化學氣相沈積(CVD)、濺鍍及電鍍操作中的一者而製備。在一些實施例中，UBM層104具有單層結構或包括由不同材料形成之若干子層的複合結構，且包括選自以下各者之一(或多)層：鎳層、鈦層、鈦鎢層、鈀層、金層、銀層，及其組合。
如圖3中所示，銀合金凸塊本體101之高度H1係自銀合金凸塊本體之頂表面至導電襯墊102之頂表面而量測。在一些實施例中，銀合金凸塊本體101或Ag1-x Yx 合金之高度H1在約9μm至約15μm之範圍內。與銀合金凸塊本體101之高度H1成比例，UBM層104之厚度T2與晶種層105之厚度T1相當。在一些實施例中，UBM層104之厚度T2在約1000Å至約3000Å之範圍內，且晶種層105之厚度T1在約1000Å至約3000Å之範圍內。
參看圖4，展示膜上晶片(COF)半導體結構30之橫截面。在一些實施例中，半導體結構30為半導體封裝。COF半導體結構30包括可撓性膜301，該可撓性膜301具有第一表面301A及第二表面301B。可撓性膜301包括但不限於可撓性印刷電路板(FPCB)或聚醯亞胺(PI)。諸如導電銅跡線之導電層302經圖案化於可撓性膜301之第一表面301A上。在圖4中，具有與圖1及圖3中所示之數字標記相同的數字標記之元件係指相同元件或其等效物，且為簡單起見而不在此處加以重複。在圖4中，兩個銀合金凸塊本體101將裝置100電耦接至可撓性膜301之導電層302。在一些實施例中，例如無溶劑環氧樹脂之具有適當黏度之底部填充材料304注入至可撓性膜301與裝置100之間的空間中。
圖4中所示的銀合金凸塊本體101包括Ag1-x Yx 合金，其中物質Y為 金、鈀，或其組合。舉例而言，Ag1-x Yx 合金可為諸如Ag1-x Aux 或Ag1-x Pdx 之二元金屬合金，此外，Ag1-x Yx 合金可為諸如Ag1-x (AuPd)x 之三元金屬合金。在一些實施例中，物質Y在Ag1-x Yx 合金中之含量介於約0.005至約0.25原子%之間。在一些實施例中，Ag1-x Yx 合金中之物質Y包括以任何權重百分比與銀形成完全固溶體之金屬。如圖4中所示，銀合金凸塊本體101之高度H1在約9μm至約15μm之範圍內，且鄰近的銀合金凸塊本體101之間的間距P低於10μm。在一些實施例中，導電襯墊102之寬度W在約20μm至約30μm之範圍內。
在圖4中，阻焊劑圖案305定位在導電層302上。焊料層306施加至銀合金凸塊本體101與導電層302之接頭。在本發明之一些實施例中，焊料層306可為習知SnPb或無鉛焊料。由點框303包圍的接頭部分經放大且於圖5中展示。參看圖5，焊料層306不僅包括焊料材料自身，且亦包括Ag1-a Sna 合金。在一些實施例中，Ag1-a Sna 合金至少包括Ag0.5 Sn0.5 合金。在某些實施例中，當用於COF的在銀合金凸塊側設定的內部引線結合(ILB)溫度為約攝氏400度時，AgSn合金系統之液相實質上大於AuSn合金系統之液相(給定在合金凸塊之自由端設定的相同結合溫度)。AgSn合金之過量液相促進銀合金凸塊本體101與導電層302之間的黏附，且因此藉由使用基於Ag之合金凸塊在AgSn合金系統中獲得較好接面可靠性。另一方面，用於COF之較低ILB溫度可用於AgSn合金系統中。例如低於攝氏400度之較低ILB溫度可防止可撓性膜301變形或收縮。在其他實施例中，各向異性導電膜(ACF)可用以連接銀合金凸塊本體101與導電層302。
參看圖5，僅展示銀合金凸塊本體101之微觀結構。銀合金凸塊本體101之平均粒徑在約0.5μm至約1.5μm之範圍內。因為銀之熔化溫度為約攝氏962度，因此施加至銀合金凸塊本體101之退火溫度可低於攝氏250度以避免圖1、圖3及圖4中所示的鈍化層103之開裂。與金 之較高熔化溫度(攝氏1064度)相比，較低熔化溫度導致較低退火溫度，且因此諸如鈍化層之先前生長的結構經受較低熱壓力。在一些實施例中，在於低於攝氏250度之溫度下對銀合金凸塊本體101進行退火之後，藉由本文中所描述的方法量測的Ag1-x Yx 合金之平均粒徑為約1μm。
參看圖6，展示多層凸塊結構40之橫截面。與圖3中之銀合金凸塊結構20相比，多層凸塊結構40進一步包括在銀合金凸塊本體101上方之金屬層107。在一些實施例中，多層凸塊結構40包括如圖1、圖3及圖4中所示的銀合金凸塊結構之銀合金凸塊結構，其中銀合金凸塊本體101之底表面連接至導電襯墊102，且其頂表面連接至金屬層107。在一些實施例中，金屬層107為不同於銀之金屬材料。在其他實施例中，多層凸塊結構40之金屬層107包括金、金合金、銅，或銅合金。在其他實施例中，多層凸塊結構40之金屬層107包括銅及其合金。金屬層107之厚度H2應足夠厚以在銀合金凸塊本體101與外部裝置或基板之間形成接頭界面，例如，可撓性膜之導電跡線(此處未圖示)。
在一些實施例中，金屬層107之厚度H2自約1μm至約3μm，且金屬層107係藉由電鍍操作而形成。在圖6中，多層凸塊結構40包括凸塊下金屬化(UBM)層104及晶種層105。在一些實施例中，晶種層105含有銀或銀合金，且係藉由化學氣相沈積(CVD)、濺鍍及電鍍操作中的一者而製備。在一些實施例中，UBM層104具有單層結構或包括由不同材料形成之若干子層的複合結構，且包括選自以下各者之一(或多)層：鎳層、鈦層、鈦鎢層、鈀層、金層、銀層，及其組合。
圖6中所示的銀合金凸塊本體101包括Ag1-x Yx 合金，其中物質Y為金、鈀，或其組合。舉例而言，Ag1-x Yx 合金可為諸如Ag1-x Aux 或Ag1-x Pdx 之二元金屬合金，此外，Ag1-x Yx 合金可為諸如Ag1-x (AuPd)x 之三元金 屬合金。在一些實施例中，物質Y在Ag1-x Yx 合金中之含量介於約0.005至約0.25原子%之間。在一些實施例中，Ag1-x Yx 合金中之物質Y包括以任何權重百分比與銀形成完全固溶體之金屬。如圖6中所示，銀合金凸塊本體101之高度H1在約9μm至約15μm之範圍內。
參看圖7，展示膜上晶片(COF)半導體結構50之橫截面。在一些實施例中，半導體結構30為半導體封裝。COF半導體結構50包括具有第一表面301A及第二表面301B之可撓性膜301。可撓性膜301包括但不限於可撓性印刷電路板(FPCB)或聚醯亞胺(PI)。諸如導電銅跡線之導電層302經圖案化於可撓性膜301之第一表面301A上，且阻焊劑圖案305定位在導電層302上。在圖7中，與圖1及圖3中所示的數字標記具有相同數字標記的元件係指相同元件或其等效物，且為簡單起見不在此處加以重複。在圖7中，包括銀合金凸塊本體101及金屬層107之兩個多層凸塊結構(101，107)將裝置100電耦接至可撓性膜301之導電層302。在一些實施例中，例如無溶劑環氧樹脂之具有適當黏度的底部填充材料304注入至可撓性膜301與裝置100之間的空間中。在金屬層107係由經電鍍金膜製成之情況下，後續結合操作可利用此項技術中對於金凸塊所習知之結合操作。
圖7中所示的銀合金凸塊本體101包括Ag1-x Yx 合金，其中物質Y為金、鈀，或其組合。舉例而言，Ag1-x Yx 合金可為諸如Ag1-x Aux 或-x Pdx 之二元金屬合金，此外，Ag1-x Yx 合金可為諸如Ag1-x (AuPd)x 之三元金屬合金。在一些實施例中，物質Y在-x YX 合金中之含量介於約0.005至約0.25原子%之間。在一些實施例中，Ag1-x Yx 合金中之物質Y包括以任何權重百分比與銀形成完全固溶體的金屬。圖7中所示的金屬層107包括不同於銀之金屬材料，例如金或銅。如圖7中所示，銀合金凸塊本體101之高度H1在約9μm至約15μm之範圍內，且鄰近的銀合金凸塊本體101之間的間距P低於10μm。金屬層107之高度H2在約1μm至 約3μm之範圍內。在一些實施例中，導電襯墊102之寬度W在約10μm至約20μm之範圍內。
在圖7中，阻焊劑圖案305定位在導電層302上。焊料層308施加至多層凸塊結構(101，107)與導電層302之接頭。在本發明之一些實施例中，焊料層306可為習知SnPb或無鉛焊料。由點框307包圍的接頭部分經放大且展示於圖8中。參看圖8，焊料層308不僅包括焊料材料自身，且亦包括Au1-a Sna 合金(若金屬層107係由Au或其合金製成)。在一些實施例中，Au1-a Sna 合金至少包括Au0.5 Sn0.5 合金。在其他實施例中，各向異性導電膜ACF)可用以連接多層凸塊結構(101，107)與導電層302。
在本發明之一些實施例中，如圖9中所示，本文中論述之銀合金凸塊本體101亦可用於玻璃上晶片(COG)半導體結構60中。透明基板之第一表面401A上的導電跡線402與待封裝之裝置100之銀合金凸塊本體101之間的電連接可為各向異性導電膜(ACF)406。舉例而言，透明基板為玻璃基板401。ACF包括塗有Au之塑膠球體406A，其直徑自約3μm至約5μm，分散在熱固性環氧樹脂基質中。在一些實施例中，用於在COG半導體結構60中使用ACF之結合溫度為約攝氏200度。
在本發明之一些實施例中，如圖10中所示，本文中論述之多層凸塊結構(101，107)亦可用於玻璃上晶片(COG)半導體結構70中。玻璃基板401之第一表面401A上的導電跡線402與待封裝之裝置100的多層凸塊結構(101，107)之間的電連接可為各向異性導電薄(ACF)406。在一些實施例中，玻璃基板401之第一表面401A上的導電跡線402係由諸如氧化銦錫(ITO)之透明且導電材料製成。舉例而言，ACF包括塗有Au之塑膠球體406A，其直徑自約3μm至約5μm，分散在熱固性環氧樹脂基質中。在一些實施例中，用於在COG半導體結構70中使用ACF之結合溫度為約攝氏200度。在一些實施例中，多層凸塊結構 (101，107)之金屬層107為經電鍍金膜，其厚度自約1μm至約3μm。在此情況下，對於金凸塊技術習知之結合操作可用於連接多層凸塊結構(101，107)與諸如玻璃基板之外部裝置。
在本發明之一些實施例中，如圖11中所示，本文中論述之多層凸塊結構(101，107)亦可用於玻璃上晶片(COG)半導體結構80中。玻璃基板401之第一表面401A上的導電跡線402與待封裝之裝置100之多層凸塊結構(101，107)之間的電連接可為各向異性導電膜(ACF)406。舉例而言，ACF包括塗有Au之塑膠球體406A，其直徑自約3μm至約5μm，分散在熱固性環氧樹脂基質中。在一些實施例中，用於在COG半導體結構80中使用ACF之結合溫度為約攝氏200度。在一些實施例中，多層凸塊結構(101，107)之金屬層107為經電鍍金膜，其厚度自約1μm至約3μm，覆蓋銀合金凸塊本體101之頂表面101B及側壁101A。在此情況下，對於金凸塊技術習知之結合操作可用於連接多層凸塊結構(101，107)與諸如玻璃基板之外部裝置。在一些實施例中，頂表面101B上之金屬層107的厚度不同於覆蓋銀合金凸塊本體101之側壁101A之金屬層107的厚度。
可易於藉由選擇適當電鍍浴來調整本文中論述的銀合金凸塊之硬度。舉例而言，可將用於COG應用之銀合金凸塊之硬度調整至約100HV。對於另一實例，可將用於COF應用之銀合金凸塊之硬度調整至約55HV。因為純銀之硬度(約85HV)介於55HV與100HV之間，因此可藉由使用不同電鍍浴來電鍍銀合金凸塊而定製具有所要硬度之銀合金。在一些實施例中，COG應用需要銀合金凸塊具有較大硬度以促進ACF結合操作。在其他實施例中，COF應用需要銀合金凸塊具有較低硬度以防止損傷可撓性膜上之導電跡線。
圖12至圖25展示本發明中描述的銀合金凸塊之製造操作。在圖12中，在鈍化層103及導電襯墊102之一部分上形成UBM層104。在一 些實施例中，UBM層104係藉由對材料進行CVD、濺鍍、電鍍或無電極鍍敷而形成，該等材料係選自鎳、鈦、鈦鎢、鈀、金、銀，及其組合。在一些實施例中，將UBM層104之厚度T2控制在自約1000Å至約3000Å之範圍內。在圖13中，將晶種層105沈積在UBM層104上。在一些實施例中，晶種層105係藉由對含有銀之材料進行CVD、濺鍍、電鍍或無電極鍍敷而形成。在一些實施例中，將晶種層105之厚度T1控制為與UBM層104之厚度T2相當。舉例而言，在自約1000Å至約3000Å之範圍內。
參看圖14，在晶種層105上方形成可為硬式遮罩或光阻劑之第一遮罩層109。在導電襯墊102上方形成第一遮罩層109之開口109A用於接收導電凸塊材料。在一些實施例中，第一遮罩層109係由厚度T3大於待鍍敷之導電凸塊之厚度的正光阻劑製成。在其他實施例中，第一遮罩層109係由負光阻劑製成。
圖15及圖16展示電鍍操作及其後之結果。圖15展示一電鍍系統，其包括容納電鍍浴113、陽極111及陰極112之容器100。在一些實施例中，陽極111不可溶且可由塗有鉑之鈦製成，沈積有恰當晶種層之晶圓襯墊定位在陰極112處，且電鍍浴113含有基於氰化物之鍍敷溶液，包括KAg(CN)2 、KAu(CN)2 、K2 Pd(CN)4 及其鹽。在一些實施例中，將電鍍浴113之pH值控制在約中性，例如自約6至約8。將電鍍浴113之溫度控制在約攝氏40度至攝氏50度。在一些實施例中，可藉由定位在容器100下之熱板(未圖示)來維持電鍍浴113之溫度。在其他實施例中，可藉由一電鍍溶液循環系統來維持電鍍浴113之溫度，在該電鍍溶液循環系統中，出口100B排放電鍍溶液，且入口100A吸入溫度受控之電鍍溶液。可將濃度自約2ml/L至約5ml/L之包括草酸鹽之適當調平劑添加至電鍍浴113。在一些實施例中，經施加以用於銀合金導電凸塊鍍敷之直流電(DC)在約0.1 ASD至約0.5 ASD之範圍內。
參看圖15，陰極112包括沈積有含有銀或銀合金之晶種層105的晶圓襯墊，且在陰極處發生的反應可為以下反應中的一者：KAg (CN )2 →K + +Ag + +2CN -
KAu (CN )2 →K + +Au + +2CN -
K 2 Pd (CN )4 →2K + +Pd 2+ +4CN -
圖15中所示的陽極111包括鉑電極，且其上發生的反應可為：2H 2 O →4H + +O 2(g ) +4e -
外部DC電流之正端連接至陽極，且外部DC電流之負端連接至陰極。如圖15中可見，經還原之銀離子及經還原之金離子沈積至晶圓襯墊之晶種層105上，填充由第一遮罩層109界定之開口109A且形成AgAu二元合金。在一些實施例中，若電鍍浴包括銀離子源(例如，KAg(CN)2 )及鈀離子源(例如，K2 Pd(CN)4 )，則經由上文描述之相同電鍍操作設定，經還原之銀離子及經還原之鈀離子沈積至晶圓襯墊之晶種層105上，填充由第一遮罩層109界定之開口109且形成AgPd二元合金。在一些實施例中，若電鍍浴包括銀離子源(例如，KAg(CN)2 及其鹽)、金離子源(例如，(CN)2 及其鹽)及鈀離子源(例如，K2 Pd(CN)4 及其鹽)，則經由上文描述之相同電鍍操作設定，經還原之銀離子、經還原之金離子及經還原之鈀離子沈積至晶圓襯墊之晶種層105上，填充由第一遮罩層109界定之開口109A，且形成AgAuPd三元合金。
在電鍍如圖6中所示的多層凸塊結構40之一些實施例中，在將AgAu、AgPd或AgAuPd合金沈積至圖15中之晶圓襯墊之晶種層上之後，接著自包括若干金屬離子源之電鍍浴移除晶圓襯墊，且將其置放至含有用於沈積如圖6中所示的非銀金屬層107之金屬離子源的一種物質之另一電鍍浴。
圖16展示在完成圖15中所示的電鍍操作之後的晶圓襯墊。在圖16中，銀合金凸塊本體101形成於導電襯墊102上方。在圖17中，若使 用光阻劑，則剝除第一遮罩層109。藉由蝕刻操作移除不由銀合金凸塊本體101覆蓋之UBM層104及晶種層105以隔離兩個銀合金導電凸塊。
圖16、圖18及圖19提及多層凸塊結構之製造步驟。在一些實施例中，在自圖15中所示的電鍍浴移除之後且在剝除光阻劑之前，接著將晶圓襯墊浸沒至含有KAu(CN)2 及其鹽之另一電鍍浴中。如圖18中所示，金屬層107形成於銀合金凸塊本體101之頂表面101B上。在圖19中，若使用光阻劑，則剝除第一遮罩層109。藉由蝕刻操作移除不由銀合金凸塊本體101覆蓋之UBM層104及晶種層105以隔離兩個多層合金凸塊。
圖16、圖20至圖23及圖25提及多層凸塊結構之製造步驟。在一些實施例中，電鍍操作用以形成多層凸塊結構。在自圖15中所示的電鍍浴移除之後且在剝除光阻劑之前，在第一遮罩層109上形成第二遮罩層110以減小第一遮罩層109之第一寬度W1。在一些實施例中，第一遮罩層109之第一寬度W1足夠寬以形成至經鍍敷銀合金凸塊本體101之側壁101A的實體接觸。在圖20及圖21中，第一遮罩層109經由部分剝除操作而變換成第二寬度W2。在一些實施例中，在剝除操作中移除不由第二硬式遮罩層110覆蓋之部分，且獲得其減小的第二寬度W2。在一些實施例中，第二遮罩層110之第二寬度W2足夠窄以在其自身與經鍍敷銀合金凸塊本體101之側壁101A之間形成一間隙。
圖22展示一電鍍系統，其包括容納電鍍浴113、陽極111及陰極112之容器100。在一些實施例中，陽極111不可溶且可由塗有鉑之鈦製成，沈積有恰當晶種層之晶圓襯墊定位在陰極112處，且電鍍浴113含有基於氰化物之鍍敷溶液，包括KAu(CN)2及其鹽。在一些實施例中，將電鍍浴113之pH值控制為約中性，例如自約6至約8。將電鍍浴113之溫度控制為約攝氏40度至攝氏50度。在一些實施例中，可藉由 定位在容器100下之熱板(未圖示)來維持電鍍浴113之溫度。在其他實施例中，可藉由一電鍍溶液循環系統來維持電鍍浴113之溫度，在該電鍍溶液循環系統中，出口100B排放電鍍溶液，且入口100A吸入溫度受控之電鍍溶液。可將濃度自約2ml/L至約5ml/L之包括草酸鹽之適當調平劑添加至電鍍浴113。在一些實施例中，經施加用於銀合金導電凸塊鍍敷之直流電(DC)在約0.1 ASD至約0.5 ASD之範圍內。
圖23展示在圖22中的電鍍操作之後自電鍍浴113取出的晶圓襯墊。金離子與銀合金凸塊本體101在其表面(包括銀合金凸塊本體101之頂表面101B及側壁101A)處反應，且形成覆蓋銀合金凸塊本體101之頂表面101B及側壁101A兩者之金屬層107。然而，在一些實施例中，金屬層107在頂表面101B處之厚度不同於金屬層107在銀合金凸塊本體101之側壁101A處的厚度。在其他實施例中，金屬層107在頂表面101B處之厚度大於金屬層107在銀合金凸塊本體101之側壁101A處的厚度。
在圖25中，藉由剝除及蝕刻操作移除第一遮罩層109以及不由銀合金凸塊本體101覆蓋之UBM層104及晶種層105以隔離兩個多層合金凸塊。
圖16、圖24及圖25提及多層凸塊結構之製造步驟。在一些實施例中，無電極鍍敷操作用以形成多層凸塊結構。在移除第一遮罩層109之後，最初由第一遮罩層109覆蓋之UBM層104及晶種層105接著被暴露。圖24展示容納無電極鍍敷浴115之容器200。將剝除第一遮罩層109之後的晶圓襯墊浸沒至含有基於氰化物之鍍敷溶液(諸如KAu(CN)2 及其鹽)的無電極鍍敷浴115中。在一些實施例中，將無電極鍍敷浴115之pH值控制為約中性，例如自約6至約8。將無電極鍍敷浴115之溫度控制為約攝氏40度至攝氏50度。在一些實施例中，可藉由定位在容器200下的熱板201維持無電極鍍敷浴115之溫度。在其他實 施例中，可藉由一無電極鍍敷溶液循環系統(未圖示)來維持無電極鍍敷浴115之溫度，在該無電極鍍敷溶液循環系統中，出口排放無電極鍍敷溶液，且入口吸入溫度受控之無電極鍍敷溶液。可將濃度自約2ml/L至約5ml/L之包括草酸鹽及其鹽之適當調平劑添加至無電極鍍敷浴115。如圖24及圖25中所示，金離子與銀合金凸塊本體101在其表面(包括銀合金凸塊本體101之頂表面101B及側壁101A)處反應，且形成覆蓋銀合金凸塊本體101之頂表面101B及側壁101A兩者之金屬層107。然而，在一些實施例中，金屬層107在頂表面101B處之厚度可與金屬層107在銀合金凸塊本體101之側壁101A處的厚度相當。在其他實施例中，藉由無電極鍍敷操作製備之金屬層107的厚度均一性比藉由電鍍操作製備之金屬層107的厚度均一性更佳。
圖25展示在圖24中但在移除不由銀合金凸塊本體101覆蓋之UBM層104及晶種層105之後的晶圓襯墊。
在本發明之一些實施例中，一種半導體結構包括：一裝置；在該裝置上之一導電襯墊；及在該導電襯墊上方之Ag1-x Yx 合金凸塊。Ag1-x Yx 凸塊之Y包含以任意權重百分比與Ag形成完全固溶體之金屬，且Ag1-x Yx 合金凸塊之X在約0.005至約0.25之範圍內。
在本發明之一些實施例中，該Ag1-x Yx 合金凸塊之該Y為Au及Pd中之至少一者。
在本發明之一些實施例中，該Ag1-x Yx 合金凸塊之粒徑分佈之一個標準差在約0.2μm至約0.4μm之範圍內。
在本發明之一些實施例中，Ag1-x Yx 合金凸塊之高度在約9μm至約15μm之範圍內。
在本發明之一些實施例中，該半導體結構進一步包括在該導電襯墊與該-x Yx 合金凸塊之間的一凸塊下金屬化(UBM)層。該UBM層包含Ti、TiW及Ag中之至少一者。
在本發明之一些實施例中，該UBM層之厚度在約1000Å至約3000Å之範圍內。
在本發明之一些實施例中，該半導體結構進一步包括在UBM層與該Ag1-x Yx 合金凸塊之間的一晶種層，且該晶種層包含Ag。
在本發明之一些實施例中，該半導體結構中之該晶種層之厚度在約1000Å至約3000Å之範圍內。
在本發明之一些實施例中，一種半導體結構包括：一裝置；在該裝置上之一導電襯墊；在該導電襯墊上方之一經電鍍Ag1-x Yx 合金凸塊；及在該Ag1-x Yx 合金凸塊上方之一金屬層。該Ag1-x Yx 凸塊之Y包含以任意權重百分比與Ag形成完全固溶體之金屬，且Ag1-x Yx 合金凸塊之X在約0.005至約0.25之範圍內。該Ag1-x Yx 合金凸塊上方之該金屬層包含Au及Cu中之至少一者。
在本發明之一些實施例中，具有一上覆金屬層之該Ag1-x YX 合金凸塊之Y包含Au及Pd中之至少一者。
在本發明之一些實施例中，一個標準差與具有一上覆金屬層之經電鍍Ag1-x Yx 合金凸塊之粒徑分佈的均值之間的差異在約0.2μm至約0.4μm之範圍內。
在本發明之一些實施例中，具有一上覆金屬層之經電鍍Ag1-x YX 合金凸塊之高度在約9μm至約15μm之範圍內。
在本發明之一些實施例中，具有一上覆金屬層之該經電鍍Ag1-x YX 合金凸塊進一步包含在該導電襯墊與該經電鍍Ag1-x Yx 合金凸塊之間的一凸塊下金屬化(UBM)層，且其中該UBM層包含Ti、TiW及Ag中之至少一者。
在本發明之一些實施例中，具有一上覆金屬層之該經電鍍Ag1-x Yx 合金凸塊進一步包含在該UBM層與該經電鍍Ag1-x Yx 合金凸塊之間的一晶種層，且其中該晶種層包含Ag。
在本發明之一些實施例中，該金屬層定位於該經電鍍Ag1-x Yx 合金凸塊上方，且覆蓋具有一上覆金屬層之該經電鍍Ag1-x YX 合金凸塊之一側壁。
在本發明之一些實施例中，在具有一上覆金屬層之該經電鍍Ag1 -x YX 合金凸塊上方的該金屬層之高度在約1μm至約3μm之範圍內。
在本發明之一些實施例中，一種膜上晶片(COF)半導體結構包括：一可撓性膜，其具有一第一表面及一第二表面；在該可撓性膜之該第一表面上的一導電層；在該導電層上方之一半導體晶片；及一經電鍍Ag1-x YX 合金凸塊，其電耦接該半導體晶片與該導電層。該經電鍍Ag1-x Yx 合金凸塊之X在約0.005至約0.25之範圍內。
在本發明之一些實施例中，該COF半導體結構中之該經電鍍Ag1-x Yx 合金凸塊的Y包括以任何權重百分比形成完全固溶體的金屬。
在本發明之一些實施例中，該COF半導體結構中之該經電鍍Ag1-x Yx 合金凸塊的Y為Pd或Au。
在本發明之一些實施例中，該COF半導體結構中之該經電鍍Ag1-x YX 合金凸塊進一步包含在該經電鍍Ag1-x Yx 合金凸塊與該導電層之間的一非銀金屬層。
在本發明之一些實施例中，該非銀金屬層覆蓋該COF半導體結構中之該經電鍍Ag1-x Yx 合金凸塊的一側壁。
在本發明之一些實施例中，該COF半導體結構進一步包括在該導電層與該經電鍍Ag1-x Yx 合金凸塊之間的一焊料層及一Sn-Ag合金層。
在本發明之一些實施例中，該-x Yx 合金凸塊在該COF半導體結構中之一縱向橫截面平面上的平均粒徑在約0.5μm至約1.5μm之範圍內。
在本發明之一些實施例中，一種玻璃上晶片(COG)半導體結構包括：一透明基板，其具有一第一表面及一第二表面；在該透明基板之 該第一表面上的一透明導電層；在該導電層上方之一半導體晶片；及一經電鍍Ag1-x YX 合金凸塊，其電耦接該半導體晶片與該導電層。該經電鍍Ag1-x Yx 合金凸塊之X在約0.005至約0.25之範圍內。
在本發明之一些實施例中，一COG半導體結構中之該經電鍍Ag1-x Yx 合金凸塊的Y包含Pd及Au中之至少一者。
在本發明之一些實施例中，一COG半導體結構中之該經電鍍Ag1-x YX 合金凸塊進一步包含在該經電鍍Ag1-x Yx 合金凸塊與該導電層之間的一非銀金屬層。
在本發明之一些實施例中，該非銀金屬層覆蓋一COG半導體結構中之該經電鍍Ag1-x Yx 合金凸塊的一側壁。
在本發明之一些實施例中，該-x Yx 合金凸塊在一COG半導體結構中之一縱向橫截面平面上的平均粒徑在約0.5μm至約1.5μm之範圍內。
此外，本申請案之範疇不意欲限於說明書中描述之製程、機器、製造，及物質組成、構件、方法及步驟之特定實施例。如熟習此項技術者將易於自本發明之揭示內容而瞭解，可根據本發明利用執行與本文中所描述的對應實施例執行實質上相同的功能或達成與該等對應實施例實質上相同的結果的當前現有或稍後待開發的程序、機器、製造、物質組成、構件、方法或步驟。
因此，所附申請專利範圍意欲在其範疇中包括此等程序、機器、製造，及物質組成、構件、方法或步驟。此外，每一請求項構成一單獨實施例，且各種請求項及實施例之組合在本發明之範疇內。
30‧‧‧膜上晶片(COF)半導體結構
100‧‧‧容器
101‧‧‧銀合金凸塊本體
102‧‧‧導電襯墊
103‧‧‧鈍化層
301‧‧‧可撓性膜
301A‧‧‧第一表面
301B‧‧‧第二表面
302‧‧‧導電層
303‧‧‧點框
304‧‧‧底部填充材料
305‧‧‧阻焊劑圖案
306‧‧‧焊料層

Claims (25)

  1. 一種半導體結構，其包含：一裝置；在該裝置上之一導電襯墊；在該導電襯墊上方之一Ag1-x Yx 合金凸塊，及在該導電襯墊與該Ag1-x Yx 合金凸塊之間的一晶種層，且該晶種層包含Ag，其中該Ag1-x Yx 凸塊之Y包含以任意權重百分比與Ag形成完全固溶體之金屬，且其中該Ag1-x Yx 合金凸塊之X在約0.005至約0.25之一範圍內。
  2. 如請求項1之半導體結構，其中該Y包含Au及Pd中之至少一者。
  3. 如請求項1之半導體結構，一個標準差與該Ag1-x Yx 合金凸塊之一粒徑分佈之一均值之間的一差異在約0.2μm至約0.4μm之一範圍內。
  4. 如請求項1之半導體結構，其中該Ag1-x Yx 合金凸塊之一高度在約9μm至約15μm之一範圍內。
  5. 如請求項1之半導體結構，其進一步包含在該導電襯墊與該Ag1-x Yx 合金凸塊之間的一凸塊下金屬化(UBM)層，且其中該UBM層包含Ti、TiW及Ag中之至少一者。
  6. 如請求項5之半導體結構，該UBM層之一厚度在約1000Å至約3000Å之一範圍內。
  7. 如請求項1之半導體結構，該晶種層之一厚度在約1000Å至約3000Å之一範圍內。
  8. 一種半導體結構，其包含： 一裝置；在該裝置上之一導電襯墊；在該導電襯墊上方之一經電鍍Ag1-x Yx 合金凸塊；在該Ag1-x YX 合金凸塊上方之一金屬層，及在該導電襯墊與該Ag1-x Yx 合金凸塊之間的一晶種層，且該晶種層包含Ag，其中該經電鍍Ag1-x Yx 凸塊之Y包含以任意權重百分比與Ag形成完全固溶體之金屬，其中該經電鍍Ag1-x Yx 合金凸塊之X在約0.005至約0.25之一範圍內，且其中該金屬層包含Au及Cu中之至少一者。
  9. 如請求項8之半導體結構，其中該Y包含Au及Pd中之至少一者。
  10. 如請求項8之半導體結構，一個標準差與該經電鍍Ag1-x Yx 合金凸塊之一粒徑分佈之一均值之間的一差異在約0.2μm至約0.4μm之一範圍內。
  11. 如請求項8之半導體結構，其中該經電鍍Ag1-x Yx 合金凸塊之一高度在約9μm至約15μm之一範圍內。
  12. 如請求項8之半導體結構，其進一步包含在該導電襯墊與該經電鍍Ag1-x Yx 合金凸塊之間的一凸塊下金屬化(UBM)層，且其中該UBM層包含Ti、TiW及Ag中之至少一者。
  13. 如請求項8之半導體結構，其中該金屬層位於該經電鍍Ag1-x Yx 合金凸塊上方，且覆蓋該經電鍍Ag1-x Yx 合金凸塊之一側壁。
  14. 如請求項8之半導體結構，該金屬層之一高度在約1μm至約3μm之一範圍內。
  15. 一種膜上晶片(COF)半導體結構，其包含：一可撓性膜，其具有一第一表面及一第二表面； 在該可撓性膜之該第一表面上的一導電層；在該導電層上方之一半導體晶片；一經電鍍Ag1-x Yx 合金凸塊，其電耦接該半導體晶片與該導電層，其中該經電鍍Ag1-x Yx 合金凸塊之X在約0.005至約0.25之一範圍內；及在該導電層與該經電鍍Ag1-x Yx 合金凸塊之間的一Sn-Ag合金層。
  16. 如請求項15之COF半導體結構，其中該經電鍍Ag1-x Yx 合金凸塊的Y包含以任何權重百分比與Ag形成完全固溶體之金屬。
  17. 如請求項16之COF半導體結構，其中該經電鍍Ag1-x Yx 合金凸塊之該Y為Pd或Au。
  18. 如請求項15之COF半導體結構，其進一步包含在該經電鍍Ag1-x Yx 合金凸塊與該導電層之間的一非銀金屬層。
  19. 如請求項18之COF半導體結構，其中該非銀金屬層覆蓋該經電鍍Ag1-x Yx 合金凸塊之一側壁。
  20. 如請求項15之COF半導體結構，該Ag1-x Yx 合金凸塊在一縱向橫截面平面上之一平均粒徑在約0.5μm至約1.5μm之一範圍內。
  21. 一種玻璃上晶片(COG)半導體結構，其包含：一透明基板，其具有一第一表面及一第二表面；在該基板之該第一表面上的一透明導電層；在該導電層上方之一半導體晶片；一經電鍍Ag1-x Yx 合金凸塊，其將該半導體晶片電耦接至該導電層，其中該經電鍍Ag1-x Yx 合金凸塊之X在約0.005至約0.25之一範圍內；及在該經電鍍Ag1-x Yx 合金凸塊下的一晶種層，且該晶種層包含 Ag。
  22. 如請求項21之COG半導體結構，其中該經電鍍Ag1-x Yx 合金凸塊的Y包含Pd及Au中之至少一者。
  23. 如請求項21之COG半導體結構，其進一步包含在該經電鍍Ag1-x Yx 合金凸塊與該導電層之間的一非銀金屬層。
  24. 如請求項23之COG半導體結構，其中該非銀金屬層覆蓋該經電鍍Ag1-x Yx 合金凸塊之一側壁。
  25. 如請求項21之COG半導體結構，該Ag1-x Yx 合金凸塊在一縱向橫截面平面上之一平均粒徑在約0.5μm至約1.5μm之一範圍內。
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