TWI455142B - Data storage device and data read method of a flash memory - Google Patents
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Description
本發明係有關於資料儲存裝置，特別是有關於快閃記憶體。The present invention relates to data storage devices, and more particularly to flash memory.
快閃記憶體(flash memory)係一種非揮發記憶體，亦即，當快閃記憶體不接受供電時，快閃記憶體中儲存的資料亦不會因失去電力而消失，因此快閃記憶體廣泛地被運用在電力有限的可攜式裝置供儲存資料。快閃記憶體包含多個記憶單元(memory cell)，每一記憶單元可儲存2N 種電位。例如，每一記憶單元可儲存2種電位的快閃記憶體稱之為單層單元(single level cell,SLC)快閃記憶體，每一記憶單元可儲存4種電位的快閃記憶體稱之為多層單元(multi level cell,MLC)快閃記憶體，而每一記憶單元可儲存8種電位的快閃記憶體稱之為三層單元(triple level cell,TLC)快閃記憶體。Flash memory is a kind of non-volatile memory, that is, when the flash memory does not receive power, the data stored in the flash memory will not disappear due to loss of power, so the flash memory Widely used in portable devices with limited power for storing data. The flash memory contains a plurality of memory cells, each of which can store 2 N potentials. For example, each memory unit can store two kinds of potential flash memory, which is called a single level cell (SLC) flash memory, and each memory unit can store four kinds of potential flash memory. It is a multi-level cell (MLC) flash memory, and each memory cell can store 8 kinds of potential flash memory called triple level cell (TLC) flash memory.
當主機欲由快閃記憶體讀取資料時，快閃記憶體會依據一組讀取電壓以判定所欲讀取的記憶單元的電壓落在讀取電壓的哪一範圍，從而認定所欲讀取的記憶單元所儲存之資料值為何。舉例來說，當快閃記憶體為單層單元快閃記憶體時，對應的讀取電壓僅有一個分界值，當記憶單元的電壓高於該分界值時記憶單元之資料儲存值會被判定為位元0，而當記憶單元的電壓低於該分界值時記憶單元之資料儲存值會被判定為位元1。另外，當快閃記憶體為多層單元快閃記憶體時，對應的讀取電壓有三個分界值，以依據記憶單元的電壓與三個分界值的相對大小辨別記憶單元之資料儲存值為位元11、01、00、或10。同樣的，當快閃記憶體為三層單元快閃記憶體時，對應的讀取電壓有七個分界值，以依據記憶單元的電壓與七個分界值的相對大小辨別記憶單元之資料儲存值為位元111、011、001、101、100、000、010、或110。第1圖為三層單元快閃記憶體的一組讀取電壓的示意圖。讀取電壓可因三層單元快閃記憶體之記憶單元所儲存的位元數目而不同。When the host wants to read data from the flash memory, the flash memory determines the desired reading according to a set of read voltages to determine which range of the read voltage the voltage of the memory cell to be read falls. What is the value of the data stored in the memory unit? For example, when the flash memory is a single-layer cell flash memory, the corresponding read voltage has only one demarcation value. When the voltage of the memory cell is higher than the demarcation value, the data storage value of the memory cell is determined. It is bit 0, and when the voltage of the memory cell is lower than the threshold value, the data storage value of the memory unit is determined as bit 1. In addition, when the flash memory is a multi-level cell flash memory, the corresponding read voltage has three demarcation values, and the data storage value of the memory cell is discriminated according to the relative magnitude of the voltage of the memory cell and the three demarcation values. 11, 01, 00, or 10. Similarly, when the flash memory is a three-layer cell flash memory, the corresponding read voltage has seven demarcation values to distinguish the data storage value of the memory cell according to the relative magnitude of the voltage of the memory cell and the seven demarcation values. It is a bit 111, 011, 001, 101, 100, 000, 010, or 110. Figure 1 is a schematic diagram of a set of read voltages for a three-layer cell flash memory. The read voltage may vary depending on the number of bits stored in the memory cells of the three-layer cell flash memory.
因此，讀取電壓決定了快閃記憶體之記憶單元的讀出資料值。亦即，一記憶單元所儲存的電壓經過不同的讀取電壓的判定可產生不同的資料讀出值。因此，當快閃記憶體收到主機讀取資料的命令而對儲存資料進行讀取，但讀出資料卻發生錯誤時，可嘗試運用不同的讀取電壓重新對儲存資料進行讀取。然而，如何自依據多個不同的讀取電壓所產生的多個不同的讀出資料值中選擇正確的讀出資料值是一個問題。因此，本發明提出一種快閃記憶體之資料讀取的方法，以便於讀出資料卻發生錯誤時，仍可藉修改讀取電壓而產生正確的讀出資料值。Therefore, the read voltage determines the read data value of the memory cell of the flash memory. That is, the determination of the voltage stored in a memory cell through different read voltages may result in different data readout values. Therefore, when the flash memory receives the command to read the data from the host and reads the stored data, but the data is read incorrectly, an attempt can be made to read the stored data again using different read voltages. However, how to select the correct read data value from a plurality of different read data values generated from a plurality of different read voltages is a problem. Therefore, the present invention provides a method for reading data of a flash memory so that when a data is read but an error occurs, the read voltage can be modified to generate a correct read data value.
有鑑於此，本發明之目的在於提供一種快閃記憶體之資料讀取的方法，以解決習知技術存在之問題。於一實施例中，該快閃記憶體包含多個頁(page)，每一該等頁皆被寫入一筆該預定資訊。首先，以一原始讀取電壓自該快閃記憶體讀取一位址，以得到一原始資料以及一原始錯誤修正碼。接著，以一第一錯誤修正程序(error correction process)依據該原始錯誤修正碼修正該原始資料之錯誤位元。當該第一錯誤修正程序無法修正該原始資料之錯誤位元時，以該原始讀取電壓自該快閃記憶體讀取對應於該原始資料之該預定資訊，以得到一校正資訊(calibration information)。接著，依據該校正資訊與該預定資訊之差別修改該原始資料以產生一修改資料。接著，依據該校正資訊與該預定資訊之差別修改該原始錯誤修正碼以產生一修改錯誤修正碼。接著，以一第二錯誤修正程序依據該修改錯誤修正碼修正該修改資料之錯誤位元。最後，當該第二錯誤修正程序成功地修正該原始資料之錯誤位元而得到一第二輸出資料時，將該第二輸出資料作為讀出資料而傳送至一主機。In view of the above, an object of the present invention is to provide a method for reading data of a flash memory to solve the problems of the prior art. In one embodiment, the flash memory includes a plurality of pages, each of which is written with a predetermined amount of information. First, an address is read from the flash memory at an original read voltage to obtain an original data and an original error correction code. Then, the error bit of the original data is corrected according to the original error correction code by a first error correction process. When the first error correction program cannot correct the error bit of the original data, the predetermined information corresponding to the original data is read from the flash memory by the original read voltage to obtain a calibration information (calibration information) ). Then, the original data is modified according to the difference between the correction information and the predetermined information to generate a modified data. Then, the original error correction code is modified according to the difference between the correction information and the predetermined information to generate a modified error correction code. Then, the error bit of the modified data is corrected according to the modified error correction code by a second error correction program. Finally, when the second error correction program successfully corrects the error bit of the original data to obtain a second output data, the second output data is transmitted to the host as read data.
本發明更提供一種資料儲存裝置。於一實施例中，該資料儲存裝置耦接至一主機，包括一快閃記憶體以及一控制器。該快閃記憶體包括多個頁以供儲存資料，其中每一該等頁皆被寫入一預定資訊。該控制器命令該快閃記憶體以一原始讀取電壓讀取一位址以得到一原始資料以及一原始錯誤修正碼，以一第一錯誤修正程序(error correction process)依據該原始錯誤修正碼修正該原始資料之錯誤位元，以及當該第一錯誤修正程序無法修正該原始資料之錯誤位元時，命令該快閃記憶體以該原始讀取電壓讀取對應於該原始資料之該預定資訊以得到一校正資訊(calibration information)，依據該校正資訊與該預定資訊之差別修改該原始資料以產生一修改資料，依據該校正資訊與該預定資訊之差別修改該原始錯誤修正碼以產生一修改錯誤修正碼，以一第二錯誤修正程序依據該修改錯誤修正碼修正該修改資料之錯誤位元，以及當該第二錯誤修正程序成功地修正該原始資料之錯誤位元而得到一第二輸出資料時將該第二輸出資料作為讀出資料而傳送至該主機。The invention further provides a data storage device. In one embodiment, the data storage device is coupled to a host, including a flash memory and a controller. The flash memory includes a plurality of pages for storing data, wherein each of the pages is written with a predetermined information. The controller instructs the flash memory to read an address with an original read voltage to obtain a raw data and an original error correction code, and the first error correction process is based on the original error correction code. Correcting an error bit of the original data, and when the first error correction program cannot correct the error bit of the original data, instructing the flash memory to read the predetermined correspondence corresponding to the original data with the original read voltage The information is obtained by a calibration information, and the original data is modified according to the difference between the correction information and the predetermined information to generate a modified data, and the original error correction code is modified according to the difference between the correction information and the predetermined information to generate a Modifying the error correction code, correcting the error bit of the modified data according to the modified error correction code by a second error correction program, and obtaining a second when the second error correction program successfully corrects the error bit of the original data When the data is output, the second output data is transmitted to the host as read data.
為了讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉數較佳實施例，並配合所附圖示，作詳細說明如下：The above and other objects, features, and advantages of the present invention will become more apparent and understood.
第2圖為依據本發明之快閃記憶體用以儲存資料之一區塊(block)200的示意圖。資料區塊200包括多個頁(page)201~20K以供儲存資料，每一頁可儲存多個資料區段(sector)。於一實施例中，每一資料區段之大小為512位元組，而資料區塊200的一頁可儲存4個資料區段。一般而言，為了減少資料儲存時產生的錯誤，於一資料區段儲存至快閃記憶體之前，快閃記憶體的控制器會事先依據資料區段編碼一錯誤修正碼(Error correction code,ECC)，並在儲存資料區段時一併將對應的錯誤修正碼儲存至快閃記憶體。舉例來說，頁201儲存了4個資料區段201a、201b、201c、以及201d，每一資料區段201a、201b、201c、以及201d皆包含一對應的錯誤修正碼。另外，為了自依據多組讀取電壓自快閃記憶體所讀取多個的讀出資料中找出正確的讀出資料，控制器會於儲存資料時一併將一預定資訊寫入快閃記憶體中。於一實施例中，資料區塊200的每一頁儲存一預定資訊。例如，頁201儲存一預定資訊201e。於一實施例中，該預定資訊僅有一位元組。例如，該預定資訊之值可為0x55(位元01010101)。2 is a schematic diagram of a block 200 for storing data in accordance with the flash memory of the present invention. The data block 200 includes a plurality of pages 201-20K for storing data, and each page can store a plurality of data sectors. In one embodiment, each data segment has a size of 512 bytes, and a page of data block 200 stores 4 data segments. In general, in order to reduce the errors generated during data storage, the flash memory controller encodes an error correction code (ECC) according to the data segment before storing the data segment in the flash memory. ), and store the data section and store the corresponding error correction code to the flash memory. For example, page 201 stores four data sections 201a, 201b, 201c, and 201d, each of which contains a corresponding error correction code. In addition, in order to find the correct read data from the plurality of read data read from the flash memory according to the plurality of sets of read voltages, the controller writes a predetermined information to the flash when the data is stored. In memory. In one embodiment, each page of the data block 200 stores a predetermined message. For example, page 201 stores a predetermined message 201e. In an embodiment, the predetermined information has only one tuple. For example, the value of the predetermined information may be 0x55 (bit 0101101).
第3圖為依據本發明之資料儲存裝置302的區塊圖。資料儲存裝置302耦接至一主機304。於一實施例中，資料儲存裝置302包括一控制器312以及一快閃記憶體314。控制器312依據主機304之指示存取快閃記憶體314之資料。當主機304向資料儲存裝置302發送寫入命令時，控制器312依據寫入命令將資料寫入快閃記憶體314。特別是，控制器312會於寫入資料時將一預定資訊一併寫入快閃記憶體314，如第2圖所示。當主機304向資料儲存裝置302發送讀取命令時，控制器312依據讀取命令將資料由快閃記憶體314讀出。然而，即使讀出的資料發生讀取錯誤，控制器312依然可命令快閃記憶體314以不同的讀取電壓產生多個讀取資料值，並依據事先儲存於快閃記憶體314中的預定資訊決定正確的讀取資料值，以避免讀取錯誤的發生。Figure 3 is a block diagram of a data storage device 302 in accordance with the present invention. The data storage device 302 is coupled to a host 304. In one embodiment, the data storage device 302 includes a controller 312 and a flash memory 314. The controller 312 accesses the data of the flash memory 314 in accordance with the instruction of the host 304. When the host 304 sends a write command to the data storage device 302, the controller 312 writes the data to the flash memory 314 in accordance with the write command. In particular, the controller 312 writes a predetermined piece of information to the flash memory 314 when the data is written, as shown in FIG. When the host 304 sends a read command to the data storage device 302, the controller 312 reads the data from the flash memory 314 in accordance with the read command. However, even if a read error occurs in the read data, the controller 312 can instruct the flash memory 314 to generate a plurality of read data values at different read voltages, and according to the reservation stored in the flash memory 314 in advance. Information determines the correct reading of data values to avoid read errors.
第4圖為依據本發明之快閃記憶體之資料讀取的方法400的流程圖。控制器312依據方法400以對快閃記憶體314進行資料讀取。於一實施例中，控制器312包括錯誤修正模組322、資料修改模組324、以及緩衝器326。首先，控制器312命令快閃記憶體314以一原始電壓讀取一位址(步驟402)。當快閃記憶體314依據控制器312的命令進行資料讀取而讀出一原始資料及對應的錯誤修正碼後，錯誤修正模組322會以一錯誤修正程序(error correction process)依據該錯誤修正碼修正該原始資料的錯誤位元(步驟404)。此時，若該原始資料的錯誤位元被成功地修正而產生一輸出資料(步驟406)，則控制器312將錯誤修正模組322產生的輸出資料儲存至緩衝器326，再由緩衝器326將輸出資料輸送至主機304(步驟420)。Figure 4 is a flow diagram of a method 400 of reading data from a flash memory in accordance with the present invention. Controller 312 performs data reading on flash memory 314 in accordance with method 400. In one embodiment, the controller 312 includes an error correction module 322, a data modification module 324, and a buffer 326. First, controller 312 instructs flash memory 314 to read an address at an original voltage (step 402). After the flash memory 314 reads the original data and the corresponding error correction code according to the command of the controller 312, the error correction module 322 corrects the error according to an error correction process. The code corrects the error bit of the original data (step 404). At this time, if the error bit of the original data is successfully corrected to generate an output data (step 406), the controller 312 stores the output data generated by the error correction module 322 to the buffer 326, and then the buffer 326. The output data is delivered to host 304 (step 420).
若該原始資料的錯誤位元無法被成功地修正(步驟406)，則錯誤修正模組322無法產生一正確的輸出資料，以供傳送至主機304。此時，控制器312要求快閃記憶體314以該原始讀取電壓讀取對應於該原始資料之一預定資訊，以得到一校正資訊(步驟408)。於一實施例中，該預定資訊與該原始資料儲存於快閃記憶體314的同一區塊的同一頁，如第2圖所示。控制器312便可依據所讀出的校正資訊與原本的預定資訊之差別以找出錯誤位元發生的型態。舉例來說，假設原本的預定資訊為位元組0x55(位元串01010101)，而快閃記憶體314依據該原始讀取電壓所讀出的校正資訊為位元組0x54(位元串01010100)。由此，控制器312可得知預定資訊0x55中的部份位元1經由原始讀取電壓被判斷為校正資訊0x54中的位元0，因此控制器312可自校正資訊中決定一錯誤位元值0。亦即，校正資訊中部份的位元0為錯誤位元。If the error bit of the original material cannot be successfully corrected (step 406), the error correction module 322 cannot generate a correct output data for transmission to the host 304. At this time, the controller 312 requests the flash memory 314 to read the predetermined information corresponding to the original data with the original read voltage to obtain a correction information (step 408). In one embodiment, the predetermined information is stored in the same page as the original data in the same block of the flash memory 314, as shown in FIG. The controller 312 can find out the type of error bit occurrence based on the difference between the read correction information and the original predetermined information. For example, suppose the original predetermined information is a byte 0x55 (bit string 01010101), and the correction information read by the flash memory 314 according to the original read voltage is a byte 0x54 (bit string 01010100). . Thus, the controller 312 can know that part of the bit 1 in the predetermined information 0x55 is determined to be the bit 0 in the correction information 0x54 via the original read voltage, so the controller 312 can determine an error bit from the correction information. The value is 0. That is, the bit 0 of the correction information is an error bit.
接著，控制器312要求快閃記憶體314以一修改讀取電壓讀取該位址(步驟410)，其中該修改讀取電壓與該原始讀取電壓不相同。於一實施例中，控制器312依據預定資訊與校正資訊調整原始讀取電壓以得到該修改讀取電壓。於一實施例中，快閃記憶體314包括一讀取電壓設定電路330，可依據控制器312的指示更改讀取電壓的設定值。接著，快閃記憶體314依據該修改讀取電壓進行資料讀取，以得到一重讀資料以及一重讀錯誤修正碼(步驟410)。當然，由於讀取電壓不相同，重讀資料與原始資料的部份位元會不同，而重讀錯誤修正碼與原始錯誤修正碼的部份位元亦會不同。此時，資料修改模組324便可根據由校正資訊與預定資訊之差異所決定的錯誤位元值，修改重讀資料與原始資料的部份差異位元，以得到具有較高正確率的一修改資料(步驟412)。同樣的，資料修改模組324亦可根據由校正資訊與預定資訊之差異所決定的錯誤位元值，修改重讀錯誤修正碼與原始錯誤修正碼的部份差異位元，以得到具有較高正確率的一修改錯誤修正碼(步驟414)。步驟412及414的詳細流程將以第5圖進行說明。Next, the controller 312 requests the flash memory 314 to read the address with a modified read voltage (step 410), wherein the modified read voltage is not the same as the original read voltage. In one embodiment, the controller 312 adjusts the original read voltage according to the predetermined information and the correction information to obtain the modified read voltage. In one embodiment, the flash memory 314 includes a read voltage setting circuit 330 that changes the set value of the read voltage in accordance with an instruction from the controller 312. Next, the flash memory 314 performs data reading according to the modified read voltage to obtain a reread data and a reread error correction code (step 410). Of course, since the read voltages are different, the re-reading data and the original data will be different in some bits, and the re-reading error correction code and the original error correction code will also be different. At this time, the data modification module 324 can modify the partial difference bits of the reread data and the original data according to the error bit value determined by the difference between the correction information and the predetermined information, so as to obtain a modification with a higher correct rate. Information (step 412). Similarly, the data modification module 324 can also modify the partial error bits of the reread error correction code and the original error correction code according to the error bit value determined by the difference between the correction information and the predetermined information, so as to obtain a higher correctness. A modified error correction code for the rate (step 414). The detailed flow of steps 412 and 414 will be described with reference to FIG.
第5圖為依據本發明修改原始資料及原始錯誤修正碼之方法500的流程圖。資料修改模組324依據方法500產生修改資料以及修改錯誤修正碼。首先，資料修改模組324辨別原始資料與重讀資料不相同的多個第一差異位元(步驟502)。假設原始資料為位元串0000011111，而重讀資料為0000111110。因此，原始資料與重讀資料有兩個差異位元，分別為原始資料中次序5的位元0及次序10的位元1。接著，資料修改模組324辨別原始錯誤修正碼與重讀錯誤修正碼不相同的多個第二差異位元(步驟504)。假設原始錯誤修正碼為位元串01010，而重讀錯誤修正碼為01011。因此，原始錯誤修正碼與重讀錯誤修正碼之差異位元為原始錯誤修正碼中次序5的位元1。Figure 5 is a flow diagram of a method 500 of modifying original data and original error correction code in accordance with the present invention. The data modification module 324 generates modified data and modifies the error correction code according to the method 500. First, the data modification module 324 discriminates a plurality of first difference bits that are different from the original data and the reread data (step 502). Assume that the original data is the bit string 0000011111, and the reread data is 0000111110. Therefore, the original data and the reread data have two different bits, which are the bit 0 of the order 5 and the bit 1 of the order 10 in the original data. Next, the data modification module 324 discriminates a plurality of second difference bits that are different from the reread error correction code (step 504). Assume that the original error correction code is the bit string 01010 and the reread error correction code is 01011. Therefore, the difference bit between the original error correction code and the reread error correction code is the bit 1 of the order 5 in the original error correction code.
接著，資料修改模組324比較校正資訊與預定資訊之差異以自位元0與位元1中選取一錯誤位元值(步驟506)。一如之前所舉之例，假設預定資訊為位元組0x55(位元串01010101)，而校正資訊為位元組0x54(位元串01010100)，因此資料修改模組324可自校正資訊中決定一錯誤位元值0。接著，資料修改模組324自原始資料之多個第一差異位元中辨別出具有該錯誤位元值之多個第三差異位元(步驟508)，並反轉原始資料之該等第三差異位元之值以得到該修改資料(步驟510)。例如，由於原始資料的位元串0000011111的兩個差異位元中僅有次序5的位元0與錯誤位元值0相等，因此資料修改模組324反轉原始資料中次序5的位元0為位元1，而得到修改資料之位元串0000111111。Next, the data modification module 324 compares the difference between the correction information and the predetermined information to select an error bit value from the bit 0 and the bit 1 (step 506). As in the previous example, it is assumed that the predetermined information is the byte 0x55 (bit string 01010101), and the correction information is the byte 0x54 (bit string 01010100), so the data modification module 324 can determine from the correction information. An error bit value of 0. Next, the data modification module 324 identifies a plurality of third difference bits having the error bit value from the plurality of first difference bits of the original data (step 508), and inverts the third of the original data. The value of the difference bit is obtained to obtain the modified material (step 510). For example, since only the bit 0 of the order 5 of the two difference bits of the bit string 0000011111 of the original material is equal to the error bit value 0, the data modification module 324 inverts the bit 0 of the order 5 in the original material. For bit 1, the bit string 0000111111 of the modified data is obtained.
接著，資料修改模組324自原始錯誤修正碼之多個第二差異位元中辨別出具有該錯誤位元值之多個第四差異位元(步驟512)，並反轉原始錯誤修正碼之該等第四差異位元之值以得到該修改錯誤修正碼(步驟514)。例如，由於原始錯誤修正碼的位元串01010中僅有次序5的差異位元0與錯誤位元值0相等，因此資料修改模組324反轉原始錯誤修正碼中次序5的位元0為位元1，而得到修改錯誤修正碼之位元串01011。Next, the data modification module 324 discriminates a plurality of fourth difference bits having the error bit value from the plurality of second difference bits of the original error correction code (step 512), and inverts the original error correction code. The values of the fourth difference bits are used to obtain the modified error correction code (step 514). For example, since only the difference bit 0 of the order 5 in the bit string 01010 of the original error correction code is equal to the error bit value 0, the data modification module 324 inverts the bit 0 of the order 5 in the original error correction code as Bit 1, and the bit string 01011 of the modified error correction code is obtained.
最後，當資料修改模組324產生修改資料及修改錯誤修正碼後，資料修改模組324將修改資料及修改錯誤修正碼送至錯誤修正模組322。接著，錯誤修正模組322以錯誤修正程序依據該修改錯誤修正碼修正該修改資料之錯誤位元(步驟416)。此時，若錯誤修正模組322可成功地修正該修改資料之錯誤位元而產生一輸出資料(步驟418)，則錯誤修正模組322將輸出資料傳送至緩衝器326。接著，緩衝器326將正確的輸出資料傳送至主機304，以完成讀取動作之執行。反之，若錯誤修正模組322無法成功地修正該修改資料之錯誤位元，則控制器312可再度藉讀取電壓設定電路330重新設定一新修改讀取電壓，然後重新執行步驟410~418。萬一錯誤修正模組322仍然無法成功地修正該修改資料之錯誤位元，則控制器312回報主機304讀取資料失敗(步驟422)。Finally, after the data modification module 324 generates the modification data and modifies the error correction code, the data modification module 324 sends the modification data and the modification error correction code to the error correction module 322. Next, the error correction module 322 corrects the error bit of the modified data according to the modified error correction code by the error correction program (step 416). At this time, if the error correction module 322 can successfully correct the error bit of the modified data to generate an output data (step 418), the error correction module 322 transmits the output data to the buffer 326. Next, buffer 326 transmits the correct output data to host 304 to complete the execution of the read operation. On the other hand, if the error correction module 322 cannot successfully correct the error bit of the modified data, the controller 312 can again reset the newly modified read voltage by the read voltage setting circuit 330, and then perform steps 410-418 again. In the event that the error correction module 322 still fails to successfully correct the error bit of the modified data, the controller 312 reports that the host 304 failed to read the data (step 422).
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技術者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
200．．．資料區塊200. . . Data block
201a~201d、202a~202d、20ka~20kd．．．資料區段201a~201d, 202a~202d, 20ka~20kd. . . Data section
201e、202e、20ke．．．預定資訊201e, 202e, 20ke. . . Booking information
302．．．資料儲存裝置302. . . Data storage device
304．．．主機304. . . Host
312．．．控制器312. . . Controller
314．．．快閃記憶體314. . . Flash memory
322．．．錯誤修正模組322. . . Error correction module
324．．．資料修改模組324. . . Data modification module
326．．．緩衝器326. . . buffer
以及as well as
330．．．讀取電壓設定電路330. . . Read voltage setting circuit
第1圖為三層單元快閃記憶體的一組讀取電壓的示意圖；Figure 1 is a schematic diagram of a set of read voltages of a three-layer unit flash memory;
第2圖為依據本發明之快閃記憶體用以儲存資料之一區塊的示意圖；2 is a schematic diagram of a flash memory for storing a block of data according to the present invention;
第3圖為依據本發明之資料儲存裝置的區塊圖；Figure 3 is a block diagram of a data storage device in accordance with the present invention;
第4圖為依據本發明之快閃記憶體之資料讀取的方法的流程圖；以及Figure 4 is a flow chart showing a method of reading data of a flash memory according to the present invention;
第5圖為依據本發明修改原始資料及原始錯誤修正碼之方法的流程圖。Figure 5 is a flow chart of a method of modifying the original data and the original error correction code in accordance with the present invention.
302．．．資料儲存裝置302. . . Data storage device
304．．．主機304. . . Host
312．．．控制器312. . . Controller
314．．．快閃記憶體314. . . Flash memory
322．．．錯誤修正模組322. . . Error correction module
324．．．資料修改模組324. . . Data modification module
326．．．緩衝器326. . . buffer
以及as well as
330．．．讀取電壓設定電路330. . . Read voltage setting circuit
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