US9424126B2 - Memory controller - Google Patents
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- US9424126B2 US9424126B2 US14/205,800 US201414205800A US9424126B2 US 9424126 B2 US9424126 B2 US 9424126B2 US 201414205800 A US201414205800 A US 201414205800A US 9424126 B2 US9424126 B2 US 9424126B2
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- 230000008569 process Effects 0.000 claims abstract description 103
- 238000012545 processing Methods 0.000 claims abstract description 12
- 238000012937 correction Methods 0.000 description 31
- 238000010586 diagram Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 230000006870 function Effects 0.000 description 3
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- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
Definitions
- Embodiments described herein relate generally to a memory controller.
- NAND flash memory (hereinafter referred to as a NAND memory) in a writing data unit called a page.
- a NAND memory a NAND flash memory
- FIG. 1 is a block diagram illustrating an example of a configuration of a semiconductor storage device (storage device) according to a first embodiment.
- FIG. 2 is a diagram illustrating an example of a configuration of an encoder/decoder according to the first embodiment.
- FIG. 3 is a view illustrating one example of a format of data stored in a non-volatile memory.
- FIG. 4 is a view illustrating a state in which some user data in a format of a group data are stored in the non-volatile memory.
- FIG. 5 is a view illustrating one example of a first decoding control according to the first embodiment.
- FIG. 6 is a view illustrating one example of a storage state in a non-volatile memory according to a second embodiment.
- FIG. 7 is a view illustrating one example of a procedure of initialization of Parity-B Buffer after writing by a reception of a command is performed according to the embodiment.
- FIG. 8 is a view illustrating a skip region.
- FIG. 9 is a view illustrating an example of a configuration of an encoder/decoder according to a third embodiment.
- a memory controller includes: an encoder configured to sequentially calculate parity based on inputted data, a parity buffer configured to store at least either one of completed parity calculated based on predetermined size of the data and intermediate parity calculated based on the data having size less than the predetermined size; a write processing unit configured to write the data and the completed parity to a non-volatile memory; a decoder configured to perform a decoding process based on the data and the parity; and a controller configured to allow the decoder to perform decoding based on the data read from the non-volatile memory and the intermediate parity stored in the parity buffer, when a size of the data inputted to the encoder is less than the predetermined size, and a read request to the data inputted to the encoder is received.
- FIG. 1 is a block diagram illustrating an example of a configuration of a semiconductor storage device (storage device) according to a first embodiment.
- FIG. 2 is a diagram illustrating an example of a configuration of a encoder/decoder according to the first embodiment.
- FIG. 3 is a view illustrating one example of a format of data stored in a non-volatile memory.
- FIG. 4 is a view illustrating a state in which some user data in a format of a group data are stored in the non-volatile memory.
- FIG. 5 is a view illustrating one example of a first decoding control according to the first embodiment.
- FIG. 6 is a view illustrating one example of a storage state in a non-volatile memory according to a second embodiment.
- FIG. 7 is a view illustrating one example of a procedure of initialization of Parity-B Buffer after writing by a reception of a command is performed according to the embodiment.
- FIG. 8 is a view illustrating a skip region.
- FIG. 9 is a view illustrating an example of a configuration of a encoder/decoder according to a third embodiment.
- FIG. 1 is a block diagram illustrating an example of a configuration of a semiconductor storage device (storage device) according to a first embodiment.
- the semiconductor storage device 1 according to the present embodiment includes a memory controller 2 , and a non-volatile memory (non-volatile memory, hereinafter abbreviated as NV-Memory in the drawing according to need) 3 .
- the storage device 1 is connectable to a host 4 .
- NV-Memory non-volatile memory
- FIG. 1 a state in which the storage device 1 is connected to the host 4 is shown.
- the host 4 is, for example, an electronic apparatus such as a personal computer or a mobile terminal.
- the non-volatile memory 3 is a non-volatile memory that stores data in a non-volatile manner, and it is a NAND memory, for example.
- a NAND memory is used as the non-volatile memory 3 .
- a storage unit other than the NAND memory may be used.
- the NAND memory generally writes and reads data in a writing unit generally called a page.
- the memory controller 2 controls writing to the non-volatile memory 3 in accordance with a write command (request) from the host 4 .
- the memory controller 2 also controls reading from the non-volatile memory 3 in accordance with a read command (request) from the host 4 .
- the memory controller 2 includes a Host I/F 21 , a memory I/F (write processing unit) 22 , a control unit 23 , an encoder/decoder 24 , and a Volatile-Memory 25 , these of which are interconnected with an internal bus 20 each other.
- the Host I/F 21 outputs a command or user data (write data) received from the host 4 to the internal bus 20 .
- the Host I/F 21 also transmits user data read from the non-volatile memory 3 or a response from the control unit 23 to the host 4 .
- the memory I/F 22 controls a process of writing user data on the non-volatile memory 3 and a process of reading the data from the non-volatile memory 3 based on the instruction from the control unit 23 .
- the control unit 23 generally controls the semiconductor storage device 1 .
- the control unit 23 is a Central Processing Unit (CPU), or Micro Processing Unit (MPU) and the like, for example.
- CPU Central Processing Unit
- MPU Micro Processing Unit
- the control unit 23 When receiving a command from the host 4 via the Host I/F 21 , the control unit 23 performs a control according to this command. For example, the control unit 23 instructs the memory I/F 22 to write user data and parity to the non-volatile memory 3 , or to read user data and parity from the non-volatile memory 3 in accordance with the command from the host 4 .
- the control unit 23 decides a memory region on the non-volatile memory 3 to the user data stored in the Volatile-Memory 25 .
- the user data is data transmitted from the host 4 as the data to be written on the non-volatile memory 3 .
- the user data is stored in the Volatile-Memory 25 via the internal bus 20 .
- the control unit 23 decides the memory region on a page basis that is a writing data unit.
- data of a predetermined size (first data size) stored in one page of the non-volatile memory 3 is defined as a page data.
- the page data is a write unit data.
- User data of a predetermined size (second data size) stored in one page of the non-volatile memory 3 is defined as a unit data.
- the page data includes the unit data and inner-page parity corresponding to the unit data, if inner-page parity is generated.
- the page data is equal to the unit data, if inner-page parity is not generated.
- one page of the non-volatile memory 3 indicates a memory region composed of a memory cell group commonly connected to one word line.
- the memory cell is a single-level cell
- the memory cells commonly connected to one word line correspond to one page.
- the memory cell is a multiple level cell
- the memory cells commonly connected to one word line correspond to plural pages. For example, when a multiple level cell that can store two bits is used, the memory cells commonly connected to one word line correspond to two pages.
- the control unit 23 decides the memory region on the non-volatile memory 3 that is the writing destination for each unit data.
- a physical address is allocated to the memory region in the non-volatile memory 3 .
- the control unit 23 manages the memory region, which is the destination to which the unit data is to be written, by using the physical address.
- the control unit 23 designates the decided memory region (physical address), and instructs the memory I/F 22 to write the user data on the designated memory region in the non-volatile memory 3 .
- the control unit 23 manages a correspondence between a logical address (logical address managed by the host 4 ) and a physical address of user data. When receiving a read command from the host 4 , the control unit 23 specifies the physical address, and instructs the memory I/F 22 to read the user data from the specified physical address.
- the encoder/decoder 24 executes an error-correction coding process to generate parity based on the user data (write-data) which are to be stored in the Volatile-Memory 25 .
- the error-correction coding process is executed using plural unit data to generate inter-page parity (Parity-B) as a first coding process.
- the error-correction coding process is executed using one unit data to generate inner-page parity (Parity-A) as a second coding process. It is to be noted that, in the first coding process, the error-correction coding process is executed even to plural Parity-A corresponding to plural unit data to generate inter-page parity (Parity-B).
- the user data and the Parity-A (second parity) generated using the user data are stored in one page in the non-volatile memory 3 .
- the Parity-B (first parity) is stored in a parity page on the non-volatile memory 3 .
- the parity page is a page in the non-volatile memory 3 into which unit data is not stored but Parity-B is stored.
- the second coding process may not be executed. When the second coding process is not executed, the error-correction coding process is executed using plural unit data to generate Parity-B.
- the encoder/decoder 24 executes a second decoding process using the user data (read-data) and Parity-A read from the non-volatile memory 3 .
- the encoder/decoder 24 cannot correct an error by the second decoding process, it executes a first decoding process using the user data and Parity-B for plural pages read from the non-volatile memory 3 .
- the encoder/decoder 24 executes the first decoding process without executing the second decoding process.
- FIG. 1 illustrates the configuration in which the memory controller 2 includes the encoder/decoder 24 and the memory I/F 22 .
- the encoder/decoder 24 may be incorporated in the memory I/F 22 .
- the Volatile-Memory 25 temporarily stores the user data received from the host 4 until it is stored in the non-volatile memory 3 , or temporarily stores the data read from the non-volatile memory 3 until it is transmitted to the host 4 .
- the Volatile-Memory 25 is composed of a general-purpose memory such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).
- FIG. 2 is a diagram illustrating an example of a configuration of the encoder/decoder 24 .
- the encoder/decoder 24 includes an Encoder-A 241 , an Encoder-B 242 , a Decoder-A 243 , a Decoder-B 244 , and a Parity Controller 246 .
- the Encoder-A 241 executes the second coding process.
- the Encoder-B 242 executes the first coding process.
- the Decoder-A 243 executes the second decoding process.
- the Decoder-B 244 executes the first decoding process.
- the Volatile-Memory 25 includes an Encoder Buffer 51 , a Parity-B Buffer 52 , and a Decoder Buffer 53 .
- the Encoder Buffer 51 , the Parity-B Buffer 52 , and the Decoder Buffer 53 are included in the Volatile-Memory 25 separate from the encoder/decoder 24 .
- a Volatile-Memory including the Encoder Buffer 51 , the Parity-B Buffer 52 , and the Decoder Buffer 53 may be provided in the encoder/decoder 24 .
- FIG. 3 is a view illustrating one example of a format of data stored in the non-volatile memory 3 according to the present embodiment.
- the data length such as a coding length n, information length k, and the like is represented by a byte unit below. However, this does not mean that the size of one symbol in the error-correction coding is one byte. Any restriction is imposed on the size of one symbol.
- Data in FIG. 3 indicates user data.
- the data length of one page is specified as n A bytes, and the data length of unit data is specified as k A bytes.
- the Encoder-A 241 generates Parity-A of (n A ⁇ k A ) bytes using the user data of k A bytes.
- the Encoder-B 242 generates Parity-B of (n B ⁇ k B ) bytes using user data of k B bytes composed of one byte data from k B unit data.
- n A ⁇ n B bytes data illustrated in FIG. 3 are defined as a group data.
- the group data has a predetermined data size (third data size).
- the user data received from the host 4 is stored in the Encoder Buffer 51 in the Volatile-Memory 25 .
- the Encoder-B 242 reads the user data stored in the Encoder Buffer 51 for each unit data, and executes the first coding process using the unit data among the group data.
- the Encoder-B 242 finally generates Parity-B (first parity) using k B unit data as illustrated in FIG. 3 .
- Parity-B first parity
- the Encoder-B 242 repeats an operation of storing an intermediate result (uncompleted Parity-B, intermediate parity) into the Parity-B Buffer 52 for every input of unit data. Specifically, the Encoder-B 242 stores the parity, which is calculated by the first coding process using the unit data, into the Parity-B Buffer 52 as the intermediate result. Then, the Encoder-B 242 calculates parity by the first coding process using the user data newly inputted and the intermediate result stored in the Parity-B Buffer 52 . The calculated parity is stored in the Parity-B Buffer 52 as the intermediate result.
- the Encoder Buffer 51 repeats the operation described above, and when the number of inputted unit data reaches k B , the Encoder Buffer 51 stores the parity calculated by the first coding process into the Encoder-B 242 as the Parity-B.
- the Encoder-B 242 inputs the inputted Parity-B into the Encoder-A 241 .
- the Encoder-A 241 executes the second coding process using the unit data or the Parity-B inputted from the Encoder-B 242 to generate Parity-A (second parity).
- the Encoder-A 241 inputs the unit data or the Parity-B and the generated Parity-A to the memory I/F 22 .
- the memory I/F 22 stores the inputted unit data or the Parity-B and the Parity-A into the non-volatile memory 3 on the page basis.
- FIG. 2 does not illustrate the memory I/F 22 .
- the memory I/F 22 reads the user data and the Parity-A from the non-volatile memory 3 on the page basis based on the instruction from the control unit 23 .
- the read user data and the Parity-A are inputted to the Decoder-A 243 .
- the Decoder-A 243 performs the second decoding process using the inputted user data and the Parity-A.
- the Decoder-A 243 stores the inputted user data in the Decoder Buffer 53 .
- the Decoder-A 243 executes the error correction to the user data stored in the Decoder Buffer 53 .
- the result of the first decoding process is notified to the control unit 23 .
- the control unit 23 controls to read user data having no error and user data whose error correction is possible from the Decoder Buffer 53 .
- the read data is transferred to the host 4 via the Host I/F 21 .
- the control unit 23 instructs the memory I/F 22 to read the group data (user data, Parity-A, and Parity-B) including the user data to which the error correction is impossible.
- the read data (user data and Parity-A, or Parity-A and Parity-B) is inputted to the Decoder-A 24 on the page basis.
- the Decoder-A 243 executes the second decoding process using the inputted user data (user data and Parity-A, or Parity-B and Parity-A).
- the Decoder-A 243 stores the inputted user data (or Parity-B) in the Decoder Buffer 53 .
- the Decoder-A 243 executes the error correction to the user data (or Parity-B) stored in the Decoder Buffer 53 .
- the Decoder-B 244 executes the first decoding process using the user data and the Parity-B in the group data stored in the Decoder Buffer 53 .
- the Decoder-B 244 executes the error correction to the user data stored in the Decoder Buffer 53 .
- the control unit 23 controls to transfer the user data after the error correction to the host 4 via the Host I/F 21 .
- each user data is protected using two parities, which are the Parity-A generated using user data in one page and the Parity-B generated using user data in plural pages, as described above.
- the decoding process using the Parity-B is then performed, whereby more errors can be corrected than in the case where only the Parity-A is used.
- the second decoding process can be executed using the user data to which the error correction is performed by the decoding process using the Parity-B and the Parity-A to perform the error correction, and then, the first decoding process can be performed using the user data to which the error correction is already performed and the Parity-B. In this way, the second decoding process and the first decoding process are repeated, whereby more errors can be corrected, and the reliability of the storage device 1 can be enhanced.
- the Parity-B is generated using plural pages, the amount of data forming the group data becomes large. Therefore, there may be the case where the amount of write-data (user data) transmitted from the host 4 is less than the data amount (k A ⁇ k B bytes) forming the format of the group data illustrated in FIG. 3 . In this case, the user data and the Parity-A transmitted from the host 4 are written on the non-volatile memory 3 , but the Parity-B is not written on the non-volatile memory 3 , since it is not completed. On the other hand, the intermediate result of the Parity-B is stored in the Parity-B Buffer 52 .
- FIG. 4 is a view illustrating a state in which partial user data in the format of the group data are stored in the non-volatile memory 3 .
- the user data less than k B and the Parity-A are stored in the non-volatile memory 3 .
- the intermediate result (uncompleted Parity-B) generated using the user data stored in the non-volatile memory 3 is stored in the Parity-B Buffer 52 .
- the memory controller 2 receives a read request to data that is already stored in the non-volatile memory 3 from the host 4 .
- the second decoding process can be executed, since the unit data and the Parity-A are stored in the non-volatile memory 3 .
- the general first decoding process cannot be executed, since the Parity-B is not stored in the non-volatile memory 3 .
- a data path that copies the intermediate result stored in the Parity-B Buffer 52 and stores the copied result to the Decoder Buffer 53 is provided to execute the execution of the first decoding process even in this case.
- the Parity Controller 246 manages the calculation state of the Parity-B, i.e., how many unit data are stored in the Encoder-B 242 .
- the Parity Controller 246 controls to copy the intermediate result stored in the Parity-B Buffer 52 and store the copied result to the Decoder Buffer 53 , according to the calculation state.
- the Parity Controller 246 may be provided outside the encoder/decoder 24 .
- FIG. 5 is a view illustrating one example of a procedure of the first decoding control according to the present embodiment.
- the Encoder-A 241 executes the second decoding process using the input data (unit data and Parity-A, or Parity-B and Parity-A).
- the first decoding control illustrated in FIG. 5 is started.
- the Parity Controller 246 determines whether the calculation of the Parity-B of the group data including this user data is completed or not (step S 1 ).
- the Parity Controller 246 reads all component codewords in the group data from the non-volatile memory 3 , and stores these data into the Decoder Buffer 53 (step S 2 ).
- the Decoder-A 243 and the Decoder-B 244 executes iterative decoding using the group data stored in the Decoder Buffer 53 (step S 3 ), and then, the process is terminated.
- the iterative decoding means the process of repeating the second decoding process and the first decoding process, such that the second decoding process is performed using the result obtained by the error correction in the first decoding process as described above. When all errors can be corrected by the first decoding process in the first try, the process is terminated without being iterated.
- the Parity Controller 246 controls to copy the intermediate result stored in the Parity-B Buffer 52 and store the copied result to the Decoder Buffer 53 (step S 4 ).
- a region corresponding to the group data (the format illustrated in FIG. 3 ) is secured on the Decoder Buffer 53 .
- the intermediate result is stored in the region corresponding to the Parity-B among the region corresponding to the group data on the Decoder Buffer 53 .
- the Parity Controller 246 pads the region where the user data is not written on the non-volatile memory 3 , in the region corresponding to the group data on the Decoder Buffer 53 , with zero (step S 5 ).
- step S 5 the process proceeds to step S 3 . If the process passes steps S 4 and S 5 , only the data that was already stored in the non-volatile memory 3 is read as all component codewords in the group data in step S 2 .
- the user data read from the non-volatile memory 3 is inputted to the Decoder-B 244 as the part of group data, corresponding to data that is already stored on the non-volatile memory 3 .
- zero is inputted to the Decoder-B 244 as the part corresponding to data that is not yet written on the non-volatile memory 3 .
- the intermediate result is inputted to the Decoder-B 244 as Parity-B.
- the Decoder-B 244 can correct an error in the user data that is already stored in the non-volatile memory 3 using the inputted user data and the intermediate result.
- the intermediate result is stored in the region corresponding to the Parity-B in the Decoder Buffer 53 , when the read request to the user data, which is already written, in the group data is issued, and an error correction is impossible by the second decoding process, in the state in which the group data is not completely written on the non-volatile memory 3 .
- the user data can be protected even if all component codewords in the group data are not written on the non-volatile memory 3 .
- the storage device 1 when a command, such as a flash command issued upon a power shutdown, instructing forced writing is received from the host 4 , the intermediate result stored in the Parity-B Buffer 52 is written on the non-volatile memory 3 .
- the configuration of the storage device 1 according to the present embodiment is the same as the configuration of the first embodiment.
- FIG. 6 is a view illustrating one example of a storage state in a non-volatile memory 3 according to the present embodiment.
- the control unit 23 instructs the Parity Controller 246 and the memory I/F 22 to store the intermediate result in the non-volatile memory 3 .
- the Parity Controller 246 controls to read the intermediate result from the Parity-B Buffer 52 , and input the read result into the Encoder-B 242 based on the instruction from the control unit 23 .
- the Encoder-B 242 inputs the intermediate result to the Encoder-A 241 as it is.
- the Encoder-A 241 generates the Parity-A according to the second coding process using the inputted intermediate result.
- the memory I/F 22 writes the intermediate result and the Parity-A to the page, storing the Parity-B, in the non-volatile memory 3 .
- the Encoder-A 241 and the Encoder-B 242 execute the second coding process and the first coding process respectively, as in the first embodiment.
- FIG. 7 is a view illustrating one example of a procedure of initialization of the Parity-B Buffer 52 after writing is performed in response to a command according to the present embodiment.
- FIG. 7 illustrates the procedure of the initialization when the writing is performed in response to the command, power supply is shut down, and then, the power supply is turned on.
- the control unit 23 checks whether the intermediate result is stored in the non-volatile memory 3 or not (step S 11 ). When the intermediate result is stored in the non-volatile memory 3 , the control unit 23 instructs the memory I/F 22 to read the intermediate result from the non-volatile memory 3 .
- the memory I/F 22 reads the intermediate result from the non-volatile memory 3 according to the instruction (step S 12 ).
- the control unit 23 instructs the Parity Controller 246 to store the intermediate result read from the non-volatile memory 3 to the Parity-B Buffer 52 .
- the Parity Controller 246 stores the intermediate result to the Parity-B Buffer 52 based on the instruction (step S 13 ). In this case, the control unit 23 initializes the Encoder Buffer 51 with zero padding. After the execution of step S 13 , the initialization process is terminated.
- step S 11 No the control unit 23 checks whether the intermediate result on the Parity-B Buffer 52 is lost or not due to the power shutdown (step S 14 ).
- step S 14 the control unit 23 instructs the memory I/F 22 to read the unit data and the Parity-A corresponding to the group data of which the writing is not completed before the reception of the command from the non-volatile memory 3 .
- the memory I/F 22 reads the unit data and the Parity-A from the non-volatile memory 3 on the page basis according to the instruction (step S 15 ).
- the control unit 23 stores the read unit data and the Parity-A into the Encoder Buffer 51 (step S 16 ).
- the Encoder-B 242 performs the first encoding process using the unit data stored in the Encoder Buffer 51 to re-calculate the Parity-B (intermediate result), and stores the calculated result (intermediate result) into the Parity-B Buffer 52 (step S 17 ).
- the control unit 23 determines whether reading of all user data and Parity-A that are already stored in the non-volatile memory 3 are terminated (step S 18 ). When reading is terminated (step S 18 , Yes), the control unit 23 terminates the initialization process. When reading is not terminated, the process returns to step S 15 .
- step S 14 No When the intermediate result on the Parity-B Buffer 52 is not lost due to the power shutdown (step S 14 No), the control unit 23 initializes the Encoder Buffer 51 with zero padding (step S 19 ), and then, terminates the initialization process.
- the control unit 23 performs the process of writing the data (hatched portion in FIG. 6 ) that is not yet written in the group data.
- the Encoder-B 242 executes the first decoding process based on the intermediate result stored in the Parity-B Buffer 52 and the unit data newly inputted, and stores the result after the process into the Parity-B Buffer 52 as the intermediate result.
- the first coding process by the Encoder-B 242 is completed, whereby the Parity-B is completed.
- the completed Parity-B is written in the non-volatile memory 3 .
- the page to which the completed Parity-B is written is different from the page to which the intermediate result is stored.
- the intermediate result is written on the page different from the page where the Parity-B of the group data has to be stored, and the completed Parity-B is written on the page where the Parity-B of the group data has to be stored.
- the intermediate result may be written on the page where the Parity-B of the group data is stored, and the completed Parity-B may be written on another page.
- the first coding process that is executed before the power shutdown can be continued, when the power supply is turned on after the power shutdown.
- the operation (the operation in which the intermediate result is stored in the region corresponding to the Parity-B in the Decoder Buffer 53 , when the read request to the user data, which is already written, in the group data is issued, and an error correction is impossible by the second decoding process, in the state in which the group data is not completely written on the non-volatile memory 3 of storing the intermediate result stored in the Parity-B Buffer 52 into the Decoder Buffer 53 ) as in the first embodiment may be further performed, or may not be performed.
- the uncompleted Parity-B (intermediate result) is stored in the non-volatile memory 3 . Therefore, the first decoding process can be executed to the user data in the group data, which is not completed. The continuation of the calculation of the Parity-B can be executed, by using the intermediate result, for the data that is not written in the group data.
- the writing to the memory region in the non-volatile memory 3 might be skipped.
- the writing to the non-volatile memory 3 might be skipped.
- the third embodiment describes the case where the region to which the writing is skipped (hereinafter referred to as a skip region) is present.
- data is written to the non-volatile memory 3 in the format illustrated in FIG. 3 in the present embodiment.
- FIG. 8 is a view illustrating the skip region. The hatched region in FIG.
- the region not hatched indicates the region where the unit data and the Parity-A (and/or the Parity-B and the Parity-A) are written on the non-volatile memory 3 .
- the Encoder-B 242 performs the first coding process using the user data excluding the data in the skip region (i.e., the user data written on the non-volatile memory 3 ) to generate the Parity-B.
- the control unit 23 inputs zero to the Encoder-B 242 instead of the data in the skip region.
- the Encoder-B 242 executes the first coding process to generate the Parity-B as in the first embodiment, and the completed Parity-B corresponds to the user data including the data in the skip region. Therefore, valid data of input data to the first coding process for the group data including the skip region is less than the one for the general group data (the group data not containing the skip region).
- the Parity-B generated using the user data including the data in the skip region is referred to as shortened Parity-B.
- the shortened Parity-B is parity (shortened code parity) generated using the user data excluding the data in the skip region, i.e., the user data with an amount less than the ordinary data.
- the writing process (including the encoding process) other than the process described above in the present embodiment is the same as that in the first embodiment.
- the configuration of the storage device 1 according to the present embodiment may be the same as that in the first embodiment, or may be the one illustrated in FIG. 9 .
- the control unit 23 manages the skip region using a table. The control unit 23 recognizes the skip region by referring to this table.
- the control unit 23 controls to store the user data, the Parity-A, and the shortened Parity-B read from the non-volatile memory 3 on the Decoder Buffer 53 .
- the skip region is written with zero instead of the data in the skip region in the group data on the Decoder Buffer 53 .
- the Encoder-B 242 performs the first decoding process using the data on the Decoder Buffer 53 . With this, the error correction can be carried out to the user data read from the non-volatile memory 3 using the shortened Parity-B.
- FIG. 9 is a view illustrating an example of a configuration of a encoder/decoder 24 a according to the present embodiment.
- a storage device is the same as the storage device 1 in the first embodiment, except that the encoder/decoder 24 in the storage device 1 according to the first embodiment is replaced by the encoder/decoder 24 a .
- the components having the same function as in the first embodiment are identified by the same numerals, and the redundant description will not be repeated.
- the encoder/decoder 24 a is formed by adding a Randomizer 247 and 0/1 Counter 248 to the encoder/decoder 24 in the first embodiment.
- the Randomizer 247 randomizes the unit data and the Parity-A (or the Parity-B and the Parity-A) outputted from the Encoder-A 241 .
- the data after the randomization includes zero and one that are almost equal in number.
- the memory I/F 22 stores the data after the randomization into the non-volatile memory 3 for each page.
- the storage format to the non-volatile memory 3 is the same as that illustrated in FIG. 3 .
- the Randomizer 247 has a function as De-Randomizer, and it de-randomizes (the transformation process reverse to the randomization) the data read from the non-volatile memory 3 , and inputs the resultant data to the Decoder-A 243 .
- the Randomizer 247 has a function of inputting the data read from the non-volatile memory 3 into the 0/1 Counter 248 .
- the 0/1 Counter 248 determines whether the value of the inputted data is zero or one for each bit, and counts the number of zero bits (the number of zero) and the number of one bits (the number of one).
- the first coding process using the configuration illustrated in FIG. 9 is the same as the configuration of recognizing the skip region using a table.
- the reading process from the non-volatile memory 3 when the configuration illustrated in FIG. 9 is used will be described.
- the Encoder-A 241 performs the second decoding process using the unit data and the Parity-A after the de-randomization.
- Each page in the skip region on the non-volatile memory 3 is all written with zero or all written with one.
- the read data is all zero or all one. Therefore, when the Randomizer 247 executes the de-randomization, the data in the skip region has a random number sequence. Accordingly, the error correction is impossible by the second decoding process.
- the Parity Controller 246 (or the control unit 23 ) instructs the Randomizer 247 to input the data corresponding to the unit data to which the error correction is impossible and having the Parity-A before the de-randomization into the 0/1 Counter 248 .
- the Randomizer 247 inputs the data before the de-randomization to the 0/1 Counter 248 based on the instruction.
- the 0/1 Counter 248 counts the number of zero and the number of one in the data before the de-randomization, and notifies the Parity Controller 246 (or the control unit 23 ) of the counting result.
- the Parity Controller 246 determines whether there is a difference between the number of zero and the number of one based on the counting result. Specifically, the Parity Controller 246 (or the control unit 23 ) can determine whether there is a difference between the number of zero and the number of one based on as to whether the ratio of the number of zero and the number of one falls within “1 ⁇ ” to “1+ ⁇ ” ( ⁇ is a constant).
- the method of determining whether there is a difference is not limited thereto.
- the Parity Controller 246 determines that it is the data in the skip region.
- the Parity Controller 246 (or the control unit 23 ) then writes zero in the region in the Decoder Buffer 53 corresponding to the skip region.
- the first decoding process is the same as that in the case where the skip region is managed using a table.
- the shortened Parity-B storing zero instead of the data in the skip region is generated, and the shortened Parity-B is written on the non-volatile memory 3 .
- the decoding process is performed using the shortened Parity-B by inputting zero instead of the data in the skip region. Accordingly, the error correction by the first decoding process can be executed even in the case where the data includes the skip region.
Abstract
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Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102305095B1 (en) * | 2015-04-13 | 2021-09-24 | 삼성전자주식회사 | Method for operating non-volatile memory controller |
US9830086B2 (en) * | 2016-03-03 | 2017-11-28 | Samsung Electronics Co., Ltd. | Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group |
US10289487B2 (en) | 2016-04-27 | 2019-05-14 | Silicon Motion Inc. | Method for accessing flash memory module and associated flash memory controller and memory device |
CN107391296B (en) | 2016-04-27 | 2020-11-06 | 慧荣科技股份有限公司 | Method for accessing flash memory module and related flash memory controller and memory device |
US9910772B2 (en) | 2016-04-27 | 2018-03-06 | Silicon Motion Inc. | Flash memory apparatus and storage management method for flash memory |
CN107391026B (en) | 2016-04-27 | 2020-06-02 | 慧荣科技股份有限公司 | Flash memory device and flash memory management method |
US10025662B2 (en) | 2016-04-27 | 2018-07-17 | Silicon Motion Inc. | Flash memory apparatus and storage management method for flash memory |
TWI614759B (en) * | 2016-04-27 | 2018-02-11 | 慧榮科技股份有限公司 | Method, flash memory controller, memory device for accessing flash memory |
US10110255B2 (en) | 2016-04-27 | 2018-10-23 | Silicon Motion Inc. | Method for accessing flash memory module and associated flash memory controller and memory device |
US10019314B2 (en) | 2016-04-27 | 2018-07-10 | Silicon Motion Inc. | Flash memory apparatus and storage management method for flash memory |
CN111679787B (en) | 2016-04-27 | 2023-07-18 | 慧荣科技股份有限公司 | Flash memory device, flash memory controller and flash memory storage management method |
CN109313593B (en) * | 2016-09-16 | 2022-03-01 | 株式会社日立制作所 | Storage system |
US11016848B2 (en) * | 2017-11-02 | 2021-05-25 | Seagate Technology Llc | Distributed data storage system with initialization-less parity |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5406425A (en) * | 1991-08-06 | 1995-04-11 | R-Byte, Inc. | ISO/IEC compatible digital audio tape digital data storage system with increased data transfer rate |
JP2003036693A (en) | 2001-05-16 | 2003-02-07 | Fujitsu Ltd | Error detecting/correcting method for multi-level semiconductor memory, and multi-level semiconductor memory having error detecting/correcting function |
US6904492B2 (en) * | 2001-12-19 | 2005-06-07 | Hewlett-Packard Development Company, L.P. | Write-once memory device including non-volatile memory for temporary storage |
US6990623B2 (en) | 2001-05-16 | 2006-01-24 | Fujitsu Limited | Method for error detection/correction of multilevel cell memory and multilevel cell memory having error detection/correction function |
JP2006040013A (en) | 2004-07-28 | 2006-02-09 | Renesas Technology Corp | Memory card and nonvolatile storage |
US20090041110A1 (en) * | 2007-03-27 | 2009-02-12 | Qualcomm Incorporated | Rate matching with multiple code block sizes |
JP2009080651A (en) | 2007-09-26 | 2009-04-16 | Toshiba Corp | Semiconductor memory device and its control method |
US7581153B2 (en) * | 2004-09-10 | 2009-08-25 | Rino Micheloni | Memory with embedded error correction codes |
JP2009211742A (en) | 2008-03-01 | 2009-09-17 | Toshiba Corp | Error correcting device and error correcting method |
US8006165B2 (en) * | 2006-06-30 | 2011-08-23 | Kabushiki Kaisha Toshiba | Memory controller and semiconductor memory device |
US8023535B2 (en) * | 2007-02-09 | 2011-09-20 | Lg Electronics Inc. | Broadcasting signal receiver and method for transmitting/receiving broadcasting signal |
US8045591B2 (en) * | 2007-02-09 | 2011-10-25 | Lg Electronics Inc. | Broadcasting signal receiver and method for transmitting/receiving broadcasting signal |
US8726121B2 (en) * | 2007-03-27 | 2014-05-13 | Qualcomm Incorporated | Circular buffer based rate matching |
-
2014
- 2014-03-12 US US14/205,800 patent/US9424126B2/en active Active
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5406425A (en) * | 1991-08-06 | 1995-04-11 | R-Byte, Inc. | ISO/IEC compatible digital audio tape digital data storage system with increased data transfer rate |
JP2003036693A (en) | 2001-05-16 | 2003-02-07 | Fujitsu Ltd | Error detecting/correcting method for multi-level semiconductor memory, and multi-level semiconductor memory having error detecting/correcting function |
US6990623B2 (en) | 2001-05-16 | 2006-01-24 | Fujitsu Limited | Method for error detection/correction of multilevel cell memory and multilevel cell memory having error detection/correction function |
US6904492B2 (en) * | 2001-12-19 | 2005-06-07 | Hewlett-Packard Development Company, L.P. | Write-once memory device including non-volatile memory for temporary storage |
JP2006040013A (en) | 2004-07-28 | 2006-02-09 | Renesas Technology Corp | Memory card and nonvolatile storage |
US7581153B2 (en) * | 2004-09-10 | 2009-08-25 | Rino Micheloni | Memory with embedded error correction codes |
US8006165B2 (en) * | 2006-06-30 | 2011-08-23 | Kabushiki Kaisha Toshiba | Memory controller and semiconductor memory device |
US8023535B2 (en) * | 2007-02-09 | 2011-09-20 | Lg Electronics Inc. | Broadcasting signal receiver and method for transmitting/receiving broadcasting signal |
US8045591B2 (en) * | 2007-02-09 | 2011-10-25 | Lg Electronics Inc. | Broadcasting signal receiver and method for transmitting/receiving broadcasting signal |
US20090041110A1 (en) * | 2007-03-27 | 2009-02-12 | Qualcomm Incorporated | Rate matching with multiple code block sizes |
US8726121B2 (en) * | 2007-03-27 | 2014-05-13 | Qualcomm Incorporated | Circular buffer based rate matching |
JP2009080651A (en) | 2007-09-26 | 2009-04-16 | Toshiba Corp | Semiconductor memory device and its control method |
US7900117B2 (en) | 2007-09-26 | 2011-03-01 | Kabushiki Kaisha Toshiba | Semiconductor memory device and its control method |
US8312348B2 (en) | 2008-03-01 | 2012-11-13 | Kabushiki Kaisha Toshiba | Error correcting device and error correcting method |
JP2009211742A (en) | 2008-03-01 | 2009-09-17 | Toshiba Corp | Error correcting device and error correcting method |
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