TWI451572B - 雙擴散金屬氧化物半導體元件及其製造方法 - Google Patents

雙擴散金屬氧化物半導體元件及其製造方法 Download PDF

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TWI451572B
TWI451572B TW100102809A TW100102809A TWI451572B TW I451572 B TWI451572 B TW I451572B TW 100102809 A TW100102809 A TW 100102809A TW 100102809 A TW100102809 A TW 100102809A TW I451572 B TWI451572 B TW I451572B
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metal oxide
oxide semiconductor
double
annular structure
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TW100102809A
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TW201232777A (en
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Ching Yao Yang
Tsung Yi Huang
Huan Ping Chu
Hung Der Su
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Richtek Technology Corp
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Priority to TW100102809A priority Critical patent/TWI451572B/zh
Priority to CN201110060970.7A priority patent/CN102623497B/zh
Priority to CN201310574182.9A priority patent/CN103646964B/zh
Priority to US13/066,622 priority patent/US8653594B2/en
Publication of TW201232777A publication Critical patent/TW201232777A/zh
Priority to US14/146,548 priority patent/US8709900B1/en
Priority to US14/146,512 priority patent/US8729630B1/en
Priority to US14/146,528 priority patent/US8728895B1/en
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Publication of TWI451572B publication Critical patent/TWI451572B/zh

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Description

雙擴散金屬氧化物半導體元件及其製造方法
本發明係有關一種雙擴散金屬氧化物半導體元件及其製造方法，特別是指一種具有環狀結構閘極之雙擴散金屬氧化物半導體元件及其製造方法。
第1A-1C圖顯示先前技術之雙擴散金屬氧化物半導體元件(double diffused metal oxide semiconductor,DMOS)上視與剖視圖。請同時參照第1A-1C圖，於P型矽基板11中形成絕緣結構12以定義第一元件區100與第二元件區200，絕緣結構12例如為區域氧化(local oxidation of silicon,LOCOS)結構。於基板11上，形成閘極13；於第一元件區100中，形成本體區14、輕摻雜汲極區15、本體極16、與源極17；於第二元件區200中，形成汲極18。其中，閘極13為環狀結構，當元件於正常操作時，源極17與汲極18間會形成通道。但在通道的邊緣，也就是閘極13環狀結構的角落，因為此處P型雜質摻雜的本體區14，其雜質濃度相對其他區域較淡，擴散的範圍較小，而N型雜質摻雜的輕摻雜汲極區15，在角落與通道中段的雜質濃度大致相等。因此，在正常操作元件時，造成角落的阻值較低，而使元件的特性受到影響，，如第2A與2B圖所示，其中第2A圖顯示元件汲極電流Id和閘極電壓Vg的對數關係，第2B圖顯示元件汲極電導和閘極電壓的關係。自2A與2B圖可以看出，角落阻值較低，而使元件提早導通，如兩圖中之實際狀況實線所示意，而偏離了設計元件時所需要的理想狀況，如圖中之虛線所示意。
詳言之，閘極13環狀結構的通道中段，可由第1A圖中，AA’剖線來代表；而閘極13環狀結構的角落，則可由第1A圖中，BB’剖線來代表。在環狀結構的角落，請參照第1B圖，由本體區14與閘極13的相對位置關係可看出，因本體區14濃度較淡，其擴散的範圍也比較小；而在環狀結構的通道中段，請參照第1C圖，由本體區14與閘極13的相對位置關係可看出，此處本體區14濃度較濃，其擴散的範圍也比較大。比較兩處輕摻雜汲極區14與閘極13相對位置關係，可看出在環狀結構角落的N型輕摻雜汲極15所看到的P型雜質濃度較低，也因此其阻值較低，其次臨界電壓(sub-threshold voltage)也較低。這可能造成在元件達到臨界電壓前，會有如第2A圖所示的提早導通狀況，造成元件的臨界電壓降低。
有鑑於此，本發明即針對上述先前技術之不足，提出一種雙擴散金屬氧化物半導體元件及其製造方法，可改善元件提早導通狀況，提高元件操作之臨界電壓；改善閘極環狀結構角落的元件操作參數，增加元件的應用範圍。
本發明目的在提供一種雙擴散金屬氧化物半導體元件及其製造方法。
為達上述之目的，本發明提供了一種雙擴散金屬氧化物半導體元件，包含：一基板，其具有絕緣結構以定義第一元件區與第二元件區；一閘極，位於該基板表面上，由上視圖視之，其具有一環狀結構，環繞該第一元件區，且該環狀結構部分或全部位於該第一元件區內；一本體區，位於該第一元件區中，其具有第一導電型雜質摻雜，且其範圍由該環狀結構定義；一輕摻雜汲極區，位於該本體區中，其具有第二導電型雜質摻雜；一源極，位於該本體區中，其具有第二導電型雜質摻雜；一本體極，位於該本體區中，其具有第一導電型雜質摻雜；以及一汲極，位於該第二元件區中；其中，由上視圖視之，該輕摻雜汲極區、該源極、與該本體極於該環狀結構內由外而內排列；且其中，該環狀結構之角落完全設置於該絕緣結構上。
在其中一種實施型態中，該環狀結構大致呈矩形，其較短的兩側邊完全設置於該絕緣結構上。
就另一觀點，本發明也提供了一種雙擴散金屬氧化物半導體元件，包含：一基板，其具有絕緣結構以定義第一元件區與第二元件區；一閘極，位於該基板表面上，由上視圖視之，其具有一環狀結構，環繞該第一元件區，且該環狀結構部分或全部位於該第一元件區內；一本體區，位於該第一元件區中，其具有第一導電型雜質摻雜，且其範圍由該環狀結構定義；一輕摻雜汲極區，位於該本體區中，其具有第二導電型雜質摻雜；一源極，位於該本體區中，其具有第二導電型雜質摻雜；一本體極，位於該本體區中，其具有第一導電型雜質摻雜；以及一汲極，位於該第二元件區中；其中，由上視圖視之，該輕摻雜汲極區、該源極、與該本體極於該環狀結構內由外而內排列；且其中，該輕摻雜汲極區與該環狀結構之角落間，分開一段預設距離。
在其中一種實施型態中，該預設距離，不小於最小設計線寬、或不小於1微米。
就另一觀點，本發明也提供了一種雙擴散金屬氧化物半導體元件製造方法，包含：提供一基板，並於其中形成一絕緣結構以定義第一元件區與第二元件區；於該基板表面上形成一閘極，由上視圖視之，該閘極具有一環狀結構，環繞該第一元件區，且該環狀結構部分或全部位於該第一元件區內；於該第一元件區中形成一本體區，其具有第一導電型雜質摻雜，且其範圍由該環狀結構定義；於該本體區中形成一輕摻雜汲極區，其具有第二導電型雜質摻雜；於該本體區中形成一源極，其具有第二導電型雜質摻雜；於該本體區中形成一本體極，其具有第一導電型雜質摻雜；以及於該第二元件區中形成一汲極；其中，由上視圖視之，該輕摻雜汲極區、該源極、與該本體極於該環狀結構內由外而內排列；且其中，該環狀結構之角落完全設置於該絕緣結構上。
就另一觀點，本發明也提供了一種雙擴散金屬氧化物半導體元件製造方法，包含：提供一基板，並於其中形成一絕緣結構以定義第一元件區與第二元件區；於該基板表面上形成一閘極，由上視圖視之，該閘極具有一環狀結構，環繞該第一元件區，且該環狀結構部分或全部位於該第一元件區內；於該第一元件區中形成一本體區，其具有第一導電型雜質摻雜，且其範圍由該環狀結構定義；於該本體區中形成一輕摻雜汲極區，其具有第二導電型雜質摻雜；於該本體區中形成一源極，其具有第二導電型雜質摻雜；於該本體區中形成一本體極，其具有第一導電型雜質摻雜；以及於該第二元件區中形成一汲極；其中，由上視圖視之，該輕摻雜汲極區、該源極、與該本體極於該環狀結構內由外而內排列；且其中，該輕摻雜汲極區與該環狀結構之角落間，分開一段預設距離。
該雙擴散金屬氧化物半導體元件例如可為兩共源極之橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件或雙擴散汲極金屬氧化物半導體(double diffused drain metal oxide semiconductor,DDDMOS)元件。
底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
本發明中的圖式均屬示意，主要意在表示製程步驟以及各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。
請參閱第3A-3L圖，顯示本發明的第一個實施例，第3A-3L圖顯示橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)之製造流程示意圖。第3B圖顯示在第3A圖中，CC’剖線的剖視示意圖。請同時參閱第3A與3B圖，首先提供具有第一導電型基板11，基板11例如但不限於P型基板，並於其中形成絕緣結構12以定義第一元件區100與第二元件區200，絕緣結構12例如可為如第3B圖所示之LOCOS結構，亦可為淺溝槽絕緣(shallow trench isolation,STI)結構。
接下來請參閱第3C與3D圖，於基板11上，形成閘極13，由上視圖第3C圖視之，閘極13具有環狀結構，環繞第一元件區100，且環狀結構部分位於第一元件區100內，須注意的是，由上視圖第3C圖視之，閘極13環狀結構的上下兩側邊，完全位於絕緣結構12之上，如DD’剖線的剖視示意圖第3D圖所示，這是為了當LDMOS元件於正常操作時，使環狀結構之角落能位在絕緣結構12上，使得閘極13不會在環狀結構的角落導通或漏電。
接下來請參閱第3E與3F圖，藉由微影技術與閘極13的遮罩，並以離子植入技術，將第一導電型雜質，例如但不限於為P型雜質，以加速離子的形式，植入定義的區域內，以形成本體區14。
再接下來請參閱第3G與3H圖，藉由微影技術與閘極13的遮罩，並以離子植入技術，將第二導電型雜質，例如但不限於為N型雜質，以加速離子的形式，植入定義的區域內，以形成輕摻雜汲極區15。
再接下來請參閱第3I與3J圖，藉由沉積與自我對準蝕刻(self-alignment etch)技術，在閘極13外側，形成間隔層13a。接下來請參閱第3K與3L圖，藉由微影技術、閘極13、以及間隔層13a的遮罩，並以離子植入技術，分別將第一導電型雜質，例如但不限於為P型雜質，以加速離子的形式，植入定義的區域內，以形成本體極16；並將第二導電型雜質例如但不限於為N型雜質，以加速離子的形式，植入定義的區域內，以形成源極17與汲極18。其中，由上視圖第3K圖視之，輕摻雜汲極區15、源極17、與本體極16於環狀結構內由外而內排列，以形成兩共源極之LDMOS元件。
第4A與第4B圖顯示本發明的第二個實施例，與第一個實施例不同的是，此LDMOS元件並非以將閘極13環狀結構的上下兩端，完全位於絕緣結構12之上；而是如第4A圖所示，調整輕摻雜汲極區15與環狀結構的上下兩側邊相接之處，使其相距一段距離d 與d’ (d 與d’ 可以相同或不同)，其EE’剖線之剖視圖，如第4B圖所示，其用意亦在於使環狀結構之角落，也就是通道的邊緣，能在LDMOS元件操作時，使得閘極13不會在環狀結構的角落導通或漏電。在較佳實施型態中，該距離d 與d’ 宜不小於最小設計線寬，所謂最小設計線寬係指製造此LDMOS元件時，所使用的半導體製程技術之最小設計線寬，而更佳為1微米以上。
請參閱第5A-5H圖，顯示本發明的第三個實施例，本實施例與第一個實施例相似，但應用本發明於另一種DMOS元件，也就是雙擴散汲極金屬氧化物半導體(double diffused drain metal oxide semiconductor,DDDMOS)之製造流程示意圖。第5B圖顯示在第5A圖中，FF’剖線的剖視示意圖。請同時參閱第5A與5B圖，首先提供具有第一導電型基板11，基板11例如但不限於P型基板，並於其中形成絕緣結構12以定義第一元件區100與第二元件區200，絕緣結構12例如可為如第5B圖所示之STI結構，亦可為LOCOS結構。
接下來請參閱第5C與5D圖，於基板11上，形成閘極13，由上視圖第5C圖視之，閘極13具有環狀結構，環繞第一元件區100，且環狀結構全部位於第一元件區100內，接下來藉由微影技術與閘極13的遮罩，並以離子植入技術，將第一導電型雜質，例如但不限於為P型雜質，以加速離子的形式，植入定義的區域內，以形成本體區14。再接下來，藉由微影技術與閘極13的遮罩，並以離子植入技術，將第二導電型雜質，例如但不限於為N型雜質，以加速離子的形式，植入定義的區域內，以形成輕摻雜汲極區15。需注意的是，相較於習知技術(其實「昔」比較對，但慣用「習」)，本實施例調整輕摻雜汲極區15與環狀結構的上下兩側邊相接之處，使其相距至少一最小距離，其FF’剖線之剖視圖，如第5D圖所示。與其他實施例相同，其用意亦在於使環狀結構之角落，也就是通道的邊緣，能在DDDMOS元件操作時，使得閘極13不會在環狀結構的角落導通或漏電。其中，該最小距離宜不小於最小設計線寬，所謂最小設計線寬係指製造此LDMOS元件時，所使用的半導體製程技術之最小設計線寬，而更佳為1微米以上。
再接下來請參閱第5E與5F圖，藉由沉積與自我對準蝕刻(self-alignment etch)技術，在閘極13外側，形成間隔層13a。接下來請參閱第5G與5H圖，藉由微影技術、閘極13、以及間隔層13a的遮罩，並以離子植入技術，分別將第一導電型雜質，例如但不限於為P型雜質，以加速離子的形式，植入定義的區域內，以形成本體極16；並將第二導電型雜質例如但不限於為N型雜質，以加速離子的形式，植入定義的區域內，以形成源極17與汲極18。其中，由上視圖第5G圖視之，輕摻雜汲極區15、源極17、與本體極16於環狀結構內由外而內排列，以形成兩共源極之DDDMOS元件。
第6A與第6B圖顯示本發明的第四個實施例，與第一個實施例不同的是，此LDMOS元件中閘極13環狀結構的上下兩側邊，不僅完全位於絕緣結構12之上，且其與絕緣結構12邊緣的距離加大；其用意在說明，在環狀結構之角落，由上視圖第6A圖與剖線GG’之剖視圖第6B圖所示，不必須與本體區14相接，重點在於使通道的邊緣，能在LDMOS元件操作時，使得閘極13不會在環狀結構的角落導通或漏電。由此可知，閘極13亦可以為各種形狀之設計，而不限定於各實施例所示之矩形。
第7A與第7B圖顯示本發明的第五個實施例，與第三個實施例不同的是，此DDDMOS元件之絕緣結構12係LOCOS結構，其剖線HH’之剖視圖如第7B圖所示，與其他實施例相同，其用意亦在於使環狀結構之角落，也就是通道的邊緣，能在DDDMOS元件操作時，使得閘極13不會在環狀結構的角落導通或漏電。
第8A-8C圖顯示本發明的第六個實施例，與第三個實施例不同的是，此DDDMOS元件更包含汲極擴散區19，其剖線II’與JJ’之剖視圖如第8B與8C圖所示，本實施例旨在說明在DDDMOS元件結構中，亦可包含汲極擴散區19以形成通道之一部分。
第9A-9C圖顯示本發明的第七個實施例，與第六個實施例相似，不同的是，此DMOS元件不包含汲極擴散區19，而是於元件區100中，以全面性離子植入方式形成具有第二導電型雜質摻雜之井區20，其剖線KK’與LL’之剖視圖如第9B與9C圖所示，本實施例旨在說明在DMOS元件結構中，亦可包含井區20以形成通道之一部分。
以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，在不影響元件主要的特性下，可加入其他製程步驟或結構，如深井區等；又如，微影技術並不限於光罩技術，亦可包含電子束微影技術；再如，本發明亦可以應用於共汲極之雙擴散金屬氧化物半導體元件，只要將相關之其他區，例如本體區、本體極、與輕摻雜汲極區等作相對設置即可；又如，本發明亦可以應用於其他具有閘極環狀結構之元件。本發明的範圍應涵蓋上述及其他所有等效變化。
11．．．基板
12．．．絕緣結構
13．．．閘極
14．．．本體區
15．．．輕摻雜汲極區
16．．．本體極
17．．．源極
18．．．汲極
19．．．汲極擴散區
20．．．井區
100,200．．．元件區
Id．．．汲極電流
gm．．．汲極電導
Vg．．．閘極電壓
第1A-1C圖顯示先前技術之雙擴散金屬氧化物半導體元件上視與剖視圖。
第2A圖顯示先前技術之雙擴散金屬氧化物半導體元件之汲極電流－閘極電壓特性曲線。
第2B圖顯示先前技術之雙擴散金屬氧化物半導體元件之汲極電導－閘極電壓特性曲線。
第3A-3L圖顯示本發明的第一個實施例。
第4A與第4B圖顯示本發明的第二個實施例。
第5A-5H圖顯示本發明的第三個實施例。
第6A與第6B圖顯示本發明的第四個實施例。
第7A與第7B圖顯示本發明的第五個實施例。
第8A-8C圖顯示本發明的第六個實施例。
第9A-9C圖顯示本發明的第七個實施例。
11．．．基板
12．．．絕緣結構
13．．．閘極
14．．．本體區
15．．．輕摻雜汲極區
16．．．本體極
17．．．源極

Claims (10)

  1. 一種雙擴散金屬氧化物半導體元件，包含：一基板，其具有絕緣結構以定義第一元件區與第二元件區；一閘極，位於該基板表面上，由上視圖視之，其具有一環狀結構，環繞該第一元件區，且該環狀結構部分或全部位於該第一元件區內；一本體區，位於該第一元件區中，其具有第一導電型雜質摻雜，且其範圍由該環狀結構定義；一輕摻雜汲極區，位於該本體區中，其具有第二導電型雜質摻雜；一源極，位於該本體區中，其具有第二導電型雜質摻雜；一本體極，位於該本體區中，其具有第一導電型雜質摻雜；以及一汲極，位於該第二元件區中；其中，由上視圖視之，該輕摻雜汲極區、該源極、與該本體極於該環狀結構內由外而內排列；且其中，位於該環狀結構角落之閘極完全設置於該絕緣結構上。
  2. 如申請專利範圍第1項所述之雙擴散金屬氧化物半導體元件，其中該環狀結構大致呈矩形，其較短的兩側邊完全設置於該絕緣結構上。
  3. 一種雙擴散金屬氧化物半導體元件，包含：一基板，其具有絕緣結構以定義第一元件區與第二元件區；一閘極，位於該基板表面上，由上視圖視之，其具有一環狀結構，環繞該第一元件區，且該環狀結構部分或全部位 於該第一元件區內；一本體區，位於該第一元件區中，其具有第一導電型雜質摻雜，且其範圍由該環狀結構定義；一輕摻雜汲極區，位於該本體區中，其具有第二導電型雜質摻雜；一源極，位於該本體區中，其具有第二導電型雜質摻雜；一本體極，位於該本體區中，其具有第一導電型雜質摻雜；以及一汲極，位於該第二元件區中；其中，由上視圖視之，該輕摻雜汲極區、該源極、與該本體極於該環狀結構內由外而內排列；且其中，該輕摻雜汲極區與位於該環狀結構角落之閘極間，分開一段預設距離，且由上視圖視之，該輕摻雜汲極與該環狀結構彼此不相互重疊。
  4. 如申請專利範圍第3項所述之雙擴散金屬氧化物半導體元件，其中該預設距離，不小於最小設計線寬、或不小於1微米。
  5. 如申請專利範圍第1或3項所述之雙擴散金屬氧化物半導體元件，其中，該雙擴散金屬氧化物半導體元件包含兩共源極之橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件或雙擴散汲極金屬氧化物半導體(double diffused drain metal oxide semiconductor,DDDMOS)元件。
  6. 一種雙擴散金屬氧化物半導體元件製造方法，包含：提供一基板，並於其中形成一絕緣結構以定義第一元件區與第二元件區； 於該基板表面上形成一閘極，由上視圖視之，該閘極具有一環狀結構，環繞該第一元件區，且該環狀結構部分或全部位於該第一元件區內；於該第一元件區中形成一本體區，其具有第一導電型雜質摻雜，且其範圍由該環狀結構定義；於該本體區中形成一輕摻雜汲極區，其具有第二導電型雜質摻雜；於該本體區中形成一源極，其具有第二導電型雜質摻雜；於該本體區中形成一本體極，其具有第一導電型雜質摻雜；以及於該第二元件區中形成一汲極；其中，由上視圖視之，該輕摻雜汲極區、該源極、與該本體極於該環狀結構內由外而內排列；且其中，位於該環狀結構角落之閘極完全設置於該絕緣結構上。
  7. 如申請專利範圍第6項所述之雙擴散金屬氧化物半導體元件製造方法，其中該環狀結構大致呈矩形，其較短的兩側邊完全設置於該絕緣結構上。
  8. 一種雙擴散金屬氧化物半導體元件製造方法，包含：提供一基板，並於其中形成一絕緣結構以定義第一元件區與第二元件區；於該基板表面上形成一閘極，由上視圖視之，該閘極具有一環狀結構，環繞該第一元件區，且該環狀結構部分或全部位於該第一元件區內；於該第一元件區中形成一本體區，其具有第一導電型雜質摻雜，且其範圍由該環狀結構定義；於該本體區中形成一輕摻雜汲極區，其具有第二導電型雜 質摻雜；於該本體區中形成一源極，其具有第二導電型雜質摻雜；於該本體區中形成一本體極，其具有第一導電型雜質摻雜；以及於該第二元件區中形成一汲極；其中，由上視圖視之，該輕摻雜汲極區、該源極、與該本體極於該環狀結構內由外而內排列；且其中，該輕摻雜汲極區與位於該環狀結構角落之閘極間，分開一段預設距離，且由上視圖視之，該輕摻雜汲極與該環狀結構彼此不相互重疊。
  9. 如申請專利範圍第8項所述之雙擴散金屬氧化物半導體元件製造方法，其中該預設距離，不小於最小設計線寬、或不小於1微米。
  10. 如申請專利範圍第6或8項所述之雙擴散金屬氧化物半導體元件製造方法，其中該雙擴散金屬氧化物半導體元件包含兩共源極之橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件或雙擴散汲極金屬氧化物半導體(double diffused drain metal oxide semiconductor,DDDMOS)元件。
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