TWI447927B - Method of manufacturing solar cell having partially etched front side using resist material - Google Patents

Method of manufacturing solar cell having partially etched front side using resist material Download PDF

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TWI447927B
TWI447927B TW100109369A TW100109369A TWI447927B TW I447927 B TWI447927 B TW I447927B TW 100109369 A TW100109369 A TW 100109369A TW 100109369 A TW100109369 A TW 100109369A TW I447927 B TWI447927 B TW I447927B
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layer
semiconductor layer
type semiconductor
resist material
solar cell
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TW100109369A
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Chinese (zh)
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TW201240126A (en
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Ying Yen Chiu
Kuan Lun Chang
Hung Yi Chang
yi min Pan
Chi Hsiung Chang
Chun Min Wu
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Big Sun Energy Technology Inc
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Description

以抗蝕材料製作局部正面蝕刻之太陽能電池之方法Method for making partially front-etched solar cells with resist material

本發明係關於一種以抗蝕材料製作局部正面蝕刻之太陽能電池之方法。The present invention relates to a method of fabricating a partially front etched solar cell from a resist material.

現有之具有選擇性射極(Selective emitter)的太陽能電池，由於具有提高的開路電壓(Voc)、短路電流(Isc)、填充因子(fill factor)以及光電轉換效率，所以已經漸漸成為市場的主流。這種太陽能電池的結構具有高度摻雜的N型矽以及低度摻雜的N型矽，而高度摻雜的N型矽作為正面電極的載體，使得接觸電阻降低，進而使太陽能電池的串聯電阻減小。另一方面，高度摻雜的矽層與低度摻雜的矽層之間的接面亦可提升載子的收集率。因此，這種太陽能電池具有相當多的優點。Existing solar cells with selective emitters have gradually become mainstream in the market due to their increased open circuit voltage (Voc), short circuit current (Isc), fill factor, and photoelectric conversion efficiency. The structure of the solar cell has a highly doped N-type germanium and a low-doped N-type germanium, and the highly doped N-type germanium serves as a carrier for the front electrode, so that the contact resistance is lowered, thereby making the series resistance of the solar cell Reduced. On the other hand, the junction between the highly doped germanium layer and the lowly doped germanium layer can also increase the carrier collection rate. Therefore, such solar cells have considerable advantages.

然而，這種太陽能電池的製造方法的製程大部分是相當複雜且成本高昂，又需要導入新的機台與新的製程，所以這種太陽能電池的成本無法有效被降低。However, the manufacturing process of such a solar cell is mostly complicated and costly, and it is necessary to introduce a new machine and a new process, so the cost of such a solar cell cannot be effectively reduced.

因此，本發明之一個目的係提供一種以抗蝕材料製作局部正面蝕刻之太陽能電池之方法，用以降低製造成本。Accordingly, it is an object of the present invention to provide a method of fabricating a partially front etched solar cell from a resist material to reduce manufacturing costs.

為達上述目的，本發明提供一種以抗蝕材料製作局部正面蝕刻之太陽能電池之方法，包含以下步驟：對一裸晶進行一預處理，以得到一預處理過之晶片，其具有一第一型半導體層、位於第一型半導體層上之一第二型半導體層及位於第二型半導體層上之一磷矽玻璃層；於磷矽玻璃層塗上一抗蝕材料層，以覆蓋磷矽玻璃層之一部分；以抗蝕材料層作為遮罩來蝕刻磷矽玻璃層及第二型半導體層，以使第二型半導體層具有一第一部分及一第二部分；以及移除抗蝕材料層及磷矽玻璃層，以獲得一無PSG之晶片。In order to achieve the above object, the present invention provides a method for fabricating a partially front-etched solar cell using a resist material, comprising the steps of: pretreating a die to obtain a pretreated wafer having a first a semiconductor layer, a second type semiconductor layer on the first type semiconductor layer and a phosphorous glass layer on the second type semiconductor layer; a resist material layer is coated on the phosphorous glass layer to cover the phosphor a portion of the glass layer; etching the phosphor glass layer and the second type semiconductor layer with the resist material layer as a mask such that the second type semiconductor layer has a first portion and a second portion; and removing the resist material layer And a phosphorous glass layer to obtain a wafer without PSG.

藉此，可以有效簡化生產製程、降低製造成本並提高太陽能電池的效率。Thereby, the production process can be simplified, the manufacturing cost can be reduced, and the efficiency of the solar cell can be improved.

為讓本發明之上述內容能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下。In order to make the above description of the present invention more comprehensible, a preferred embodiment will be described below in detail with reference to the accompanying drawings.

圖1至10顯示依據本發明之以抗蝕材料製作局部正面蝕刻之太陽能電池之方法之各步驟的結構圖。圖11顯示依據本發明之以抗蝕材料製作局部正面蝕刻之太陽能電池之方法之流程圖。1 to 10 are structural views showing the steps of a method of fabricating a partially front-etched solar cell using a resist material in accordance with the present invention. Figure 11 is a flow chart showing a method of fabricating a partially front etched solar cell from a resist material in accordance with the present invention.

如圖1、2與11所示，於步驟(a)，對一裸晶10進行一預處理，以得到一預處理過之晶片20，其具有一第一型半導體層21、位於第一型半導體層21上之一第二型半導體層22及位於第二型半導體層22上之一磷矽玻璃(PSG)層23。圖1所示的是一種裸晶10，譬如是N型矽晶圓或P型矽晶圓。於以下描述中，係以P型矽晶圓作為例子說明。As shown in FIGS. 1, 2 and 11, in step (a), a pretreatment of a die 10 is performed to obtain a preprocessed wafer 20 having a first type semiconductor layer 21 in the first type. A second type semiconductor layer 22 on the semiconductor layer 21 and a phosphorous glass (PSG) layer 23 on the second type semiconductor layer 22. Figure 1 shows a die 10, such as an N-type germanium wafer or a P-type germanium wafer. In the following description, a P-type germanium wafer is taken as an example.

準備好圖1的裸晶10以後，先對其作清潔、表面粗化等處理。然後，再對裸晶10進行一擴散處理，以形成預處理過之晶片20。舉例而言，擴散處理可以使用三氯氧磷(POCL3 )而在高溫爐中進行。擴散處理可以是單階段或是多階段，目的是用以形成摻雜濃度不同的第一部分22A及第二部分22B。舉例而言，第一型半導體層21係為P型矽層，第二型半導體層22係為N型矽層，第一部分22A係為N+矽層，第二部分22B係為N++矽層，亦即，第二部分22B之摻雜濃度高於第一部分22A之摻雜濃度。因此，第二型半導體層包含摻雜濃度不同之第一部分22A及第二部分22B，第二部分22B位於第一部分22A上，磷矽玻璃層23位於第二部分22B上。After the bare crystal 10 of FIG. 1 is prepared, it is first cleaned, roughened, and the like. Then, the die 10 is subjected to a diffusion process to form the pretreated wafer 20. For example, the diffusion treatment can be carried out in a high temperature furnace using phosphorus oxychloride (POCL 3 ). The diffusion treatment may be single-stage or multi-stage, and the purpose is to form the first portion 22A and the second portion 22B having different doping concentrations. For example, the first type semiconductor layer 21 is a P type germanium layer, the second type semiconductor layer 22 is an N type germanium layer, the first portion 22A is an N+ germanium layer, and the second portion 22B is an N++ germanium layer. That is, the doping concentration of the second portion 22B is higher than the doping concentration of the first portion 22A. Therefore, the second type semiconductor layer includes the first portion 22A and the second portion 22B having different doping concentrations, the second portion 22B is located on the first portion 22A, and the phosphor glass layer 23 is located on the second portion 22B.

接著，如圖3與11所示，於步驟(b)，於磷矽玻璃層23塗上一抗蝕材料層30，以覆蓋磷矽玻璃層23之一部分。被覆蓋的部分即是欲作為選擇性射極之部分。Next, as shown in FIGS. 3 and 11, in step (b), a layer of resist material 30 is applied to the phosphorous-glass layer 23 to cover a portion of the phosphorous-glass layer 23. The covered part is intended to be part of the selective emitter.

然後，如圖4與11所示，於步驟(c)，以抗蝕材料層30作為遮罩來蝕刻磷矽玻璃層23及第二型半導體層22之第二部分22B，以使第二型半導體層22具有如圖4所示之第一部分22A及第二部分22B。於一例子中，可以採用的蝕刻液譬如是氫氧化鉀(KOH)水溶液或稀釋過的氫氟酸(HF)。Then, as shown in FIGS. 4 and 11, in step (c), the phosphorous-glass layer 23 and the second portion 22B of the second-type semiconductor layer 22 are etched with the resist layer 30 as a mask to make the second type The semiconductor layer 22 has a first portion 22A and a second portion 22B as shown in FIG. In one example, an etchant such as an aqueous solution of potassium hydroxide (KOH) or diluted hydrofluoric acid (HF) may be employed.

接著，如圖5、6與11所示，於步驟(d)，移除抗蝕材料層30及磷矽玻璃層23，以獲得一無PSG之晶片40。因此，無PSG之晶片40具有第一型半導體層21、位於第一型半導體層21上之第一部分22A、以及位於第一部 分22A上之第二部分22B。磷矽玻璃層23可以於抗蝕材料層30被移除後才被移除。或者，亦可以直接蝕刻掉磷矽玻璃層23而使抗蝕材料層30失去支撐的載體而同時被移除。於一例子中，可利用有機溶劑來移除抗蝕材料層30，之後利用稀釋過的氫氟酸(HF)來移除磷矽玻璃層23。Next, as shown in FIGS. 5, 6, and 11, in step (d), the resist material layer 30 and the phosphorous glass layer 23 are removed to obtain a PSG-free wafer 40. Therefore, the PSG-free wafer 40 has the first type semiconductor layer 21, the first portion 22A on the first type semiconductor layer 21, and the first portion. The second portion 22B on 22A. The phosphorous glass layer 23 can be removed after the resist material layer 30 is removed. Alternatively, the phosphorous-glass layer 23 may be directly etched away to cause the resist material layer 30 to lose its supporting carrier while being removed. In one example, the organic solvent may be utilized to remove the resist material layer 30, after which the phosphorous glass layer 23 is removed using diluted hydrofluoric acid (HF).

然後，如圖7-11所示，於步驟(e)對無PSG之晶片40進行一後處理，以形成太陽能電池1。後處理步驟將說明於下。首先，如圖7所示，於第二型半導體層22之第一部分22A及第二部分22B上形成一抗反射層50。抗反射層50之材料包含氮化矽。值得注意的是，在形成抗反射層50以前，亦可以對無PSG之晶片40進行氧化以形成保護層。Then, as shown in FIGS. 7-11, the PS40-free wafer 40 is subjected to a post-treatment in the step (e) to form the solar cell 1. The post-processing steps will be explained below. First, as shown in FIG. 7, an anti-reflection layer 50 is formed on the first portion 22A and the second portion 22B of the second type semiconductor layer 22. The material of the anti-reflective layer 50 contains tantalum nitride. It is noted that the PSG-free wafer 40 can also be oxidized to form a protective layer prior to forming the anti-reflective layer 50.

接著，如圖8所示，於抗反射層50上形成一正面電極層51及於第一型半導體層21之一背面21B形成一背面金屬層52及一背面電極層53。正面電極層51一般具有多個指狀電極。Next, as shown in FIG. 8, a front electrode layer 51 is formed on the anti-reflective layer 50, and a back metal layer 52 and a back electrode layer 53 are formed on the back surface 21B of the first type semiconductor layer 21. The front electrode layer 51 generally has a plurality of finger electrodes.

然後，如圖9所示，燒結正面電極層51及背面電極層53以使正面電極層51穿透抗反射層50電連接至第二型半導體層22，並使背面電極層53電連接至第一型半導體層21。於此時，靠近背面金屬層52的第一型半導體層21會變成高濃度的P+矽層。Then, as shown in FIG. 9, the front electrode layer 51 and the back electrode layer 53 are sintered such that the front electrode layer 51 is electrically connected to the second type semiconductor layer 22 through the antireflection layer 50, and the back electrode layer 53 is electrically connected to the first A type semiconductor layer 21. At this time, the first type semiconductor layer 21 close to the back metal layer 52 becomes a high concentration P+ germanium layer.

接著，如圖10所示，形成邊緣絕緣溝槽60貫穿抗反.射層50、第二型半導體層22及第一型半導體層21。Next, as shown in FIG. 10, the edge insulating trench 60 is formed to penetrate the anti-reflection layer 50, the second type semiconductor layer 22, and the first type semiconductor layer 21.

後處理的程序跟傳統的太陽能電池的製作方式是類 似的，而預處理的程序亦可採用傳統的製程。本發明的特點，在於磷矽玻璃(PSG)層的移除是在形成選擇性射極以後，而非在形成選擇性射極以前。如果磷矽玻璃(PSG)層是在選擇性射極以前，則抗蝕材料層30需要直接塗在高濃度摻雜的第二部分22B上，最後移除抗蝕材料層30時會傷害到高濃度摻雜的第二部分22B，而降低太陽能電池的光電轉換效率。由於PSG移除是相當成熟且不會傷害到高濃度摻雜的第二部分22B，所以本發明之製造方法是相當有助於提升太陽能電池的光電轉換效率。此外，這種製造方法亦不需要增購新的機台，也不需要高昂的生產成本，即能達到提升太陽能電池的效率的目的。Post-processing procedures and traditional solar cell manufacturing methods are Similarly, the pre-processed program can also use the traditional process. A feature of the invention is that the removal of the phosphorous bismuth (PSG) layer is after the formation of the selective emitter, rather than before the formation of the selective emitter. If the phosphorous bismuth glass (PSG) layer is before the selective emitter, the resist material layer 30 needs to be directly coated on the high concentration doped second portion 22B, and the last time the resist material layer 30 is removed, the damage is high. The doped second portion 22B is concentrated to reduce the photoelectric conversion efficiency of the solar cell. Since the PSG removal is quite mature and does not harm the high concentration doped second portion 22B, the manufacturing method of the present invention is quite helpful in improving the photoelectric conversion efficiency of the solar cell. In addition, this manufacturing method does not require the purchase of a new machine, nor does it require high production costs, that is, the purpose of improving the efficiency of the solar cell.

在較佳實施例之詳細說明中所提出之具體實施例僅用以方便說明本發明之技術內容，而非將本發明狹義地限制於上述實施例，在不超出本發明之精神及以下申請專利範圍之情況，所做之種種變化實施，皆屬於本發明之範圍。The specific embodiments of the present invention are intended to be illustrative only and not to limit the invention to the above embodiments, without departing from the spirit of the invention and the following claims. The scope of the invention and the various changes made are within the scope of the invention.

(a)-(e)‧‧‧方法步驟(a)-(e)‧‧‧ Method steps

1‧‧‧太陽能電池1‧‧‧Solar battery

10‧‧‧裸晶10‧‧‧Bare crystal

20‧‧‧預處理過之晶片20‧‧‧Preprocessed wafers

21‧‧‧第一型半導體層21‧‧‧First type semiconductor layer

21B‧‧‧背面21B‧‧‧Back

22‧‧‧第二型半導體層22‧‧‧Second type semiconductor layer

22A‧‧‧第一部分22A‧‧‧Part 1

22B‧‧‧第二部分22B‧‧‧Part II

23‧‧‧磷矽玻璃(PSG)層23‧‧‧ Phosphorus glass (PSG) layer

30‧‧‧抗蝕材料層30‧‧‧resist layer

40‧‧‧無PSG之晶片40‧‧‧No PSG chip

50‧‧‧抗反射層50‧‧‧Anti-reflective layer

51‧‧‧正面電極層51‧‧‧ front electrode layer

52‧‧‧背面金屬層52‧‧‧Back metal layer

53‧‧‧背面電極層53‧‧‧Back electrode layer

60‧‧‧邊緣絕緣溝槽60‧‧‧Edge insulation trench

圖1至10顯示依據本發明之以抗蝕材料製作局部正面蝕刻之太陽能電池之方法之各步驟的結構圖。1 to 10 are structural views showing the steps of a method of fabricating a partially front-etched solar cell using a resist material in accordance with the present invention.

圖11顯示依據本發明之以抗蝕材料製作局部正面蝕刻之太陽能電池之方法之流程圖。Figure 11 is a flow chart showing a method of fabricating a partially front etched solar cell from a resist material in accordance with the present invention.

(a)-(e)．．．方法步驟(a)-(e). . . Method step

Claims (10)

一種以抗蝕材料製作局部正面蝕刻之太陽能電池之方法，依序包含以下步驟：(a)對一裸晶進行一預處理，以得到一預處理過之晶片，其具有一第一型半導體層、位於該第一型半導體層上之一第二型半導體層及位於該第二型半導體層上之一磷矽玻璃(PSG)層，該第二型半導體層包含摻雜濃度不同之一第一部分及一第二部分，該第二部分位於該第一部分上，該磷矽玻璃層位於該第二部分上；(b)於該磷矽玻璃層塗上一抗蝕材料層，以覆蓋該磷矽玻璃層之一部分；(c)以該抗蝕材料層作為遮罩來蝕刻該磷矽玻璃層及該第二型半導體層之該第二部分；以及(d)移除該抗蝕材料層及該磷矽玻璃層，以獲得一無PSG之晶片，該無PSG之晶片具有該第一型半導體層、位於該第一型半導體層上之該第二型半導體層之該第一部分、以及位於該第二型半導體層之該第一部分上之該第二型半導體層之該第二部分，該第二部分之摻雜濃度高於該第一部分之摻雜濃度。 A method for fabricating a partially front-etched solar cell using a resist material, comprising the steps of: (a) pre-treating a die to obtain a pre-processed wafer having a first type of semiconductor layer a second type semiconductor layer on the first type semiconductor layer and a phosphorous glass (PSG) layer on the second type semiconductor layer, the second type semiconductor layer comprising one of different doping concentrations And a second portion, the second portion is located on the first portion, the phosphor glass layer is located on the second portion; (b) the phosphor glass layer is coated with a resist material layer to cover the phosphor a portion of the glass layer; (c) etching the phosphor glass layer and the second portion of the second semiconductor layer with the resist material layer as a mask; and (d) removing the resist material layer and the a phosphor glass layer to obtain a PSG-free wafer having the first type semiconductor layer, the first portion of the second type semiconductor layer on the first type semiconductor layer, and the first portion The first part of the second type semiconductor layer The second portion of the semiconductor layer, doping concentration of the doping concentration is higher than the second portion of the first portion. 如申請專利範圍第1項所述之方法，更包含：(e)對該無PSG之晶片進行一後處理，以形成該太陽能電池。 The method of claim 1, further comprising: (e) performing a post-treatment on the PSG-free wafer to form the solar cell. 如申請專利範圍第2項所述之方法，其中該後處理包含：(e1)於該第二型半導體層之該第一部分及第二部分上 形成一抗反射層；(e2)於該抗反射層上形成一正面電極層及於該第一型半導體層之一背面形成一背面金屬層及一背面電極層；以及(e3)燒結該正面電極層及該背面電極層以使該正面電極層電連接至該第二型半導體層，並使該背面電極層電連接至該第一型半導體層。 The method of claim 2, wherein the post-processing comprises: (e1) on the first portion and the second portion of the second type semiconductor layer Forming an anti-reflection layer; (e2) forming a front electrode layer on the anti-reflection layer; forming a back metal layer and a back electrode layer on a back surface of the first type semiconductor layer; and (e3) sintering the front electrode And a layer of the back electrode layer to electrically connect the front electrode layer to the second type semiconductor layer and electrically connect the back electrode layer to the first type semiconductor layer. 如申請專利範圍第3項所述之方法，其中該後處理更包含：(e4)形成邊緣絕緣溝槽貫穿該抗反射層、該第二型半導體層及該第一型半導體層。 The method of claim 3, wherein the post-processing further comprises: (e4) forming an edge insulating trench extending through the anti-reflective layer, the second semiconductor layer, and the first semiconductor layer. 如申請專利範圍第2項所述之方法，其中該抗反射層之材料包含氮化矽。 The method of claim 2, wherein the material of the anti-reflective layer comprises tantalum nitride. 如申請專利範圍第1項所述之方法，更包含：對該無PSG之晶片進行氧化。 The method of claim 1, further comprising: oxidizing the PSG-free wafer. 如申請專利範圍第1項所述之方法，其中該預處理包含：(a1)清潔該裸晶；(a2)粗化該裸晶；以及(a3)對該裸晶進行一擴散處理，以形成該預處理過之晶片。 The method of claim 1, wherein the pretreatment comprises: (a1) cleaning the bare crystal; (a2) roughening the bare crystal; and (a3) performing a diffusion treatment on the bare crystal to form The pretreated wafer. 如申請專利範圍第7項所述之方法，其中該擴散處理係使用三氯氧磷(POCL3 )來進行。The method of claim 7, wherein the diffusion treatment is carried out using phosphorus oxychloride (POCL 3 ). 如申請專利範圍第1項所述之方法，其中該第一型半導體層係為P型矽層，該第二型半導體層係為N 型矽層，該第一部分係為N+矽層，該第二部分係為N++矽層。 The method of claim 1, wherein the first type semiconductor layer is a P type germanium layer, and the second type semiconductor layer is N The first layer is an N+ layer and the second portion is an N++ layer. 如申請專利範圍第1項所述之方法，其中該磷矽玻璃層係於該抗蝕材料層被移除後才被移除。 The method of claim 1, wherein the phosphor glass layer is removed after the resist material layer is removed.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200929567A (en) * 2007-12-19 2009-07-01 Big Sun Energy Technology Inc Solar cell with edge isolated structure and method of manufacturing the same
TW201007968A (en) * 2008-07-16 2010-02-16 Applied Materials Inc Hybrid heterojunction solar cell fabrication using a doping layer mask
US20100037941A1 (en) * 2008-08-13 2010-02-18 E. I. Du Pont De Nemours And Company Compositions and processes for forming photovoltaic devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200929567A (en) * 2007-12-19 2009-07-01 Big Sun Energy Technology Inc Solar cell with edge isolated structure and method of manufacturing the same
TW201007968A (en) * 2008-07-16 2010-02-16 Applied Materials Inc Hybrid heterojunction solar cell fabrication using a doping layer mask
US20100037941A1 (en) * 2008-08-13 2010-02-18 E. I. Du Pont De Nemours And Company Compositions and processes for forming photovoltaic devices

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