TWI447864B - 封裝基板及其製法 - Google Patents

封裝基板及其製法 Download PDF

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TWI447864B
TWI447864B TW100120097A TW100120097A TWI447864B TW I447864 B TWI447864 B TW I447864B TW 100120097 A TW100120097 A TW 100120097A TW 100120097 A TW100120097 A TW 100120097A TW I447864 B TWI447864 B TW I447864B
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layer
pattern
insulating layer
package substrate
line pattern
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TW100120097A
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TW201250945A (en
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Tsung Yuan Chen
Shih Lian Cheng
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Unimicron Technology Corp
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Priority to TW100120097A priority Critical patent/TWI447864B/zh
Priority to CN201110244464.3A priority patent/CN102820270B/zh
Priority to US13/241,264 priority patent/US8604359B2/en
Publication of TW201250945A publication Critical patent/TW201250945A/zh
Priority to US14/073,846 priority patent/US8955218B2/en
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Publication of TWI447864B publication Critical patent/TWI447864B/zh

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    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
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    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
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    • H01L21/4814Conductive parts
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
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    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
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    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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Description

封裝基板及其製法
本發明是有關於一種封裝基板及其製法,且特別是有關於一種直接在基板表面製作中介層並製作內埋線路的封裝基板及其製法。
因應半導體封裝元件的微縮及高密度等需求,業界已發展出一種三維封裝技術,例如,直通矽晶穿孔(Through-Silicon Via,TSV)封裝技術。TSV封裝技術可大幅度提高晶片的晶體管立體密度,使半導體產業可以超越摩爾定律的發展速度。TSV封裝技術的等級是L/S(線寬/線距比)小於6/6,使用矽載板,成本約為覆晶球格陣列(FCBGA)基板的四倍。
目前,由於成本上的考量,業界亟欲將覆晶球格陣列技術應用在三維封裝領域中,以代替較昂貴的TSV封裝技術,但是會遭遇到以下問題。首先,在L/S<6/6的製程挑戰下,現階段的半加成(Semi-additive process,SAP)製程仍無法製造出這類封裝產品。其次,IC載板產業上所使用的介電材,其熱膨脹係數(thermal expansion,CTE)與矽材相差過大,因而可能會產生可靠度上的問題。此外,超高密度的中介層(interposer)佈局,會受限於目前防焊開口(SRO)>65um的製程瓶頸。最後,以目前的技術水平,基板的盲口開口仍有需大於40μm的限制,故浪費掉許多線路佈局空間。
由此可知,產業上亟需一種封裝基板及其製法,可解決上述先前技術所遇到之瓶頸及問題。
本發明提出一種封裝基板及其製法,其主要結合雷射埋線技術(Laser Embedded,LE)、熱固化介電材技術(Thermal Curing Dielectric,TCD)以及化學機械研磨技術(Chemical Mechanical Polishing,CMP),而直接在基板表面製作中介層並製作內線路,以解決上述封裝技術之限制,並提升封裝基板之積集度。
本發明提供一種封裝基板,包含有一核心層、一第一介電層、一第二線路圖案、一第一防焊層以及一絕緣層。核心層的一第一表面設有一第一線路圖案。第一介電層覆蓋第一線路圖案。第二線路圖案設於第一介電層上,且第二線路圖案包含有一內連線路圖案,其位於一晶片接合區域(chip mounting area)內。第一防焊層覆蓋住晶片接合區域以外的第二線路圖案。絕緣層覆蓋住晶片接合區域以及內連線路圖案。複數個埋入式接墊,設於絕緣層之一上表面,且接墊上表面齊平或不高於絕緣層之上表面。其中該埋入式接墊透過至少一設於該絕緣層內的導電插塞電連接該內連線路圖,且該埋入式接墊、該內連線路圖案、該導電插塞以及該絕緣層構成一中介層(interposer)
本發明提供一種封裝基板的製法。提供一基板,包含有至少一內層線路圖案以及至少一外層線路圖案。外層線路圖案包含有一內連線路圖案,其位於一晶片接合區域內。於基板上覆蓋一防焊層,覆蓋住外層線路圖案。將晶片接合區域內的防焊層去除,曝露出內連線路圖案。於晶片接合區域內形成一絕緣層,覆蓋住內連線路圖案。對絕緣層進行一固化製程。於絕緣層的一上表面形成複數個埋入式接墊。
基於上述,本發明提出一種封裝基板及其製法,其具有一內埋線路圖案的絕緣層作為中介層,可取代傳統中直通矽晶穿孔封裝之次基板而直接製作於基板中。如此,可一併解決習知中半加成製程在線寬限制下無法製造的問題、封裝基板之介電材與矽材相差過大而產生之可靠度問題、防焊開口之尺寸無法縮小之瓶頸、以及基板的盲孔開口過大的問題。因此,本發明之封裝基板具有尺寸更小以及可靠度更好之優勢。
第1-10圖係為依據本發明一較佳實施例所繪示的封裝基板之製作方法之剖面示意圖。首先,提供一基板100,包含有內層線路圖案110a、110b以及外層線路圖案120a、120b。本實施例中,基板100可例如為四層基板,但在其他實施例中亦可為六層基板或八層基板等,本發明不以此為限。內層線路圖案110及外層線路圖案120可以下列步驟形成,但本發明不以此為限。
如第1圖所示,首先,提供一核心層130。於核心層130中具有至少一導電通孔140以電性連接核心層130相對兩面之內層線路圖案110a與內層線路圖案110b。核心層130例如為一玻纖預浸絕緣材,但不限於此。內層線路圖案110a與內層線路圖案110b可包含銅等導電材質。導電通孔140可以利用例如雷射鑽孔、機械鑽孔或微影製程等各種方法形成。
接著,在核心層130相對兩面上分別壓合一第一介電層150a與一第二介電層150b,其中第一介電層150a與第二介電層150b分別覆蓋內層線路圖案110a與內層線路圖案110b。然後,於第一介電層150a與第二介電層150b的表面上分別形成外層線路圖案120a與外層線路圖案120b。根據本發明之較佳實施例,第一介電層150a與一第二介電層150b的材質可以是,例如,味之素樹脂(Ajinomoto Bond Film,ABF),但亦可為其他絕緣材質。外層線路圖案120a與外層線路圖案120b可包含銅等導電材質。值得注意的是,外層線路圖案120a包含有一內連線路圖案122a,其位於一晶片接合區域A內。
如第2圖所示,接著於基板100的二相對外側表面S1、S2上分別覆蓋防焊層210a、210b,其中,防焊層210a覆蓋住外層線路圖案120a以及第一介電層150a,防焊層210b覆蓋住外層線路圖案120b以及第二介電層150b。接著,將外側表面S1上之晶片接合區域A內的防焊層210a去除,曝露出內連線路圖案122a,以及在晶片接合區域A外的防焊層210a中形成複數個防焊開口R1,其分別曝露出複數個接墊220a。同樣地,將外側表面S2上之防焊層210b形成複數個防焊開口R2,其分別曝露出複數個接墊220b。防焊層210a以及防焊層210b係可由環氧樹脂形成,其中環氧樹脂可以包含可感光之樹脂成分,如此可直接對於防焊層210a以及防焊層210b進行曝光顯影,並分別形成開口R1以及R2。
如第3圖所示,接著於晶片接合區域A內,以塗佈法或印刷法在基板100的外側表面S1上形成一絕緣層230,例如,熱固化介電材(Thermal Curing Dielectric,TCD),覆蓋住內連線路圖案122a。接著,再對絕緣層230進行一固化製程。依據本發明之較佳實施例,絕緣層230與第一介電層150a直接接觸。依據本發明之較佳實施例,絕緣層230不會與防焊層210a重疊。然而,在本發明其它實施例中,絕緣層230有可能與防焊層210a重疊。
接著,第4-8圖例示於絕緣層230的上表面S3形成複數個埋入式接墊的方法。如第4圖所示,於晶片接合區域A以外形成一抗鍍銅層P,其中,抗鍍銅層P之材質例如抗鍍銅介電材,但本發明不以此為限。抗鍍銅層P可以利用印刷等方式形成。如第5圖所示,以雷射埋線技術(Laser Embedded,LE),於絕緣層230的上表面S3形成複數個溝槽t。如第6圖所示,於溝槽t中填入一導電層240,其中導電層可包括一銅層,例如,利用電鍍法或選擇性化學銅填入溝槽t中,但本發明不以此為限。如第7圖所示,可選擇性地先剝除抗鍍銅層P,以暴露出其下方之防焊層210a及接墊220a。如第8圖所示,例如利用化學機械研磨製程等方式,對導電層240進行平坦化,俾形成複數個埋入式接墊250以及導電插塞260,其中埋入式接墊250與內連線路圖案122a可透過絕緣層230內的導電插塞260電連接。如此一來,由埋入式接墊250、內連線路圖案122a、導電插塞260以及絕緣層230構成一內建的中介層(interposer)290。此內建的中介層290可整合於封裝基板製程中,直接形成於基板100之一表面上。
如第9圖所示,在對導電層240進行平坦化之後,可於複數個埋入式接墊250表面形成一保護層270,用以防止埋入式接墊250直接與空氣接觸氧化,其中保護層270可包含無電鍍鎳/無電鍍鈀/浸鍍 金(electroless nickel/electroless palladium/immersion gold,ENEPIG)、無電鍍鎳/自催化金(electroless nickel/auto-catalytic gold,ENAG)或有機保焊劑等等。
如第10圖所示,藉由將埋入式接墊250與晶片300中的金屬凸塊或焊墊錫球310接合,以及於絕緣層230與晶片300中填入底膠,可使晶片300與絕緣層230緊密接合,形成一封裝構件400。如此,俾使晶片300與基板100接合。在一較佳實施例中,絕緣層230的熱膨脹係數與晶片300的熱膨脹係數互相匹配。另外,可使複數個錫球280,分別設於複數個開口R2內,並與複數個錫球焊墊220b接合。
詳細而言,可將此封裝構件400以核心層130為中心軸分為上、下二部分。封裝構件400之上部分包含有核心層130、第一介電層150a、外層線路圖案120a、防焊層210a以及絕緣層230。核心層130的一第一表面S4設有內層線路圖案110a。第一介電層150a覆蓋內層線路圖案110a。外層線路圖案120a設於第一介電層上150a,且外層線路圖案120a包含有一內連線路圖案122a,其位於一晶片接合區域A內。防焊層210a覆蓋住晶片接合區域A以外的外層線路圖案120a。絕緣層230覆蓋住晶片接合區域A以及內連線路圖案。複數個埋入式接墊250,設於絕緣層230之一上表面S3上。此外,封裝構件400之下部分包含核心層130、內層線路圖案110b、第二介電層150b、外層線路圖案120b、防焊層210b以及複數個錫球280。內層線路圖案110b設於核心層130的一第二表面S5。第二介電層150b覆蓋內層線路圖案110b。外層線路圖案120b設於第二 介電層150b上。外層線路圖案120b包含有複數個錫球焊墊220b。防焊層210b覆蓋住第二介電層150b以及外層線路圖案120b,其中防焊層210b包含有複數個開口R2,分別曝露出複數個錫球焊墊220b。複數個錫球280分別設於複數個開口R2內,並與複數個錫球焊墊220b接合。
綜上所述,本發明提出一種封裝基板及其製法,其具有一內埋線路圖案的絕緣層作為中介層,可取代傳統矽次基板,而且本發明中介層係直接製作並內建於基板上。詳細而言,本發明之封裝基板係結合雷射埋線技術(Laser Embedded,LE)、熱固化介電材技術(Thermal Curing Dielectric,TCD)、化學機械研磨技術(Chemical Mechanical Polishing,CMP)以及選擇性化學銅(Selective E-less Copper Plating),如此可一併解決習知技術半加成製程在線寬限制下無法製造的問題、封裝基板之介電材與矽材CTE相差過大而產生之可靠度問題、防焊開口之尺寸無法縮小之瓶頸、以及基板的盲孔開口過大浪費佈線面積的問題。因此,本發明可大幅降低製程時間以及製程成本。並且,本發明之封裝基板具有尺寸更小以及可靠度更好之優勢。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
100‧‧‧基板
110a‧‧‧內層線路圖案
110b‧‧‧內層線路圖案
120a‧‧‧外層線路圖案
120b‧‧‧外層線路圖案
122a‧‧‧內連線路圖案
130‧‧‧核心層
140‧‧‧導電通孔
150a‧‧‧第一介電層
150b‧‧‧第二介電層
210a‧‧‧防焊層
210b‧‧‧防焊層
220a‧‧‧接墊
220b‧‧‧錫球焊墊
230‧‧‧絕緣層
240‧‧‧導電層
250‧‧‧埋入式接墊
260‧‧‧導電插塞
270‧‧‧保護層
280‧‧‧錫球
290‧‧‧內建的中介層
300‧‧‧晶片
310‧‧‧焊墊錫球
400‧‧‧封裝基板
A‧‧‧晶片接合區域
P‧‧‧抗鍍銅層
R1、R2‧‧‧開口
S1、S2‧‧‧外側表面
S3‧‧‧上表面
S4‧‧‧第一表面
S5‧‧‧第二表面
t‧‧‧溝槽
第1-10圖係為依據本發明一較佳實施例所繪示的封裝基板之製作 方法之剖面示意圖。
100‧‧‧基板
110a‧‧‧第一線路圖案
110b‧‧‧第三線路圖案
120a‧‧‧第二線路圖案
120b‧‧‧第四線路圖案
122a‧‧‧內連線路圖案
130‧‧‧核心層
150a‧‧‧第一介電層
150b‧‧‧第二介電層
210a‧‧‧第一防焊層
210b‧‧‧第二防焊層
220a、220b‧‧‧錫球焊墊
230‧‧‧絕緣層
250‧‧‧埋入式接墊
280‧‧‧錫球
300‧‧‧晶片
310‧‧‧焊墊錫球
400‧‧‧封裝基板
A‧‧‧晶片接合區域
R2‧‧‧開口
S3‧‧‧上表面
S4‧‧‧第一表面
S5‧‧‧第二表面

Claims (10)

  1. 一種封裝基板,包含有:一核心層,其一第一表面設有一第一線路圖案;一第一介電層,覆蓋該第一線路圖案;一第二線路圖案,設於該第一介電層上,該第二線路圖案包含有一內連線路圖案,其位於一晶片接合區域(chip mounting area)內;一第一防焊層,覆蓋住該晶片接合區域以外的該第二線路圖案;一絕緣層,覆蓋住該晶片接合區域以及該內連線路圖案;以及複數個埋入式接墊,設於該絕緣層之一上表面,其中該埋入式接墊透過至少一設於該絕緣層內的導電插塞電連接該內連線路圖,且該埋入式接墊、該內連線路圖案、該導電插塞以及該絕緣層構成一中介層(interposer)。
  2. 如申請專利範圍第1項所述之封裝基板,其中該絕緣層包含熱固型介電材(thermal curing dielectric)。
  3. 如申請專利範圍第1項所述之封裝基板,其中該絕緣層與該第一介電層直接接觸。
  4. 如申請專利範圍第1項所述之封裝基板,其中該絕緣層的熱膨脹係數與一晶片的熱膨脹係數互相匹配。
  5. 如申請專利範圍第1項所述之封裝基板,其中另包含有一保護 層,設於各該複數個埋入式接墊的表面上。
  6. 如申請專利範圍第1項所述之封裝基板,其中另包含:一第三線路圖案,設於該核心層的一第二表面;一第二介電層,覆蓋該第三線路圖案;一第四線路圖案,設於該第二介電層上,該第四線路圖案包含有複數個錫球焊墊;一第二防焊層,覆蓋住該第二介電層以及該第四線路圖案,其中該第二防焊層包含有複數個開口,分別曝露出該複數個錫球焊墊;以及複數個錫球,分別設於該複數個開口內,並與該複數個錫球焊墊接合。
  7. 一種封裝基板的製法,包含有:提供一基板,包含有至少一內層線路圖案以及至少一外層線路圖案,該外層線路圖案包含有一內連線路圖案,其位於一晶片接合區域內;於該基板上覆蓋一防焊層,覆蓋住該外層線路圖案;將該晶片接合區域內的該防焊層去除,曝露出該內連線路圖案;於該晶片接合區域內形成一絕緣層,覆蓋住該內連線路圖案;對該絕緣層進行一固化製程;以及於該絕緣層的一上表面形成複數個透過設於該絕緣層內的導電插塞電連接該內連線路圖案的埋入式接墊,使得該埋入式接墊、該 內連線路圖案、該導電插塞以及該絕緣層共同構成一中介層(interposer)。
  8. 如申請專利範圍第7項所述之封裝基板的製法,其中前述形成複數個埋入式接墊係包含以下步驟:於該晶片接合區域以外形成一抗鍍銅層;以雷射於該絕緣層的該上表面形成複數個溝槽;於該溝槽中填入一導電層;以及研磨該導電層,俾形成該複數個埋入式接墊。
  9. 如申請專利範圍第8項所述之封裝基板的製法,其中前述於該溝槽中填入導電層係利用電鍍法或選擇性化學銅。
  10. 如申請專利範圍第7項所述之封裝基板的製法,其中該絕緣層包含熱固型介電材(thermal curing dielectric)。
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Publication number Priority date Publication date Assignee Title
KR20140019173A (ko) * 2012-08-06 2014-02-14 삼성전기주식회사 솔더 코팅볼을 이용한 패키징 방법 및 이에 따라 제조된 패키지
KR20150024150A (ko) * 2013-08-26 2015-03-06 삼성전기주식회사 인쇄회로기판 및 그 제조방법
JP2015050314A (ja) * 2013-08-31 2015-03-16 イビデン株式会社 結合型プリント配線板及びその製造方法
CN104637825B (zh) * 2013-11-14 2017-12-22 中芯国际集成电路制造(上海)有限公司 半导体器件收缩尺寸的封装结构及方法
KR102214512B1 (ko) 2014-07-04 2021-02-09 삼성전자 주식회사 인쇄회로기판 및 이를 이용한 반도체 패키지
TWI641094B (zh) * 2014-09-17 2018-11-11 矽品精密工業股份有限公司 基板結構及其製法
CN106486445A (zh) * 2015-09-02 2017-03-08 力成科技股份有限公司 封装基板及半导体封装结构
CN106658977B (zh) * 2015-10-29 2019-11-12 碁鼎科技秦皇岛有限公司 电路板的线路制作方法及利用该方法制作的电路板
US10872852B2 (en) * 2016-10-12 2020-12-22 Micron Technology, Inc. Wafer level package utilizing molded interposer
TWI669797B (zh) * 2016-11-16 2019-08-21 矽品精密工業股份有限公司 電子裝置及其製法與基板結構
KR102173615B1 (ko) * 2018-07-19 2020-11-03 스템코 주식회사 다층 회로 기판 및 그 제조 방법
WO2020073264A1 (zh) * 2018-10-11 2020-04-16 深圳市修颐投资发展合伙企业(有限合伙) 复合工艺扇出封装方法
TWI775145B (zh) * 2019-10-09 2022-08-21 財團法人工業技術研究院 多晶片封裝件及其製造方法
CN112652608A (zh) 2019-10-09 2021-04-13 财团法人工业技术研究院 多芯片封装件及其制造方法
CN111901986A (zh) * 2020-08-17 2020-11-06 龙岩金时裕电子有限公司 一种高密度互连pcb板制造方法
US20220312591A1 (en) * 2021-03-26 2022-09-29 Juniper Networks, Inc. Substrate with conductive pads and conductive layers
KR20230040809A (ko) * 2021-09-16 2023-03-23 엘지이노텍 주식회사 회로기판 및 이를 포함하는 패키지 기판

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7382057B2 (en) * 2006-03-29 2008-06-03 Phoenix Precision Technology Corporation Surface structure of flip chip substrate
US20100071950A1 (en) * 2008-09-22 2010-03-25 Kyocera Slc Technologies Corporation Wiring Board and Manufacturing Method Thereof
US20100294552A1 (en) * 2009-05-19 2010-11-25 Shinko Electric Industries Co., Ltd Electronic component mounted structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0547842A (ja) * 1991-08-21 1993-02-26 Hitachi Ltd 半導体装置
TWI263704B (en) * 2003-03-18 2006-10-11 Ngk Spark Plug Co Wiring board
CN100581326C (zh) * 2004-01-30 2010-01-13 揖斐电株式会社 多层印刷配线板及其制造方法
JP4559163B2 (ja) * 2004-08-31 2010-10-06 ルネサスエレクトロニクス株式会社 半導体装置用パッケージ基板およびその製造方法と半導体装置
JP5079475B2 (ja) * 2007-12-05 2012-11-21 新光電気工業株式会社 電子部品実装用パッケージ
US7790503B2 (en) * 2007-12-18 2010-09-07 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device module

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7382057B2 (en) * 2006-03-29 2008-06-03 Phoenix Precision Technology Corporation Surface structure of flip chip substrate
US20100071950A1 (en) * 2008-09-22 2010-03-25 Kyocera Slc Technologies Corporation Wiring Board and Manufacturing Method Thereof
US20100294552A1 (en) * 2009-05-19 2010-11-25 Shinko Electric Industries Co., Ltd Electronic component mounted structure

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