TWI447568B - Power supply control circuit - Google Patents

Power supply control circuit Download PDF

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TWI447568B
TWI447568B TW097142159A TW97142159A TWI447568B TW I447568 B TWI447568 B TW I447568B TW 097142159 A TW097142159 A TW 097142159A TW 97142159 A TW97142159 A TW 97142159A TW I447568 B TWI447568 B TW I447568B
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power supply
switching element
computer
field effect
effect transistor
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TW097142159A
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TW201017391A (en
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Hua Zou
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Hon Hai Prec Ind Co Ltd
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Description

供電控制電路 Power supply control circuit

本發明係關於一種供電控制電路，尤指一種對電腦部件進行供電之控制電路。 The present invention relates to a power supply control circuit, and more particularly to a control circuit for supplying power to computer components.

電源是電腦之功率部件，電腦中每個部件之電能來源都是依靠電源，電源是保證電腦硬體正常運作最基本之前提，因此供電電源之穩定性與可靠性對電腦各部件之正常工作將有著直接之關鍵性之影響。 The power supply is the power component of the computer. The power source of each component in the computer depends on the power supply. The power supply is the most basic to ensure the normal operation of the computer hardware. Therefore, the stability and reliability of the power supply will work properly for all components of the computer. There is a direct and critical impact.

電腦部件如滑鼠、鍵盤等USB設備之傳統供電電路中，當電腦從一狀態轉換到另一狀態如從軟體關機狀態轉換到電腦正常工作狀態後，由於與電腦之ATX電源相連接之電源狀態訊號需經過100-400毫秒之延時才能從低電平變為高電平，而電源狀態訊號為高電平後給USB設備供電之電壓才會達到穩定，故在電源狀態訊號從低電平轉換為高電平時，給USB設備供電之電壓會出現從一電壓跳變為另一電壓之不穩定現象，由此可引起USB設備無法被識別等狀況發生。 In a traditional power supply circuit of a USB component such as a mouse or a keyboard, when the computer is switched from one state to another, such as from a software shutdown state to a normal working state of the computer, the power state is connected to the ATX power supply of the computer. The signal needs to go through a delay of 100-400 milliseconds to change from low level to high level, and the voltage supply to the USB device will be stable after the power state signal is high, so the power state signal is converted from low level. When it is high, the voltage applied to the USB device will be unstable from one voltage to another, which may cause the USB device to be unidentified.

鑒於上述內容，有必要提供一種供電控制電路，可使得電腦從一狀態轉換到另一狀態後，電腦部件之供電電壓均保持穩定，而不會發生跳變。 In view of the above, it is necessary to provide a power supply control circuit that allows the power supply voltage of the computer components to remain stable without transitioning after the computer is switched from one state to another.

一種供電控制電路，包括第一至第六開關元件、第一至第四電阻，第一至第六開關元件均包括第一至第三端，該第一開關元件之第一端透過該第一電阻連接一輔助電源，該第一開關元件之第二端與一電腦主機板之南橋晶片連接以接收一主機板狀態訊號，該第一開關元件之第三端透過該第二電阻連接該輔助電源，還連接該第三開關元件之第一端，該第二開關元件之第一端接收一電源狀態訊號，該第二開關元件之第二端接地，該第二開關元件之第三端連接該第一開關元件之第一端，該第四開關元件之第一端連接一第一系統電源，該第四開關元件之第二端接地，該第四開關元件之第三端透過該第三電阻連接該輔助電源，還連接該第五開關元件之第一端，該第五開關元件之第二端接地，該第五開關元件之第三端透過該第四電阻連接一第二系統電源，還連接該第六開關元件之第一端，該第三開關元件之第二端及該第六開關元件之第二端分別連接該輔助電源及該第一系統電源，該第三開關元件之第三端及該第六開關元件之第三端連接一電腦部件之供電端，該第一系統電源小於第二系統電源之電壓，當電腦從軟體關機狀態切換為電腦正常工作狀態後及當電腦從待機狀態被喚醒而進入電腦正常工作狀態後，該主機板狀態訊號為高電平，該電源狀態訊號經一段時間延遲後由低電平變為高電平，該第四開關元件導通、第五開關元件截止及第六開關元件導通，該電腦部件之供電端均由第一系統電源穩定供電；當電腦從正常工作狀態切換為電腦待機狀態後，該主機板狀態訊號及電源狀態訊號為低電平，該第二開關元件截止，第一開關元件及第三開關元件導通，該電腦部件之供電端由該輔助電源穩定供電。 A power supply control circuit includes first to sixth switching elements, first to fourth resistors, each of the first to sixth switching elements including first to third ends, the first end of the first switching element is transmitted through the first The second end of the first switching element is connected to the south bridge of a computer motherboard to receive a motherboard status signal, and the third end of the first switching element is connected to the auxiliary power supply through the second resistor And connecting a first end of the third switching element, the first end of the second switching element receives a power state signal, the second end of the second switching element is grounded, and the third end of the second switching element is connected to the a first end of the first switching element, the first end of the fourth switching element is connected to a first system power supply, the second end of the fourth switching element is grounded, and the third end of the fourth switching element is transmitted through the third resistor Connecting the auxiliary power source, and further connecting the first end of the fifth switching element, the second end of the fifth switching element is grounded, and the third end of the fifth switching element is connected to the second system power supply through the fourth resistor, connection a first end of the sixth switching element, a second end of the third switching element and a second end of the sixth switching element are respectively connected to the auxiliary power source and the first system power supply, and the third end of the third switching element The third end of the sixth switching component is connected to the power supply end of the computer component, and the first system power is less than the voltage of the second system power supply, when the computer is switched from the software shutdown state to the normal working state of the computer and when the computer is from the standby state After waking up and entering the normal working state of the computer, the status signal of the motherboard is high, the power status signal is changed from low level to high level after a period of delay, the fourth switching element is turned on, and the fifth switching element is turned off. And the sixth switching element is turned on, the power supply end of the computer component is stably powered by the first system power; after the computer is switched from the normal working state to the computer standby state, the motherboard state signal and the power state signal are low, The second switching element is turned off, the first switching element and the third switching element are turned on, and the power supply end of the computer component is stably powered by the auxiliary power source.

該供電控制電路透過控制該第四、第五及第六開關元件是否導通 ，當該第六開關元件導通時，該電腦部件之供電端由第一系統電源穩定供電，還透過控制該第一、第二及第三開關元件是否導通，當該第三開關元件導通時，該電腦部件之供電端由輔助電源穩定供電，從而保證電腦從一狀態轉換到另一狀態後，電腦部件之供電電壓均保持穩定，而不會發生跳變。 The power supply control circuit controls whether the fourth, fifth, and sixth switching elements are turned on When the sixth switching element is turned on, the power supply end of the computer component is stably powered by the first system power supply, and further, by controlling whether the first, second, and third switching elements are turned on, when the third switching element is turned on, The power supply end of the computer component is stably powered by the auxiliary power supply, so that after the computer is switched from one state to another, the power supply voltage of the computer component is stable without jumping.

Q1-Q6‧‧‧場效應電晶體 Q1-Q6‧‧‧ Field Effect Transistor

C1、C2‧‧‧電容 C1, C2‧‧‧ capacitor

R1-R6‧‧‧電阻 R1-R6‧‧‧ resistance

圖1係本發明供電控制電路之較佳實施方式之電路圖。 1 is a circuit diagram of a preferred embodiment of a power supply control circuit of the present invention.

請參閱圖1，本發明供電控制電路之較佳實施方式包括場效應電晶體Q1-Q6、電阻R1-R6、電容C1及C2。該供電控制電路連接在一ATX電源(未示出)與一電腦部件(未示出)之間，該ATX電源包括一輔助電源5V_SB、兩系統電源5V_SYS及12V_SYS、一電源狀態訊號引腳。 Referring to FIG. 1, a preferred embodiment of the power supply control circuit of the present invention includes field effect transistors Q1-Q6, resistors R1-R6, and capacitors C1 and C2. The power control circuit is connected between an ATX power supply (not shown) and a computer component (not shown). The ATX power supply includes an auxiliary power supply 5V_SB, two system power supplies 5V_SYS and 12V_SYS, and a power status signal pin.

該場效應電晶體Q1之源極透過該電阻R5連接該輔助電源5V_SB，還與一電腦主機板上之南橋晶片(未示出)連接以接收一主機板狀態訊號GPIO_S3_EN，該場效應電晶體Q1之閘極連接該場效應電晶體Q2之汲極，還透過該電阻R1連接該輔助電源5V_SB，該場效應電晶體Q1之汲極透過該電阻R2連接該輔助電源5V_SB，還連接該場效應電晶體Q3之閘極。該場效應電晶體Q2之閘極連接該電源狀態訊號引腳以接收一電源狀態訊號PWROK_ATX，源極接地。該場效應電晶體Q4之閘極透過該電阻R6連接該系統電源5V_SYS，還透過該電容C1接地，該場效應電晶體Q4之源極接地，汲極透過該電阻R3連接該輔助電源5V_SB，還連接該場效應電晶體Q5之閘極。該場效應電晶體Q5之源極接地，該場效應電晶體Q5之汲極透過 該電阻R4連接該系統電源12V_SYS，還連接該場效應電晶體Q6之閘極。該場效應電晶體Q6及Q3之源極分別連接該系統電源5V_SYS及該輔助電源5V_SB。該兩場效應電晶體Q6及Q3之汲極連接電腦部件之供電端Us，還透過該電容C2接地。 The source of the field effect transistor Q1 is connected to the auxiliary power source 5V_SB through the resistor R5, and is also connected to a south bridge chip (not shown) on a computer motherboard to receive a motherboard status signal GPIO_S3_EN, the field effect transistor Q1. The gate is connected to the drain of the field effect transistor Q2, and is connected to the auxiliary power source 5V_SB through the resistor R1. The drain of the field effect transistor Q1 is connected to the auxiliary power source 5V_SB through the resistor R2, and is connected to the field effect electric The gate of crystal Q3. The gate of the field effect transistor Q2 is connected to the power state signal pin to receive a power state signal PWROK_ATX, and the source is grounded. The gate of the field effect transistor Q4 is connected to the system power supply 5V_SYS through the resistor R6, and is also grounded through the capacitor C1. The source of the field effect transistor Q4 is grounded, and the drain is connected to the auxiliary power supply 5V_SB through the resistor R3. The gate of the field effect transistor Q5 is connected. The source of the field effect transistor Q5 is grounded, and the gate of the field effect transistor Q5 is transmitted through The resistor R4 is connected to the system power supply 12V_SYS and is also connected to the gate of the field effect transistor Q6. The sources of the field effect transistors Q6 and Q3 are respectively connected to the system power supply 5V_SYS and the auxiliary power supply 5V_SB. The drains of the two effect transistors Q6 and Q3 are connected to the power supply terminal Us of the computer component, and are also grounded through the capacitor C2.

在本實施方式中，該等場效應電晶體Q1-Q6作為開關元件，其中該等場效應電晶體Q1、Q2、Q4、Q5及Q6均為NMOS場效應電晶體，該場效應電晶體Q3為PMOS場效應電晶體，在其他實施方式中，也可採用其他類型之開關元件，例如NPN型電晶體等，該電容C2為一電解電容，在其他實施方式中，也可為其他類型之電容，如固態電容等。該輔助電源5V_SB及系統電源5V_SYS之電壓均為5伏特，該系統電源12V_SYS之電壓為12伏特。 In the present embodiment, the field effect transistors Q1-Q6 are used as switching elements, wherein the field effect transistors Q1, Q2, Q4, Q5 and Q6 are NMOS field effect transistors, and the field effect transistor Q3 is In other embodiments, other types of switching elements, such as an NPN type transistor, may be used. The capacitor C2 is an electrolytic capacitor. In other embodiments, other types of capacitors may also be used. Such as solid capacitors. The voltage of the auxiliary power supply 5V_SB and the system power supply 5V_SYS is 5 volts, and the voltage of the system power supply 12V_SYS is 12 volts.

電腦之不同狀態可分為電腦軟體關機狀態、電腦正常工作狀態及電腦待機狀態，因此電腦之不同狀態之切換可分為：從電腦軟體關機狀態切換為電腦正常工作狀態、從電腦正常工作狀態切換為電腦待機狀態及從電腦待機狀態被喚醒而切換為電腦正常工作狀態。 The different states of the computer can be divided into the computer software shutdown state, the computer normal working state and the computer standby state. Therefore, the switching of different states of the computer can be divided into: switching from the computer software shutdown state to the normal working state of the computer, and switching from the normal working state of the computer. Switch to the normal working state of the computer for the computer standby state and wake up from the computer standby state.

主機板狀態訊號GPIO_S3_EN可在基本輸入輸出系統中設定電腦在不同狀態時之高低電平，在本實施方式中，主機板狀態訊號GPIO_S3_EN在電腦正常工作狀態及電腦軟體關機狀態為高電平，在電腦待機狀態為低電平。 The motherboard status signal GPIO_S3_EN can set the high and low level of the computer in different states in the basic input/output system. In this embodiment, the motherboard status signal GPIO_S3_EN is in the normal working state of the computer and the computer software is turned off to a high level. The computer standby state is low.

電源狀態訊號PWROK_ATX在電腦軟體關機狀態時為低電平，在電腦剛進入正常工作狀態之一段時間如100-400ms內為低電平，在此段時間後為高電平，在電腦待機狀態時為低電平。 The power status signal PWROK_ATX is low when the computer software is turned off, and is low during the period when the computer just enters the normal working state, such as 100-400ms, and is high after this period of time, when the computer is in standby state. Is low.

當電腦在軟體關機狀態時，該電源狀態訊號PWROK_ATX為低電平，該主機板狀態訊號GPIO_S3_EN為高電平，該系統電源5V_SYS及12V_SYS均不供電，該輔助電源5V_SB供電，該場效應電晶體Q2之閘極為低電平而使場效應電晶體Q2截止，該場效應電晶體Q1之閘極與源極之間之電壓差小於該場效應電晶體Q1之導通電壓而使場效應電晶體Q1截止，使得場效應電晶體Q3之源極與閘極之間之電壓差小於該場效應電晶體Q3之導通電壓而使場效應電晶體Q3截止，該場效應電晶體Q4之閘極無電壓而使場效應電晶體Q4截止，使得該場效應電晶體Q5之閘極為高電平而使場效應電晶體Q5導通，場效應電晶體Q6之閘極為低電平而使場效應電晶體Q6截止，則電腦部件之供電端Us無電壓輸出。 When the computer is in the software shutdown state, the power status signal PWROK_ATX is low, the motherboard status signal GPIO_S3_EN is high, the system power supply 5V_SYS and 12V_SYS are not powered, the auxiliary power supply 5V_SB is powered, the field effect transistor The gate of Q2 is extremely low and the field effect transistor Q2 is turned off. The voltage difference between the gate and the source of the field effect transistor Q1 is smaller than the on-voltage of the field effect transistor Q1, so that the field effect transistor Q1 The cutoff causes the voltage difference between the source and the gate of the field effect transistor Q3 to be smaller than the on-state voltage of the field effect transistor Q3 to turn off the field effect transistor Q3, and the gate of the field effect transistor Q4 has no voltage. The field effect transistor Q4 is turned off, so that the gate of the field effect transistor Q5 is at a high level to turn on the field effect transistor Q5, and the gate of the field effect transistor Q6 is at a low level to turn off the field effect transistor Q6. Then, the power supply terminal Us of the computer component has no voltage output.

當電腦從電腦軟體關機狀態切換為電腦正常工作狀態後，該電源狀態訊號PWROK_ATX經一段時間如100-400毫秒延時後由低電平變為高電平，該主機板狀態訊號GPIO_S3_EN為高電平，系統電源5V_SYS及12V_SYS也供電，當電源狀態訊號PWROK_ATX為低電平時，該場效應電晶體Q2之閘極為低電平而使場效應電晶體Q2截止，該場效應電晶體Q1之閘極與源極之間之電壓差小於該場效應電晶體Q1之導通電壓而使場效應電晶體Q1截止，場效應電晶體Q3之源極與閘極之間之電壓差小於該場效應電晶體Q3之導通電壓而使場效應電晶體Q3截止，經該電容C1延遲大約10毫秒以使系統電源5V_SYS穩定供電後，該場效應電晶體Q4之閘極為高電平而使場效應電晶體Q4導通，使場效應電晶體Q5之閘極為低電平而使場效應電晶體Q5截止，該場效應電晶體Q6之閘極與源極之間之電壓差大於該場效應電晶體Q6之導通電壓而使場效應電晶體Q6導通，從而該系統電源5V_SYS給該電腦部件之供電端Us穩定供電。當電源狀 態訊號PWROK_ATX轉換為高電平時，該場效應電晶體Q2之閘極為高電平而使場效應電晶體Q2導通，該場效應電晶體Q1之閘極與源極之間之電壓差小於該場效應電晶體Q1之導通電壓而使場效應電晶體Q1截止，使得場效應電晶體Q3之源極與閘極之間之電壓差小於該場效應電晶體Q3之導通電壓而使場效應電晶體Q3截止，該場效應電晶體Q4仍導通，使場效應電晶體Q5之閘極為低電平而使場效應電晶體Q5截止，該場效應電晶體Q6仍導通，從而該系統電源5V_SYS仍給該電腦部件之供電端Us穩定供電。因此當電腦從電腦待機狀態切換為電腦正常工作狀態後，該電源狀態訊號PWROK_ATX由低電平變為高電平時，該電腦部件之供電端Us均由系統電源5V_SYS穩定供電。 When the computer is switched from the computer software shutdown state to the normal working state of the computer, the power state signal PWROK_ATX changes from low level to high level after a period of time such as 100-400 milliseconds delay, and the motherboard state signal GPIO_S3_EN is high level. The system power supply 5V_SYS and 12V_SYS are also powered. When the power state signal PWROK_ATX is low, the gate of the field effect transistor Q2 is at a low level to turn off the field effect transistor Q2, and the gate of the field effect transistor Q1 is The voltage difference between the sources is smaller than the on-voltage of the field effect transistor Q1 to turn off the field effect transistor Q1, and the voltage difference between the source and the gate of the field effect transistor Q3 is smaller than that of the field effect transistor Q3. Turning on the voltage causes the field effect transistor Q3 to turn off. After the capacitor C1 is delayed by about 10 milliseconds to stabilize the system power supply 5V_SYS, the gate of the field effect transistor Q4 is at a high level to turn on the field effect transistor Q4. The gate of the field effect transistor Q5 is extremely low, and the field effect transistor Q5 is turned off. The voltage difference between the gate and the source of the field effect transistor Q6 is greater than that of the field effect transistor Q6. The field-effect transistor Q6 is turned on, so that the system power supply terminal of the computer to 5V_SYS member of Us stable power supply. When power supply When the state signal PWROK_ATX is converted to a high level, the gate of the field effect transistor Q2 is at a high level to turn on the field effect transistor Q2, and the voltage difference between the gate and the source of the field effect transistor Q1 is smaller than the field. The on-voltage of the effect transistor Q1 causes the field effect transistor Q1 to be turned off, so that the voltage difference between the source and the gate of the field effect transistor Q3 is smaller than the on-state voltage of the field effect transistor Q3, so that the field effect transistor Q3 By the end, the field effect transistor Q4 is still turned on, so that the gate of the field effect transistor Q5 is at a low level and the field effect transistor Q5 is turned off, and the field effect transistor Q6 is still turned on, so that the system power supply 5V_SYS is still given to the computer. The power supply terminal Us of the component is stably powered. Therefore, when the computer is switched from the standby state of the computer to the normal working state of the computer, when the power state signal PWROK_ATX changes from a low level to a high level, the power supply terminal Us of the computer component is stably powered by the system power supply 5V_SYS.

當電腦從電腦正常工作狀態切換為電腦待機狀態後，該電源狀態訊號PWROK_ATX及該主機板狀態訊號GPIO_S3_EN均為低電平，系統電源5V_SYS及12V_SYS不供電，該輔助電源5V_SB供電，該場效應電晶體Q2之閘極為低電平而使場效應電晶體Q2截止，場效應電晶體Q1之閘極為高電平而使場效應電晶體Q1導通，該場效應電晶體Q3之源極與閘極之間之電壓差大於該場效應電晶體Q3之導通電壓而使場效應電晶體Q3導通，該場效應電晶體Q4之閘極為低電平而使場效應電晶體Q4截止，使場效應電晶體Q5之閘極為高電平而使場效應電晶體Q5導通，該場效應電晶體Q6之閘極為低電平而使場效應電晶體Q6截止，從而該輔助電源5V_SB給該供電端Us穩定供電。因此電腦從電腦正常工作狀態切換為電腦待機狀態後，該電腦部件之供電端Us由輔助電源5V_SB穩定供電。 When the computer is switched from the normal working state of the computer to the standby state of the computer, the power status signal PWROK_ATX and the motherboard status signal GPIO_S3_EN are both low, the system power supply 5V_SYS and 12V_SYS are not powered, and the auxiliary power supply 5V_SB is powered, the field effect electric The gate of the crystal Q2 is extremely low, and the field effect transistor Q2 is turned off. The gate of the field effect transistor Q1 is at a high level to turn on the field effect transistor Q1. The source and gate of the field effect transistor Q3 are turned on. The voltage difference between the two is greater than the turn-on voltage of the field effect transistor Q3 to turn on the field effect transistor Q3. The gate of the field effect transistor Q4 is at a low level to turn off the field effect transistor Q4, so that the field effect transistor Q5 is turned off. The gate is extremely high and the field effect transistor Q5 is turned on. The gate of the field effect transistor Q6 is at a low level to turn off the field effect transistor Q6, so that the auxiliary power source 5V_SB supplies power to the power supply terminal Us stably. Therefore, after the computer is switched from the normal working state of the computer to the standby state of the computer, the power supply terminal Us of the computer component is stably powered by the auxiliary power source 5V_SB.

當電腦從電腦待機狀態被喚醒而進入電腦正常工作狀態後，其工 作過程與當電腦從電腦軟體關機狀態切換為電腦正常工作狀態後之工作過程相同，即當該電源狀態訊號PWROK_ATX由低電平變為高電平時，該電腦部件之供電端Us均由系統電源5V_SYS穩定供電。 When the computer is awakened from the standby state of the computer and enters the normal working state of the computer, its work The working process is the same as when the computer is switched from the computer software shutdown state to the normal working state of the computer, that is, when the power state signal PWROK_ATX changes from low level to high level, the power supply terminal Us of the computer component is powered by the system power. 5V_SYS is stable.

在其他實施方式中可以刪除產生分壓作用之電阻R5，即該場效應電晶體Q1只接收該主機板狀態訊號GPIO_S3_EN，也可以刪除產生濾波作用之電容C2，即該兩場效應電晶體Q6及Q3之汲極僅與該供電端Us相連，產生分壓作用之電阻R6及產生延遲作用之電容C1也可同時刪除，即將該場效應電晶體Q4之閘極與該系統電源5V_SYS直接相連。 In other embodiments, the resistor R5 that generates the voltage dividing function can be deleted, that is, the field effect transistor Q1 can only receive the motherboard status signal GPIO_S3_EN, and can also delete the filter capacitor C2, that is, the two field effect transistors Q6 and The drain of Q3 is only connected to the power supply terminal Us. The resistor R6 that generates the voltage divider and the capacitor C1 that generates the delay function can also be deleted at the same time, that is, the gate of the field effect transistor Q4 is directly connected to the system power supply 5V_SYS.

該供電控制電路透過系統電源5V_SYS控制該等場效應電晶體Q3、Q5及Q6是否導通，當該場效應電晶體Q6導通時，該電腦部件之供電端Us由系統電源5V_SYS穩定供電，還透過該電源狀態訊號PWROK_ATX及主機板狀態訊號GPIO_S3_EN控制該場效應電晶體Q1、Q2及Q3是否導通，當該場效應電晶體Q3導通時，該電腦部件之供電端Us由輔助電源5V_SB穩定供電，從而保證電腦從一狀態轉換到另一狀態後，電腦部件之供電電壓均保持穩定，而不會發生跳變。 The power supply control circuit controls whether the field effect transistors Q3, Q5 and Q6 are turned on through the system power supply 5V_SYS. When the field effect transistor Q6 is turned on, the power supply terminal Us of the computer component is stably powered by the system power supply 5V_SYS, and The power state signal PWROK_ATX and the motherboard status signal GPIO_S3_EN control whether the field effect transistors Q1, Q2 and Q3 are turned on. When the field effect transistor Q3 is turned on, the power supply terminal Us of the computer component is stably powered by the auxiliary power source 5V_SB, thereby ensuring After the computer transitions from one state to another, the power supply voltage of the computer components remains stable without hopping.

綜上所述，本發明符合發明專利要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施例，舉凡熟悉本案技藝之人士，在爰依本發明精神所作之等效修飾或變化，皆應涵蓋於以下之申請專利範圍內。 In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

Q1-Q6‧‧‧場效應電晶體 Q1-Q6‧‧‧ Field Effect Transistor

C1、C2‧‧‧電容 C1, C2‧‧‧ capacitor

R1-R6‧‧‧電阻 R1-R6‧‧‧ resistance

Claims (7)

一種供電控制電路，包括第一至第六開關元件、第一至第四電阻，第一至第六開關元件均包括第一至第三端，該第一開關元件之第一端透過該第一電阻連接一輔助電源，該第一開關元件之第二端與一電腦主機板之南橋晶片連接以接收一主機板狀態訊號，該第一開關元件之第三端透過該第二電阻連接該輔助電源，還連接該第三開關元件之第一端，該第二開關元件之第一端接收一電源狀態訊號，該第二開關元件之第二端接地，該第二開關元件之第三端連接該第一開關元件之第一端，該第四開關元件之第一端連接一第一系統電源，該第四開關元件之第二端接地，該第四開關元件之第三端透過該第三電阻連接該輔助電源，還連接該第五開關元件之第一端，該第五開關元件之第二端接地，該第五開關元件之第三端透過該第四電阻連接一第二系統電源，還連接該第六開關元件之第一端，該第三開關元件之第二端及該第六開關元件之第二端分別連接該輔助電源及該第一系統電源，該第三開關元件之第三端及該第六開關元件之第三端連接一電腦部件之供電端，該第一系統電源小於第二系統電源之電壓，當電腦從軟體關機狀態切換為電腦正常工作狀態後及當電腦從待機狀態被喚醒而進入電腦正常工作狀態後，該主機板狀態訊號為高電平，該電源狀態訊號經一段時間延遲後由低電平變為高電平，該第四開關元件導通、第五開關元件截止及第六開關元件導通，該電腦部件之供電端均由第一系統電源穩定供電；當電腦從正常工作狀態切換為電腦待機狀態後，該主機板狀態訊號及電源狀態訊號為低電平，該第二開關元件截止，第一開關元件及第三開關元件導通，該電腦部件之供電端由該輔助電源穩定供電。 A power supply control circuit includes first to sixth switching elements, first to fourth resistors, each of the first to sixth switching elements including first to third ends, the first end of the first switching element is transmitted through the first The second end of the first switching element is connected to the south bridge of a computer motherboard to receive a motherboard status signal, and the third end of the first switching element is connected to the auxiliary power supply through the second resistor And connecting a first end of the third switching element, the first end of the second switching element receives a power state signal, the second end of the second switching element is grounded, and the third end of the second switching element is connected to the a first end of the first switching element, the first end of the fourth switching element is connected to a first system power supply, the second end of the fourth switching element is grounded, and the third end of the fourth switching element is transmitted through the third resistor Connecting the auxiliary power source, and further connecting the first end of the fifth switching element, the second end of the fifth switching element is grounded, and the third end of the fifth switching element is connected to the second system power supply through the fourth resistor, connection a first end of the sixth switching element, a second end of the third switching element and a second end of the sixth switching element are respectively connected to the auxiliary power source and the first system power supply, and the third end of the third switching element The third end of the sixth switching component is connected to the power supply end of the computer component, and the first system power is less than the voltage of the second system power supply, when the computer is switched from the software shutdown state to the normal working state of the computer and when the computer is from the standby state After waking up and entering the normal working state of the computer, the status signal of the motherboard is high, the power status signal is changed from low level to high level after a period of delay, the fourth switching element is turned on, and the fifth switching element is turned off. And the sixth switching element is turned on, the power supply end of the computer component is stably powered by the first system power; after the computer is switched from the normal working state to the computer standby state, the motherboard state signal and the power state signal are low, The second switching element is turned off, the first switching element and the third switching element are turned on, and the power supply end of the computer component is stably powered by the auxiliary power source. 如申請專利範圍第1項所述之供電控制電路，其還包括一第五電阻，該第五電阻連接於該輔助電源和該第一開關元件之第二端之間。 The power supply control circuit of claim 1, further comprising a fifth resistor connected between the auxiliary power source and the second end of the first switching element. 如申請專利範圍第1項所述之供電控制電路，其還包括一第六電阻及一第一電容，該第六電阻連接在該第一系統電源和該第四開關元件之第一端之間，該第一電容連接在該第四開關元件之第一端及地之間。 The power supply control circuit of claim 1, further comprising a sixth resistor and a first capacitor connected between the first system power supply and the first end of the fourth switching component The first capacitor is connected between the first end of the fourth switching element and the ground. 如申請專利範圍第1項所述之供電控制電路，其還包括一第二電容，該第二電容連接在該電腦部件之供電端及地之間。 The power supply control circuit of claim 1, further comprising a second capacitor connected between the power supply end of the computer component and the ground. 如申請專利範圍第4項所述之供電控制電路，其中該第二電容為一電解電容。 The power supply control circuit of claim 4, wherein the second capacitor is an electrolytic capacitor. 如申請專利範圍第1項所述之供電控制電路，其中該第一系統電源為一5伏特之系統電源，該第二系統電源為一12伏特之系統電源，該輔助電源為一5伏特之輔助電源。 The power supply control circuit of claim 1, wherein the first system power supply is a 5 volt system power supply, and the second system power supply is a 12 volt system power supply, the auxiliary power supply is a 5 volt auxiliary. power supply. 如申請專利範圍第1項所述之供電控制電路，其中該第一、第二、第四、第五及第六開關元件均為NMOS場效應電晶體，該第三開關元件為一PMOS場效應電晶體，該第一至第六開關元件之第一、第二及第三端分別對應該場效應電晶體之閘極、源極和汲極。 The power supply control circuit of claim 1, wherein the first, second, fourth, fifth, and sixth switching elements are all NMOS field effect transistors, and the third switching element is a PMOS field effect. The first, second and third ends of the first to sixth switching elements respectively correspond to the gate, the source and the drain of the field effect transistor.
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