TWI427469B - Motherboard power control circuit - Google Patents

Motherboard power control circuit Download PDF

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TWI427469B
TWI427469B TW99122642A TW99122642A TWI427469B TW I427469 B TWI427469 B TW I427469B TW 99122642 A TW99122642 A TW 99122642A TW 99122642 A TW99122642 A TW 99122642A TW I427469 B TWI427469 B TW I427469B
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power switch
field effect
circuit
effect transistor
motherboard
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TW99122642A
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TW201202909A (en
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Chia Chun Liao
Kun Yi Jao
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Ennoconn Corp
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Description

主機板電源控制電路Motherboard power control circuit

本發明係關於一種主機板電源控制電路。The present invention relates to a motherboard power control circuit.

目前，電腦主機板上都會有一個電源開關電路，該電源開關電路連接在機箱面板上的電源開關與SIO(超級輸入輸出晶片)晶片之間，如果電腦主機板處於工作狀態時，持續按住電源開關一段時間(如四秒)，則該SIO晶片接收到該電源開關電路發送的對應電源開關訊號並根據該電源開關訊號控制電腦主機板強制關機。雖然該設定的時間可防止人為誤關閉電腦主機板，但仍無法完全杜絕此誤操作現象的發生，某些時候還是有可能會誤按下電源開關很長時間而使電腦強制關機。At present, there is a power switch circuit on the computer motherboard. The power switch circuit is connected between the power switch on the chassis panel and the SIO (Super Input Output Chip) chip. If the computer motherboard is in operation, press and hold the power. After switching for a period of time (such as four seconds), the SIO chip receives the corresponding power switch signal sent by the power switch circuit and controls the computer motherboard to forcibly shut down according to the power switch signal. Although this set time can prevent people from accidentally turning off the computer motherboard, it can not completely prevent this misoperation. In some cases, it is possible to accidentally press the power switch for a long time to force the computer to shut down.

鑒於以上內容，有必要提供一種主機板電源控制電路，透過該主機板電源控制電路可選擇性的設定該電源開關是否具有強制關機的功能。In view of the above, it is necessary to provide a motherboard power control circuit through which the power control circuit of the motherboard can selectively set whether the power switch has a forced shutdown function.

一種主機板電源控制電路，用於對一電腦主機板上的電源開關電路進行控制，該主機板電源控制電路包括一關機訊號切換電路及一關機訊號處理電路，該關機訊號切換電路與該電腦主機板上的南橋晶片及該電源開關電路相連，該關機訊號切換電路用於接收該南橋晶片發送的一切換訊號及接收該電源開關電路發送的電源開關訊號，並根據該切換訊號選擇性地將該電源開關訊號輸出至該電腦主機板上的SIO晶片或該關機訊號處理電路，該關機訊號處理電路用於接收該電源開關訊號並將該電源開關訊號進行處理後發送給該SIO晶片，以使該SIO晶片不會根據處理後的電源開關訊號進行強制關機動作。A motherboard power control circuit is configured to control a power switch circuit on a computer motherboard, the motherboard power control circuit includes a shutdown signal switching circuit and a shutdown signal processing circuit, the shutdown signal switching circuit and the computer host The south bridge chip on the board is connected to the power switch circuit, and the shutdown signal switching circuit is configured to receive a switching signal sent by the south bridge chip and receive a power switch signal sent by the power switch circuit, and selectively select the power switch signal according to the switching signal The power switch signal is output to the SIO chip on the computer motherboard or the shutdown signal processing circuit, and the shutdown signal processing circuit is configured to receive the power switch signal and process the power switch signal to send to the SIO chip, so that the The SIO chip does not perform a forced shutdown based on the processed power switch signal.

相較習知技術，該主機板電源控制電路可以透過該關機訊號切換電路選擇性地將該電源開關訊號輸出至該電腦主機板上的SIO晶片或該關機訊號處理電路，該關機訊號處理電路接收該電源開關訊號並將該電源開關訊號進行處理後發送給該SIO晶片，以使該SIO晶片不會根據處理後的電源開關訊號進行強制關機動作。如此，用戶可以根據需要選擇是否使用電源開關的強制關機功能。Compared with the prior art, the motherboard power control circuit can selectively output the power switch signal to the SIO chip or the shutdown signal processing circuit on the computer motherboard through the shutdown signal switching circuit, and the shutdown signal processing circuit receives The power switch signal is processed and sent to the SIO chip, so that the SIO chip does not perform a forced shutdown according to the processed power switch signal. In this way, the user can select whether to use the forced shutdown function of the power switch as needed.

請參考圖1，本發明主機板電源控制電路10設於一電腦主機板100上。該電腦主機板100還包括一電源開關電路20、一南橋晶片30、一SIO晶片40。該電腦主機板100還包括其他元件，如中央處理器、北橋晶片等(未示出)，由於該等元件為習知技術，故此處不加以詳細描述。Referring to FIG. 1, the motherboard power control circuit 10 of the present invention is disposed on a computer motherboard 100. The computer motherboard 100 further includes a power switch circuit 20, a south bridge wafer 30, and an SIO wafer 40. The computer motherboard 100 also includes other components, such as a central processing unit, a north bridge wafer, etc. (not shown), which are not described in detail herein because they are conventional techniques.

該主機板電源控制電路10的較佳實施方式包括一關機訊號切換電路12及一關機訊號處理電路14。該電源開關電路20用於發送一電源開關訊號，該電源開機訊號在電腦主機板的電源開關(未示出)未按下時為高電平，在該電源開關按下時為低電平。該關機訊號切換電路12與該南橋晶片30及該電源開關電路20相連，該關機訊號切換電路12用於接收該南橋晶片30發送的一切換訊號及接收該電源開關電路20發送的電源開關訊號，並根據該切換訊號選擇性地將該電源開關訊號輸出至該SIO晶片40或該關機訊號處理電路14。其中，該南橋晶片30發送的切換訊號可透過修改BIOS內的相應參數來進行設定。The preferred embodiment of the motherboard power control circuit 10 includes a shutdown signal switching circuit 12 and a shutdown signal processing circuit 14. The power switch circuit 20 is configured to send a power switch signal that is high when the power switch (not shown) of the computer motherboard is not pressed, and is low when the power switch is pressed. The shutdown signal switching circuit 12 is connected to the south bridge chip 30 and the power switch circuit 20, and the shutdown signal switching circuit 12 is configured to receive a switching signal sent by the south bridge chip 30 and receive a power switching signal sent by the power switch circuit 20. And selectively outputting the power switch signal to the SIO chip 40 or the shutdown signal processing circuit 14 according to the switching signal. The switching signal sent by the south bridge chip 30 can be set by modifying corresponding parameters in the BIOS.

當用戶還需使用電源開關來進行強制關機時，透過修改BIOS內的相應參數設定南橋晶片30發送給該關機訊號切換電路12的電源開關訊號為低電平(其他實施方式也可為高電平或其他訊號)，此時該關機訊號切換電路12將該電源開關電路20發送的電源開關訊號直接發送給該SIO晶片40，當該電源開關訊號長時間為低電平時(如四秒鐘，即持續按下電源開關四秒鐘)，該SIO晶片40將根據該低電平訊號強制關閉電腦主機板100。When the user also needs to use the power switch to perform the forced shutdown, the power switch signal sent by the south bridge chip 30 to the shutdown signal switching circuit 12 is set to a low level by modifying the corresponding parameters in the BIOS (other embodiments may also be a high level). Or the other signal), the shutdown signal switching circuit 12 sends the power switch signal sent by the power switch circuit 20 directly to the SIO chip 40, when the power switch signal is low for a long time (for example, four seconds, The SIO chip 40 will forcibly turn off the computer motherboard 100 according to the low level signal by continuously pressing the power switch for four seconds.

當用戶不需使用電源開關來進行強制關機時(即為了防止人為誤操作時)，透過修改BIOS內的相應參數設定南橋晶片30發送給該關機訊號切換電路12的電源開關訊號為高電平(其他實施方式也可為低電平或其他訊號)，此時該關機訊號切換電路12將該電源開關電路20發送的電源開關訊號發送給該關機訊號處理電路14，當該電源開關訊號長時間為低電平時(如四秒鐘，即持續按下電源開關四秒鐘)，該關機訊號處理電路14仍然發送高電平訊號給該SIO晶片40，此時電腦主機板100不會被強制關機，有效地防止了人為誤按下電源開關很長時間而使電腦主機板100強制關機。When the user does not need to use the power switch to perform the forced shutdown (ie, to prevent human error), the power switch signal sent by the south bridge chip 30 to the shutdown signal switching circuit 12 is set to a high level by modifying the corresponding parameters in the BIOS (others). The power switch signal sent by the power switch circuit 20 is sent to the power-off signal processing circuit 14 when the power switch signal is low for a long time. At the level (for example, four seconds, that is, the power switch is continuously pressed for four seconds), the shutdown signal processing circuit 14 still sends a high level signal to the SIO wafer 40, and the computer motherboard 100 is not forced to be turned off, which is effective. The ground prevents the human motherboard 100 from being forcibly shut down by pressing the power switch for a long time.

本實施方式中，該關機訊號切換電路12包括第一至第三場效應電晶體Q1-Q3、一電壓源Vcc、一電阻R1。該第一場效應電晶體Q1的源極連接至該電源開關電路20，該第一及第三場效應電晶體Q1及Q3的閘極連接至該南橋晶片30，該第一場效應電晶體Q1的汲極連接至該關機訊號處理電路14。該第二場效應電晶體Q2的源極連接至該第一場效應電晶體Q1的源極，該第二場效應電晶體Q2的閘極連接至該第三場效應電晶體Q3的汲極，該第二場效應電晶體Q2的汲極連接至該關機訊號處理電路14，該第三場效應電晶體Q3的汲極透過電阻R1連接至該電壓源Vcc，該第三場效應電晶體Q3的源極接地。In this embodiment, the shutdown signal switching circuit 12 includes first to third field effect transistors Q1-Q3, a voltage source Vcc, and a resistor R1. The source of the first field effect transistor Q1 is connected to the power switch circuit 20, and the gates of the first and third field effect transistors Q1 and Q3 are connected to the south bridge wafer 30. The first field effect transistor Q1 The drain is connected to the shutdown signal processing circuit 14. The source of the second field effect transistor Q2 is connected to the source of the first field effect transistor Q1, and the gate of the second field effect transistor Q2 is connected to the drain of the third field effect transistor Q3. The drain of the second field effect transistor Q2 is connected to the shutdown signal processing circuit 14, the drain of the third field effect transistor Q3 is connected to the voltage source Vcc through the resistor R1, and the third field effect transistor Q3 The source is grounded.

該關機訊號處理電路14包括一雙D型觸發器U1(本實施方式中型號為74LCX74)、兩電阻R2及R3、兩電容C1及C2、兩二極體組件U2及U3(本實施方式中型號分別為BAT54A及BAT54C)。該二極體組件U2包括兩二極體D1及D2，該二極體組件U3包括兩二極體D3及D4。該第一場效應電晶體Q1的汲極連接至該雙D型觸發器U1的輸入端SD1#，還透過電阻R2連接該電壓源Vcc，該雙D型觸發器U1的輸入端CD1#、CP1及接地端GND接地。該雙D型觸發器U1的輸入端D1接該電壓源Vcc，該雙D型觸發器U1的輸出端Q1連接至輸入端CP2。該雙D型觸發器U1的輸出端Q1#及Q2空接，該雙D型觸發器U1的電壓端Vcc、輸入端D2、輸入端SD#2連接該電壓源Vcc並透過電容C1接地。該雙D型觸發器U1的輸入端CD2#透過電容C2接地，還透過電阻R3連接至該雙D型觸發器U1的輸出端Q2#。該二極體D3及D4的陰極連接該雙D型觸發器U1的輸入端CD2#，陽極連接該雙D型觸發器U1的輸出端Q2#，該二極體組件U3用於防止訊號回流。該雙D型觸發器U1的輸出端Q2#還連接至該二極體D2的陰極，該第二場效應電晶體Q2的汲極連接至該二極體D1的陰極，該兩二極體D1及D2的陽極連接至該SIO晶片40。當該雙D型觸發器U1的輸入端SD1#接收到的訊號一直為高電平時，該雙D型觸發器U1的輸出端Q2#也將一直輸出高電平；當該雙D型觸發器U1的輸入端SD1#接收到的訊號從高電平變為低電平並持續一段時間(如四秒鐘，即按下了電源開關)時，該雙D型觸發器U1的輸出端Q2#僅僅從高電平變為低電平一短暫時間後又變為高電平，而該短暫時間遠小於可強制關閉電腦主機板100所需的時間。本實施方式中僅給出上述一種連接方式，也可根據需要進行相應調整，只要滿足上述關係即可，或者滿足雙D型觸發器U1的輸出端Q2#始終輸出高電平訊號。其他實施方式中，還可選擇其他類型的觸發器來代替該雙D型觸發器U1。The shutdown signal processing circuit 14 includes a dual D-type flip-flop U1 (model 74LCX74 in this embodiment), two resistors R2 and R3, two capacitors C1 and C2, two diode assemblies U2 and U3 (models in this embodiment) BAT54A and BAT54C). The diode assembly U2 includes two diodes D1 and D2, and the diode assembly U3 includes two diodes D3 and D4. The drain of the first field effect transistor Q1 is connected to the input terminal SD1# of the double D-type flip-flop U1, and is also connected to the voltage source Vcc through the resistor R2. The input terminals CD1# and CP1 of the double D-type flip-flop U1 are connected. And ground GND is grounded. The input terminal D1 of the double D-type flip-flop U1 is connected to the voltage source Vcc, and the output terminal Q1 of the double D-type flip-flop U1 is connected to the input terminal CP2. The output terminals Q1# and Q2 of the double D-type flip-flop U1 are connected to the air. The voltage terminal Vcc, the input terminal D2, and the input terminal SD#2 of the double D-type flip-flop U1 are connected to the voltage source Vcc and grounded through the capacitor C1. The input terminal CD2# of the double D-type flip-flop U1 is grounded through the capacitor C2, and is also connected to the output terminal Q2# of the double D-type flip-flop U1 through the resistor R3. The cathodes of the diodes D3 and D4 are connected to the input terminal CD2# of the double D-type flip-flop U1, and the anode is connected to the output terminal Q2# of the double D-type flip-flop U1. The diode assembly U3 is used to prevent signal backflow. The output terminal Q2# of the double D-type flip-flop U1 is also connected to the cathode of the diode D2, and the drain of the second field effect transistor Q2 is connected to the cathode of the diode D1, the two diodes D1 And the anode of D2 is connected to the SIO wafer 40. When the signal received by the input terminal SD1# of the double D-type flip-flop U1 is always at a high level, the output terminal Q2# of the double D-type flip-flop U1 will also always output a high level; when the double D-type flip-flop When the signal received by SD1# of U1 changes from high level to low level for a period of time (such as four seconds, when the power switch is pressed), the output terminal Q2# of the double D type flip-flop U1 It changes from high level to low level for a short time and then goes high again, and this short time is much smaller than the time required to forcibly turn off the computer motherboard 100. In the present embodiment, only one type of connection is given, and the corresponding adjustment may be performed as needed, as long as the above relationship is satisfied, or the output terminal Q2# of the double D-type flip-flop U1 always outputs a high level signal. In other embodiments, other types of flip-flops may be selected instead of the dual D-type flip-flop U1.

具體地，當用戶還需使用電源開關來進行強制關機時，透過修改BIOS內的相應參數設定南橋晶片30發送給該關機訊號切換電路12的電源開關訊號為低電平，此時該關機訊號切換電路12中的第一及第三場效應電晶體Q1及Q3截止而第二場效應電晶體Q2導通，故該電源開關電路20發送的電源開關訊號將經該二極體組件U2發送給該SIO晶片40，當該電源開關訊號長時間為低電平時(如四秒鐘，即持續按下電源開關四秒鐘)，該SIO晶片40將根據該低電平訊號強制關閉電腦主機板100。此外，加入該二極體組件U2是為了防止訊號回流，也可根據需要刪除，以降低成本。Specifically, when the user still needs to use the power switch to perform the forced shutdown, the power switch signal sent by the south bridge chip 30 to the shutdown signal switching circuit 12 is set to a low level by modifying the corresponding parameter in the BIOS, and the shutdown signal is switched at this time. The first and third field effect transistors Q1 and Q3 in the circuit 12 are turned off and the second field effect transistor Q2 is turned on. Therefore, the power switch signal sent by the power switch circuit 20 is sent to the SIO via the diode assembly U2. On the wafer 40, when the power switch signal is low for a long time (for example, four seconds, that is, the power switch is continuously pressed for four seconds), the SIO chip 40 will forcibly turn off the computer motherboard 100 according to the low level signal. In addition, the diode assembly U2 is added to prevent signal reflow, and can also be deleted as needed to reduce cost.

當用戶不需使用電源開關來進行強制關機時(即為了防止人為誤操作時)，透過修改BIOS內的相應參數設定南橋晶片30發送給該關機訊號切換電路12的電源開關訊號為高電平，此時該關機訊號切換電路12將該電源開關電路20發送的電源開關訊號發送給該關機訊號處理電路14，由於該關機訊號處理電路14具有之前敘述的關係，可當該電源開關訊號長時間為低電平時(如四秒鐘，即持續按下電源開關四秒鐘)，該關機訊號處理電路14仍然發送高電平訊號給該SIO晶片40(雖有短暫低電平，但由於時間不夠長仍不會強制關機)，此時電腦主機板100不會被強制關機，如此，有效地防止了人為誤按下電源開關很長時間而使電腦主機板100強制關機。When the user does not need to use the power switch to perform the forced shutdown (ie, to prevent human error), the power switch signal sent by the south bridge chip 30 to the shutdown signal switching circuit 12 is set to a high level by modifying the corresponding parameter in the BIOS. The power-off switch circuit 12 sends the power switch signal sent by the power switch circuit 20 to the power-off signal processing circuit 14. Since the power-off signal processing circuit 14 has the previously described relationship, the power switch signal can be low for a long time. At the level (eg, four seconds, that is, the power switch is continuously pressed for four seconds), the shutdown signal processing circuit 14 still sends a high level signal to the SIO wafer 40 (although there is a brief low level, but the time is not long enough The system will not be forced to shut down. At this time, the computer motherboard 100 will not be forcibly shut down. This effectively prevents the human motherboard 100 from being forcibly shut down due to human error by pressing the power switch for a long time.

綜上所述，本發明符合發明專利要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施例，舉凡熟悉本案技藝之人士，在爰依本發明精神所作之等效修飾或變化，皆應涵蓋於以下之申請專利範圍內。In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

100．．．電腦主機板100. . . Computer motherboard

10．．．主機板電源控制電路10. . . Motherboard power control circuit

12．．．關機訊號切換電路12. . . Shutdown signal switching circuit

14．．．關機訊號處理電路14. . . Shutdown signal processing circuit

20．．．電源開關電路20. . . Power switch circuit

30．．．南橋晶片30. . . South Bridge Chip

40．．．SIO晶片40. . . SIO chip

Q1-Q3．．．場效應電晶體Q1-Q3. . . Field effect transistor

Vcc．．．電壓源Vcc. . . power source

R1-R3．．．電阻R1-R3. . . resistance

U1．．．雙D型觸發器U1. . . Double D type trigger

C1、C2．．．電容C1, C2. . . capacitance

U2、U3．．．二極體組件U2, U3. . . Diode component

D1-D4．．．二極體D1-D4. . . Dipole

圖1係本發明主機板電源控制電路較佳實施方式與一電源開關電路、一南橋晶片及一SIO晶片的電路圖。1 is a circuit diagram of a preferred embodiment of a power supply control circuit for a motherboard of the present invention, a power switch circuit, a south bridge chip, and an SIO chip.

100．．．電腦主機板100. . . Computer motherboard

10．．．主機板電源控制電路10. . . Motherboard power control circuit

12．．．關機訊號切換電路12. . . Shutdown signal switching circuit

14．．．關機訊號處理電路14. . . Shutdown signal processing circuit

20．．．電源開關電路20. . . Power switch circuit

30．．．南橋晶片30. . . South Bridge Chip

40．．．SIO晶片40. . . SIO chip

Q1-Q3．．．場效應電晶體Q1-Q3. . . Field effect transistor

Vcc．．．電壓源Vcc. . . power source

R1-R3．．．電阻R1-R3. . . resistance

U1．．．雙D型觸發器U1. . . Double D type trigger

C1、C2．．．電容C1, C2. . . capacitance

U2、U3．．．二極體組件U2, U3. . . Diode component

D1-D4．．．二極體D1-D4. . . Dipole

Claims (7)

一種主機板電源控制電路，用於對一電腦主機板上的電源開關電路進行控制，該主機板電源控制電路包括一關機訊號切換電路及一關機訊號處理電路，該關機訊號切換電路與該電腦主機板上的南橋晶片及該電源開關電路相連，該關機訊號切換電路用於接收該南橋晶片發送的一切換訊號及接收該電源開關電路發送的電源開關訊號，並根據該切換訊號選擇性地將該電源開關訊號輸出至該電腦主機板上的SIO晶片或該關機訊號處理電路，該關機訊號處理電路用於接收該電源開關訊號並將該電源開關訊號進行處理後發送給該SIO晶片，以使該SIO晶片不會根據處理後的電源開關訊號進行強制關機動作。A motherboard power control circuit is configured to control a power switch circuit on a computer motherboard, the motherboard power control circuit includes a shutdown signal switching circuit and a shutdown signal processing circuit, the shutdown signal switching circuit and the computer host The south bridge chip on the board is connected to the power switch circuit, and the shutdown signal switching circuit is configured to receive a switching signal sent by the south bridge chip and receive a power switch signal sent by the power switch circuit, and selectively select the power switch signal according to the switching signal The power switch signal is output to the SIO chip on the computer motherboard or the shutdown signal processing circuit, and the shutdown signal processing circuit is configured to receive the power switch signal and process the power switch signal to send to the SIO chip, so that the The SIO chip does not perform a forced shutdown based on the processed power switch signal. 如申請專利範圍第1項所述之主機板電源控制電路，其中該南橋晶片發送的切換訊號是透過修改BIOS內的相應參數來進行設定。The motherboard power control circuit according to claim 1, wherein the switching signal sent by the south bridge chip is set by modifying corresponding parameters in the BIOS. 如申請專利範圍第1項所述之主機板電源控制電路，其中該關機訊號切換電路包括第一至第三場效應電晶體、一電壓源、一第一電阻，該第一場效應電晶體的源極連接至該電源開關電路，該第一及第三場效應電晶體的閘極連接至該南橋晶片，該第一場效應電晶體的汲極連接至該關機訊號處理電路，該第二場效應電晶體的源極連接至該第一場效應電晶體的源極，該第二場效應電晶體的閘極連接至該第三場效應電晶體的汲極，該第二場效應電晶體的汲極連接至該SIO晶片，該第三場效應電晶體的汲極透過該第一電阻連接至該電壓源，該第三場效應電晶體的源極接地。The motherboard power control circuit of claim 1, wherein the shutdown signal switching circuit comprises first to third field effect transistors, a voltage source, and a first resistor, the first field effect transistor a source is connected to the power switch circuit, a gate of the first and third field effect transistors is connected to the south bridge chip, and a drain of the first field effect transistor is connected to the shutdown signal processing circuit, the second field a source of the effect transistor is coupled to a source of the first field effect transistor, and a gate of the second field effect transistor is coupled to a drain of the third field effect transistor, the second field effect transistor A drain is connected to the SIO wafer, and a drain of the third field effect transistor is connected to the voltage source through the first resistor, and a source of the third field effect transistor is grounded. 如申請專利範圍第3項所述之主機板電源控制電路，其中該關機訊號處理電路包括一觸發器，該第一場效應電晶體的汲極連接至該觸發器的一輸入端，該觸發器的一輸出端連接至該SIO晶片。The motherboard power supply control circuit of claim 3, wherein the shutdown signal processing circuit comprises a flip-flop, the drain of the first field effect transistor being connected to an input of the flip-flop, the flip-flop An output is coupled to the SIO wafer. 如申請專利範圍第4項所述之主機板電源控制電路，其中該關機訊號處理電路還包括一二極體組件，該二極體組件包括第一及第二二極體，該第一二極體連接在該第二場效應電晶體與該SIO晶片之間，該第二二極體連接在該觸發器的輸出端與該SIO晶片之間。The motherboard power control circuit of claim 4, wherein the shutdown signal processing circuit further comprises a diode assembly, the diode assembly including first and second diodes, the first diode The body is connected between the second field effect transistor and the SIO wafer, and the second diode is connected between the output end of the flip-flop and the SIO wafer. 如申請專利範圍第4項所述之主機板電源控制電路，其中該關機訊號處理電路還包括一二極體組件、一第二電阻及一電容，該觸發器的輸出端連接至該二極體組件的陽極，該二極體組件的陰極透過該電容接地，還透過該第二電阻連接至該觸發器的輸出端。The motherboard power control circuit of claim 4, wherein the shutdown signal processing circuit further includes a diode component, a second resistor, and a capacitor, the output end of the trigger being connected to the diode The anode of the component, the cathode of the diode component is grounded through the capacitor, and is also connected to the output of the flip-flop through the second resistor. 如申請專利範圍第4項所述之主機板電源控制電路，其中該觸發器為一雙D型觸發器。The motherboard power control circuit of claim 4, wherein the trigger is a pair of D-type flip-flops.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200422952A (en) * 2003-04-18 2004-11-01 Inventec Corp Secure shutdown method of embedded computer system under operating system
JP2005062955A (en) * 2003-08-14 2005-03-10 Toshiba Corp Electronic apparatus and power source control method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200422952A (en) * 2003-04-18 2004-11-01 Inventec Corp Secure shutdown method of embedded computer system under operating system
JP2005062955A (en) * 2003-08-14 2005-03-10 Toshiba Corp Electronic apparatus and power source control method
TW200515156A (en) * 2003-08-14 2005-05-01 Toshiba Kk Electronic device and power control method

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