TW201401027A

TW201401027A - Starting control circuit

Info

Publication number: TW201401027A
Application number: TW101124098A
Authority: TW
Inventors: Guang-Dong Yuan; zhong-ping Yang; Chung-Chi Huang; Hai-Qing Zhou
Original assignee: Hon Hai Prec Ind Co Ltd
Priority date: 2012-06-29
Filing date: 2012-07-04
Publication date: 2014-01-01
Also published as: CN103513741A

Abstract

The present invention provides a starting control circuit, which is applied to a server system included a plural of servers. The starting control circuit is connected to adjacent every two servers of the server system. The starting control circuit includes a first input and a starting signal output. When a server starts working and outputs a control signal to the first input, the starting control circuit outputs a starting signal to its adjacent server after a predetermined delay time. The starting control circuit can control the plurality of servers of the server system start to work in turn, so as to reduce starting current and improve work stability of the server system.

Description

開機控制電路Boot control circuit

本發明涉及一種開機控制電路。The invention relates to a power-on control circuit.

伺服器作爲信息行業的必要設備應用越來越廣泛，伺服器的功耗一般較大，且一台機架式或刀片式伺服器由多台伺服器構成。當伺服器開啓時，多台伺服器同時開機會瞬間産生很大的衝擊電流，導致電源供電不穩定甚至電源跳閘，從而導致伺服器工作的穩定性較低。As the necessary equipment for the information industry, the server is more and more widely used. The power consumption of the server is generally large, and one rack or blade server is composed of multiple servers. When the server is turned on, multiple servers simultaneously generate a large inrush current at the same time, resulting in unstable power supply or even power supply trip, resulting in low stability of the servo operation.

有鑒於此，有必要提供一種可控制多台伺服器依次開機的開機控制電路。In view of this, it is necessary to provide a boot control circuit that can control multiple servers to be turned on in sequence.

本發明提供一種開機控制電路，應用於具有多台伺服器的伺服器系統。該開機控制電路設置於伺服器系統的每相鄰的二伺服器之間。該開機控制電路包括第一輸入端及開機訊號輸出端，該伺服器系統的一伺服器開機時，輸出一控制訊號至該開機控制電路的第一輸入端，該開機控制電路經一預定延時後經該開機訊號輸出端輸出開機訊號至該伺服器的相鄰伺服器。The invention provides a boot control circuit applied to a server system having multiple servers. The power-on control circuit is disposed between each adjacent two servers of the server system. The boot control circuit includes a first input end and a boot signal output end. When a server of the server system is powered on, a control signal is output to the first input end of the boot control circuit, and the boot control circuit passes a predetermined delay. The boot signal output terminal outputs a boot signal to an adjacent server of the server.

本發明提供一開機控制電路，設置於伺服器內部。該開機控制電路包括第一輸入端，該伺服器開機時，輸出一控制訊號至該開機控制電路的第一輸入端，該開機控制電路經一預定延時後輸出開機訊號至與該伺服器相鄰的伺服器。The invention provides a boot control circuit which is arranged inside the server. The power-on control circuit includes a first input end, and when the server is powered on, outputs a control signal to the first input end of the power-on control circuit, and the power-on control circuit outputs a power-on signal to be adjacent to the server after a predetermined delay Server.

相較於先前技術，本發明的開機控制電路可以控制伺服器系統的多台伺服器依次開機，從而可减小開機電流，提高伺服器工作的穩定性。Compared with the prior art, the power-on control circuit of the present invention can control multiple servers of the server system to be sequentially turned on, thereby reducing the startup current and improving the stability of the server operation.

請參閱圖1，圖1是本發明開機控制電路100的第一實施方式工作環境示意圖。該開機控制電路100，應用於具有多台伺服器的伺服器系統10。該伺服器系統10包括機櫃110及複數個伺服器，該複數個伺服器設置於機櫃110之中。每相鄰的二伺服器之間設置一開機控制電路100。在圖1所示的實施方式中，主要是基於該伺服器系統10包括第一伺服器120、第二伺服器130及第三伺服器140的情形對本發明進行說明。Please refer to FIG. 1. FIG. 1 is a schematic diagram showing the working environment of the first embodiment of the boot control circuit 100 of the present invention. The boot control circuit 100 is applied to a server system 10 having a plurality of servers. The server system 10 includes a cabinet 110 and a plurality of servers, and the plurality of servers are disposed in the cabinet 110. A boot control circuit 100 is disposed between each adjacent two servers. In the embodiment shown in FIG. 1, the present invention is mainly described based on the case where the server system 10 includes the first server 120, the second server 130, and the third server 140.

具體地，該伺服器系統10可以是機架式伺服器、塔式伺服器或刀片式伺服器。第一伺服器120、第二伺服器130及第三伺服器140開機時，開機訊號需由高電平訊號瞬間轉換爲低電平訊號，現有技術中由按下電源開關鍵實現。第一伺服器120、第二伺服器130及第三伺服器140待機時，主板電源提供5V的待機電源5V_SB。In particular, the server system 10 can be a rack server, a tower server or a blade server. When the first server 120, the second server 130, and the third server 140 are powered on, the power-on signal needs to be instantaneously converted into a low-level signal by the high-level signal, which is implemented by pressing the power-on key in the prior art. When the first server 120, the second server 130, and the third server 140 are in standby, the motherboard power supply provides 5V standby power 5V_SB.

在本實施方式中，該開機控制電路100設置於機櫃上。In this embodiment, the boot control circuit 100 is disposed on the cabinet.

以下僅對第一伺服器120與第二伺服器130的開機方式進行說明，其他相鄰的二伺服器的開機方式相同，在此不再贅述。該開機控制電路100包括第一輸入端101及開機訊號輸出端105。該第一輸入端與該第一伺服器120連接，該開機訊號輸出端105與該第二伺服器130連接。當該第一伺服器120開機時，該第一伺服器120輸出一控制訊號經該第一輸入端101至該開機控制電路100，該開機控制電路100經一預定延時後經該開機訊號輸出端105輸出開機訊號至該第二伺服器130，該第二伺服器130開機。In the following, only the first server 120 and the second server 130 are powered on. The other two servers are powered on in the same manner, and are not described here. The power-on control circuit 100 includes a first input terminal 101 and a power-on signal output terminal 105. The first input terminal is connected to the first server 120, and the boot signal output terminal 105 is connected to the second server 130. When the first server 120 is powered on, the first server 120 outputs a control signal to the power-on control circuit 100 via the first input terminal 101, and the power-on control circuit 100 passes through the power-on signal output terminal after a predetermined delay. 105 outputs a power-on signal to the second server 130, and the second server 130 is powered on.

本實施方式中，伺服器的電源管理執行高級配置與電源介面（Advanced Configuration and Power Interface, ACPI）的規定。ACPI規定了S0：正常工作；S1：CPU停止工作；S2：CPU關閉；S3：僅有內存工作；S4：內存信息寫入硬碟，所有部件停止工作；S5：關機六種工作狀態。當進入ACPI規定的S3狀態時，開機訊號需由低電平訊號轉換爲高電平訊號，且該伺服器輸出第一使能訊號；當進入ACPI規定的S5狀態時，開機訊號需由低電平訊號轉換爲高電平訊號，且該伺服器輸出第二使能訊號。In the present embodiment, the power management of the server performs the configuration of the Advanced Configuration and Power Interface (ACPI). ACPI specifies S0: normal operation; S1: CPU stops working; S2: CPU is turned off; S3: only memory works; S4: memory information is written to hard disk, all components stop working; S5: shutdown six working states. When entering the S3 state specified by ACPI, the power-on signal needs to be converted from a low-level signal to a high-level signal, and the server outputs a first enable signal; when entering the S5 state specified by ACPI, the power-on signal needs to be low-powered. The flat signal is converted to a high level signal, and the server outputs a second enable signal.

當第一伺服器120正常工作時，該開機訊號輸出端105持續輸出低電平訊號。而當第二伺服器130進入S3、S5狀態時，該開機訊號需轉換爲高電平訊號。爲保證該第二伺服器130可進入S3或S5狀態，該開機控制電路100還包括第一控制電路107及第二控制電路109。該第一控制電路107接收該第二伺服器130輸出的第一使能訊號並且控制該第二伺服器130正常進入S3狀態。該第二控制電路109接收該第二伺服器130輸出的第二使能訊號並控制該第二伺服器130正常進入S5狀態。When the first server 120 is working normally, the power-on signal output terminal 105 continuously outputs a low-level signal. When the second server 130 enters the S3 and S5 states, the power-on signal needs to be converted into a high-level signal. In order to ensure that the second server 130 can enter the S3 or S5 state, the boot control circuit 100 further includes a first control circuit 107 and a second control circuit 109. The first control circuit 107 receives the first enable signal output by the second server 130 and controls the second server 130 to normally enter the S3 state. The second control circuit 109 receives the second enable signal output by the second server 130 and controls the second server 130 to normally enter the S5 state.

請一併參閱圖2，圖2是圖1所示的開機控制電路100具體電路示意圖。該開機控制電路100還包括第二輸入端103、第一電阻R1、第二電阻R2、第一電容C1及第一電晶體Q1。該第一輸入端101與該第一伺服器120連接，該第一輸入端101經該第一電阻R1連接至該第一電晶體Q1的基極、該第一電晶體Q1的基極還經該第一電容C1接地。該第一電晶體Q1的射極接地，該第一電晶體Q1的集極經該第二電阻R2與該第二輸入端103連接。該第二輸入端103用於連接待機電源5V_SB。該第一電晶體Q1的集極還經該開機訊號輸出端105與該第二伺服器130連接。其中，該第一電阻R1與該第一電容C1組成一RC延時電路。在本實施方式中，該第一電晶體Q1爲NPN型電晶體。Please refer to FIG. 2 together. FIG. 2 is a schematic circuit diagram of the boot control circuit 100 shown in FIG. The power-on control circuit 100 further includes a second input terminal 103, a first resistor R1, a second resistor R2, a first capacitor C1, and a first transistor Q1. The first input terminal 101 is connected to the first server 120. The first input terminal 101 is connected to the base of the first transistor Q1 via the first resistor R1, and the base of the first transistor Q1 is also The first capacitor C1 is grounded. The emitter of the first transistor Q1 is grounded, and the collector of the first transistor Q1 is connected to the second input terminal 103 via the second resistor R2. The second input terminal 103 is used to connect the standby power source 5V_SB. The collector of the first transistor Q1 is also connected to the second server 130 via the power-on signal output terminal 105. The first resistor R1 and the first capacitor C1 form an RC delay circuit. In the present embodiment, the first transistor Q1 is an NPN type transistor.

當該第一伺服器120開機時，該第一伺服器120輸出一控制訊號至該第一輸入端101。在本實施方式中，該控制訊號爲幅值爲5V的電壓訊號。該控制訊號經該第一電阻R1與該第一電容C1組成的RC延時電路後傳送至該第一電晶體Q1的基極，該控制訊號使該第一電晶體Q1導通，此時該第一電晶體Q1的射極接地，該第一電晶體Q1的集極亦接地，該開機訊號輸出端105輸出開機訊號至該第二伺服器130，該第二伺服器130開機。When the first server 120 is powered on, the first server 120 outputs a control signal to the first input terminal 101. In this embodiment, the control signal is a voltage signal having an amplitude of 5V. The control signal is transmitted to the base of the first transistor Q1 via the RC delay circuit composed of the first resistor R1 and the first capacitor C1, and the control signal turns on the first transistor Q1. The emitter of the transistor Q1 is grounded, the collector of the first transistor Q1 is also grounded, and the power-on signal output terminal 105 outputs a power-on signal to the second server 130, and the second server 130 is powered on.

在本實施方式中，通過調整該第一電阻R1的阻值及該第一電容C1的容抗可靈活調整該第二伺服器130與該第一伺服器120之間的開機間隔時間。In this embodiment, the turn-on interval between the second server 130 and the first server 120 can be flexibly adjusted by adjusting the resistance of the first resistor R1 and the capacitive reactance of the first capacitor C1.

具體地，該第一控制電路107包括第一使能訊號輸入端S3#、第三電阻R3、第四電阻R4、第二電晶體Q2及第三電晶體Q3。該第一使能訊號輸入端S3#經該第三電阻R3與該第二電晶體Q2的基極連接，該第二電晶體Q2的射極接地，該第二電晶體Q2的集極經該第四電阻R4與該待機電源5V_SB連接，該第二電晶體Q2的集極還與該第三電晶體Q3的基極連接，該第三電晶體Q3的射極接地，該第三電晶體Q3的集極與該第一電晶體Q1的基極連接。該第二電晶體Q2、第三電晶體Q3均爲NPN型電晶體。Specifically, the first control circuit 107 includes a first enable signal input terminal S3#, a third resistor R3, a fourth resistor R4, a second transistor Q2, and a third transistor Q3. The first enable signal input terminal S3# is connected to the base of the second transistor Q2 via the third resistor R3, the emitter of the second transistor Q2 is grounded, and the collector of the second transistor Q2 passes through the The fourth resistor R4 is connected to the standby power source 5V_SB, the collector of the second transistor Q2 is also connected to the base of the third transistor Q3, the emitter of the third transistor Q3 is grounded, and the third transistor Q3 is connected. The collector is connected to the base of the first transistor Q1. The second transistor Q2 and the third transistor Q3 are both NPN type transistors.

當該第二伺服器130進入S3狀態時，該第一使能訊號輸入端S3#接收第一使能訊號，該第一使能訊號爲低電平訊號。該第一使能訊號控制該第二電晶體Q2截止，該第三電晶體Q3的基極輸入爲5V的待機電源5V_SB訊號，該第三電晶體Q3導通，該第一電晶體Q1的基極經該第三電晶體Q3接地，該第一電晶體Q1截止，該開機訊號輸出端105輸出訊號由低電平訊號轉換爲高電平訊號。從而該第二伺服器130可無影響地進入S3狀態。When the second server 130 enters the S3 state, the first enable signal input terminal S3# receives the first enable signal, and the first enable signal is a low level signal. The first enable signal controls the second transistor Q2 to be turned off. The base input of the third transistor Q3 is a 5V standby power supply 5V_SB signal, and the third transistor Q3 is turned on, and the base of the first transistor Q1 is turned on. After the third transistor Q3 is grounded, the first transistor Q1 is turned off, and the output signal of the power-on signal output terminal 105 is converted from a low level signal to a high level signal. Thereby the second server 130 can enter the S3 state without any influence.

該第二控制電路109包括第二使能訊號輸入端S5#、第五電阻R5、第六電阻R6、第四電晶體Q4及第五電晶體Q5。該第二使能訊號輸入端S5#經該第五電阻R5與該第四電晶體Q4的基極連接，該第四電晶體Q4的射極接地，該第四電晶體Q4的集極經該第六電阻R6與該待機電源5V_SB連接，該第四電晶體Q4的集極還與該第五電晶體Q5的基極連接，該第五電晶體Q5的射極接地，該第五電晶體Q5的集極與該第一電晶體Q1的基極連接。該第四電晶體Q4、第五電晶體Q5均爲NPN型電晶體。The second control circuit 109 includes a second enable signal input terminal S5#, a fifth resistor R5, a sixth resistor R6, a fourth transistor Q4, and a fifth transistor Q5. The second enable signal input terminal S5# is connected to the base of the fourth transistor Q4 via the fifth resistor R5, the emitter of the fourth transistor Q4 is grounded, and the collector of the fourth transistor Q4 passes through the The sixth resistor R6 is connected to the standby power source 5V_SB, the collector of the fourth transistor Q4 is also connected to the base of the fifth transistor Q5, the emitter of the fifth transistor Q5 is grounded, and the fifth transistor Q5 is connected. The collector is connected to the base of the first transistor Q1. The fourth transistor Q4 and the fifth transistor Q5 are both NPN type transistors.

當該第二伺服器130進入S5狀態時，該第二使能訊號輸入端S5#接收第二使能訊號，該第二使能訊號爲一低電平訊號。該第二使能訊號控制該第四電晶體Q4截止，該第五電晶體Q5的基極輸入爲5V的待機電源5V_SB訊號，該第五電晶體Q5導通，該第一電晶體Q1的基極經該第五電晶體Q5接地，該第一電晶體Q1截止，該開機訊號輸出端105輸出訊號由低電平訊號轉換爲高電平訊號。從而該第二伺服器130可無影響地進入S5狀態。When the second server 130 enters the S5 state, the second enable signal input terminal S5# receives the second enable signal, and the second enable signal is a low level signal. The second enable signal controls the fourth transistor Q4 to be turned off. The base input of the fifth transistor Q5 is a 5V standby power supply 5V_SB signal, and the fifth transistor Q5 is turned on, and the base of the first transistor Q1 is turned on. After the fifth transistor Q5 is grounded, the first transistor Q1 is turned off, and the output signal of the power-on signal output terminal 105 is converted from a low level signal to a high level signal. Thereby the second server 130 can enter the S5 state without any influence.

請參閱圖3，圖3是本發明的開機控制電路的第二實施方式工作環境示意圖。第二實施方式與第一實施方式之區別在於：該開機控制電路200設置於該第一伺服器220、第二伺服器230及第三伺服器240中。該開機控制電路200包括第一輸入端201。當該第一伺服器220開機並輸出控制訊號至該第二伺服器230的開機控制電路200的第一輸入端201，該第二伺服器230的開機控制電路200接收該控制訊號並經一預定延時後控制該第二伺服器230開機。該第一伺服器220中的開機控制電路200還接收相鄰第二伺服器230輸出的第一使能訊號、第二使能訊號，以使該第二伺服器230正常進入S3或S5狀態。該開機控制電路200的具體結構、工作方式均與第一實施方式中的開機控制電路100相同，在此不在贅述。Please refer to FIG. 3. FIG. 3 is a schematic diagram showing the working environment of the second embodiment of the boot control circuit of the present invention. The difference between the second embodiment and the first embodiment is that the power-on control circuit 200 is disposed in the first server 220, the second server 230, and the third server 240. The power-on control circuit 200 includes a first input 201. When the first server 220 is powered on and outputs a control signal to the first input terminal 201 of the power-on control circuit 200 of the second server 230, the power-on control circuit 200 of the second server 230 receives the control signal and performs a predetermined request. The second server 230 is controlled to be turned on after the delay. The power-on control circuit 200 of the first server 220 further receives the first enable signal and the second enable signal output by the adjacent second server 230, so that the second server 230 normally enters the S3 or S5 state. The specific structure and operation mode of the power-on control circuit 200 are the same as those of the power-on control circuit 100 in the first embodiment, and are not described herein.

在其他實施方式中，該開機控制電路200設置於除第一伺服器220之外的所有伺服器中，該第一伺服器220開機時輸出控制訊號至該第二伺服器230中的開機控制電路。In other embodiments, the power-on control circuit 200 is disposed in all servers except the first server 220, and the first server 220 outputs a control signal to the power-on control circuit in the second server 230 when the first server 220 is turned on. .

使用前述的開機控制電路，可以控制伺服器系統的複數個伺服器依次開機，可以有效减小開機電流，提高伺服器工作的穩定性。進一步，該第一控制電路與第二控制電路可避免一伺服器對下一伺服器進入S3、S5狀態的影響。By using the above-mentioned power-on control circuit, multiple servos of the server system can be controlled to be sequentially turned on, which can effectively reduce the starting current and improve the stability of the servo operation. Further, the first control circuit and the second control circuit can avoid the influence of a server on the state of the next server entering the S3, S5 state.

雖然本發明以優選實施例揭示如上，然其並非用以限定本發明，任何本領域技術人員，在不脫離本發明的精神和範圍內，當可做各種的變化，這些依據本發明精神所做的變化，都應包含在本發明所要求的保護範圍之內。While the invention has been described above in terms of a preferred embodiment thereof, it is not intended to limit the invention, and various modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Changes are intended to be included within the scope of the claimed invention.

10．．．伺服器系統10. . . Server system

100、200．．．開機控制電路100, 200. . . Boot control circuit

110．．．機櫃110. . . Cabinet

120、220．．．第一伺服器120, 220. . . First server

130、230．．．第二伺服器130, 230. . . Second server

140、240．．．第三伺服器140, 240. . . Third server

5V_SB．．．待機電源5V_SB. . . Standby power

101、201．．．第一輸入端101, 201. . . First input

103．．．第二輸入端103. . . Second input

105．．．開機訊號輸出端105. . . Boot signal output

107．．．第一控制電路107. . . First control circuit

109．．．第二控制電路109. . . Second control circuit

R1．．．第一電阻R1. . . First resistance

R2．．．第二電阻R2. . . Second resistance

R3．．．第三電阻R3. . . Third resistance

R4．．．第四電阻R4. . . Fourth resistor

R5．．．第五電阻R5. . . Fifth resistor

R6．．．第六電阻R6. . . Sixth resistor

Q1．．．第一電晶體Q1. . . First transistor

Q2．．．第二電晶體Q2. . . Second transistor

Q3．．．第三電晶體Q3. . . Third transistor

Q4．．．第四電晶體Q4. . . Fourth transistor

Q5．．．第五電晶體Q5. . . Fifth transistor

C1．．．第一電容C1. . . First capacitor

S3#．．．第一使能訊號輸入端S3#. . . First enable signal input

S5#．．．第二使能訊號輸入端S5#. . . Second enable signal input

圖1是本發明開機控制電路第一實施方式工作環境示意圖。1 is a schematic diagram of a working environment of a first embodiment of a boot control circuit of the present invention.

圖2是圖1所示的開機控制電路具體電路示意圖。2 is a schematic circuit diagram of the power-on control circuit shown in FIG. 1.

圖3是本發明開機控制電路第二實施方式工作爲環境示意圖。FIG. 3 is a schematic diagram showing the operation of the second embodiment of the power-on control circuit of the present invention.

10．．．伺服器系統10. . . Server system

100．．．開機控制電路100. . . Boot control circuit

110．．．機櫃110. . . Cabinet

120．．．第一伺服器120. . . First server

130．．．第二伺服器130. . . Second server

140．．．第三伺服器140. . . Third server

101．．．第一輸入端101. . . First input

105．．．開機訊號輸出端105. . . Boot signal output

107．．．第一控制電路107. . . First control circuit

109．．．第二控制電路109. . . Second control circuit

Claims

一種開機控制電路，應用於具有多台伺服器的伺服器系統；該開機控制電路設置於伺服器系統的每相鄰的二伺服器之間；該開機控制電路包括第一輸入端及開機訊號輸出端，該伺服器系統的一伺服器開機時，輸出一控制訊號至該開機控制電路的第一輸入端，該開機控制電路經一預定延時後經該開機訊號輸出端輸出開機訊號至該伺服器的相鄰伺服器。A boot control circuit is applied to a server system having a plurality of servers; the boot control circuit is disposed between each adjacent two servers of the server system; the boot control circuit includes a first input end and a boot signal output End, when a server of the server system is powered on, outputting a control signal to the first input end of the boot control circuit, and the boot control circuit outputs a boot signal to the server via the boot signal output after a predetermined delay Adjacent server.

如申請專利範圍第1項所述之開機控制電路，其中，該伺服器系統還包括機櫃，該開機控制電路設置於該機櫃上。The power-on control circuit of claim 1, wherein the server system further comprises a cabinet, and the power-on control circuit is disposed on the cabinet.

如申請專利範圍第2項所述之開機控制電路，其中，該開機控制電路還包括第二輸入端、第一電阻、第二電阻、第一電容及第一電晶體；該第一輸入端與一伺服器連接，該第一輸入端經該第一電阻連接至該第一電晶體的基極、該第一電晶體的基極還經該第一電容接地；該第一電晶體的射極接地，該第一電晶體的集極經該第二電阻與該第二輸入端連接；該第二輸入端連接待機電源；該第一電晶體的集極還經該開機訊號輸出端與下一伺服器連接。The boot control circuit of claim 2, wherein the boot control circuit further includes a second input terminal, a first resistor, a second resistor, a first capacitor, and a first transistor; the first input terminal a server is connected, the first input is connected to the base of the first transistor via the first resistor, and the base of the first transistor is further grounded via the first capacitor; an emitter of the first transistor Grounding, the collector of the first transistor is connected to the second input terminal via the second resistor; the second input terminal is connected to the standby power source; the collector of the first transistor is further connected to the power-on signal output terminal and the next Server connection.

如申請專利範圍第3項所述之開機控制電路，其中，通過調整該第一電阻的阻值及該第一電容的容抗調整相鄰伺服器之間的開機間隔時間。The boot control circuit of claim 3, wherein the turn-on interval between adjacent servers is adjusted by adjusting a resistance of the first resistor and a capacitive reactance of the first capacitor.

如申請專利範圍第4項所述之開機控制電路，其中，該開機控制電路還包括第一控制電路，伺服器進入S3狀態時輸出第一使能訊號，該第一控制電路用於接收第一使能訊號並使與一伺服器相鄰的伺服器正常進入S3狀態。The power-on control circuit of claim 4, wherein the power-on control circuit further includes a first control circuit, and the server outputs a first enable signal when the server enters the S3 state, and the first control circuit is configured to receive the first Enable the signal and make the server adjacent to a server enter the S3 state normally.

如申請專利範圍第5項所述之開機控制電路，其中，該第一控制電路包括第一使能訊號輸入端、第三電阻、第四電阻、第二電晶體及第三電晶體；該第一使能訊號輸入端經該第三電阻與該第二電晶體的基極連接，該第二電晶體的射極接地，該第二電晶體的集極經該第四電阻與該待機電源連接，該第二電晶體集極還與該第三電晶體的基極連接，該第三電晶體的射極接地，該第三電晶體的集極與該第一電晶體的基極連接。The power-on control circuit of claim 5, wherein the first control circuit comprises a first enable signal input terminal, a third resistor, a fourth resistor, a second transistor, and a third transistor; An enable signal input terminal is connected to a base of the second transistor via the third resistor, an emitter of the second transistor is grounded, and a collector of the second transistor is connected to the standby power source via the fourth resistor The second transistor collector is further connected to the base of the third transistor, the emitter of the third transistor is grounded, and the collector of the third transistor is connected to the base of the first transistor.

如申請專利範圍第3項所述之開機控制電路，其中，該開機控制電路還包括第二控制電路，伺服器進入S5狀態時，輸出第二使能訊號，該第二控制電路用於接收第二使能訊號並控制與一伺服器相鄰的伺服器正常進入S5狀態。The power-on control circuit of claim 3, wherein the power-on control circuit further includes a second control circuit, and when the server enters the S5 state, the second enable signal is output, and the second control circuit is configured to receive the second The second enable signal and control the server adjacent to a server to enter the S5 state normally.

如申請專利範圍第7項所述之開機控制電路，其中，該第二控制電路包括第二使能訊號輸入端、第五電阻、第六電阻、第四電晶體及第五電晶體；該第二使能訊號輸入端經該第五電阻與該第四電晶體的基極連接，該第四電晶體的射極接地，該第四電晶體的集極經該第六電阻與該待機電源連接，該第四電晶體的集極還與該第五電晶體的基極連接，該第五電晶體的射極接地，該第五電晶體的集極與該第一電晶體的基極連接。The power-on control circuit of claim 7, wherein the second control circuit includes a second enable signal input terminal, a fifth resistor, a sixth resistor, a fourth transistor, and a fifth transistor; The second enable signal input terminal is connected to the base of the fourth transistor via the fifth resistor, the emitter of the fourth transistor is grounded, and the collector of the fourth transistor is connected to the standby power source via the sixth resistor The collector of the fourth transistor is further connected to the base of the fifth transistor, the emitter of the fifth transistor is grounded, and the collector of the fifth transistor is connected to the base of the first transistor.

一種開機控制電路，設置於伺服器內部；該開機控制電路包括第一輸入端，該伺服器開機時，輸出一控制訊號至該開機控制電路的第一輸入端，該開機控制電路經一預定延時後輸出開機訊號至與該伺服器相鄰的伺服器。A boot control circuit is disposed inside the server; the boot control circuit includes a first input end, and when the server is powered on, outputs a control signal to the first input end of the boot control circuit, and the boot control circuit passes a predetermined delay After that, the boot signal is output to the server adjacent to the server.

一種開機控制電路，應用於多台伺服器組成的伺服器系統，該開機控制電路設置於除第一伺服器之外的其他伺服器之中；該第一伺服器開機時輸出控制訊號至與該第一伺服器相鄰的伺服器中的開機控制電路，該開機控制電路包括第一輸入端，該第一輸入端接收該控制訊號，該開機控制電路經一預定延時後輸出開機訊號使該與第一伺服器相鄰的伺服器開機。A boot control circuit is applied to a server system composed of a plurality of servers, the boot control circuit is disposed in a server other than the first server; and the first server outputs a control signal to the a power-on control circuit in the server adjacent to the first server, the power-on control circuit includes a first input end, the first input end receives the control signal, and the power-on control circuit outputs a power-on signal after a predetermined delay to make the The server adjacent to the first server is powered on.