TWI440153B - Package substrate and fabrication method thereof - Google Patents

Package substrate and fabrication method thereof Download PDF

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Publication number
TWI440153B
TWI440153B TW097150014A TW97150014A TWI440153B TW I440153 B TWI440153 B TW I440153B TW 097150014 A TW097150014 A TW 097150014A TW 97150014 A TW97150014 A TW 97150014A TW I440153 B TWI440153 B TW I440153B
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layer
circuit
package substrate
dielectric layer
layers
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TW097150014A
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Chinese (zh)
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TW201025533A (en
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Pao Hung Chou
Chih Hao Hsu
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Unimicron Technology Crop
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Publication of TWI440153B publication Critical patent/TWI440153B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

封裝基板及其製法Package substrate and its preparation method

本發明係有關於一種封裝基板及其製法，尤指一種能降低厚度之封裝基板及其製法。The invention relates to a package substrate and a preparation method thereof, in particular to a package substrate capable of reducing thickness and a preparation method thereof.

為滿足半導體封裝件高積集度及微型化的封裝需求，以供更多主、被動元件及線路載接，半導體封裝基板係以多層板(Multi－layer board)為主流，俾在有限的空間下運用層間連接技術(Interlayer connection)以擴大封裝基板上可供利用的線路佈局面積，藉此配合高線路密度之積體電路需要，降低封裝基板的厚度，以在相同基板單位面積下容納更多數量的線路及電子元件。In order to meet the high integration of semiconductor packages and miniaturized packaging requirements for more active and passive components and line carriers, semiconductor package substrates are dominated by multi-layer boards and are limited in space. Under the use of Interlayer connection technology to expand the layout area available on the package substrate, thereby matching the high line density of integrated circuit needs, reducing the thickness of the package substrate to accommodate more in the same substrate unit area The number of lines and electronic components.

請參閱第1A至1C圖，係為習知朝上空腔區(cavity－up)之打線式(wire bonding)封裝基板之製法；如第1A圖所示，提供第一、第二及第三核心板10a,10b,10c，該第一核心板10a具有第一及第二線路層11a,11b，該第二核心板10b具有第三及第四線路層11c,11d，該第三核心板10c具有第五及第六線路層11e,11f；且於該第一核心板10a及第二線路層11b上形成有第一介電層12a，且於該第二核心板10b及第四線路層11d上形成有第二介電層12b。藉由鑽孔機貫穿該第一核心板10a及第一介電層12a以形成第一開口13a，再藉由鑽孔機貫穿該第二核心板10b及第二介電層12b以形成第二開口13b；又於該第三核心板10c上設有晶片置放墊 14。Please refer to FIGS. 1A to 1C for the fabrication of a conventional wire bonding package substrate; as shown in FIG. 1A, first, second and third core plates 10a are provided. , 10b, 10c, the first core board 10a has first and second circuit layers 11a, 11b, the second core board 10b has third and fourth circuit layers 11c, 11d, and the third core board 10c has a fifth And a sixth circuit layer 11e, 11f; and a first dielectric layer 12a formed on the first core board 10a and the second circuit layer 11b, and formed on the second core board 10b and the fourth circuit layer 11d The second dielectric layer 12b. A first opening 13a is formed through the first core board 10a and the first dielectric layer 12a by a drill, and then penetrates the second core board 10b and the second dielectric layer 12b by a drill to form a second Opening 13b; further providing a wafer placement pad on the third core board 10c 14.

如第1B圖所示，將該第一介電層12a壓合於該第二核心板10b及第三線路層11c上，且將該第二介電層12b壓合於該第三核心板10c及第五線路層11e上，令該第一、第二及第三核心板10a,10b,10c結合成基板本體，且該第一開口13a對應連通該第二開口13b以形成凹槽13，而該凹槽13顯露該第三線路層11c及晶片置放墊14。再形成貫穿該基板本體之導電通孔100，以電性連接該第一、第二、第三、第四、第五及第六線路層11a,11b,11c,11d,11e,11f，俾形成封裝基板；該第一線路層11a具有第一打線墊110a，且顯露之第三線路層11c作為第二打線墊110b，而該第六線路層11f具有植球墊111。As shown in FIG. 1B, the first dielectric layer 12a is pressed onto the second core board 10b and the third circuit layer 11c, and the second dielectric layer 12b is pressed against the third core board 10c. And the fifth circuit layer 11e, the first, second and third core plates 10a, 10b, 10c are combined into a substrate body, and the first opening 13a correspondingly communicates with the second opening 13b to form the recess 13 The recess 13 exposes the third wiring layer 11c and the wafer placement pad 14. Forming a conductive via 100 extending through the substrate body to electrically connect the first, second, third, fourth, fifth, and sixth circuit layers 11a, 11b, 11c, 11d, 11e, 11f, and the like The first circuit layer 11a has a first wire pad 110a, and the exposed third circuit layer 11c serves as a second wire pad 110b, and the sixth circuit layer 11f has a ball pad 111.

如第1C圖所示，分別於該第一核心板10a、第一線路層11a、第三核心板10c及第六線路層11f上形成防焊層15，且該防焊層15形成有開孔150以露出各該植球墊111及第一打線墊110a。提供一具有相對之作用面16a及非作用面16b之半導體晶片16，且以該非作用面16b將該半導體晶片16結合於該晶片置放墊14上，又該半導體晶片16之作用面16a以導線17電性連接至各該第一及第二打線墊110a,110b。於該防焊層15上及該凹槽13中形成封裝材18，以包覆該半導體晶片16及導線17，且於各該植球墊111上形成焊料球19，以供電性連接至其他電子裝置。As shown in FIG. 1C, a solder resist layer 15 is formed on the first core board 10a, the first circuit layer 11a, the third core board 10c, and the sixth circuit layer 11f, respectively, and the solder resist layer 15 is formed with an opening. 150 to expose each of the ball pad 111 and the first wire pad 110a. A semiconductor wafer 16 having an opposite active surface 16a and a non-active surface 16b is provided, and the semiconductor wafer 16 is bonded to the wafer placement pad 14 by the non-active surface 16b, and the active surface 16a of the semiconductor wafer 16 is wired. 17 is electrically connected to each of the first and second wire pads 110a, 110b. A package 18 is formed on the solder resist layer 15 and the recess 13 to cover the semiconductor wafer 16 and the wires 17, and solder balls 19 are formed on each of the ball pads 111 to be electrically connected to other electrons. Device.

惟，習知封裝基板之製法中，需先以鑽孔機分別於該第一核心板10a及第一介電層12a上形成第一開口13a、以及於該第二核心板10b與第二介電層12b上形成第二開口13b，再將該第一、第二及第三核心板10a,10b,10c與第一及第二介電層12a,12b壓合而成該基板本體；故，於各該核心板上製作線路層及規劃該晶片置放墊14時，需相互考量配線位置及配合該凹槽13位置，使製程複雜且繁瑣，俾各該核心板分開製作線路層，不僅使用較多物料而提高成本，且難以達到高佈線密度之需求。However, in the manufacturing method of the conventional package substrate, the first opening 13a is formed on the first core board 10a and the first dielectric layer 12a by the drilling machine, and the second core board 10b and the second medium are respectively formed by the drilling machine. a second opening 13b is formed on the electrical layer 12b, and the first, second and third core plates 10a, 10b, 10c are pressed together with the first and second dielectric layers 12a, 12b to form the substrate body; When the circuit layer is formed on each of the core boards and the wafer placement pad 14 is planned, the wiring position and the position of the groove 13 need to be considered for each other, so that the process is complicated and cumbersome, and the core boards are separately fabricated to form a circuit layer, which is not only used. More materials increase costs and it is difficult to achieve high wiring density requirements.

再者，藉由習知各該核心板分開製作之製法，因使用多層之核心板及介電層，如圖中之三層核心板配合兩層介電層，以致於整體結構之厚度大幅提升，俾不符合低厚度之需求，而無法達到產品輕薄短小的目標。Furthermore, by the conventional method of separately manufacturing the core board, the multi-layer core board and the dielectric layer are used, and the three-layer core board in the figure is combined with two dielectric layers, so that the thickness of the overall structure is greatly improved. , 俾 does not meet the needs of low thickness, and can not achieve the goal of light and thin products.

因此，鑒於上述之問題，如何避免習知封裝基板及其製法之種種問題，實已成為目前亟欲解決之課題。Therefore, in view of the above problems, how to avoid various problems of the conventional package substrate and its manufacturing method has become a problem to be solved at present.

鑒於上述習知技術之缺失，本發明之主要目的係提供一種能降低厚度之封裝基板及其製法。In view of the above-mentioned deficiencies of the prior art, the main object of the present invention is to provide a package substrate capable of reducing the thickness and a method of manufacturing the same.

為達上述及其他目的，本發明揭露一種封裝基板，係包括：核心板，係具有相對之第一表面及第二表面，且該第一及第二表面上分別設有第一線路層及第二線路層，該第二線路層具有一晶片置放墊，且該核心板具有一貫穿該第一及第二表面之第一開口以顯露該晶片置放墊，且該第一線路層具有圍繞該第一開口周緣之複數第一打線墊；第 一介電層，係設於該核心板之第一表面及該第一線路層上，並具有一對應且大於該第一開口之第二開口，以顯露該第一開口及該些第一打線墊；第二介電層，係設於該核心板之第二表面及該第二線路層上，且該第一開口顯露部份之第二介電層；第三線路層，係設於該第一介電層上，且電性連接該第一線路層，該第三線路層並具有圍繞該第二開口周緣之複數第二打線墊；以及第四線路層，係設於該第二介電層上，且電性連接該第二線路層。To achieve the above and other objects, the present invention discloses a package substrate, comprising: a core plate having opposite first and second surfaces, and the first and second surfaces are respectively provided with a first circuit layer and a first a second circuit layer having a wafer placement pad, the core plate having a first opening extending through the first and second surfaces to expose the wafer placement pad, and the first circuit layer has a surrounding a plurality of first wire mats on the periphery of the first opening; a dielectric layer is disposed on the first surface of the core board and the first circuit layer, and has a second opening corresponding to the first opening to expose the first opening and the first lines a second dielectric layer is disposed on the second surface of the core board and the second circuit layer, and the first opening exposes a portion of the second dielectric layer; the third circuit layer is disposed on the second dielectric layer The first dielectric layer is electrically connected to the first circuit layer, the third circuit layer has a plurality of second bonding pads surrounding the circumference of the second opening; and a fourth circuit layer is disposed on the second dielectric layer The electrical layer is electrically connected to the second circuit layer.

前述之封裝基板中，該核心板可設有電性連接該第一及第二線路層之複數導電通孔；該封裝基板亦可具有貫穿該第一介電層、核心板及第二介電層之導電通孔，以電性連接該第一、第二、第三及第四線路層。In the foregoing package substrate, the core board may be provided with a plurality of conductive vias electrically connected to the first and second circuit layers; the package substrate may also have a first dielectric layer, a core board and a second dielectric The conductive vias of the layer are electrically connected to the first, second, third and fourth circuit layers.

前述之封裝基板復可包括第一防焊層，係設於該第一介電層及第三線路層上，且具有開口以外露各該第二打線墊、第一及第二開口。The package substrate may include a first solder resist layer disposed on the first dielectric layer and the third circuit layer, and having openings to expose the second wire pads, the first and second openings.

前述之封裝基板中，該第四線路層可具有複數電性接觸墊，令該封裝基板包括設於該第二介電層及第四線路層上之第二防焊層，係具有複數開孔以外露各該電性接觸墊，俾該些電性接觸墊上可設有表面處理層。In the above package substrate, the fourth circuit layer may have a plurality of electrical contact pads, and the package substrate includes a second solder resist layer disposed on the second dielectric layer and the fourth circuit layer, and has a plurality of openings Each of the electrical contact pads is exposed, and a surface treatment layer may be disposed on the electrical contact pads.

前述之封裝基板中，該第三及第四線路層係可具有設於該第一及第二介電層中且電性連接該第一及第二線路層之導電盲孔；又該第四線路層係可具有設於該第二介電層中且對應連接至該晶片置放墊之散熱盲孔。In the above package substrate, the third and fourth circuit layers may have conductive blind holes disposed in the first and second dielectric layers and electrically connected to the first and second circuit layers; The circuit layer may have a heat dissipation blind hole disposed in the second dielectric layer and correspondingly connected to the wafer placement pad.

此外，前述之封裝基板中，該第二線路層復可具有複 數第三打線墊，且該第一及第二開口顯露該些第三打線墊；較佳地，該些電性接觸墊、第一、第二及第三打線墊上可設有表面處理層。In addition, in the foregoing package substrate, the second circuit layer has a complex The third wire bonding pad is provided, and the first and second openings expose the third wire bonding pads; preferably, the electrical contact pads, the first, second and third wire bonding pads may be provided with a surface treatment layer.

本發明復提供一種封裝基板之製法，係包括：提供一具有相對之第一及第二表面之核心板，該核心板之第一及第二表面上分別設有第一及第二初始金屬層；形成貫穿該核心板、第一及第二初始金屬層之複數通孔；於各該通孔之孔壁、該第一及第二初始金屬層上形成導電晶種層；於該第一及第二初始金屬層上之導電晶種層上形成阻層，且於各該阻層中形成複數圖案化之開口區，以顯露各該通孔、該第一及第二初始金屬層上之部份導電晶種層；於各該開口區中之第一及第二初始金屬層之導電晶種層上分別電鍍形成第一及第二金屬層，並於各該通孔中形成導電通孔，且該第一金屬層具有第一打線區，而該第二金屬層具有晶片置放區；移除該阻層；蝕刻該第一打線區外之第一金屬層及第一初始金屬層以形成第一線路層，並蝕刻該晶片置放區外之第二金屬層及第二初始金屬層以形成第二線路層，且各該導電通孔電性連接該第一及第二線路層；於該核心板之第一表面及第一金屬層上形成第一介電層，且該第一介電層具有一對應該晶片置放區及第一打線區之空白區，且於該核心板之第二表面及第二金屬層上形成第二介電層；於該第一及第二介電層上形成及第四第三線路層，且該第四線路層具有複數電性接觸墊，且該第一介電層之空白區未形成該第三線路層，又該第三線路層 具有圍繞該空白區周緣之第二打線區，該第二打線區具有複數第二打線墊；於該空白區形成一貫穿該核心板之第一及第二表面之第一開口、及貫穿該第一介電層之第二開口，且該第二開口對應且大於該第一開口，以顯露該晶片置放區及該第一打線區；以及蝕刻該第一打線區之部分第一金屬層及部分第一初始金屬層，以形成複數第一打線墊，且蝕刻移除對應該晶片置放區之第二初始金屬層及其覆蓋之導電晶種層，以形成晶片置放墊。The invention provides a method for manufacturing a package substrate, comprising: providing a core plate having opposite first and second surfaces, wherein the first and second surfaces of the core plate are respectively provided with first and second initial metal layers Forming a plurality of through holes penetrating the core plate, the first and second initial metal layers; forming a conductive seed layer on the hole walls of the through holes, the first and second initial metal layers; Forming a resist layer on the conductive seed layer on the second initial metal layer, and forming a plurality of patterned open areas in each of the resist layers to expose each of the through holes, the first and second initial metal layers a conductive seed layer; a first and a second metal layer are respectively plated on the conductive seed layers of the first and second initial metal layers in each of the open regions, and conductive vias are formed in each of the through holes, And the first metal layer has a first bonding region, and the second metal layer has a wafer placement region; removing the resist layer; etching the first metal layer outside the first bonding region and the first initial metal layer to form a first circuit layer and etching a second metal layer outside the wafer placement area a second initial metal layer to form a second circuit layer, wherein each of the conductive vias is electrically connected to the first and second circuit layers; and a first dielectric layer is formed on the first surface of the core plate and the first metal layer And the first dielectric layer has a pair of blank areas corresponding to the wafer placement area and the first bonding area, and forming a second dielectric layer on the second surface of the core board and the second metal layer; Forming a fourth and third circuit layers on the first and second dielectric layers, and the fourth circuit layer has a plurality of electrical contact pads, and the blank region of the first dielectric layer does not form the third circuit layer, and Third circuit layer Having a second wire-bonding zone surrounding the periphery of the blank area, the second wire-bonding zone has a plurality of second wire-bonding pads; forming a first opening extending through the first and second surfaces of the core plate in the blank area, and penetrating the first opening a second opening of the dielectric layer, and the second opening corresponds to and larger than the first opening to expose the wafer placement area and the first bonding area; and etching a portion of the first metal layer of the first bonding area and Part of the first initial metal layer to form a plurality of first wire pads, and etching removes the second initial metal layer corresponding to the wafer placement region and the conductive seed layer covered thereby to form a wafer placement pad.

前述之製法中，該第一及第二開口係可以雷射燒融貫穿該空白區對應之第一介電層、核心板之第一及第二表面而形成。In the above method, the first and second openings may be formed by laser firing through the first dielectric layer and the first and second surfaces of the core plate corresponding to the blank region.

前述之製法復可包括移除該阻層之後，於該第一打線區及晶片置放區形成保護層，並於形成該第一及第二線路層後，再移除該保護層。The foregoing method may further include forming a protective layer on the first bonding region and the wafer placement region after removing the resist layer, and removing the protective layer after forming the first and second wiring layers.

前述之製法復可包括於形成該第三及第四線路層之後，於該第一介電層及第三線路層上形成第一防焊層，且該第一防焊層形成有開口，以顯露各該第二打線墊及該空白區，並於該第二介電層及第四線路層上形成第二防焊層，而該第二防焊層形成有複數開孔，以對應顯露各該電性接觸墊。The foregoing method may include forming a first solder resist layer on the first dielectric layer and the third wiring layer after forming the third and fourth circuit layers, and the first solder resist layer is formed with an opening to Forming each of the second bonding pads and the blank area, and forming a second solder resist layer on the second dielectric layer and the fourth wiring layer, and the second solder resist layer is formed with a plurality of openings to correspondingly expose each The electrical contact pad.

前述之製法復可包括於各該電性接觸墊及第二打線墊上形成保護層，並於形成各該第一打線墊及該晶片置放墊後，再移除該保護層。The foregoing method may include forming a protective layer on each of the electrical contact pads and the second bonding pads, and removing the protective layer after forming the first bonding pads and the wafer placing pads.

前述之製法中，該第二金屬層復可具有圍繞該晶片置 放區周緣之第三打線區，而該第一打線區係可對應且大於該第三打線區，並於形成該晶片置放墊之同時，並於該第三打線區形成複數第三打線墊。前述之製法復可包括於各該電性接觸墊、第一、第二及第三打線墊上形成表面處理層。In the foregoing method, the second metal layer may have a surrounding a third hitting area on the periphery of the discharge zone, wherein the first hitting zone is corresponding to and larger than the third hitting zone, and at the same time as forming the wafer placing pad, forming a plurality of third wire mats in the third hitting zone . The foregoing method may include forming a surface treatment layer on each of the electrical contact pads, the first, second and third wire pads.

前述之製法中，該第三及第四線路層復可具有複數位於該第一及第二介電層中之導電盲孔，以分別電性連接該第一及第二線路層。又該第四線路層復可具有至少一設於該第二介電層中且對應連接該晶片置放墊之散熱盲孔。In the above method, the third and fourth circuit layers may have a plurality of conductive blind vias in the first and second dielectric layers to electrically connect the first and second circuit layers, respectively. The fourth circuit layer further has at least one heat dissipation blind hole disposed in the second dielectric layer and correspondingly connected to the wafer placement pad.

前述之製法復可包括形成貫穿該第一介電層、核心板及第二介電層之導電通孔，以電性連接該第一、第二、第三及第四線路層。The foregoing method may include forming conductive vias penetrating through the first dielectric layer, the core plate and the second dielectric layer to electrically connect the first, second, third and fourth circuit layers.

由上可知，本發明封裝基板及其製法，係藉由雷射燒融單一核心板及第一介電層以形成連通之第一及第二開口，相較於習知技術之多層核心板及介電層，本發明因只使用單一核心板配合介電層，不僅製程簡單且快速，且可達到降低整體封裝結構厚度之目的。As can be seen from the above, the package substrate of the present invention and the method for manufacturing the same are to fuse a single core plate and a first dielectric layer by laser to form a first and second openings, which are compared with the conventional core board and the prior art. The dielectric layer, the present invention uses only a single core plate to match the dielectric layer, not only the process is simple and fast, but also can achieve the purpose of reducing the thickness of the overall package structure.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

請參閱第2A圖至第2N圖，係提供本發明之封裝基板之製法。Referring to FIGS. 2A to 2N, a method of manufacturing the package substrate of the present invention is provided.

如第2A圖所示，提供一具有相對之第一及第二表面 20a,20b之核心板20，於該核心板20之第一及第二表面20a,20b上分別形成第一及第二初始金屬層21a,21b，且於該核心板20中形成貫穿之複數通孔200；再於各該通孔200之孔壁、第一及第二初始金屬層21a,21b上形成導電晶種層(seed layer)210。所述之第一及第二初始金屬層21a,21b係為銅箔。Providing an opposite first and second surface as shown in FIG. 2A The core board 20 of 20a, 20b forms first and second initial metal layers 21a, 21b on the first and second surfaces 20a, 20b of the core board 20, respectively, and forms a plurality of through-throughs in the core board 20. The hole 200; and a conductive seed layer 210 is formed on the hole wall of each of the through holes 200 and the first and second initial metal layers 21a, 21b. The first and second initial metal layers 21a, 21b are copper foil.

接著，於該第一及第二初始金屬層21a,21b上之導電晶種層210上形成阻層22，且於該阻層22中形成複數圖案化之開口區220，以顯露各該通孔200、該第一及第二初始金屬層21a,21b上之部份導電晶種層210。Then, a resist layer 22 is formed on the conductive seed layer 210 on the first and second initial metal layers 21a, 21b, and a plurality of patterned open regions 220 are formed in the resist layer 22 to expose the via holes. 200. A portion of the conductive seed layer 210 on the first and second initial metal layers 21a, 21b.

如第2B圖所示，藉由該導電晶種層210，於各該開口區220中電鍍金屬，以於該第一及第二初始金屬層21a,21b上分別形成第一及第二金屬層23a,23b，且於各該通孔200中形成導電通孔200’。As shown in FIG. 2B, the conductive seed layer 210 is plated with metal in each of the open regions 220 to form first and second metal layers on the first and second initial metal layers 21a, 21b, respectively. 23a, 23b, and a conductive via 200' is formed in each of the via holes 200.

如第2C圖所示，移除該阻層22，以露出該第一及第二金屬層23a,23b；其中，該圖案化之第一金屬層23a具有第一打線區A，而該第二金屬層23b具有晶片置放區W及圍繞該晶片置放區W周緣之第三打線區C，且該第一打線區A所圍繞之輪廓係對應且大於該第三打線區C所圍繞之輪廓。再於該第一打線區A、晶片置放區W及第三打線區C上形成保護層24。As shown in FIG. 2C, the resist layer 22 is removed to expose the first and second metal layers 23a, 23b; wherein the patterned first metal layer 23a has a first bonding region A, and the second The metal layer 23b has a wafer placement area W and a third line area C surrounding the periphery of the wafer placement area W, and the contour of the first line area A corresponds to and is larger than the contour of the third line area C. . A protective layer 24 is formed on the first bonding region A, the wafer placement region W, and the third bonding region C.

如第2D圖所示，接著，以蝕刻方式移除顯露之導電晶種層210及其覆蓋之第一及第二初始金屬層21a,21b，且一併移除部分之第一及第二金屬層23a,23b，以於該核 心板20之第一及第二表面20a,20b上分別形成第一及第二線路層21a’,21b’，且各該導電通孔200’電性連接該第一及第二線路層21a’,21b’；藉由該保護層24之保護作用，令該第一打線區A之第一金屬層23a及該第三打線區C之第二金屬層23b僅受側蝕效應之影響，而該晶片置放區W則未受蝕刻影響。As shown in FIG. 2D, the exposed conductive seed layer 210 and its covered first and second initial metal layers 21a, 21b are removed by etching, and the first and second metals are removed together. Layers 23a, 23b for the core First and second circuit layers 21a', 21b' are formed on the first and second surfaces 20a, 20b of the core 20, and each of the conductive vias 200' is electrically connected to the first and second circuit layers 21a' 21b'; the protection of the protective layer 24, the first metal layer 23a of the first bonding region A and the second metal layer 23b of the third bonding region C are only affected by the side etching effect, and The wafer placement area W is not affected by the etching.

如第2E圖所示，移除該保護層24；然，如第2E’圖所示，於其他實施例中，可依封裝基板之需求，若無需於該第三打線區C形成打線墊，於先前步驟中，該第二初始金屬層21b及第二金屬層23b則無需形成於該第三打線區C上。後續製程中，以第2E圖為接續製程之結構。As shown in FIG. 2E, the protective layer 24 is removed. However, as shown in FIG. 2E', in other embodiments, the wire bonding pad may be formed in the third bonding region C according to the requirements of the package substrate. In the previous step, the second initial metal layer 21b and the second metal layer 23b need not be formed on the third bonding region C. In the subsequent process, the structure of the subsequent process is taken as the second process.

如第2F圖所示，於該核心板20之第一表面20a及第一金屬層23a上形成第一介電層25a，且於該核心板20之第二表面20b及第二金屬層23b上形成第二介電層25b。所述之第一介電層25a具有一對應該晶片置放區W及第一打線區A之空白區S，該空白區S將不設計任何線路，以利於後續之雷射燒融(laser ablation)製程。As shown in FIG. 2F, a first dielectric layer 25a is formed on the first surface 20a of the core board 20 and the first metal layer 23a, and is disposed on the second surface 20b and the second metal layer 23b of the core board 20. A second dielectric layer 25b is formed. The first dielectric layer 25a has a pair of blank areas S corresponding to the wafer placement area W and the first wiring area A. The blank area S will not be designed to facilitate subsequent laser ablation (laser ablation). )Process.

如第2G圖所示，於該第一介電層25a上形成第三線路層21c，且該空白區S上不具有該第三線路層21c，該第三線路層21c並具有圍繞該空白區S周緣之第二打線區B，該第二打線區B具有複數第二打線墊210b；又於該第二介電層25b上形成第四線路層21d，且該第四線路層21d具有複數例如為植球墊之電性接觸墊212。As shown in FIG. 2G, a third wiring layer 21c is formed on the first dielectric layer 25a, and the blanking region S does not have the third wiring layer 21c, and the third wiring layer 21c has a surrounding blank area. a second bonding area B of the periphery of the S, the second bonding area B has a plurality of second bonding pads 210b; a fourth wiring layer 21d is further formed on the second dielectric layer 25b, and the fourth wiring layer 21d has a plurality of It is an electrical contact pad 212 of the ball pad.

所述之第三及第四線路層21c,21d復具有位於該第 一及第二介電層25a,25b中之複數導電盲孔213，以分別電性連接該第一及第二線路層21a’,21b’；又該第四線路層21d復具有至少一散熱盲孔214，係設於該第二介電層25b中且對應連接該晶片置放區W。於其他實施例中(圖式中未表示)，亦可藉由該第二介電層25b本身之厚度不大而具有基本之散熱功用，因而無需形成該導熱盲孔214，以節省製程步驟及時間。The third and fourth circuit layers 21c, 21d have the same a plurality of conductive vias 213 in the first and second dielectric layers 25a, 25b for electrically connecting the first and second circuit layers 21a', 21b', respectively; and the fourth circuit layer 21d has at least one heat dissipation blind The hole 214 is disposed in the second dielectric layer 25b and is correspondingly connected to the wafer placement area W. In other embodiments (not shown in the drawings), the second dielectric layer 25b itself has a small heat dissipation function, so that the heat conduction blind hole 214 is not required to be formed, thereby saving process steps and time.

另外，亦可形成貫穿該核心板20、第一及第二介電層25a,25b之導電通孔250，以電性連接該第一、第二、第三及第四線路層21a’,21b’,21c,21d。In addition, conductive vias 250 extending through the core plate 20 and the first and second dielectric layers 25a, 25b may be formed to electrically connect the first, second, third, and fourth circuit layers 21a', 21b. ', 21c, 21d.

如第2H圖所示，於該第一介電層25a及第三線路層21c上形成第一防焊層26a，且於該第一防焊層26a上形成開口260a，以顯露各該第二打線墊210b及該空白區S，並於該第二介電層25b及第四線路層21d上形成第二防焊層26b，且於該第二防焊層26b上形成複數開孔260b，以對應顯露各該電性接觸墊212。As shown in FIG. 2H, a first solder resist layer 26a is formed on the first dielectric layer 25a and the third wiring layer 21c, and an opening 260a is formed on the first solder resist layer 26a to expose each of the second layers. a wire pad 210b and the blank area S, and a second solder resist layer 26b formed on the second dielectric layer 25b and the fourth circuit layer 21d, and a plurality of openings 260b are formed on the second solder resist layer 26b to Correspondingly, each of the electrical contact pads 212 is exposed.

然，如第2H’圖所示，於其他實施例中，所述之導電盲孔213’及散熱盲孔214’亦可於孔壁上形成金屬，再以防焊材填塞各該導電盲孔213’及散熱盲孔214’。於後續製程中，以第2H圖為接續製程之結構。As shown in FIG. 2H′, in other embodiments, the conductive blind vias 213 ′ and the heat dissipation blind vias 214 ′ may also form a metal on the sidewalls of the holes, and then fill the conductive vias with a solder resist. 213' and heat dissipation blind hole 214'. In the subsequent process, the structure of the subsequent process is taken as the 2H picture.

如第2I及2J圖所示，於各該電性接觸墊212及第二打線墊210b上形成保護層24’，如第2I圖所示；再於該空白區S上以雷射燒融形成一貫穿該核心板20之第一及第二表面20a,20b之第一開口201a、及貫穿該第一介 電層25a且連通該第一開口201a之第二開口201b，且該第二開口201b係對應並大於該第一開口201a，以形成階狀，而顯露出該晶片置放區W、第三打線區C及第一打線區A，如第2J圖所示。As shown in FIGS. 2I and 2J, a protective layer 24' is formed on each of the electrical contact pads 212 and the second bonding pads 210b, as shown in FIG. 2I; and then formed by laser firing on the blank region S. a first opening 201a penetrating the first and second surfaces 20a, 20b of the core board 20, and a first opening The second layer 201b is connected to the second opening 201b of the first opening 201a, and the second opening 201b is corresponding to and larger than the first opening 201a to form a step, and the wafer placement area W and the third line are exposed. Zone C and the first zone A are as shown in Figure 2J.

本發明於形成該第二開口201b時，藉由該第一打線區A之第一金屬層23a及第一初始金屬層21a之保護，可避免雷射破壞該第一打線區A的核心板20之第一表面20a；並於形成該第一開口201a時，藉由對應於該晶片置放區W、第三打線區C及兩區之間之第二初始金屬層21b之保護，可避免雷射破壞各區所對應之第二介電層25b。When the second opening 201b is formed, the protection of the first metal layer 23a and the first initial metal layer 21a of the first bonding area A can prevent the laser from damaging the core board 20 of the first bonding area A. The first surface 20a; and when the first opening 201a is formed, the lightning can be avoided by the protection corresponding to the wafer placement area W, the third wiring area C and the second initial metal layer 21b between the two areas The second dielectric layer 25b corresponding to each region is destroyed.

如第2K圖所示，藉由蝕刻移除該第一開口201a中對應於該晶片置放區W、第三打線區C及兩區之間所設之第二初始金屬層21b及其覆蓋之導電晶種層210，以於該第一開口201a中顯露出部份之第二介電層25b及第二金屬層23b，令該晶片置放區W之第二金屬層23b形成一晶片置放墊27，且令該第三打線區C之第二金屬層23b形成複數第三打線墊210c。As shown in FIG. 2K, the second initial metal layer 21b corresponding to the wafer placement area W, the third bonding area C, and the two regions in the first opening 201a and the coverage thereof are removed by etching. The conductive seed layer 210 is formed to expose a portion of the second dielectric layer 25b and the second metal layer 23b in the first opening 201a, so that the second metal layer 23b of the wafer placement area W forms a wafer. The pad 27 and the second metal layer 23b of the third wire bonding region C form a plurality of third wire pads 210c.

再者，於蝕刻移除該第二初始金屬層21b之同時，亦蝕刻該第二開口201b中之第一打線區A上之部分第一金屬層23a及部分第一初始金屬層21a，以形成複數第一打線墊210a。Further, while the second initial metal layer 21b is removed by etching, a portion of the first metal layer 23a and a portion of the first initial metal layer 21a on the first bonding region A in the second opening 201b are also etched to form The plurality of first wire pads 210a.

本發明藉由形成該保護層24’，可避免各該電性接觸墊212及第二打線墊210b受蝕刻製程之破壞。然，如第2K’圖所示，於其他實施例中，若以第2E’圖作為製程步驟 中，於該第三打線區C上將不會形成打線墊。於後續製程中，以第2K圖作為接續製程之結構。In the present invention, by forming the protective layer 24', the electrical contact pads 212 and the second bonding pads 210b can be prevented from being damaged by the etching process. However, as shown in FIG. 2K', in other embodiments, the second E' map is used as a processing step. In the third line area C, no wire mat will be formed. In the subsequent process, the 2K figure is used as the structure of the subsequent process.

如第2L及2M圖所示，且請一併參閱第2L’圖；移除該保護層24’，以顯露出各該電性接觸墊212及第二打線墊210b，如第2L及2L’圖所示；再於各該電性接觸墊212、第一、第二及第三打線墊210a,210b,201c上形成表面處理層28，俾完成本發明之封裝基板，如第2M圖所示。然，如第2M’圖所示，於其他實施例中，若以第2K’圖作為製程步驟中，則因無第三打線墊201c，故該表面處理層28並無需形成於該第三打線墊201c上。2L and 2M, and please refer to FIG. 2L'; remove the protective layer 24' to expose each of the electrical contact pads 212 and the second bonding pads 210b, such as 2L and 2L' The surface treatment layer 28 is formed on each of the electrical contact pads 212, the first, second, and third wire pads 210a, 210b, 201c to complete the package substrate of the present invention, as shown in FIG. 2M. . However, as shown in FIG. 2M′, in other embodiments, if the second K′ map is used as the processing step, the surface treatment layer 28 does not need to be formed on the third bonding line because there is no third bonding pad 201c. On the pad 201c.

如第2N圖所示，係為本發明之封裝基板後續所製成之半導體封裝結構；提供一半導體晶片29，係具有相對之作用面29a及非作用面29b，該作用面29a係以導線30分別電性連接各該第一、第二及第三打線墊210a,210b,201c，且該半導體晶片29之非作用面29b係結合至該晶片置放墊27上，該半導體晶片29並藉由該散熱盲孔214以達到散熱之目的。As shown in FIG. 2N, the semiconductor package structure is formed by the package substrate of the present invention; a semiconductor wafer 29 is provided, which has an opposite active surface 29a and a non-active surface 29b, and the active surface 29a is provided with a wire 30. Each of the first, second, and third bonding pads 210a, 210b, 201c is electrically connected to the non-active surface 29b of the semiconductor wafer 29, and the semiconductor wafer 29 is bonded to the wafer mounting pad 27. The heat dissipation blind hole 214 is used for heat dissipation.

於其他實施例中(未圖示)，若以第2M’圖所示之結構進行打線製程，該作用面29a僅以導線30電性連接各該第一及第二打線墊210a,210b。In another embodiment (not shown), if the wire bonding process is performed in the configuration shown in FIG. 2M', the active surface 29a is electrically connected only to the first and second wire bonding pads 210a, 210b by the wires 30.

又，於該第一及第二開口201a,201b中與該第一防焊層26a上形成封裝材31，以包覆該半導體晶片29及導線30；另外，可於各該電性接觸墊212上形成焊料球32，以供該封裝基板電性連接至其他電子裝置。Further, a package 31 is formed on the first and second openings 201a, 201b and the first solder resist 26a to cover the semiconductor wafer 29 and the wires 30. In addition, the electrical contact pads 212 may be formed on the first and second solder masks 26a. A solder ball 32 is formed thereon for electrically connecting the package substrate to other electronic devices.

因此，本發明僅需在該核心板20及第一介電層25a上以雷射燒融形成第一及第二開口201a,201b，相較於習知技術之多層核心板及介電層，本發明只使用單一層核心板20，不僅製程簡單且快速，且材料成本較低，並使整體封裝基板厚度大幅減小；若依本發明之製法將可製作出輕薄短小之產品。Therefore, the present invention only needs to form the first and second openings 201a, 201b by laser ablation on the core board 20 and the first dielectric layer 25a, compared to the multi-layer core board and the dielectric layer of the prior art. The invention only uses a single layer core plate 20, which not only has a simple and fast process, but also has a low material cost and greatly reduces the thickness of the whole package substrate; if the method of the invention is used, a light and short product can be produced.

另外，本發明藉由在該核心板20之相對第一及第二表面20a,20b上分別形成該第一及第二線路層21a’,21b’，而令該第一及第二線路層21a’,21b’形成複數第一及第三打線墊210a,210c；相較於習知技術之各核心板分開設計線路，本發明在單一核心板20上設計線路，不僅便於設計，且該核心板20之兩側均可形成打線墊。In addition, the first and second circuit layers 21a, 21b' are formed on the opposite first and second surfaces 20a, 20b of the core board 20, and the first and second circuit layers 21a are formed. ', 21b' forms a plurality of first and third wire mats 210a, 210c; the present invention designs a circuit on a single core board 20, which is not only convenient for design, but also is designed to be separate from the core boards of the prior art. A wire mat can be formed on both sides of the 20th.

本發明復提供一種封裝基板，係包括：具有相對之第一及第二表面20a,20b之核心板20、第一及第二線路層21a’,21b’、第一及第二介電層25a,25b、第三及第四線路層21c,21d、與第一及第二防焊層26a,26b。The present invention further provides a package substrate comprising: a core board 20 having first and second surfaces 20a, 20b opposite thereto, first and second circuit layers 21a', 21b', first and second dielectric layers 25a , 25b, third and fourth circuit layers 21c, 21d, and first and second solder resist layers 26a, 26b.

所述之核心板20具有一貫穿該第一及第二表面20a,20b之第一開口201a，且於該核心板20中設有導電通孔200’，以電性連接該第一及第二線路層21a’,21b’。The core plate 20 has a first opening 201a extending through the first and second surfaces 20a, 20b, and a conductive through hole 200' is disposed in the core plate 20 to electrically connect the first and second ends. Circuit layers 21a', 21b'.

所述之第一及第二線路層21a’,21b’分別設於該第一及第二表面20a,20b上，該第一線路層21a’具有圍繞該第一開口201a周緣之複數第一打線墊210a，且該第二線路層21b’具有一顯露於該第一開口201a之晶片置放墊27。The first and second circuit layers 21a', 21b' are respectively disposed on the first and second surfaces 20a, 20b, and the first circuit layer 21a' has a plurality of first lines around the circumference of the first opening 201a. Pad 210a, and the second circuit layer 21b' has a wafer placement pad 27 exposed in the first opening 201a.

所述之第一介電層25a設於該核心板20之第一表面20a及該第一線路層21a’上，並具有一對應且大於該第一開口201a之第二開口201b，以顯露該第一開口201a及該些第一打線墊210a。The first dielectric layer 25a is disposed on the first surface 20a of the core board 20 and the first circuit layer 21a', and has a second opening 201b corresponding to and larger than the first opening 201a to reveal the The first opening 201a and the first wire pads 210a.

所述之第二介電層25b設於該核心板20之第二表面20b及該第二線路層21b’上，且該第一開口201a顯露部份之第二介電層25b。The second dielectric layer 25b is disposed on the second surface 20b of the core board 20 and the second circuit layer 21b', and the first opening 201a exposes a portion of the second dielectric layer 25b.

所述之第三線路層21c設於該第一介電層25a上，且藉由位於該第一介電層25a中之導電盲孔213電性連接該第一線路層21a’，該第三線路層21c並具有圍繞該第二開口201b周緣之複數第二打線墊210b。The third circuit layer 21c is disposed on the first dielectric layer 25a, and is electrically connected to the first circuit layer 21a' by a conductive blind hole 213 located in the first dielectric layer 25a. The circuit layer 21c has a plurality of second wire pads 210b surrounding the circumference of the second opening 201b.

所述之第四線路層21d設於該第二介電層25b上，且該第四線路層21d具有位於該第二介電層25b中之導電盲孔213及散熱盲孔214，該導電盲孔213電性連接該第二線路層21b’，而該散熱盲孔214對應連接至該晶片置放墊27，該第四線路層21d並具有複數例如為植球墊之電性接觸墊212。The fourth circuit layer 21d is disposed on the second dielectric layer 25b, and the fourth circuit layer 21d has a conductive blind hole 213 and a heat dissipation blind hole 214 in the second dielectric layer 25b. The hole 213 is electrically connected to the second circuit layer 21b', and the heat dissipation blind hole 214 is correspondingly connected to the wafer placement pad 27. The fourth circuit layer 21d has a plurality of electrical contact pads 212, for example, a ball pad.

所述之第一防焊層26a設於該第一介電層25a及第三線路層21c上，且具有開口260a以外露各該第二打線墊210b、第一及第二開口201a,201b，而該第二防焊層26b設於該第二介電層25b及第四線路層21d上，且具有複數開孔260b以外露各該電性接觸墊212。The first solder resist layer 26a is disposed on the first dielectric layer 25a and the third circuit layer 21c, and has an opening 260a for exposing each of the second bonding pads 210b, the first and second openings 201a, 201b, The second solder resist layer 26b is disposed on the second dielectric layer 25b and the fourth circuit layer 21d, and has a plurality of openings 260b for exposing the electrical contact pads 212.

所述之封裝基板復包括導電通孔250，係貫穿設於該第一介電層25a、核心板20及第二介電層25b中，以電 性連接該第一、第二、第三及第四線路層21a’,21b’,21c,21d。The package substrate further includes a conductive via 250 disposed through the first dielectric layer 25a, the core board 20, and the second dielectric layer 25b to electrically The first, second, third and fourth circuit layers 21a', 21b', 21c, 21d are connected.

又該第二線路層21b’復具有複數第三打線墊210c，且該第一及第二開口201a,201b顯露該些第三打線墊210c。另外，該些電性接觸墊212、第一、第二及第三打線墊210a,210b,210c上設有表面處理層28。Further, the second circuit layer 21b' has a plurality of third wire pads 210c, and the first and second openings 201a, 201b expose the third wire pads 210c. In addition, the electrical contact pads 212, the first, second and third wire pads 210a, 210b, 210c are provided with a surface treatment layer 28.

綜上所述，本發明之封裝基板及其製法，因僅使用單一核心板配合介電層，故有效達到降低整體封裝結構厚度之目的。In summary, the package substrate of the present invention and the method for manufacturing the same have the purpose of reducing the thickness of the overall package structure by using only a single core plate to match the dielectric layer.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10a‧‧‧第一核心板10a‧‧‧First core board

10b‧‧‧第二核心板10b‧‧‧second core board

10c‧‧‧第三核心板10c‧‧‧ third core board

100,200’,250‧‧‧導電通孔100,200’, 250‧‧‧ conductive through holes

11a,21a’‧‧‧第一線路層11a, 21a’‧‧‧ first circuit layer

11b,21b’‧‧‧第二線路層11b, 21b’‧‧‧ second circuit layer

11c,21c‧‧‧第三線路層11c, 21c‧‧‧ third circuit layer

11d,21d‧‧‧第四線路層11d, 21d‧‧‧ fourth circuit layer

11e‧‧‧第五線路層11e‧‧‧ fifth circuit layer

11f‧‧‧第六線路層11f‧‧‧ sixth circuit layer

110a,210a‧‧‧第一打線墊110a, 210a‧‧‧ first line mat

110b,210b‧‧‧第二打線墊110b, 210b‧‧‧second line mat

111‧‧‧植球墊111‧‧‧Ball mat

12a,25a‧‧‧第一介電層12a, 25a‧‧‧First dielectric layer

12b,25b‧‧‧第二介電層12b, 25b‧‧‧ second dielectric layer

13‧‧‧凹槽13‧‧‧ Groove

13a,201a‧‧‧第一開口13a, 201a‧‧‧ first opening

13b,201b‧‧‧第二開口13b, 201b‧‧‧ second opening

14,27‧‧‧晶片置放墊14,27‧‧‧ wafer placement mat

15‧‧‧防焊層15‧‧‧ solder mask

150,260b‧‧‧開孔150, 260b‧‧‧ openings

16,29‧‧‧半導體晶片16,29‧‧‧Semiconductor wafer

16a,29a‧‧‧作用面16a, 29a‧‧‧Action surface

16b,29b‧‧‧非作用面16b, 29b‧‧‧Non-active surface

17,30‧‧‧導線17,30‧‧‧Wire

18,31‧‧‧封裝材18,31‧‧‧Package

19,32‧‧‧焊料球19,32‧‧‧ solder balls

20‧‧‧核心板20‧‧‧ core board

20a‧‧‧第一表面20a‧‧‧ first surface

20b‧‧‧第二表面20b‧‧‧second surface

200‧‧‧通孔200‧‧‧through hole

21a‧‧‧第一初始金屬層21a‧‧‧First initial metal layer

21b‧‧‧第二初始金屬層21b‧‧‧Second initial metal layer

210‧‧‧導電晶種層210‧‧‧ Conductive seed layer

210c‧‧‧第三打線墊210c‧‧‧third hit mat

212‧‧‧電性接觸墊212‧‧‧Electrical contact pads

213,213’‧‧‧導電盲孔213,213'‧‧‧ conductive blind holes

214,214’‧‧‧導熱盲孔214,214'‧‧‧ Thermal blind hole

22‧‧‧阻層22‧‧‧resist

220‧‧‧開口區220‧‧‧Open area

23a‧‧‧第一金屬層23a‧‧‧First metal layer

23b‧‧‧第二金屬層23b‧‧‧Second metal layer

24,24’‧‧‧保護層24, 24’ ‧ ‧ protective layer

26a‧‧‧第一防焊層26a‧‧‧First solder mask

26b‧‧‧第二防焊層26b‧‧‧Second solder mask

260a‧‧‧開口260a‧‧‧ openings

28‧‧‧表面處理層28‧‧‧Surface treatment layer

A‧‧‧第一打線區A‧‧‧first hitting area

B‧‧‧第二打線區B‧‧‧Second line area

C‧‧‧第三打線區C‧‧‧ third hitting area

S‧‧‧空白區S‧‧ ‧ blank area

W‧‧‧晶片置放區W‧‧‧ wafer placement area

第1A至1C圖係為習知封裝基板之製法之剖視示意圖；第2A至2M圖係為本發明封裝基板之製法之剖視示意圖；其中，第2E’、2H’、2K’及2M’圖係分別為第2E、2H、2K及2M圖之另一實施態樣，第2L’圖係為第2L圖之局部上視示意圖；以及第2N圖係為本發明封裝基板形成為半導體封裝結構之剖視示意圖。1A to 1C are schematic cross-sectional views showing a method of manufacturing a conventional package substrate; and FIGS. 2A to 2M are schematic cross-sectional views showing a method of manufacturing a package substrate of the present invention; wherein, 2E', 2H', 2K', and 2M' The figure is another embodiment of the 2E, 2H, 2K, and 2M diagrams, and the 2L' diagram is a partial top view of the 2L diagram; and the 2N diagram is the package substrate of the present invention formed into a semiconductor package structure. A schematic cross-sectional view.

20‧‧‧核心板20‧‧‧ core board

20a‧‧‧第一表面20a‧‧‧ first surface

20b‧‧‧第二表面20b‧‧‧second surface

201a‧‧‧第一開口201a‧‧‧first opening

201b‧‧‧第二開口201b‧‧‧second opening

21a’‧‧‧第一線路層21a’‧‧‧First circuit layer

21b’‧‧‧第二線路層21b’‧‧‧Second circuit layer

21c‧‧‧第三線路層21c‧‧‧ third circuit layer

21d‧‧‧第四線路層21d‧‧‧fourth circuit layer

210a‧‧‧第一打線墊210a‧‧‧First line mat

210b‧‧‧第二打線墊210b‧‧‧Second line mat

210c‧‧‧第三打線墊210c‧‧‧third hit mat

212‧‧‧電性接觸墊212‧‧‧Electrical contact pads

213‧‧‧導電盲孔213‧‧‧ Conductive blind holes

214‧‧‧導熱盲孔214‧‧‧thermal blind hole

25a‧‧‧第一介電層25a‧‧‧First dielectric layer

25b‧‧‧第二介電層25b‧‧‧Second dielectric layer

26a‧‧‧第一防焊層26a‧‧‧First solder mask

260a‧‧‧開口260a‧‧‧ openings

26b‧‧‧第二防焊層26b‧‧‧Second solder mask

260b‧‧‧開孔260b‧‧‧ opening

27‧‧‧晶片置放墊27‧‧‧ wafer placement mat

Claims (22)

一種封裝基板，係包括：一核心板，係具有相對之第一表面及第二表面，且該第一及第二表面上分別設有第一線路層及第二線路層，該第二線路層具有一晶片置放墊，且該核心板具有一貫穿該第一及第二表面之第一開口以顯露該晶片置放墊，且該第一線路層具有圍繞該第一開口周緣之複數第一打線墊；第一介電層，係設於該核心板之第一表面及該第一線路層上，並具有一對應且大於該第一開口之第二開口，以顯露該第一開口及該些第一打線墊；第二介電層，係設於該核心板之第二表面及該第二線路層上，且該第一開口顯露部份之第二介電層；第三線路層，係設於該第一介電層上，且電性連接該第一線路層，該第三線路層並具有圍繞該第二開口周緣之複數第二打線墊，該第三線路層具有複數設於該第一介電層中且電性連接該第一線路層之導電盲孔；以及第四線路層，係設於該第二介電層上，且電性連接該第二線路層，該第四線路層具有複數設於該第二介電層中且電性連接該第二線路層之導電盲孔。 A package substrate includes: a core plate having opposite first and second surfaces, and the first and second surfaces are respectively provided with a first circuit layer and a second circuit layer, and the second circuit layer Having a wafer placement pad, and the core plate has a first opening extending through the first and second surfaces to expose the wafer placement pad, and the first circuit layer has a plurality of first around the circumference of the first opening a first dielectric layer is disposed on the first surface of the core board and the first circuit layer, and has a second opening corresponding to the first opening to expose the first opening and the a first dielectric pad; a second dielectric layer is disposed on the second surface of the core plate and the second circuit layer, and the first opening exposes a portion of the second dielectric layer; the third circuit layer, Is disposed on the first dielectric layer, and electrically connected to the first circuit layer, the third circuit layer has a plurality of second wire pads surrounding the circumference of the second opening, the third circuit layer has a plurality of Conductive blind holes in the first dielectric layer and electrically connected to the first circuit layer; And the fourth circuit layer is disposed on the second dielectric layer and electrically connected to the second circuit layer, wherein the fourth circuit layer has a plurality of electrodes disposed in the second dielectric layer and electrically connected to the second circuit layer Conductive blind holes in the circuit layer. 如申請專利範圍第1項之封裝基板，復包括複數導電通孔，係設於該核心板中，以電性連接該第一及第二線路層。 The package substrate of claim 1 includes a plurality of conductive vias disposed in the core board to electrically connect the first and second circuit layers. 如申請專利範圍第1項之封裝基板，復包括表面處理層，係設於該些第一及第二打線墊上。 The package substrate of claim 1 is further comprising a surface treatment layer disposed on the first and second wire bonding pads. 如申請專利範圍第1項之封裝基板，其中，該第二線路層復具有複數第三打線墊，且該第一及第二開口顯露出該些第三打線墊。 The package substrate of claim 1, wherein the second circuit layer has a plurality of third wire pads, and the first and second openings expose the third wire pads. 如申請專利範圍第4項之封裝基板，復包括表面處理層，係設於該些第三打線墊上。 For example, the package substrate of claim 4 includes a surface treatment layer disposed on the third wire bonding pads. 如申請專利範圍第1項之封裝基板，其中，該第四線路層具有至少一散熱盲孔，係設於該第二介電層中且對應連接至該晶片置放墊。 The package substrate of claim 1, wherein the fourth circuit layer has at least one heat dissipation blind hole disposed in the second dielectric layer and correspondingly connected to the wafer placement pad. 如申請專利範圍第1項之封裝基板，復包括第一防焊層，係設於該第一介電層及第三線路層上，且該第一防焊層具有開口以外露各該第二打線墊、第一及第二開口。 The package substrate of claim 1 , further comprising a first solder resist layer disposed on the first dielectric layer and the third circuit layer, wherein the first solder resist layer has an opening exposed to the second Line mat, first and second openings. 如申請專利範圍第1項之封裝基板，其中，該第四線路層具有複數電性接觸墊。 The package substrate of claim 1, wherein the fourth circuit layer has a plurality of electrical contact pads. 如申請專利範圍第8項之封裝基板，復包括第二防焊層，係設於該第二介電層及第四線路層上，且該第二防焊層具有複數開孔以外露各該電性接觸墊。 The package substrate of claim 8 further comprising a second solder resist layer disposed on the second dielectric layer and the fourth circuit layer, wherein the second solder resist layer has a plurality of openings and is exposed Electrical contact pads. 如申請專利範圍第9項之封裝基板，復包括表面處理層，係設於該些電性接觸墊上。 The package substrate of claim 9 is further comprising a surface treatment layer disposed on the electrical contact pads. 如申請專利範圍第1項之封裝基板，復包括複數導電通孔，係貫穿設於該第一介電層、核心板及第二介電層中，以電性連接該第一、第二、第三及第四線路層。 The package substrate of claim 1 , further comprising a plurality of conductive vias disposed in the first dielectric layer, the core plate and the second dielectric layer to electrically connect the first and second Third and fourth circuit layers. 一種封裝基板之製法，係包括：提供一具有相對之第一及第二表面之核心板，該核心板之第一及第二表面上分別設有第一及第二初始金屬層；形成貫穿該核心板、第一及第二初始金屬層之複數通孔；於各該通孔之孔壁、該第一及第二初始金屬層上形成導電晶種層；於該第一及第二初始金屬層上之導電晶種層上形成阻層，且於各該阻層中形成複數圖案化之開口區，以顯露各該通孔、該第一及第二初始金屬層上之部份導電晶種層；於各該開口區中之第一及第二初始金屬層之導電晶種層上分別電鍍形成第一及第二金屬層，並於各該通孔中形成導電通孔，且該第一金屬層具有第一打線區，而該第二金屬層具有晶片置放區；移除該阻層；蝕刻該第一打線區外之第一金屬層及第一初始金屬層以形成第一線路層，並蝕刻該晶片置放區外之第二金屬層及第二初始金屬層以形成第二線路層，且各該導電通孔電性連接該第一及第二線路層；於該核心板之第一表面及第一金屬層上形成第一介電層，且該第一介電層具有一對應該晶片置放區及第一打線區之空白區，且於該核心板之第二表面及 第二金屬層上形成第二介電層；於該第一及第二介電層上分別形成第三及第四線路層，且該第四線路層具有複數電性接觸墊，且該第一介電層之空白區未形成該第三線路層，又該第三線路層具有圍繞該空白區周緣之第二打線區，該第二打線區具有複數第二打線墊；於該空白區形成一貫穿該核心板之第一及第二表面之第一開口、及貫穿該第一介電層之第二開口，且該第二開口對應且大於該第一開口，以顯露該晶片置放區及該第一打線區；以及蝕刻該第一打線區之部分第一金屬層及部分第一初始金屬層，以形成複數第一打線墊，且蝕刻移除對應該晶片置放區之第二初始金屬層及其覆蓋之導電晶種層，以形成晶片置放墊。 A method for manufacturing a package substrate, comprising: providing a core plate having opposite first and second surfaces, wherein the first and second surfaces of the core plate are respectively provided with first and second initial metal layers; a plurality of through holes of the core plate, the first and second initial metal layers; forming a conductive seed layer on the hole walls of the through holes, the first and second initial metal layers; and the first and second initial metals Forming a resist layer on the conductive seed layer on the layer, and forming a plurality of patterned open areas in each of the resist layers to expose each of the via holes, a portion of the conductive seed on the first and second initial metal layers a first and a second metal layer are respectively formed on the conductive seed layers of the first and second initial metal layers in each of the open regions, and conductive vias are formed in each of the via holes, and the first The metal layer has a first bonding region, and the second metal layer has a wafer placement region; removing the resist layer; etching the first metal layer outside the first bonding region and the first initial metal layer to form a first wiring layer And etching the second metal layer outside the wafer placement area and the second initial gold Forming a second circuit layer, and each of the conductive vias is electrically connected to the first and second circuit layers; forming a first dielectric layer on the first surface of the core plate and the first metal layer, and the a dielectric layer having a pair of blank areas corresponding to the wafer placement area and the first bonding area, and on the second surface of the core board Forming a second dielectric layer on the second metal layer; forming third and fourth circuit layers on the first and second dielectric layers, respectively, and the fourth circuit layer has a plurality of electrical contact pads, and the first The third circuit layer is not formed in the blank area of the dielectric layer, and the third circuit layer has a second bonding area surrounding the periphery of the blank area, the second bonding area has a plurality of second bonding pads; and a blank area is formed in the blank area a first opening extending through the first and second surfaces of the core board and a second opening extending through the first dielectric layer, and the second opening corresponds to and larger than the first opening to expose the wafer placement area and a first bonding region; and etching a portion of the first metal layer and a portion of the first initial metal layer of the first bonding region to form a plurality of first bonding pads, and etching to remove the second initial metal corresponding to the wafer placement region The layer and its covered conductive seed layer are formed to form a wafer placement pad. 如申請專利範圍第12項之封裝基板之製法，復包括移除該阻層之後，於該第一打線區及晶片置放區形成保護層，並於形成該第一及第二線路層之後，再移除該保護層。 The method for manufacturing a package substrate according to claim 12, further comprising: after removing the resist layer, forming a protective layer on the first bonding region and the wafer placement region, and after forming the first and second wiring layers, The protective layer is removed again. 如申請專利範圍第12項之封裝基板之製法，復包括於形成該第三及第四線路層之後，於該第一介電層及第三線路層上形成第一防焊層，且該第一防焊層中形成有開口，以顯露各該第二打線墊及該空白區，並於該第二介電層及第四線路層上形成第二防焊層，而該第二防焊層形成有複數開孔，以對應顯露各該電性接 觸墊。 The method for manufacturing a package substrate according to claim 12, further comprising forming a first solder resist layer on the first dielectric layer and the third circuit layer after forming the third and fourth circuit layers, and the An opening is formed in a solder resist layer to expose each of the second bonding pads and the blank region, and a second solder resist layer is formed on the second dielectric layer and the fourth wiring layer, and the second solder resist layer Forming a plurality of openings to correspondingly expose each of the electrical connections Touch pad. 如申請專利範圍第14項之封裝基板之製法，復包括於各該電性接觸墊及第二打線墊上形成保護層，並於形成各該第一打線墊及該晶片置放墊後，再移除該保護層。 The method for manufacturing a package substrate according to claim 14 is further included on each of the electrical contact pads and the second wire bonding pad to form a protective layer, and after forming each of the first bonding pads and the wafer placing pad, In addition to the protective layer. 如申請專利範圍第12項之封裝基板之製法，其中，該第二金屬層復具有圍繞該晶片置放區周緣之第三打線區，而該第一打線區係對應且大於該第三打線區，並於形成該晶片置放墊之同時，並於該第三打線區形成複數第三打線墊。 The method for manufacturing a package substrate according to claim 12, wherein the second metal layer has a third bonding area surrounding a periphery of the wafer placement area, and the first wiring area corresponds to and is larger than the third bonding area. And forming a plurality of third bonding pads in the third bonding region while forming the wafer placement pad. 如申請專利範圍第16項之封裝基板之製法，復包括於各該電性接觸墊、第一、第二及第三打線墊上形成表面處理層。 The method for manufacturing a package substrate according to claim 16 is further comprising forming a surface treatment layer on each of the electrical contact pads, the first, second and third wire bonding pads. 如申請專利範圍第12項之封裝基板之製法，其中，該第三及第四線路層復具有複數位於該第一及第二介電層中之導電盲孔，以分別電性連接該第一及第二線路層。 The method for manufacturing a package substrate according to claim 12, wherein the third and fourth circuit layers have a plurality of conductive blind holes in the first and second dielectric layers to electrically connect the first And a second circuit layer. 如申請專利範圍第12項之封裝基板之製法，其中，該第四線路層復具有至少一散熱盲孔，係設於該第二介電層中且對應連接該晶片置放墊。 The method for manufacturing a package substrate according to claim 12, wherein the fourth circuit layer has at least one heat dissipation blind hole, and is disposed in the second dielectric layer and correspondingly connected to the wafer placement pad. 如申請專利範圍第12項之封裝基板之製法，其中，該第一及第二開口係以雷射燒融貫穿該空白區對應之第一介電層、核心板之第一及第二表面而形成。 The method for manufacturing a package substrate according to claim 12, wherein the first and second openings are laser-fired through the first dielectric layer and the first and second surfaces of the core plate corresponding to the blank region; form. 如申請專利範圍第12項之封裝基板之製法，復包括 形成貫穿該第一介電層、核心板及第二介電層之導電通孔，以電性連接該第一、第二、第三及第四線路層。 For example, the method of manufacturing the package substrate of claim 12, including Conductive vias penetrating the first dielectric layer, the core plate, and the second dielectric layer are formed to electrically connect the first, second, third, and fourth circuit layers. 如申請專利範圍第12項之封裝基板之製法，復包括於各該電性接觸墊、第一及第二打線墊上形成表面處理層。 The method for manufacturing a package substrate according to claim 12, further comprising forming a surface treatment layer on each of the electrical contact pads and the first and second wire bonding pads.
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TWI572267B (en) * 2014-09-29 2017-02-21 旭德科技股份有限公司 Multi-layer circuit board with cavity and method of manufacturing the same

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TWI704658B (en) * 2019-06-04 2020-09-11 恆勁科技股份有限公司 Package substrate
TWI780876B (en) * 2021-08-25 2022-10-11 旭德科技股份有限公司 Package carrier and package structure

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI572267B (en) * 2014-09-29 2017-02-21 旭德科技股份有限公司 Multi-layer circuit board with cavity and method of manufacturing the same
US9883599B2 (en) 2014-09-29 2018-01-30 Subtron Technology Co., Ltd. Manufacturing method for multi-layer circuit board having cavity

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