TWI758756B - Package carrier and manufacturing method thereof - Google Patents

Package carrier and manufacturing method thereof Download PDF

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Publication number
TWI758756B
TWI758756B TW109121264A TW109121264A TWI758756B TW I758756 B TWI758756 B TW I758756B TW 109121264 A TW109121264 A TW 109121264A TW 109121264 A TW109121264 A TW 109121264A TW I758756 B TWI758756 B TW I758756B
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layer
substrate
build
pad
conductive
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TW109121264A
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TW202201675A (en
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林緯廸
簡俊賢
陳裕華
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欣興電子股份有限公司
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Priority to TW109121264A priority Critical patent/TWI758756B/en
Priority to US16/942,743 priority patent/US11139234B1/en
Priority to US17/402,635 priority patent/US11532543B2/en
Publication of TW202201675A publication Critical patent/TW202201675A/en
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Publication of TWI758756B publication Critical patent/TWI758756B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0156—Temporary polymeric carrier or foil, e.g. for processing or transferring
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material

Abstract

A package carrier includes a substrate, at least one interposer, a conductive structure layer, a first build-up structure and a second build-up structure. The interposer is disposed in at least one opening of the substrate, and the interposer includes a glass substrate, at least one conductive via, at least one first pad and at least one second pad. The conductive via passes through the glass substrate, and the first and the second pads are respectively disposed on an upper and a lower surfaces of the glass substrate opposite to each other and connected to opposite ends of the conductive via. The conductive structure layer is disposed on the substrate and structurally and electrically connects the first and the second pads. The first and the second build-up structures are respectively disposed on a first and a second surfaces of the substrate and electrically connected to the conductive structure layer.

Description

封裝載板及其製作方法Package carrier and method of making the same

本發明是有關於一種基板結構及其製作方法，且特別是有關於一種封裝載板及其製作方法。 The present invention relates to a substrate structure and a manufacturing method thereof, and in particular, to a package carrier and a manufacturing method thereof.

目前的內埋式被動元件基板(Embedded Passive Substrate,FPS)的結構僅能單面連接，在被動元件的背面無法佈局導線，因而無法有效利用。一般來說，被動元件與基板之間的連接是透過導電盲孔；或者是，以基板上的導線圖案直接連接至被動元件的接點進行單面導線佈局。由於導電盲孔具有較多的連接介面，即有上、下兩連接介面，因而易造成導電性不佳。再者，導電盲孔還具有孔底接觸面積較小的特性，由於須進行除膠渣製程，若無法有效地清除孔底的殘留物，將導致電性可靠度不佳。此外，目前的基板大都為銅箔基板，因其本身材料特性較易產生不規則的翹曲，而使得晶片封裝區的共面性不佳，且晶片無法有效地配置在銅箔基板上的晶片封裝區內，進而導致封裝良率低。另外，被動元件的尺寸較小，亦無法提供做為封裝區的剛性支撐結構。 The structure of the current embedded passive element substrate (Embedded Passive Substrate, FPS) can only be connected on one side, and wires cannot be laid out on the backside of the passive element, so it cannot be effectively used. Generally speaking, the connection between the passive element and the substrate is through conductive blind vias; or, the conductor pattern on the substrate is directly connected to the contact of the passive element for single-sided conductor layout. Since the conductive blind via has more connection interfaces, that is, there are upper and lower connection interfaces, it is easy to cause poor conductivity. In addition, the conductive blind hole also has the characteristics of a small contact area at the bottom of the hole. Since a desmear process is required, if the residue at the bottom of the hole cannot be effectively removed, the electrical reliability will be poor. In addition, most of the current substrates are copper foil substrates, which are prone to irregular warpage due to their own material properties, which makes the coplanarity of the chip packaging area poor, and the chips cannot be effectively arranged on the copper foil substrates. within the packaging area, resulting in a low packaging yield. In addition, the size of passive components is small and cannot provide a rigid support structure for the packaging area.

本發明提供一種封裝載板，其具有較佳的共平面性。 The present invention provides a package carrier with better coplanarity.

本發明還提供一種封裝載板的製作方法，用以製作上述的封裝載板，可提升晶片封裝良率及結構剛性，且具有較佳的導電性能及結構可靠度。 The present invention also provides a manufacturing method of a package carrier board, which is used to manufacture the above-mentioned package carrier board, which can improve the chip package yield and structural rigidity, and has better electrical conductivity and structural reliability.

本發明的封裝載板，包括一基板、至少一中介板、一導電結構層、一第一增層結構以及一第二增層結構。基板具有彼此相對的一第一表面與一第二表面以及連接第一表面與第二表面的至少一開口。中介板配置於基板的開口內，且中介板包括玻璃基板、至少一導電通孔、至少一第一接墊以及至少一第二接墊。導電通孔貫穿玻璃基板，而第一接墊與第二接墊分別配置於玻璃基板彼此相對的一上表面與一下表面上且連接至導電通孔的相對兩端。導電結構層配置於基板上且結構性及電性連接第一接墊與第二接墊。第一增層結構配置於基板的第一表面上且與導電結構層電性連接。第二增層結構配置於基板的第二表面上且與導電結構層電性連接。 The package carrier of the present invention includes a substrate, at least one interposer, a conductive structure layer, a first build-up structure and a second build-up structure. The substrate has a first surface and a second surface opposite to each other and at least one opening connecting the first surface and the second surface. The interposer is disposed in the opening of the substrate, and the interposer includes a glass substrate, at least one conductive through hole, at least one first pad and at least one second pad. The conductive through hole penetrates through the glass substrate, and the first pad and the second pad are respectively disposed on an upper surface and a lower surface of the glass substrate opposite to each other and connected to opposite ends of the conductive through hole. The conductive structure layer is disposed on the substrate and is structurally and electrically connected to the first pad and the second pad. The first build-up structure is disposed on the first surface of the substrate and is electrically connected with the conductive structure layer. The second build-up structure is disposed on the second surface of the substrate and is electrically connected with the conductive structure layer.

在本發明的一實施例中，上述的封裝載板還包括一絕緣層，填滿基板的開口，且覆蓋玻璃基板的上表面與下表面，並暴露出第一接墊與第二接墊。絕緣層切齊於基板的第一表面與第二表面。 In an embodiment of the present invention, the package carrier further includes an insulating layer that fills the opening of the substrate, covers the upper surface and the lower surface of the glass substrate, and exposes the first pad and the second pad. The insulating layer is aligned with the first surface and the second surface of the substrate.

在本發明的一實施例中，上述的基板還具有至少一貫 孔。導電結構層包括一第一圖案化線路層、一第二圖案化線路層以及至少一導通層。導通層覆蓋貫孔的內壁，且連接位於第一表面上的第一圖案化線路層及位於第二表面上的第二圖案化線路層。第一圖案化線路層與第一接墊結構性且電性連接。第二圖案化線路層與第二接墊結構性且電性連接。 In an embodiment of the present invention, the above-mentioned substrate further has at least a consistent hole. The conductive structure layer includes a first patterned circuit layer, a second patterned circuit layer and at least one conduction layer. The conduction layer covers the inner wall of the through hole and connects the first patterned circuit layer on the first surface and the second patterned circuit layer on the second surface. The first patterned circuit layer is structurally and electrically connected to the first pad. The second patterned circuit layer is structurally and electrically connected to the second pad.

在本發明的一實施例中，上述的封裝載板還包括一第一防焊層、一第二防焊層、一第一表面處理層以及一第二表面處理層。第一防焊層配置於第一增層結構上。第一防焊層具有多個第一開口，而第一開口暴露出部分第一增層結構。第二防焊層配置於第二增層結構上。第二防焊層具有多個第二開口，而第二開口暴露出部分第二增層結構。第一表面處理層配置於第一開口所暴露出的第一增層結構上。第二表面處理層配置於第二開口所暴露出的第二增層結構上。 In an embodiment of the present invention, the above-mentioned package carrier further includes a first solder resist layer, a second solder resist layer, a first surface treatment layer and a second surface treatment layer. The first solder resist layer is disposed on the first build-up structure. The first solder resist layer has a plurality of first openings, and the first openings expose part of the first build-up structure. The second solder resist layer is disposed on the second build-up layer structure. The second solder mask has a plurality of second openings, and the second openings expose part of the second build-up structure. The first surface treatment layer is disposed on the first build-up structure exposed by the first opening. The second surface treatment layer is disposed on the second build-up structure exposed by the second opening.

在本發明的一實施例中，上述的封裝載板還包括多個第一焊球以及多個第二焊球。第一焊球分別配置於第一防焊層的第一開口內。第一表面處理層位於第一焊球與第一增層結構之間。第二焊球分別配置於第二防焊層的第二開口內。第二表面處理層位於第二焊球與第二增層結構之間。 In an embodiment of the present invention, the aforementioned package carrier further includes a plurality of first solder balls and a plurality of second solder balls. The first solder balls are respectively arranged in the first openings of the first solder resist layer. The first surface treatment layer is located between the first solder balls and the first build-up structure. The second solder balls are respectively disposed in the second openings of the second solder resist layer. The second surface treatment layer is located between the second solder balls and the second build-up structure.

本發明的封裝載板的製作方法，其包括以下步驟。提供具有至少一開口的一基板。將至少一中介板置放於基板的開口內。每一中介板包括一玻璃基板、至少一導電通孔、至少一第一接墊以及至少一第二接墊。導電通孔貫穿玻璃基板，而第一接墊 與第二接墊分別配置於玻璃基板彼此相對的一上表面與一下表面上且連接至導電通孔的相對兩端。形成一導電結構層於基板上，其中導電結構層結構性且電性連接第一接墊與第二接墊。分別形成一第一增層結構與一第二增層結構於基板的第一表面與第二表面上。第一增層結構與第二增層結構分別與導電結構層電性連接。 The manufacturing method of the package carrier of the present invention includes the following steps. A substrate having at least one opening is provided. At least one interposer is placed in the opening of the substrate. Each interposer includes a glass substrate, at least one conductive via, at least one first pad and at least one second pad. The conductive via penetrates through the glass substrate, and the first pad The second pad and the second pad are respectively disposed on an upper surface and a lower surface of the glass substrate opposite to each other and connected to opposite ends of the conductive through hole. A conductive structure layer is formed on the substrate, wherein the conductive structure layer is structurally and electrically connected to the first pad and the second pad. A first build-up structure and a second build-up structure are respectively formed on the first surface and the second surface of the substrate. The first build-up structure and the second build-up structure are respectively electrically connected to the conductive structure layer.

在本發明的一實施例中，上述的封裝載板的製作方法還包括：於形成導電結構層於基板上之前，形成一絕緣材料層於基板的開口內。絕緣材料層填滿開口，覆蓋玻璃基板的上表面與下表面，並延伸覆蓋至基板的第一表面以及第一接墊上。移除部分絕緣材料層而形成一絕緣層。絕緣層暴露出第一接墊與第二接墊，且切齊於基板的第一表面與第二表面。 In an embodiment of the present invention, the above-mentioned manufacturing method of the package carrier further includes: before forming the conductive structure layer on the substrate, forming an insulating material layer in the opening of the substrate. The insulating material layer fills the opening, covers the upper surface and the lower surface of the glass substrate, and extends to cover the first surface of the substrate and the first pad. Part of the insulating material layer is removed to form an insulating layer. The insulating layer exposes the first pad and the second pad, and is aligned with the first surface and the second surface of the substrate.

在本發明的一實施例中，上述的形成導電結構層於基板上的步驟，包括：形成至少一貫孔於基板上。形成一導電材料層於基板上。導電材料層覆蓋貫孔的內壁，且延伸覆蓋於絕緣層上、第一接墊與第二接墊上，以及基板的第一表面及第二表面上。圖案化導電材料層而形成導電結構層。導電結構層包括一第一圖案化線路層、一第二圖案化線路層以及至少一導通層。導通層覆蓋貫孔的內壁，且連接位於第一表面上的第一圖案化線路層及位於第二表面上的第二圖案化線路層。第一圖案化線路層與第一接墊結構性且電性連接。第二圖案化線路層與第二接墊結構性且電性連接。 In an embodiment of the present invention, the above-mentioned step of forming the conductive structure layer on the substrate includes: forming at least a through hole on the substrate. A conductive material layer is formed on the substrate. The conductive material layer covers the inner wall of the through hole, and extends to cover the insulating layer, the first pad and the second pad, and the first surface and the second surface of the substrate. The conductive material layer is patterned to form a conductive structure layer. The conductive structure layer includes a first patterned circuit layer, a second patterned circuit layer and at least one conduction layer. The conduction layer covers the inner wall of the through hole and connects the first patterned circuit layer on the first surface and the second patterned circuit layer on the second surface. The first patterned circuit layer is structurally and electrically connected to the first pad. The second patterned circuit layer is structurally and electrically connected to the second pad.

在本發明的一實施例中，上述的封裝載板的製作方法還 包括：形成一第一防焊層於第一增層結構上。第一防焊層具有多個第一開口，第一開口暴露出部分第一增層結構。形成一第二防焊層於第二增層結構上。第二防焊層具有多個第二開口，第二開口暴露出部分第二增層結構。形成一第一表面處理層於第一開口所暴露出的第一增層結構上。形成一第二表面處理層於第二開口所暴露出的第二增層結構上。 In an embodiment of the present invention, the above-mentioned manufacturing method of the package carrier is further The method includes: forming a first solder resist layer on the first build-up layer structure. The first solder resist layer has a plurality of first openings, and the first openings expose part of the first build-up structure. A second solder resist layer is formed on the second build-up structure. The second solder resist layer has a plurality of second openings, and the second openings expose part of the second build-up structure. A first surface treatment layer is formed on the first build-up structure exposed by the first opening. A second surface treatment layer is formed on the second build-up structure exposed by the second opening.

在本發明的一實施例中，上述的封裝載板的製作方法還包括：分別形成多個第一焊球於第一防焊層的第一開口內。第一表面處理層位於第一焊球與第一增層結構之間。分別形成多個第二焊球於第二防焊層的第二開口內。第二表面處理層位於第二焊球與第二增層結構之間。 In an embodiment of the present invention, the above-mentioned manufacturing method of the package carrier board further includes: respectively forming a plurality of first solder balls in the first openings of the first solder resist layer. The first surface treatment layer is located between the first solder balls and the first build-up structure. A plurality of second solder balls are respectively formed in the second openings of the second solder resist layer. The second surface treatment layer is located between the second solder balls and the second build-up structure.

基於上述，在本發明的封裝載板的設計中，是透過將中介板置放於基板的開口內來作為一被動元件使用，其中導電結構層結構性及電性連接中介板的第一接墊與第二接墊。意即，導電結構層與第一接墊之間以及導電結構層與第二接墊之間分別僅具有一個接觸面，呈現無盲孔連接且高共平面性(Coplanarity)。再者，中介板可雙面與導電結構層電性連接，除了可具有較佳的線路靈活度及利用率之外，中介板亦可作為剛性支撐結構，可提高後續封裝結構的剛性。此外，由於本發明的封裝載板為元件內埋式封裝載板，除了可具有較佳的共平面性，因而可提升後續晶片封裝良率之外，亦可具有較佳的導電性能、結構可靠度及較薄的封裝厚度。 Based on the above, in the design of the package carrier of the present invention, the interposer is used as a passive element by placing the interposer in the opening of the substrate, wherein the conductive structure layer is structurally and electrically connected to the first pad of the interposer with the second pad. That is, there is only one contact surface between the conductive structure layer and the first pad and between the conductive structure layer and the second pad, respectively, so as to have no blind via connection and high coplanarity. Furthermore, the interposer can be electrically connected to the conductive structure layer on both sides. In addition to better circuit flexibility and utilization, the interposer can also be used as a rigid support structure, which can improve the rigidity of subsequent packaging structures. In addition, since the package carrier of the present invention is a component-embedded package carrier, in addition to better coplanarity, which can improve the yield of subsequent chip packaging, it also has better electrical conductivity and reliable structure degree and thinner package thickness.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

10:黏著層 10: Adhesive layer

20:晶片 20: Wafer

100a、100b:封裝載板 100a, 100b: Package carrier board

110a、110b:基板 110a, 110b: substrate

111:第一表面 111: First surface

112:核心層 112: Core layer

113:第二表面 113: Second Surface

114:第一銅箔層 114: The first copper foil layer

115a、115b:開口 115a, 115b: Opening

116:第二銅箔層 116: Second copper foil layer

117:貫孔 117: Through hole

120:中介板 120: Intermediate board

121:上表面 121: Upper surface

122:玻璃基板 122: glass substrate

123:下表面 123: Lower surface

124:導電通孔 124: Conductive vias

126:第一接墊 126: first pad

128:第二接墊 128: Second pad

130a:絕緣材料層 130a: Layer of insulating material

130:絕緣層 130: Insulation layer

140a:導電材料層 140a: Conductive material layer

140:導電結構層 140: Conductive structure layer

142:第一圖案化線路層 142: the first patterned circuit layer

144:第二圖案化線路層 144: the second patterned circuit layer

146:導通層 146: conduction layer

150:第一增層結構 150: First build-up structure

152:介電層 152: Dielectric layer

154:線路層 154: circuit layer

156:導電盲孔 156: Conductive blind hole

160:第二增層結構 160: Second build-up structure

162:介電層 162: Dielectric layer

164:線路層 164: circuit layer

166:導電盲孔 166: Conductive blind hole

170:第一防焊層 170: The first solder mask

172:第一開口 172: First Opening

175:第二防焊層 175: Second Solder Mask

177:第二開口 177: Second Opening

180:第一表面處理層 180: The first surface treatment layer

185:第二表面處理層 185: Second surface treatment layer

190:第一焊球 190: First Solder Ball

195:第二焊球 195: Second Solder Ball

G:間隙 G: Gap

圖1A至圖1H是依照本發明的一實施例的一種封裝載板的製作方法的剖面示意圖。 1A to 1H are schematic cross-sectional views of a method for fabricating a package carrier according to an embodiment of the present invention.

圖2是依照本發明的一實施例的一種封裝載板的剖面示意圖。 2 is a schematic cross-sectional view of a package carrier according to an embodiment of the present invention.

圖3是將多個晶片封裝至圖2的封裝載板的剖面示意圖。 FIG. 3 is a schematic cross-sectional view of packaging a plurality of chips onto the package carrier of FIG. 2 .

圖1A至圖1H是依照本發明的一實施例的一種封裝載板的製作方法的剖面示意圖。關於本實施例的封裝載板的製作方法，首先，請參考圖1A，提供一基板110a。詳細來說，本實施例的基板110a包括一核心層112、一第一銅箔層114以及一第二銅箔層116，其中第一銅箔層114與第二銅箔層116分別位於核心層112的相對兩表面上。此處，基板110a例如是銅箔基板，而核心層112的材質例如是玻璃纖維，但本發明並不以此基板110a為限。於其他未繪示的實施例中，基板亦可為BT樹脂基板、塑膠基板、陶瓷基板或其他適當的基板。 1A to 1H are schematic cross-sectional views of a method for fabricating a package carrier according to an embodiment of the present invention. Regarding the manufacturing method of the package carrier of this embodiment, first, referring to FIG. 1A , a substrate 110 a is provided. In detail, the substrate 110a of this embodiment includes a core layer 112, a first copper foil layer 114 and a second copper foil layer 116, wherein the first copper foil layer 114 and the second copper foil layer 116 are respectively located in the core layer 112 on opposite surfaces. Here, the substrate 110a is, for example, a copper foil substrate, and the material of the core layer 112 is, for example, glass fiber, but the invention is not limited to the substrate 110a. In other not-shown embodiments, the substrate can also be a BT resin substrate, a plastic substrate, a ceramic substrate or other suitable substrates.

接著，請參考圖1B，形成至少一開口115a(示意地繪示 一個開口115a)於基板110a上，其中開口115a貫穿第一銅箔層114、核心層112以及第二銅箔層116。至此，已提供具有開口115a的基板110a。 Next, referring to FIG. 1B, at least one opening 115a (shown schematically) is formed An opening 115 a ) is formed on the substrate 110 a , wherein the opening 115 a penetrates through the first copper foil layer 114 , the core layer 112 and the second copper foil layer 116 . So far, the substrate 110a having the opening 115a has been provided.

緊接著，請再參考圖1B，貼附一黏著層10於基板110a上，其中基板110a具有彼此相對的一第一表面111與一第二表面113，而基板110a的第二表面113與黏著層10黏接在一起。 Next, referring to FIG. 1B again, an adhesive layer 10 is attached on the substrate 110a, wherein the substrate 110a has a first surface 111 and a second surface 113 opposite to each other, and the second surface 113 of the substrate 110a and the adhesive layer 10 are glued together.

接著，請再參考圖1B，將至少一中介板120(示意地繪示一個中介板120)置放於基板110a的開口115a內，且透過黏著層10而定位於開口115a內。詳細來說，本實施例的中介板120包括一玻璃基板122、至少一導電通孔124(示意地繪示三個導電通孔124)、至少一第一接墊126(示意地繪示三個第一接墊126)以及至少一第二接墊128(示意地繪示三個第二接墊128)。導電通孔124貫穿玻璃基板122，而第一接墊126與第二接墊128分別配置於玻璃基板122彼此相對的一上表面121與一下表面123上且連接至導電通孔124的相對兩端。也就是說，第一接墊126與第二接墊128彼此對應設置且位於導電通孔124彼此相對的兩端。較佳地，導電通孔124、第一接墊126以及第二接墊128三者具有相同的材質且呈現無縫連接。此時，中介板120的第二接墊128與黏著層10相黏接，而將中介板120定位於開口115a中。如圖1B所示，中介板120並非直接接觸開口115a，而是與開口115a的內壁之間具有一間隙G。第一接墊126可與基板110a的第一表面111共平面，而第二接墊128可與基板110a的第二表面113共 平面，但不以此為限。 Next, referring to FIG. 1B again, at least one interposer 120 (one interposer 120 is schematically shown) is placed in the opening 115 a of the substrate 110 a and positioned in the opening 115 a through the adhesive layer 10 . Specifically, the interposer 120 of this embodiment includes a glass substrate 122 , at least one conductive via 124 (three conductive vias 124 are schematically shown), and at least one first pad 126 (three are schematically shown) A first pad 126) and at least one second pad 128 (three second pads 128 are schematically shown). The conductive vias 124 penetrate through the glass substrate 122 , and the first pads 126 and the second pads 128 are respectively disposed on an upper surface 121 and a lower surface 123 of the glass substrate 122 opposite to each other and connected to opposite ends of the conductive vias 124 . . That is to say, the first pads 126 and the second pads 128 are disposed corresponding to each other and located at opposite ends of the conductive via 124 . Preferably, the conductive vias 124 , the first pads 126 and the second pads 128 have the same material and are seamlessly connected. At this time, the second pads 128 of the interposer 120 are adhered to the adhesive layer 10, and the interposer 120 is positioned in the opening 115a. As shown in FIG. 1B , the interposer 120 does not directly contact the opening 115a, but has a gap G with the inner wall of the opening 115a. The first pads 126 may be coplanar with the first surface 111 of the substrate 110a, and the second pads 128 may be coplanar with the second surface 113 of the substrate 110a plane, but not limited to this.

接著，請同時參考圖1B以及圖1C，透過壓合、填膠、塞孔等方式形成一絕緣材料層130a於基板110a的開口115a內，以對基板110a進行膜封。此時，絕緣材料層130a填滿開口115a，覆蓋玻璃基板122的上表面121與下表面123，並延伸覆蓋至基板110a的第一表面111以及第一接墊126上。 1B and 1C at the same time, an insulating material layer 130a is formed in the opening 115a of the substrate 110a by means of lamination, glue filling, plugging, etc., to seal the substrate 110a. At this time, the insulating material layer 130a fills the opening 115a, covers the upper surface 121 and the lower surface 123 of the glass substrate 122, and extends to cover the first surface 111 and the first pads 126 of the substrate 110a.

緊接著，請參考圖1C，移除黏著層10，而暴露出基板110a的第二表面113、部分絕緣材料層130a以及第二接墊128。 Next, referring to FIG. 1C , the adhesive layer 10 is removed to expose the second surface 113 of the substrate 110 a , part of the insulating material layer 130 a and the second pads 128 .

接著，請同時參考圖1C與圖1D，透過化學機械研磨法(Chemical-Mechanical Polishing,CMP)或電漿薄化(plasma thinning)等方式，移除部分絕緣材料層130a而形成一絕緣層130。此時，絕緣層130暴露出中介板120的第一接墊126與第二接墊128，且切齊於基板110a的第一表面111與第二表面113。 1C and FIG. 1D at the same time, through chemical mechanical polishing (Chemical-Mechanical Polishing, CMP) or plasma thinning (plasma thinning), etc., remove part of the insulating material layer 130a to form an insulating layer 130 . At this time, the insulating layer 130 exposes the first pads 126 and the second pads 128 of the interposer 120 and is aligned with the first surface 111 and the second surface 113 of the substrate 110a.

接著，請參考圖1E，形成至少一貫孔117(示意地繪示二個貫孔117)於基板110a上。緊接著，以電鍍或濺鍍的方式形成一導電材料層140a於基板110a上，其中導電材料層140a覆蓋貫孔117的內壁，且延伸覆蓋於絕緣層130上、第一接墊126與第二接墊128上，以及基板110a的第一表面111及第二表面113上。意即，對全板面進行金屬化。 Next, referring to FIG. 1E , at least through holes 117 (two through holes 117 are schematically shown) are formed on the substrate 110 a. Next, a conductive material layer 140a is formed on the substrate 110a by electroplating or sputtering, wherein the conductive material layer 140a covers the inner wall of the through hole 117, and extends to cover the insulating layer 130, the first pad 126 and the first pad 126. On the two pads 128, and on the first surface 111 and the second surface 113 of the substrate 110a. That is, metallization is performed on the entire board surface.

緊接著，請同時參考圖1E與圖1F，利用減層法的方式，圖案化導電材料層140a，而形成導電結構層140。導電結構層140包括一第一圖案化線路層142、一第二圖案化線路層144以及至少 一導通層146(示意地繪示二個導通層146)。導通層146覆蓋貫孔的內壁，且連接位於基板110a的第一表面111上的第一圖案化線路層142及位於基板110a的第二表面113上的第二圖案化線路層144。意即，導通層146用以導通第一圖案化線路層142與第二圖案化線路層144。此處，導電結構層140暴露出基板110a的核心層112的部分表面，且第一圖案化線路層142包括殘留的第一銅箔層114，而第二圖案化線路層144包括殘留的第二銅箔層116。特別是，第一圖案化線路層142與第一接墊126結構性且電性連接，而第二圖案化線路層144與第二接墊128結構性且電性連接。此時，第一圖案化線路層142與第一接墊126之間僅具有一個接觸平面，而第二圖案化線路層144與第二接墊128之間僅具有一個接觸平面，可具有較大的接觸面積，並可提供較佳的導電性及較佳的連接可靠度，且呈現無盲孔連接及高共平面性。至此，已形成導電結構層140於基板110a上，其中導電結構層140結構性且電性連接中介板120的第一接墊126與第二接墊128。 Next, referring to FIG. 1E and FIG. 1F at the same time, the conductive material layer 140 a is patterned by a layer reduction method to form the conductive structure layer 140 . The conductive structure layer 140 includes a first patterned circuit layer 142, a second patterned circuit layer 144 and at least A conduction layer 146 (two conduction layers 146 are schematically shown). The conduction layer 146 covers the inner wall of the through hole and connects the first patterned circuit layer 142 on the first surface 111 of the substrate 110a and the second patterned circuit layer 144 on the second surface 113 of the substrate 110a. That is, the conducting layer 146 is used to conduct the first patterned circuit layer 142 and the second patterned circuit layer 144 . Here, the conductive structure layer 140 exposes a part of the surface of the core layer 112 of the substrate 110a, the first patterned circuit layer 142 includes the residual first copper foil layer 114, and the second patterned circuit layer 144 includes the residual second copper foil layer 144. Copper foil layer 116 . In particular, the first patterned wiring layer 142 is structurally and electrically connected to the first pads 126 , and the second patterned wiring layer 144 is structurally and electrically connected to the second pads 128 . At this time, there is only one contact plane between the first patterned circuit layer 142 and the first pad 126 , and there is only one contact plane between the second patterned circuit layer 144 and the second pad 128 , which may be larger. It can provide better conductivity and better connection reliability, and present no blind hole connection and high coplanarity. So far, the conductive structure layer 140 has been formed on the substrate 110 a, wherein the conductive structure layer 140 is structurally and electrically connected to the first pads 126 and the second pads 128 of the interposer 120 .

接著，請參考圖1G，分別形成一第一增層結構150與一第二增層結構160於基板110a的第一表面111與第二表面113上。第一增層結構150與第二增層結構160分別與導電結構層140電性連接。詳細來說，第一增層結構150包括至少一介電層152(示意地繪示一層介電層152)、至少一線路層154(示意地繪示一層線路層154)以及至少一導電盲孔156(示意地繪示多個導電盲孔156)。介電層152至少覆蓋第一圖案化線路層142，且填充至貫孔 117內。線路層154配置於介電層152上，且透過導電盲孔156與第一圖案化線路層142電性連接。第二增層結構160包括至少一介電層162(示意地繪示一層介電層162)、至少一線路層164(示意地繪示一層線路層164)以及至少一導電盲孔166(示意地繪示多個導電盲孔166)。介電層162至少覆蓋第二圖案化線路層144，且填充至貫孔117內。線路層164配置於介電層162上，且透過導電盲孔166與第二圖案化線路層144電性連接。 Next, referring to FIG. 1G, a first build-up structure 150 and a second build-up structure 160 are respectively formed on the first surface 111 and the second surface 113 of the substrate 110a. The first build-up structure 150 and the second build-up structure 160 are respectively electrically connected to the conductive structure layer 140 . In detail, the first build-up structure 150 includes at least one dielectric layer 152 (a dielectric layer 152 is schematically shown), at least one circuit layer 154 (a circuit layer 154 is schematically shown), and at least one conductive blind via 156 (a plurality of conductive blind vias 156 are schematically shown). The dielectric layer 152 covers at least the first patterned circuit layer 142 and fills the through holes within 117. The circuit layer 154 is disposed on the dielectric layer 152 and is electrically connected to the first patterned circuit layer 142 through the conductive blind holes 156 . The second build-up structure 160 includes at least one dielectric layer 162 (a layer of dielectric layer 162 is schematically shown), at least one circuit layer 164 (a layer of circuit layer 164 is schematically shown), and at least one conductive blind via 166 (a layer of circuit layer 164 is schematically shown) A plurality of conductive blind vias 166) are shown. The dielectric layer 162 covers at least the second patterned circuit layer 144 and fills the through holes 117 . The circuit layer 164 is disposed on the dielectric layer 162 and is electrically connected to the second patterned circuit layer 144 through the conductive blind holes 166 .

接著，請再參考圖1G，形成一第一防焊層170於第一增層結構150上，以及形成一第二防焊層175於第二增層結構160上。第一防焊層170具有多個第一開口172，而第一開口172暴露出第一增層結構150的部分線路層154。第二防焊層175具有多個第二開口177，而第二開口177暴露出第二增層結構160的部分線路層164。緊接著，形成一第一表面處理層180於第一開口172所暴露出的第一增層結構150的部分線路層154上，以及形成一第二表面處理層185於第二開口177所暴露出的第二增層結構160的部分線路層164上，以分別保護線路層154及線路層164。 Next, referring to FIG. 1G again, a first solder resist layer 170 is formed on the first build-up structure 150 , and a second solder resist layer 175 is formed on the second build-up structure 160 . The first solder mask layer 170 has a plurality of first openings 172 , and the first openings 172 expose part of the circuit layer 154 of the first build-up structure 150 . The second solder mask layer 175 has a plurality of second openings 177 , and the second openings 177 expose part of the circuit layer 164 of the second build-up structure 160 . Next, a first surface treatment layer 180 is formed on the part of the circuit layer 154 of the first build-up structure 150 exposed by the first opening 172 , and a second surface treatment layer 185 is formed on the part of the circuit layer 154 exposed by the second opening 177 on part of the circuit layer 164 of the second build-up structure 160 to protect the circuit layer 154 and the circuit layer 164 respectively.

最後，請參考圖1H，分別形成多個第一焊球190於第一防焊層170的第一開口172內，其中第一表面處理層180位於第一焊球190與第一增層結構150之間。分別形成多個第二焊球195於第二防焊層175的第二開口177內，其中第二表面處理層185位於第二焊球195與第二增層結構160之間。此處，第一焊球190的尺寸實際上小於第二焊球195的尺寸，其中第一焊球190適於 與被動元件、主動元件或其他尺寸較小的晶片電性連接，而第二焊球195適於與封裝體或其他尺寸較大的電子裝置電性連接。至此，已完成封裝載板100a的製作。 Finally, referring to FIG. 1H , a plurality of first solder balls 190 are respectively formed in the first openings 172 of the first solder mask 170 , wherein the first surface treatment layer 180 is located on the first solder balls 190 and the first build-up structure 150 between. A plurality of second solder balls 195 are respectively formed in the second openings 177 of the second solder resist layer 175 , wherein the second surface treatment layer 185 is located between the second solder balls 195 and the second build-up structure 160 . Here, the size of the first solder ball 190 is actually smaller than the size of the second solder ball 195 , wherein the first solder ball 190 is suitable for The second solder balls 195 are suitable for electrical connection with the package body or other large-sized electronic devices for electrical connection with passive components, active components or other chips with smaller size. So far, the fabrication of the package carrier 100a has been completed.

在結構上，請再參考圖1H，封裝載板100a包括基板110a、中介板120、導電結構層140、第一增層結構150以及第二增層結構160。基板110a具有彼此相對的第一表面111與第二表面113以及連接第一表面111與第二表面113的開口115a。中介板120配置於基板110a的開口115a內，且中介板120包括玻璃基板122、導電通孔124、第一接墊126以及第二接墊128。導電通孔124貫穿玻璃基板122，而第一接墊126與第二接墊128分別配置於玻璃基板122彼此相對的上表面121與下表面123上且連接至導電通孔124的相對兩端。導電結構層140配置於基板110a上且結構性及電性連接第一接墊126與第二接墊128。第一增層結構150配置於基板110a的第一表面111上且與導電結構層140電性連接。第二增層結構160配置於基板110a的第二表面113上且與導電結構層140電性連接。 In terms of structure, please refer to FIG. 1H again, the package carrier 100 a includes a substrate 110 a , an interposer 120 , a conductive structure layer 140 , a first build-up structure 150 and a second build-up structure 160 . The substrate 110a has a first surface 111 and a second surface 113 opposite to each other and an opening 115a connecting the first surface 111 and the second surface 113 . The interposer 120 is disposed in the opening 115 a of the substrate 110 a , and the interposer 120 includes a glass substrate 122 , a conductive via 124 , a first pad 126 and a second pad 128 . The conductive via 124 penetrates through the glass substrate 122 , and the first pad 126 and the second pad 128 are respectively disposed on the upper surface 121 and the lower surface 123 of the glass substrate 122 opposite to each other and connected to opposite ends of the conductive via 124 . The conductive structure layer 140 is disposed on the substrate 110 a and is structurally and electrically connected to the first pad 126 and the second pad 128 . The first build-up structure 150 is disposed on the first surface 111 of the substrate 110 a and is electrically connected to the conductive structure layer 140 . The second build-up structure 160 is disposed on the second surface 113 of the substrate 110 a and is electrically connected to the conductive structure layer 140 .

再者，本實施例的封裝載板100a還包括絕緣層130，其中絕緣層130填滿基板110a的開口115a，且覆蓋玻璃基板120的上表面121與下表面123，並暴露出第一接墊126與第二接墊128。較佳地，絕緣層130切齊於基板110a的第一表面111與第二表面113。本實施例的基板110a還具有貫孔117，而導電結構層140包括第一圖案化線路層142、第二圖案化線路層144以及導通層 146。導通層146覆蓋貫孔117的內壁，且連接位於第一表面111上的第一圖案化線路層142及位於第二表面113上的第二圖案化線路層144。第一圖案化線路層142與第一接墊126結構性且電性連接。第二圖案化線路層144與第二接墊128結構性且電性連接。 Furthermore, the package carrier 100a of this embodiment further includes an insulating layer 130, wherein the insulating layer 130 fills the opening 115a of the substrate 110a, covers the upper surface 121 and the lower surface 123 of the glass substrate 120, and exposes the first pads 126 and the second pad 128 . Preferably, the insulating layer 130 is aligned with the first surface 111 and the second surface 113 of the substrate 110a. The substrate 110a of this embodiment further has through holes 117, and the conductive structure layer 140 includes a first patterned circuit layer 142, a second patterned circuit layer 144 and a conduction layer 146. The conduction layer 146 covers the inner wall of the through hole 117 and connects the first patterned wiring layer 142 on the first surface 111 and the second patterned wiring layer 144 on the second surface 113 . The first patterned circuit layer 142 is structurally and electrically connected to the first pads 126 . The second patterned circuit layer 144 is structurally and electrically connected to the second pads 128 .

此外，本實施例的封裝載板100a還包括第一防焊層170、第二防焊層175、第一表面處理層180以及第二表面處理層185。第一防焊層170配置於第一增層結構150上，其中第一防焊層170具有第一開口172，而第一開口172暴露出部分第一增層結構150。第二防焊層175配置於第二增層結構160上，其中第二防焊層175具有第二開口177，而第二開口177暴露出部分第二增層結構160。第一表面處理層180配置於第一開口172所暴露出的第一增層結構150上。第二表面處理層185配置於第二開口177所暴露出的第二增層結構160上。 In addition, the package carrier 100 a of this embodiment further includes a first solder resist layer 170 , a second solder resist layer 175 , a first surface treatment layer 180 and a second surface treatment layer 185 . The first solder resist layer 170 is disposed on the first build-up structure 150 , wherein the first solder resist layer 170 has a first opening 172 , and the first opening 172 exposes a part of the first build-up structure 150 . The second solder resist layer 175 is disposed on the second build-up structure 160 , wherein the second solder resist layer 175 has a second opening 177 , and the second opening 177 exposes a part of the second build-up structure 160 . The first surface treatment layer 180 is disposed on the first build-up structure 150 exposed by the first opening 172 . The second surface treatment layer 185 is disposed on the second build-up structure 160 exposed by the second opening 177 .

另外，為了與外部電路電性連接，本實施例的封裝載板100a還包括多個第一焊球190以及多個第二焊球195。第一焊球190分別配置於第一防焊層170的第一開口172內，其中第一表面處理層180位於第一焊球190與第一增層結構150之間。第二焊球195分別配置於第二防焊層175的第二開口177內，其中第二表面處理層185位於第二焊球195與第二增層結構160之間。 In addition, in order to be electrically connected to the external circuit, the package carrier 100 a of this embodiment further includes a plurality of first solder balls 190 and a plurality of second solder balls 195 . The first solder balls 190 are respectively disposed in the first openings 172 of the first solder resist layer 170 , wherein the first surface treatment layer 180 is located between the first solder balls 190 and the first build-up structure 150 . The second solder balls 195 are respectively disposed in the second openings 177 of the second solder resist layer 175 , wherein the second surface treatment layer 185 is located between the second solder balls 195 and the second build-up structure 160 .

由於本實施例的中介板120是以高剛性、高平整度及高尺寸安定性的玻璃基板122作為基底，且導電結構層140直接連接至第一接墊126與第二接墊128。意即，導電結構層140與第一 接墊126之間以及導電結構層140與第二接墊128之間分別僅具有一個接觸面，可具有較大的接觸面積，並可提供較佳的導電性及較佳的連接可靠度，且呈現無盲孔連接及高共平面性(Coplanarity)。簡言之，本實施例的中介板120可雙面與導電結構層140電性連接，除了可具有較佳的線路靈活度及利用率之外，中介板120亦可作為剛性支撐結構，可提高後續封裝結構的剛性。 Because the interposer 120 of this embodiment is based on the glass substrate 122 with high rigidity, high flatness and high dimensional stability, and the conductive structure layer 140 is directly connected to the first pad 126 and the second pad 128 . That is, the conductive structure layer 140 and the first There is only one contact surface between the pads 126 and between the conductive structure layer 140 and the second pad 128, which can have a larger contact area, and can provide better conductivity and better connection reliability, and Present no blind via connection and high coplanarity (Coplanarity). In short, the interposer 120 of this embodiment can be electrically connected to the conductive structure layer 140 on both sides. In addition to better circuit flexibility and utilization, the interposer 120 can also be used as a rigid support structure, which can improve the The rigidity of the subsequent package structure.

再者，由於本實施例的中介板120提供了高剛性、高共平性及高平整度的接點連接結構，因此後續形成在中介板120上與外部電路電性連接的第一焊球190及第二焊球195，可形成高共平面性的晶片連接點。此外，由於本實施例中介板120置放於基板110a的開口115中，可視為是一種被動元件，因此本實施例的封裝載板100a可視為一種元件內埋式封裝載板，除了可具有較佳的共平面性，因而可提升後續晶片封裝良率之外，亦可具有較佳的導電性能、結構可靠度及較薄的封裝厚度。 Furthermore, since the interposer 120 of the present embodiment provides a contact connection structure with high rigidity, high coplanarity and high flatness, the first solder balls 190 and the first solder balls 190 and the first solder balls electrically connected to the external circuit are subsequently formed on the interposer 120 . Two solder balls 195 can form high coplanarity chip connection points. In addition, since the interposer 120 of this embodiment is placed in the opening 115 of the substrate 110a and can be regarded as a passive component, the package carrier 100a of this embodiment can be regarded as a component-embedded package carrier, except that it may have a relatively Therefore, in addition to improving the yield of subsequent chip packaging, it also has better electrical conductivity, structural reliability and thinner packaging thickness.

在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。 It must be noted here that the following embodiments use the element numbers and part of the contents of the previous embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and repeated descriptions in the following embodiments will not be repeated.

圖2是依照本發明的一實施例的一種封裝載板的剖面示意圖。圖3是將多個晶片封裝至圖2的封裝載板的剖面示意圖。請先參考圖2，本實施例的封裝載板100b與圖1H的封裝載板100a相似，兩者的差異在於：本實施例的基板110b具有多個開口115b (示意地繪示二個開口115b)，而多個中介板120(示意地繪示二個中介板120)分別置放於開口115b中。在應用上，請參考圖3，可將至少一晶片20(示意地繪示二個晶片20)透過第一焊球190而接合至封裝載板100b上。也就是說，本實施例的封裝載板100b可透過多個中介板120來實現多晶片封裝，除了可提升晶片封裝良率之外，亦可達成模組化的需求。 2 is a schematic cross-sectional view of a package carrier according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of packaging a plurality of chips onto the package carrier of FIG. 2 . Please refer to FIG. 2 first, the package carrier 100b of this embodiment is similar to the package carrier 100a of FIG. 1H , the difference between the two is that the substrate 110b of this embodiment has a plurality of openings 115b (two openings 115b are schematically shown), and a plurality of interposers 120 (two interposers 120 are schematically shown) are respectively placed in the openings 115b. In application, please refer to FIG. 3 , at least one chip 20 (two chips 20 are schematically shown) can be bonded to the package carrier 100 b through the first solder balls 190 . That is to say, the package carrier 100b of the present embodiment can realize multi-chip packaging through a plurality of interposers 120, which can not only improve the yield of chip packaging, but also meet the requirement of modularization.

綜上所述，在本發明的封裝載板的設計中，是透過將中介板置放於基板的開口內來作為一被動元件使用，其中導電結構層結構性及電性連接中介板的第一接墊與第二接墊。意即，導電結構層與第一接墊之間以及導電結構層與第二接墊之間分別僅具有一個接觸面，呈現無盲孔連接且高共平面性。再者，中介板可雙面與導電結構層電性連接，除了可具有較佳的線路靈活度及利用率之外，中介板亦可作為剛性支撐結構，可提高後續封裝結構的剛性。此外，由於本發明的封裝載板為元件內埋式封裝載板，除了可具有較佳的共平面性，因而可提升後續晶片封裝良率之外，亦可具有較佳的導電性能、結構可靠度及較薄的封裝厚度。 To sum up, in the design of the package carrier of the present invention, the interposer is used as a passive element by placing the interposer in the opening of the substrate, wherein the conductive structure layer is structurally and electrically connected to the first part of the interposer. pad and second pad. That is to say, there is only one contact surface between the conductive structure layer and the first pad and between the conductive structure layer and the second pad, respectively, showing no blind via connection and high coplanarity. Furthermore, the interposer can be electrically connected to the conductive structure layer on both sides. In addition to better circuit flexibility and utilization, the interposer can also be used as a rigid support structure, which can improve the rigidity of subsequent packaging structures. In addition, since the package carrier of the present invention is a component-embedded package carrier, in addition to better coplanarity, which can improve the yield of subsequent chip packaging, it also has better electrical conductivity and reliable structure degree and thinner package thickness.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

100a:封裝載板100a: Package carrier board

110a:基板110a: Substrate

111:第一表面111: First surface

113:第二表面113: Second Surface

115a:開口115a: Opening

117:貫孔117: Through hole

120:中介板120: Intermediate board

121:上表面121: Upper surface

122:玻璃基板122: glass substrate

123:下表面123: Lower surface

124:導電通孔124: Conductive vias

126:第一接墊126: first pad

128:第二接墊128: Second pad

130:絕緣層130: Insulation layer

140:導電結構層140: Conductive structure layer

142:第一圖案化線路層142: the first patterned circuit layer

144:第二圖案化線路層144: the second patterned circuit layer

146:導通層146: conduction layer

150:第一增層結構150: First build-up structure

160:第二增層結構160: Second build-up structure

170:第一防焊層170: The first solder mask

172:第一開口172: First Opening

175:第二防焊層175: Second Solder Mask

177:第二開口177: Second Opening

180:第一表面處理層180: The first surface treatment layer

185:第二表面處理層185: Second surface treatment layer

190:第一焊球190: First Solder Ball

195:第二焊球195: Second Solder Ball

Claims (10)

一種封裝載板，包括：一基板，具有彼此相對的一第一表面與一第二表面以及連接該第一表面與該第二表面的至少一開口；至少一中介板，配置於該基板的該至少一開口內，各該中介板包括玻璃基板、至少一導電通孔、至少一第一接墊以及至少一第二接墊，該至少一導電通孔沿該基板的該第一表面的法線方向直接地垂直貫穿該玻璃基板，而該至少一第一接墊與該至少一第二接墊分別配置於該玻璃基板彼此相對的一上表面與一下表面上且連接至該導電通孔的相對兩端；一導電結構層，配置於該基板上，且結構性及電性連接該至少一第一接墊與該至少一第二接墊；一第一增層結構，配置於該基板的該第一表面上，且與該導電結構層電性連接；以及一第二增層結構，配置於該基板的該第二表面上，且與該導電結構層電性連接。 A package carrier board, comprising: a substrate having a first surface and a second surface opposite to each other and at least one opening connecting the first surface and the second surface; at least one interposer, disposed on the substrate of the substrate In at least one opening, each of the interposers includes a glass substrate, at least one conductive via, at least one first pad and at least one second pad, and the at least one conductive via is along the normal line of the first surface of the substrate The direction is directly perpendicular to the glass substrate, and the at least one first pad and the at least one second pad are respectively arranged on an upper surface and a lower surface of the glass substrate opposite to each other and connected to the opposite side of the conductive through hole. two ends; a conductive structure layer disposed on the substrate and structurally and electrically connected to the at least one first pad and the at least one second pad; a first build-up structure disposed on the substrate of the substrate on the first surface and electrically connected with the conductive structure layer; and a second build-up structure disposed on the second surface of the substrate and electrically connected with the conductive structure layer. 如請求項1所述的封裝載板，更包括：一絕緣層，填滿該基板的該至少一開口，且覆蓋該玻璃基板的該上表面與該下表面，並暴露出該至少一第一接墊與該至少一第二接墊，其中該絕緣層切齊於該基板的該第一表面與該第二表面。 The package carrier board of claim 1, further comprising: an insulating layer filling the at least one opening of the substrate, covering the upper surface and the lower surface of the glass substrate, and exposing the at least one first opening The pad and the at least one second pad, wherein the insulating layer is aligned with the first surface and the second surface of the substrate. 如請求項1所述的封裝載板，其中該基板還具有至少一貫孔，該導電結構層包括一第一圖案化線路層、一第二圖案化線路層以及至少一導通層，該至少一導通層覆蓋該至少一貫孔的內壁，且連接位於該第一表面上的該第一圖案化線路層及位於該第二表面上的該第二圖案化線路層，該第一圖案化線路層與該至少一第一接墊結構性且電性連接，而該第二圖案化線路層與該至少一第二接墊結構性且電性連接。 The package carrier according to claim 1, wherein the substrate further has at least through holes, the conductive structure layer includes a first patterned circuit layer, a second patterned circuit layer and at least one conduction layer, the at least one conduction layer The layer covers the inner wall of the at least through hole, and connects the first patterned wiring layer on the first surface and the second patterned wiring layer on the second surface, the first patterned wiring layer and the The at least one first pad is structurally and electrically connected, and the second patterned circuit layer is structurally and electrically connected to the at least one second pad. 如請求項1所述的封裝載板，還包括：一第一防焊層，配置於該第一增層結構上，該第一防焊層具有多個第一開口，而該些第一開口暴露出部分該第一增層結構；一第二防焊層，配置於該第二增層結構上，該第二防焊層具有多個第二開口，而該些第二開口暴露出部分該第二增層結構；一第一表面處理層，配置於該些第一開口所暴露出的該第一增層結構上；以及一第二表面處理層，配置於該些第二開口所暴露出的該第二增層結構上。 The package carrier according to claim 1, further comprising: a first solder resist layer disposed on the first build-up structure, the first solder resist layer having a plurality of first openings, and the first openings Part of the first build-up structure is exposed; a second solder mask is disposed on the second build-up structure, the second solder mask has a plurality of second openings, and the second openings expose part of the a second build-up structure; a first surface treatment layer disposed on the first build-up structure exposed by the first openings; and a second surface treatment layer disposed exposed by the second openings on the second build-up structure. 如請求項4所述的封裝載板，還包括：多個第一焊球，分別配置於該第一防焊層的該些第一開口內，該第一表面處理層位於該些第一焊球與該第一增層結構之間；以及多個第二焊球，分別配置於該第二防焊層的該些第二開口內，該第二表面處理層位於該些第二焊球與該第二增層結構之間。 The package carrier according to claim 4, further comprising: a plurality of first solder balls, respectively disposed in the first openings of the first solder resist layer, and the first surface treatment layer is located on the first solder balls between the ball and the first build-up structure; and a plurality of second solder balls, respectively disposed in the second openings of the second solder resist layer, the second surface treatment layer is located between the second solder balls and the between the second build-up structure. 一種封裝載板的製作方法，包括：提供具有至少一開口的一基板；將至少一中介板置放於該基板的該至少一開口內，各該中介板包括一玻璃基板、至少一導電通孔、至少一第一接墊以及至少一第二接墊，該至少一導電通孔沿該基板的該第一表面的法線方向直接地垂直貫穿該玻璃基板，而該至少一第一接墊與該至少一第二接墊分別配置於該玻璃基板彼此相對的一上表面與一下表面上且連接至該導電通孔的相對兩端；形成一導電結構層於該基板上，其中該導電結構層結構性且電性連接該至少一第一接墊與該至少一第二接墊；以及分別形成一第一增層結構與一第二增層結構於該基板的該第一表面與該第二表面上，該第一增層結構與該第二增層結構分別與該導電結構層電性連接。 A method for manufacturing a package carrier, comprising: providing a substrate with at least one opening; placing at least one interposer in the at least one opening of the substrate, each interposer comprising a glass substrate and at least one conductive through hole , at least one first pad and at least one second pad, the at least one conductive through hole directly and vertically penetrates the glass substrate along the normal direction of the first surface of the substrate, and the at least one first pad and the The at least one second pad is respectively disposed on an upper surface and a lower surface of the glass substrate opposite to each other and connected to opposite ends of the conductive via; a conductive structure layer is formed on the substrate, wherein the conductive structure layer structurally and electrically connecting the at least one first pad and the at least one second pad; and respectively forming a first build-up structure and a second build-up structure on the first surface and the second build-up structure of the substrate On the surface, the first build-up structure and the second build-up structure are respectively electrically connected to the conductive structure layer. 如請求項6所述的封裝載板的製作方法，還包括：於形成該導電結構層於該基板上之前，形成一絕緣材料層於該基板的該至少一開口內，該絕緣材料層填滿該至少一開口，覆蓋該玻璃基板的該上表面與該下表面，並延伸覆蓋至該基板的該第一表面以及該至少一第一接墊上；以及移除部分該絕緣材料層，而形成一絕緣層，其中該絕緣層暴露出該至少一第一接墊與該至少一第二接墊，且切齊於該基板的該第一表面與該第二表面。 The method for manufacturing a package carrier board according to claim 6, further comprising: before forming the conductive structure layer on the substrate, forming an insulating material layer in the at least one opening of the substrate, and the insulating material layer is filled with The at least one opening covers the upper surface and the lower surface of the glass substrate, and extends to cover the first surface of the substrate and the at least one first pad; and remove part of the insulating material layer to form a an insulating layer, wherein the insulating layer exposes the at least one first pad and the at least one second pad, and is aligned with the first surface and the second surface of the substrate. 如請求項7所述的封裝載板的製作方法，其中形成該導電結構層於該基板上的步驟，包括：形成至少一貫孔於該基板上；形成一導電材料層於該基板上，該導電材料層覆蓋該至少一貫孔的內壁，且延伸覆蓋於該絕緣層上、該至少一第一接墊與該至少一第二接墊上，以及該基板的該第一表面及該第二表面上；以及圖案化該導電材料層，而形成該導電結構層，其中該導電結構層包括一第一圖案化線路層、一第二圖案化線路層以及至少一導通層，該至少一導通層覆蓋該至少一貫孔的內壁，且連接位於該第一表面上的該第一圖案化線路層及位於該第二表面上的該第二圖案化線路層，該第一圖案化線路層與該至少一第一接墊結構性且電性連接，而該第二圖案化線路層與該至少一第二接墊結構性且電性連接。 The manufacturing method of a package carrier board according to claim 7, wherein the step of forming the conductive structure layer on the substrate includes: forming at least a through hole on the substrate; forming a conductive material layer on the substrate, the conductive layer The material layer covers the inner wall of the at least through hole, and extends to cover the insulating layer, the at least one first pad and the at least one second pad, and the first surface and the second surface of the substrate and patterning the conductive material layer to form the conductive structure layer, wherein the conductive structure layer includes a first patterned circuit layer, a second patterned circuit layer and at least one conduction layer, the at least one conduction layer covering the At least the inner wall of the through hole is connected to the first patterned circuit layer on the first surface and the second patterned circuit layer on the second surface, the first patterned circuit layer and the at least one The first pad is structurally and electrically connected, and the second patterned circuit layer is structurally and electrically connected to the at least one second pad. 如請求項6所述的封裝載板的製作方法，還包括：形成一第一防焊層於該第一增層結構上，其中該第一防焊層具有多個第一開口，該些第一開口暴露出部分該第一增層結構；形成一第二防焊層於該第二增層結構上，其中該第二防焊層具有多個第二開口，該些第二開口暴露出部分該第二增層結構；形成一第一表面處理層於該些第一開口所暴露出的該第一增層結構上；以及 形成一第二表面處理層於該些第二開口所暴露出的該第二增層結構上。 The manufacturing method of a package carrier board according to claim 6, further comprising: forming a first solder resist layer on the first build-up structure, wherein the first solder resist layer has a plurality of first openings, and the first solder resist layers have a plurality of first openings. an opening exposes a portion of the first build-up structure; a second solder mask is formed on the second build-up structure, wherein the second solder mask has a plurality of second openings, and the second openings expose portions the second build-up structure; forming a first surface treatment layer on the first build-up structure exposed by the first openings; and A second surface treatment layer is formed on the second build-up structure exposed by the second openings. 如請求項9所述的封裝載板的製作方法，還包括：分別形成多個第一焊球於該第一防焊層的該些第一開口內，其中該第一表面處理層位於該些第一焊球與該第一增層結構之間；以及分別形成多個第二焊球於該第二防焊層的該些第二開口內，其中該第二表面處理層位於該些第二焊球與該第二增層結構之間。 The method for fabricating a package carrier according to claim 9, further comprising: forming a plurality of first solder balls in the first openings of the first solder resist layer, wherein the first surface treatment layer is located on the first openings. between the first solder balls and the first build-up structure; and respectively forming a plurality of second solder balls in the second openings of the second solder mask layer, wherein the second surface treatment layer is located in the second between the solder balls and the second build-up structure.
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